Dissertations / Theses on the topic 'Hardware extensions'
To see the other types of publications on this topic, follow the link: Hardware extensions.
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 16 dissertations / theses for your research on the topic 'Hardware extensions.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Hamilton, John, Ronald Fernandes, Michael Graul, Timothy Darr, and Charles H. Jones. "Extensions to the Instrument Hardware Abstraction Language (IHAL)." International Foundation for Telemetering, 2008. http://hdl.handle.net/10150/606221.
Full textAbstract:
ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, CaliforniaIn this paper we describe extensions to the Instrument Hardware Abstraction Language (IHAL). Since IHAL was first presented to ITC in 2006, a number of improvements were made to the design of IHAL. Major changes to the schema include splitting it into multiple XML Schema (XSD) files, separation of the description of instrumentation functions from the description of the hardware, and addition of a function pool.
2
Esoul, O. "VMX-rootkit : implementing malware with hardware virtual machine extensions." Thesis, University of Salford, 2008. http://usir.salford.ac.uk/26667/.
Full textAbstract:
Stealth Malware (Rootkit) is a malicious software used by attackers who wish to run their code on a compromised computer without being detected. Over the years, rootkits have targeted different operating systems and have used different techniques and mechanisms to avoid detection. In late 2005 and early 2006, both, Intel™ and AMD™ incorporated explicit hardware support for virtualization into their CPUs. While this hardware support can help simplify the design and the implementation of a light-weight and efficient Virtual Machine Monitors (VMMs), this technology has introduced a new powerful mechanism that can be used by malware to create extremely stealthy rootkit called hardware-assisted virtual machine rootkit (HVM rootkit). An HVM rootkit is capable of totally controlling a compromised system by installing a small VMM (a.k.a. hyper- visor) underneath the operating system and its applications without altering any part of the target operating system or any part of its applications. It places the existing operating system into a virtual machine and turns it into a guest operating system on-the-fly without a reboot. The guest operating system is then totally governed and manipulated by the malicious hypervisor. In this thesis I have investigated the design and implementation of a minimal hypervisor based Rootkit that takes advantage of Intel Visualization Technology (Intel VT) for the IA-32 architecture (VT-x) and Microsoft Windows XP SP2 as the target operating system.
3
Frieb, Martin [Verfasser], and Theo [Akademischer Betreuer] Ungerer. "Hardware extensions for a timing-predictable many-core processor / Martin Frieb ; Betreuer: Theo Ungerer." Augsburg : Universität Augsburg, 2019. http://nbn-resolving.de/urn:nbn:de:bvb:384-opus4-893331.
Full text
4
Hempel, Gerald [Verfasser], Christian [Gutachter] Hochberger, Andreas [Gutachter] Koch, and Klaus [Gutachter] Kabitzsch. "Generation of Application Specific Hardware Extensions for Hybrid Architectures : The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis / Gerald Hempel ; Gutachter: Christian Hochberger, Andreas Koch, Klaus Kabitzsch." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/122694258X/34.
Full text
5
Bryksin, Vladyslav Sergeevich. "ASIC life extension through hardware patch interfaces." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1464873.
Full textAbstract:
Thesis (M.S.)--University of California, San Diego, 2009.Title from first page of PDF file (viewed July 2, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 46-47).
6
Schumacher, Guido. "Object-oriented hardware specification and design with a language extension to VHDL." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=958338353.
Full text
7
Morrissey, Joseph Patrick. "The extension and hardware implementation of the comprehensive integrated security system concept." Thesis, University of Plymouth, 1995. http://hdl.handle.net/10026.1/336.
Full textAbstract:
The current strategy to computer networking is to increase the accessibility that legitimate users have to their respective systems and to distribute functionality. This creates a more efficient working environment, users may work from home, organisations can make better use of their computing power. Unfortunately, a side effect of opening up computer systems and placing them on potentially global networks is that they face increased threats from uncontrolled access points, and from eavesdroppers listening to the data communicated between systems. Along with these increased threats the traditional ones such as disgruntled employees, malicious software, and accidental damage must still be countered. A comprehensive integrated security system ( CISS ) has been developed to provide security within the Open Systems Interconnection (OSI) and Open Distributed Processing (ODP) environments. The research described in this thesis investigates alternative methods for its implementation and its optimisation through partial implementation within hardware and software and the investigation of mechanismsto improve its security. A new deployment strategy for CISS is described where functionality is divided amongst computing platforms of increasing capability within a security domain. Definitions are given of a: local security unit, that provides terminal security; local security servers that serve the local security units and domain management centres that provide security service coordination within a domain. New hardware that provides RSA and DES functionality capable of being connected to Sun microsystems is detailed. The board can be used as a basic building block of CISS, providing fast cryptographic facilities, or in isolation for discrete cryptographic services. Software written for UNIX in C/C++ is described, which provides optimised security mechanisms on computer systems that do not have SBus connectivity. A new identification/authentication mechanism is investigated that can be added to existing systems with the potential for extension into a real time supervision scenario. The mechanism uses keystroke analysis through the application of neural networks and genetic algorithms and has produced very encouraging results. Finally, a new conceptual model for intrusion detection capable of dealing with real time and historical evaluation is discussed, which further enhances the CISS concept.
8
Necsulescu, Philip I. "Automatic Generation of Hardware for Custom Instructions." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20153.
Full textAbstract:
The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera FPGAs. It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. The performance improvement of the generated code is compared to using only the processor’s standard instruction set.
9
Cai, Zixian. "Concurrent Copying Garbage Collection with Hardware Transactional Memory." Thesis, 2020. http://hdl.handle.net/1885/262693.
Full textAbstract:
Many applications, such as video-based or transaction-based ones, are latency-critical. Any additional latency may greatly degrade the user experience, inflicting significant financial loss on the vendor. Recently, an increasing number of these applications are written in managed languages, such as C#, Java, JavaScript, and PHP, for productivity and reliability. Garbage collection (GC) provides automatic memory management to managed languages. However, GC can also induce pauses in the application, greatly affecting the user experience. This thesis explores the challenges of minimizing GC pauses. Concurrent GC reduces pauses by working concurrently with the application (the mutator). Copying GC improves the mutator locality and reduces the heap fragmentation. Concurrent copying GC achieves both, but requires heavyweight synchronization to ensure that the concurrently executing mutator has a consistent view of the heap while the collector changes it. Existing implementations of concurrent copying GC use read barriers or page protections to prevent the mutator from using stale references. Unfortunately, these synchronization mechanisms introduce high overhead to the mutator. My thesis is that, by using hardware transactional memory (HTM), mutators can execute transactionally during concurrent copying, achieving a consistent view of the heap, but with lower overhead than read barriers or page protection. The contributions of this thesis are twofold. (1) I implement and evaluate a novel algorithm of using HTM to reduce the mutator overhead of concurrent copying GC. (2) I conduct a detailed analysis of HTM capacity, filling a significant gap in the literature, and informing the design of our HTM-based algorithm. I then use the insights on HTM capacity to implement several optimizations to improve the algorithm. Using the Intel Transactional Synchronization Extension (TSX) as a case study, I measure the transaction capacity on this popular HTM implementation, and cross-validate the results with the literature and fill a gap in the literature, resolving ostensibly contradictory results. I have also explored different factors that may affect the effective capacity of transactions, which have not yet been reported in the literature (to the best of my knowledge). I implement the algorithm in MMTk, a framework for the design and implementation of GC. The implementation is evaluated on Intel TSX using several test programs. The results suggest that performing concurrent copying GC using HTM is viable. This work deepens the understanding of HTM, its strengths and weaknesses, in the research community. Strategies using this work to fully exploit the capabilities of HTM can be generalized and applied to other applications of HTM. Finally, this work enables the design and implementation of concurrent copying GC with lower mutator overhead with similar hardware support.
10
Hempel, Gerald. "Generation of Application Specific Hardware Extensions for Hybrid Architectures: The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis." 2017. https://tud.qucosa.de/id/qucosa%3A36069.
Full textAbstract:
Architectures combining a field programmable gate array (FPGA) and a general-purpose processor on a single chip became increasingly popular in recent years. On the one hand, such hybrid architectures facilitate the use of application specific hardware accelerators that improve the performance of the software on the host processor. On the other hand, it obliges system designers to handle the whole process of hardware/software co-design. The complexity of this process is still one of the main reasons, that hinders the widespread use of hybrid architectures. Thus, an automated process that aids programmers with the hardware/software partitioning and the generation of application specific accelerators is an important issue. The method presented in this thesis neither requires restrictions of the used high-level-language nor special source code annotations. Usually, this is an entry barrier for programmers without deeper understanding of the underlying hardware platform.
This thesis introduces a seamless programming flow that allows generating hardware accelerators for unrestricted, legacy C code. The implementation consists of a GCC plugin that automatically identifies application hot-spots and generates hardware accelerators accordingly. Apart from the accelerator implementation in a hardware description language, the compiler plugin provides the generation of a host processor interfaces and, if necessary, a prototypical integration with the host operating system. An evaluation with typical embedded applications shows general benefits of the approach, but also reveals limiting factors that hamper possible performance improvements.
11
Tsang, Chieh-Hao, and 臧傑晧. "Memory Virtualization on ARM Architecture with Virtualization Hardware Extension." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/99558298925363378238.
Full textAbstract:
碩士國立清華大學
資訊工程學系
101
Virtualization is a very important technique on resource sharing and server security, and it becomes an indispensable technique on cloud computing. Most of embedded hardware devices are developed on ARM architecture because of simpler instruction sets than X86 and excellent power consumption. To the accompaniment of popular cloud computing, ARM holding also targets on server market to create more business-opportunities. Therefore, ARM provided new architecture for the incoming cloud computing generation. Hardware-assisted extension is supported since ARMv7. Without hardware-assisted extension, shadow page table is the general method to implement memory virtualization. In addition, complex work for maintaining shadow page table such as walking guest page table and building reverse map are necessary for memory virtualization on ARM. In contrast to ARMv6, ARMv7-A provides a special processor mode for hypervisor implementation. Besides, there are some specific registers controlling processor, memory, or I/O virtualization. What’s more, ARMv7-A provides a two-stage memory system control which formed into 64-bit descriptor, covering 40-bit memory address space. In this thesis, I will discuss how to implement memory virtualization with ARMv7-A hardware-assisted virtualization extension.
12
Hou, Yi-Hung, and 侯宜宏. "Performance Monitor Counter Virtualization on ARM Architecture with Hardware Virtualization Extension." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/02767354489149972909.
Full textAbstract:
碩士國立交通大學
資訊科學與工程研究所
103
Virtualization is comprehensively applied in a variety of different domains, including emerging cloud environments that provide full virtualized operation system as a service. The demand for performance analysis and system diagnosis in virtualization environment is increasing. Profiling tools based on hardware performance counters are necessary for performance debugging of complex software system. All modern processors are equipped with hardware performance counters, but virtual machine monitors (VMMs) do not expose them to the guest virtual machines. Therefore, profiling tools commonly used in native environments are not available in virtualized environments, and performance analysis of software running in a virtualized environment is contrastively difficult. With virtualization hardware extension since ARM Cortex A15, system virtualization on ARM architecture supports full virtualization and earns great performance improvement. However, the hardware performance counters are still untouchable to the guest virtual machines on ARM architecture. This thesis describes the design and implementation of hardware performance counters virtualization that is used to access in the guest virtual machines on ARM architecture with hardware virtualization extension. We present experimental results based on microbenchmarks that show the accuracy and usability of the obtained measurements when compared to native execution.
13
Best, Joel. "Real-Time Operating System Hardware Extension Core for System-on-Chip Designs." Thesis, 2013. http://hdl.handle.net/10214/5257.
Full textAbstract:
This thesis presents a real-time operating system hardware extension core which supports the integration of hardware accelerators into real-time system-on-chip designs as hardware tasks. The hardware extension core utilizes reconfigurable logic to manage synchronization events, data transfers, and hardware task control. A reduction in interrupt latency, frequency, and execution time provides performance and predictability improvements for real-time applications. Required communication between the CPU and hardware accelerators is also reduced significantly. Compared to a software implementation, synthetic benchmarks of common synchronization tasks show up to a 41% increase in synchronization performance. Analysis of a test case design for audio encoding and encryption using three hardware accelerators shows results of a 2.89x throughput improvement in comparison to the use of software device driver tasks. Overall, this design simplifies the integration of hardware accelerators into real-time system-on-chip designs while improving the performance and predictability of these systems.
14
Schumacher, Guido [Verfasser]. "Object-oriented hardware specification and design with a language extension to VHDL / von Guido Schumacher." 1999. http://d-nb.info/958338353/34.
Full text
15
CHEN, WEI-REN, and 陳韋任. "The Design and Implementation of a Hardware Accelerator of Seed Extension for BWA-MEM Algorithm." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/n6sfby.
Full textAbstract:
碩士國立臺灣科技大學
電子工程系
107
The general genetic analysis process is divided into three main steps. The first step is mapping DNA reads onto a reference genome. The second and the final stages are to find mutations in DNA. Compared to the last two steps, the first step is time-consuming. The BWA-MEM algorithm was used in the first step of genetic analysis process. The Seed Extension stage in BWA-MEM algorithm is matrix calculation, which is suitable for hardware parallel calculation. Therefore, this thesis proposes an Seed Extension hardware accelerator. In this thesis, we implement a Seed Extension accelerator using a systolic array. Parallel calculations are achieved using PEs in the systolic array. In order to improve performance, the following two improvements are made: First, we use a parallel input for sending read to the systolic array. Second, we adopt a VLL architecture in the PE array, make the reference sequence into the working PE faster using the multiplexer. The Seed Extension Accelerator has been implemented and verified with an FPGA device(xc5vlx110t) of the Xilinx Vertex 5 family and a TSMC 0.18 μm cell library. In the FPGA part, it needs 17610 LUTs and 7954 registers, operates at 125 MHz, the Seed Extension operation core is 6.5x faster than the software and the average throughput is 45.90 Mbp/s. In the cell-based part, it operates at 100 MHz, the Seed Extension core operation time is 5.2x faster than the software, and the average throughput is 36.70 Mbp/s. The chip area is 1.761 mm × 1.760 mm and the core area is 1.284 mm × 1.272 mm, which is approximately equivalent to 169,660 gates, and consumes about 68.03 mW in the typical operating condition.
16
Chiang, Shou-Cheng, and 蔣守誠. "A STUDY OF THE SUCCESSFUL FACTOR OF BRAND EXTENSION FOR INFORMATION HARDWARE VENDOR ON LARGE-SCALE ORGNIZATION --A VIEW OF CUSTOMER OF NETWORK INTEGRATION DEPARTMENT OF HEWLETT-PACKARD TAIWAN." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/js4gtv.
Full textAbstract:
碩士國立臺灣科技大學
企業管理系
94
In the past 30 years, with more and more complicated rise with Internet/Intranet of company's information environment, make the demand for the computer heighten, so has brought up much computer hardware manufacturer, for example as if Dell that IBM, HP, Compaq, Sun Microsystem, Gateway, Bull have risen until recently, even because Taiwan is the important strategic place where the global computer hardware takes the place of the worker, bring up the rise like the large computer of Acer great chess computer and Asus China, it is the computer hardware trader that has so many brands alone, if count other software and networking products industry person in again again, it is very difficult for customer not to go, find out about every product of functions and characteristics, seem brand can go only indicator to judge product as consumer only at this time, the brand becomes the most frequently used tactics when being extended. This research offers through the domestic foreign language, collect relevant materials such as brand extending, pluses and minuses and benefit of the extended brand,etc., and through the large-scale customer of deep interview, synthesize customer extended consciousness intensity, brand Lenovo and cognition to brand and agree with the response of one degree of questions, to probe into the view of the extended brand and application situation. Visited deeply and referred to analyzing, the resulting conclusion of this research is as follows: First, HP has good advisor, special project file and ability of the technological service Second, HP has advertising results to the customer Third, HP has stronger mother's brand images in the large-scale organization Fourth, technology and the service of HP but transfer is that the large-scale organization adopts the main thinking of extending the products Fifth, HP raises the result of brand Lenovo by long-term cooperation Sixth, HP has ability of the globle service