Relevant bibliographies by topics / Hardware extensions

Academic literature on the topic 'Hardware extensions'

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Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Hardware extensions"

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Oliveira, Daniela, Nicholas Wetzel, Max Bucci, Jesus Navarro, Dean Sullivan, and Yier Jin. "Hardware-software collaboration for secure coexistence with kernel extensions." ACM SIGAPP Applied Computing Review 14, no. 3 (September 22, 2014): 22–35. http://dx.doi.org/10.1145/2670967.2670969.

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Nunez, J. L., and S. Jones. "Run-length coding extensions for high performance hardware data compression." IEE Proceedings - Computers and Digital Techniques 150, no. 6 (2003): 387. http://dx.doi.org/10.1049/ip-cdt:20030750.

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Craft, D. J. "A fast hardware data compression algorithm and some algorithmic extensions." IBM Journal of Research and Development 42, no. 6 (November 1998): 733–46. http://dx.doi.org/10.1147/rd.426.0733.

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Wang, Kailong, Yuxi Ling, Yanjun Zhang, Zhou Yu, Haoyu Wang, Guangdong Bai, Beng Chin Ooi, and Jin Song Dong. "Characterizing Cryptocurrency-themed Malicious Browser Extensions." Proceedings of the ACM on Measurement and Analysis of Computing Systems 6, no. 3 (December 2022): 1–31. http://dx.doi.org/10.1145/3570603.

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Due to the surging popularity of various cryptocurrencies in recent years, a large number of browser extensions have been developed as portals to access relevant services, such as cryptocurrency exchanges and wallets. This has stimulated a wild growth of cryptocurrency themed malicious extensions that cause heavy financial losses to the users and legitimate service providers. They have shown their capability of evading the stringent vetting processes of the extension stores, highlighting a lack of understanding of this emerging type of malware in our community. In this work, we conduct the first systematic study to identify and characterize cryptocurrency-themed malicious extensions. We monitor seven official and third-party extension distribution venues for 18 months (December 2020 to June 2022) and have collected around 3600 unique cryptocurrency-themed extensions. Leveraging a hybrid analysis, we have identified 186 malicious extensions that belong to five categories. We then characterize those extensions from various perspectives including their distribution channels, life cycles, developers, illicit behaviors, and illegal gains. Our work unveils the status quo of the cryptocurrency-themed malicious extensions and reveals their disguises and programmatic features on which detection techniques can be based. Our work serves as a warning to extension users, and an appeal to extension store operators to enact dedicated countermeasures. To facilitate future research in this area, we release our dataset of the identified malicious extensions and open-source our analyzer.
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Grübl, Andreas, Sebastian Billaudelle, Benjamin Cramer, Vitali Karasenko, and Johannes Schemmel. "Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System." Journal of Signal Processing Systems 92, no. 11 (July 9, 2020): 1277–92. http://dx.doi.org/10.1007/s11265-020-01558-7.

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Abstract This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65 nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Accelerated operation of neuromorphic circuits and highly-parallel digital data buses between the full-custom neuromorphic part and the PPU require custom methodologies to close the digital signal timing at the interfaces. Novel extensions to the standard digital physical implementation design flow are highlighted. We present early results from the first full-size BrainScaleS-2 ASIC containing 512 neurons and 130 K synapses, demonstrating the successful application of these methods. An application example illustrates the full functionality of the BrainScaleS-2 hybrid plasticity architecture.
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Stachour, Paul, and Bhavani Thuraisingham. "SQL extensions for security assertions." Computer Standards & Interfaces 11, no. 1 (January 1990): 5–14. http://dx.doi.org/10.1016/0920-5489(90)90067-p.

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Necula, George C., and Peter Lee. "Safe kernel extensions without run-time checking." ACM SIGOPS Operating Systems Review 30, SI (October 28, 1996): 229–43. http://dx.doi.org/10.1145/248155.238781.

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Guerra, Jorge, Luis Useche, Medha Bhadkamkar, Ricardo Koller, and Raju Rangaswami. "The case for active block layer extensions." ACM SIGOPS Operating Systems Review 42, no. 6 (October 2008): 3–9. http://dx.doi.org/10.1145/1453775.1453778.

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Jungeblut, T., C. Puttmann, R. Dreesen, M. Porrmann, M. Thies, U. Rückert, and U. Kastens. "Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography." Advances in Radio Science 8 (December 22, 2010): 295–305. http://dx.doi.org/10.5194/ars-8-295-2010.

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Abstract. The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.
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Găitan, Vasile Gheorghiță, and Ionel Zagan. "Experimental Implementation and Performance Evaluation of an IoT Access Gateway for the Modbus Extension." Sensors 21, no. 1 (January 1, 2021): 246. http://dx.doi.org/10.3390/s21010246.

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This paper presents the relevant aspects regarding the experimental implementation and performance evaluation of an Internet of things (IoT) gateway for the Modbus extension. The proposed Modbus extension specifications are extended by defining the new optimized message format, and the structure of the acquisition cycle for obtaining a deterministic temporal behavior and solutions are presented for the description of devices at the MODBUS protocol level. Three different implementations are presented, and the Modbus extension’s performance is validated regarding the efficiency in the use of the acquisition cycle time. The software and hardware processing time and the importance and effect of the various components are analyzed and evaluated. They all support the implementation of an Internet of things gateway for Modbus extension. This paper introduces solutions for the structure of the acquisition cycle to include other valuable extensions, discusses the performance of a real implementation in the form of a gateway, adds new features to the Modbus extension specification, and strengthens some of the existing ones. In accordance with the novelty and contribution of this paper to the field of local industrial networks, the results obtained in the analysis, testing, and validation of the Modbus extension protocol refer to the extending of the Modbus functions for industrial process monitoring and control management.
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Dissertations / Theses on the topic "Hardware extensions"

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Hamilton, John, Ronald Fernandes, Michael Graul, Timothy Darr, and Charles H. Jones. "Extensions to the Instrument Hardware Abstraction Language (IHAL)." International Foundation for Telemetering, 2008. http://hdl.handle.net/10150/606221.

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ITC/USA 2008 Conference Proceedings / The Forty-Fourth Annual International Telemetering Conference and Technical Exhibition / October 27-30, 2008 / Town and Country Resort & Convention Center, San Diego, California
In this paper we describe extensions to the Instrument Hardware Abstraction Language (IHAL). Since IHAL was first presented to ITC in 2006, a number of improvements were made to the design of IHAL. Major changes to the schema include splitting it into multiple XML Schema (XSD) files, separation of the description of instrumentation functions from the description of the hardware, and addition of a function pool.
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Esoul, O. "VMX-rootkit : implementing malware with hardware virtual machine extensions." Thesis, University of Salford, 2008. http://usir.salford.ac.uk/26667/.

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Stealth Malware (Rootkit) is a malicious software used by attackers who wish to run their code on a compromised computer without being detected. Over the years, rootkits have targeted different operating systems and have used different techniques and mechanisms to avoid detection. In late 2005 and early 2006, both, Intel™ and AMD™ incorporated explicit hardware support for virtualization into their CPUs. While this hardware support can help simplify the design and the implementation of a light-weight and efficient Virtual Machine Monitors (VMMs), this technology has introduced a new powerful mechanism that can be used by malware to create extremely stealthy rootkit called hardware-assisted virtual machine rootkit (HVM rootkit). An HVM rootkit is capable of totally controlling a compromised system by installing a small VMM (a.k.a. hyper- visor) underneath the operating system and its applications without altering any part of the target operating system or any part of its applications. It places the existing operating system into a virtual machine and turns it into a guest operating system on-the-fly without a reboot. The guest operating system is then totally governed and manipulated by the malicious hypervisor. In this thesis I have investigated the design and implementation of a minimal hypervisor based Rootkit that takes advantage of Intel Visualization Technology (Intel VT) for the IA-32 architecture (VT-x) and Microsoft Windows XP SP2 as the target operating system.
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Frieb, Martin [Verfasser], and Theo [Akademischer Betreuer] Ungerer. "Hardware extensions for a timing-predictable many-core processor / Martin Frieb ; Betreuer: Theo Ungerer." Augsburg : Universität Augsburg, 2019. http://nbn-resolving.de/urn:nbn:de:bvb:384-opus4-893331.

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Hempel, Gerald [Verfasser], Christian [Gutachter] Hochberger, Andreas [Gutachter] Koch, and Klaus [Gutachter] Kabitzsch. "Generation of Application Specific Hardware Extensions for Hybrid Architectures : The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis / Gerald Hempel ; Gutachter: Christian Hochberger, Andreas Koch, Klaus Kabitzsch." Dresden : Technische Universität Dresden, 2019. http://d-nb.info/122694258X/34.

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Bryksin, Vladyslav Sergeevich. "ASIC life extension through hardware patch interfaces." Diss., [La Jolla] : University of California, San Diego, 2009. http://wwwlib.umi.com/cr/ucsd/fullcit?p1464873.

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Thesis (M.S.)--University of California, San Diego, 2009.
Title from first page of PDF file (viewed July 2, 2009). Available via ProQuest Digital Dissertations. Includes bibliographical references (p. 46-47).
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Schumacher, Guido. "Object-oriented hardware specification and design with a language extension to VHDL." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=958338353.

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Morrissey, Joseph Patrick. "The extension and hardware implementation of the comprehensive integrated security system concept." Thesis, University of Plymouth, 1995. http://hdl.handle.net/10026.1/336.

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The current strategy to computer networking is to increase the accessibility that legitimate users have to their respective systems and to distribute functionality. This creates a more efficient working environment, users may work from home, organisations can make better use of their computing power. Unfortunately, a side effect of opening up computer systems and placing them on potentially global networks is that they face increased threats from uncontrolled access points, and from eavesdroppers listening to the data communicated between systems. Along with these increased threats the traditional ones such as disgruntled employees, malicious software, and accidental damage must still be countered. A comprehensive integrated security system ( CISS ) has been developed to provide security within the Open Systems Interconnection (OSI) and Open Distributed Processing (ODP) environments. The research described in this thesis investigates alternative methods for its implementation and its optimisation through partial implementation within hardware and software and the investigation of mechanismsto improve its security. A new deployment strategy for CISS is described where functionality is divided amongst computing platforms of increasing capability within a security domain. Definitions are given of a: local security unit, that provides terminal security; local security servers that serve the local security units and domain management centres that provide security service coordination within a domain. New hardware that provides RSA and DES functionality capable of being connected to Sun microsystems is detailed. The board can be used as a basic building block of CISS, providing fast cryptographic facilities, or in isolation for discrete cryptographic services. Software written for UNIX in C/C++ is described, which provides optimised security mechanisms on computer systems that do not have SBus connectivity. A new identification/authentication mechanism is investigated that can be added to existing systems with the potential for extension into a real time supervision scenario. The mechanism uses keystroke analysis through the application of neural networks and genetic algorithms and has produced very encouraging results. Finally, a new conceptual model for intrusion detection capable of dealing with real time and historical evaluation is discussed, which further enhances the CISS concept.
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Necsulescu, Philip I. "Automatic Generation of Hardware for Custom Instructions." Thèse, Université d'Ottawa / University of Ottawa, 2011. http://hdl.handle.net/10393/20153.

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The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera FPGAs. It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. The performance improvement of the generated code is compared to using only the processor’s standard instruction set.
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Cai, Zixian. "Concurrent Copying Garbage Collection with Hardware Transactional Memory." Thesis, 2020. http://hdl.handle.net/1885/262693.

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Many applications, such as video-based or transaction-based ones, are latency-critical. Any additional latency may greatly degrade the user experience, inflicting significant financial loss on the vendor. Recently, an increasing number of these applications are written in managed languages, such as C#, Java, JavaScript, and PHP, for productivity and reliability. Garbage collection (GC) provides automatic memory management to managed languages. However, GC can also induce pauses in the application, greatly affecting the user experience. This thesis explores the challenges of minimizing GC pauses. Concurrent GC reduces pauses by working concurrently with the application (the mutator). Copying GC improves the mutator locality and reduces the heap fragmentation. Concurrent copying GC achieves both, but requires heavyweight synchronization to ensure that the concurrently executing mutator has a consistent view of the heap while the collector changes it. Existing implementations of concurrent copying GC use read barriers or page protections to prevent the mutator from using stale references. Unfortunately, these synchronization mechanisms introduce high overhead to the mutator. My thesis is that, by using hardware transactional memory (HTM), mutators can execute transactionally during concurrent copying, achieving a consistent view of the heap, but with lower overhead than read barriers or page protection. The contributions of this thesis are twofold. (1) I implement and evaluate a novel algorithm of using HTM to reduce the mutator overhead of concurrent copying GC. (2) I conduct a detailed analysis of HTM capacity, filling a significant gap in the literature, and informing the design of our HTM-based algorithm. I then use the insights on HTM capacity to implement several optimizations to improve the algorithm. Using the Intel Transactional Synchronization Extension (TSX) as a case study, I measure the transaction capacity on this popular HTM implementation, and cross-validate the results with the literature and fill a gap in the literature, resolving ostensibly contradictory results. I have also explored different factors that may affect the effective capacity of transactions, which have not yet been reported in the literature (to the best of my knowledge). I implement the algorithm in MMTk, a framework for the design and implementation of GC. The implementation is evaluated on Intel TSX using several test programs. The results suggest that performing concurrent copying GC using HTM is viable. This work deepens the understanding of HTM, its strengths and weaknesses, in the research community. Strategies using this work to fully exploit the capabilities of HTM can be generalized and applied to other applications of HTM. Finally, this work enables the design and implementation of concurrent copying GC with lower mutator overhead with similar hardware support.
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Hempel, Gerald. "Generation of Application Specific Hardware Extensions for Hybrid Architectures: The Development of PIRANHA - A GCC Plugin for High-Level-Synthesis." 2017. https://tud.qucosa.de/id/qucosa%3A36069.

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Architectures combining a field programmable gate array (FPGA) and a general-purpose processor on a single chip became increasingly popular in recent years. On the one hand, such hybrid architectures facilitate the use of application specific hardware accelerators that improve the performance of the software on the host processor. On the other hand, it obliges system designers to handle the whole process of hardware/software co-design. The complexity of this process is still one of the main reasons, that hinders the widespread use of hybrid architectures. Thus, an automated process that aids programmers with the hardware/software partitioning and the generation of application specific accelerators is an important issue. The method presented in this thesis neither requires restrictions of the used high-level-language nor special source code annotations. Usually, this is an entry barrier for programmers without deeper understanding of the underlying hardware platform. This thesis introduces a seamless programming flow that allows generating hardware accelerators for unrestricted, legacy C code. The implementation consists of a GCC plugin that automatically identifies application hot-spots and generates hardware accelerators accordingly. Apart from the accelerator implementation in a hardware description language, the compiler plugin provides the generation of a host processor interfaces and, if necessary, a prototypical integration with the host operating system. An evaluation with typical embedded applications shows general benefits of the approach, but also reveals limiting factors that hamper possible performance improvements.
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Books on the topic "Hardware extensions"

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IEEE Computer Society. Design Automation Standards Committee. IEEE standard VHDL analog and mixed-signal extensions. New York, N.Y: Institute of Electrical and Electronics Engineers, 2007.

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Needamangalam, Balachander, ed. Verilog: Frequently asked questions : language, applications and extensions. New York, NY: Springer, 2004.

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Chonnad, Shivakumar S., and Needamangalam B. Balachander. Verilog : Frequently Asked Questions: Language, Applications and Extensions. Springer London, Limited, 2007.

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Verilog Frequently Asked Questions Language Applications And Extensions. Springer, 2010.

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IEEE Computer Society. Design Automation Standards Committee., Institute of Electrical and Electronics Engineers., and IEEE-SA Standards Board, eds. IEEE Standard VHDL analog and mixed-signal extensions. New York, N.Y., USA: Institute of Electrical and Electronics Engineers, 1999.

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IEEE Standard for Vhdl Analog and Mixed Signal Extensions. Institute of Electrical & Electronics Enginee, 1999.

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Chonnad, Shivakumar, and Needamangalam Balachander. Verilog: Frequently Asked Questions: Language, Applications and Extensions. Springer, 2004.

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Hukić, Mirsada, and Mirza Ponjavić. COVID-19 pandemic in Bosnia and Herzegovina: March – June 2020. Academy of Sciences and Arts of Bosnia and Herzegovina, 2020. http://dx.doi.org/10.5644/pi20.190.00.

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At the end of 2019 the world became aware of the existence of a new virus stemming from the Coronaviridae family and causing a specific disease – COVID-19. In less than three months, the virus and its consequences, developed from being a local public health problem in China to a daunting global problem we all had to face. On March 11, 2020 the World Health Organization (WHO) declared a pandemic of COVID-19. On the international scale, even in Bosnia and Herzegovina (BiH), the response of the professionals and scientists has been rapid, although not always consistently efficient enough. Despite the selfless cooperation of scientists and practitioners worldwide, countries with developed economies, good public health and a strong scientific system have had the advantage in the fight against the disease over developing countries. Despite the fact that by these criteria BiH is not one of the most resilient countries, so far, its response to the pandemic has seemed to be satisfactory. The Academy of Sciences and Arts of Bosnia and Herzegovina (ANUBiH) was one of the first institutions of the science system to respond to the pandemic. On the initiative and under the leadership of academician Mirsada Hukić, on March 22, 2020 the development of the project "Epidemic Location Intelligence System (ELIS)" and its Geoportal began on a voluntary basis, with the task of permanently monitoring the spread of COVID-19. Theoretical and professional parts of the project in the areas of medicine, public health and informatics were completed by April 2, 2020. Thanks to the support to the project by the Chairman of the Presidency of Bosnia and Herzegovina, Mr. Šefik Džaferović, the expert system received additional hardware support and was filled in time with data from across the country. This enabled the system to become operational as early as on April 8, 2020. The results of all these efforts are visible in this publication. Initially, the ELIS project was important for the epidemiological and public health area. The abundance of collected data and obtained virus samples enabled the extension of the project idea to the sequencing of viruses found in BiH and their typology. The transition of research to the clinical aspects of COVID-19 is the next phase in the development of the ELIS project. ANUBiH has already started the work on examining the economic and pedagogical consequences of COVID-19 in order to look at this medical phenomenon in the broadest possible context. All the results of ANUBiH in response to the epidemic challenges of COVID-19 are achieved due to the synergistic action of numerous individuals and institutions in different fields of science and public health in cooperation with government. Therefore, I believe that the ELIS project has shown the way to go in solving the burning problems of our society which we will encounter in the future.
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Book chapters on the topic "Hardware extensions"

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Eveking, H. "Automatic verification of extensions of hardware descriptions." In Computer-Aided Verification ’90, 3–14. Providence, Rhode Island: American Mathematical Society, 1991. http://dx.doi.org/10.1090/dimacs/003/02.

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Benzakki, Judith, and Bachir Djafri. "Object Oriented Extensions to VHDL, The LaMI proposal." In Hardware Description Languages and their Applications, 334–47. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35064-6_27.

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Bettarelli, Ferruccio, Emanuele Ciavattini, Ariano Lattanzi, Giovanni Beltrame, Fabrizio Ferrandi, Luca Fossati, Christian Pilato, et al. "Extensions of the hArtes Tool Chain." In Hardware/Software Co-design for Heterogeneous Multi-core Platforms, 193–227. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-1406-9_6.

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Stam, Martijn, and Arjen K. Lenstra. "Efficient Subgroup Exponentiation in Quadratic and Sixth Degree Extensions." In Cryptographic Hardware and Embedded Systems - CHES 2002, 318–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/3-540-36400-5_24.

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Malenko, Maja, and Marcel Baunach. "Hardware/Software Co-designed Security Extensions for Embedded Devices." In Architecture of Computing Systems – ARCS 2019, 3–14. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-18656-2_1.

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Groß, Hannes, and Thomas Plos. "On Using Instruction-Set Extensions for Minimizing the Hardware-Implementation Costs of Symmetric-Key Algorithms on a Low-Resource Microcontroller." In Radio Frequency Identification. Security and Privacy Issues, 149–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-36140-1_11.

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Keerup, Kalmer, Dan Bogdanov, Baldur Kubo, and Per Gunnar Auran. "Privacy-Preserving Analytics, Processing and Data Management." In Big Data in Bioeconomy, 157–68. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-71069-9_12.

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AbstractTypically, data cannot be shared among competing organizations due to confidentiality or regulatory restrictions. We present several technological alternatives to solve the problem: secure multi-party computation (MPC), trusted execution environments (TEE) and multi-key fully homomorphic encryption (MKFHE). We compare these privacy-enhancing technologies from deployment and performance point of view and explain how we selected technology and machine learning methods. We introduce a demonstrator built in the DataBio project for securely combining private and public data for planning of fisheries. The secure machine learning of best catch locations is a web solution utilizing Intel® Software Guard Extensions (Intel® SGX)-based TEE and built with the Sharemind HI (Hardware Isolation) development tools. Knowing where to go fishing is a competitive advantage that a fishery is not interested to share with competitors. Therefore, joint intelligence from public and private sector data while protecting secrets of each contributing organization is an important enabler. Finally, we discuss the wider business impact of secure machine learning in situations where data confidentiality is a concern.
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Schlager, Christian, Richard Messnarz, Harald Sporer, Armin Riess, Ralf Mayer, and Steffen Bernhardt. "Hardware SPICE Extension for Automotive SPICE 3.1." In Communications in Computer and Information Science, 480–91. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-97925-0_41.

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Lavice, Arthur, Nadia El Mrabet, Alexandre Berzati, and Jean-Baptiste Rigaud. "Hardware Implementation of Multiplication over Quartic Extension Fields." In Proceedings of the Seventh International Conference on Mathematics and Computing, 575–89. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6890-6_43.

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Grabher, Philipp, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Dan Page, Stefan Tillich, and Marcin Wójcik. "An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension." In Cryptographic Hardware and Embedded Systems – CHES 2011, 1–16. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23951-9_1.

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Conference papers on the topic "Hardware extensions"

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Alwardi, Zaid, Robert Wille, and Rolf Drechsler. "Extensions to the Reversible Hardware Description Language SyReC." In 2017 IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL). IEEE, 2017. http://dx.doi.org/10.1109/ismvl.2017.41.

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Marshall, Ben, Daniel Page, and Thinh Pham. "Implementing the Draft RISC-V Scalar Cryptography Extensions." In HASP '20: Hardware and Architectural Support for Security and Privacy. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3458903.3458904.

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Tarango, Joseph, Eamonn Keogh, and Philip Brisk. "Instruction set extensions for Dynamic Time Warping." In 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). IEEE, 2013. http://dx.doi.org/10.1109/codes-isss.2013.6659005.

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Mondelli, Andrea, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero, and Roberto Giorgi. "Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions." In 2015 Euromicro Conference on Digital System Design (DSD). IEEE, 2015. http://dx.doi.org/10.1109/dsd.2015.62.

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Eustache, Y., J. P. Diguet, and M. Elkhodary. "RTOS extensions for dynamic hardware / software monitoring and configuration management." In Proceedings 20th IEEE International Parallel & Distributed Processing Symposium. IEEE, 2006. http://dx.doi.org/10.1109/ipdps.2006.1639482.

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Manssour, Noura Ait, Vianney LapOtre, Guy Gogniat, and Arnaud Tisserand. "Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks." In 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE, 2022. http://dx.doi.org/10.1109/ddecs54261.2022.9770170.

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Ul Haq, Muhammad Shams, Lejian Liao, and Lerong Ma. "Transitioning Native Application into Virtual Machine by Using Hardware Virtualization Extensions." In 2016 International Symposium on Computer, Consumer and Control (IS3C). IEEE, 2016. http://dx.doi.org/10.1109/is3c.2016.108.

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Gunther, Stephan M., Maximilian Riemensberger, and Wolfgang Utschick. "Efficient GF arithmetic for linear network coding using hardware SIMD extensions." In 2014 International Symposium on Network Coding (NetCod). IEEE, 2014. http://dx.doi.org/10.1109/netcod.2014.6892123.

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Rawat, Hemendra K., and Patrick Schaumont. "SIMD Instruction Set Extensions for Keccak with Applications to SHA-3, Keyak and Ketje." In the Hardware and Architectural Support for Security and Privacy 2016. New York, New York, USA: ACM Press, 2016. http://dx.doi.org/10.1145/2948618.2948622.

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Chakrabarti, Somnath, Matthew Hoekstra, Dmitrii Kuvaiskii, and Mona Vij. "Scaling Intel® Software Guard Extensions Applications with Intel® SGX Card." In HASP '19: Workshop on Hardware and Architectural Support for Security and Privacy. New York, NY, USA: ACM, 2019. http://dx.doi.org/10.1145/3337167.3337173.

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