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1
Persson, Robert. "PPS5000 Thruster Emulator Architecture Development & Hardware Design." Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-72827.
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This Master's Thesis handles prestudy work and early hardware development that resulted in architectural definitions and prototype hardware of electronic ground support equipment. This equipment is destined to emulate the electric power consumption of the PPS5000 Hall Effect Thruster (HET), for use in satellite end-to-end tests of the all-electric Geostationary Satellite Electra, developed at OHB Sweden AB. The Thruster Emulator (TEM) was defined through a resulting compilation of intricate interdependent components that interface the satellite power system and the thruster, which yielded an architecture development to support some basic predefined emulator requirements. This architecture was then analyzed to form a base-line conceptual function of the emulator system, which incorporates the entire HET functionality. Six primary HET impedances were defined, of which the three most complex impedances were investigated fully. For the primary thruster discharge, research is shown of the complexity of implementing advanced electronic load hardware directly to the satellite's 5kW power system with respect to the transient primary plasma discharge during thruster start up, and with limitations on the electronic load reducing emulator-thruster similarities. Additionally, a fully functional plasma ignition emulator prototype circuit board was built to be used in the final hardware of the TEM to emulate the external HET cathode start-up functionality. Finally, a feasibility study for designing a possible solution for the large PPS5000 electromagnet impedance was performed, resulting in the manufacture of two prototype inductors with unsatisfying performance results according to the design requirements.
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Stanley, Berdenia Walker. "Hierarchical multiway partitioning strategy with hardware emulator architecture intelligence." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13360.
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Witkowsky, Jason. "A hardware emulator testbed for a software-defined radio." Thesis, Peninsula Technikon, 2003. http://hdl.handle.net/20.500.11838/1170.
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Submitted in fulfillment of the requirement for the
Masters degree of Technology (MTech): Electrical Engineering, 2003Contemporary software-defined radio (SDR) is continuously changing and challenging the way traditional RF systems operate. Having more of a radio system’s operation in software enables further flexibility through the use of software manipulation. Due to practical limitations, however, it is not always feasible to have the entire radio system’s operations performed using software. Practical limitations, therefore, require that a SDR employs some form of RF front-end in order to interface the antenna signals and the signals prior to the data converters. As technology grows in support of SDR development, this hardware interface is becoming increasingly smaller. The problem with the rapid rate at which SDR developments are occurring is that RF hardware needs to change accordingly. Therefore, the RF hardware front-end can be seen as a non-standardised piece of equipment. To the designer, this means having to prototype in hardware in order to experiment with various types of SDR hardware front-ends. One of a SDR’s main attractions is the inherent property of software testability. Taking this fact into account, this thesis investigates the design and operation of a basic softwaredriven RF front-end emulator for a SDR. Basic prototype software models are identified and developed in order to test their performance within the emulator. The focus of the thesis, however, is geared toward the development of a software architecture that enables a high degree of interchangeability amongst the underlying modelled components. In the case of a SDR, the advantage of prototyping in software is in predicting the behaviour of a system prior to having to perform any physical developments. This property of software testability in the emulator can only fully be appreciated if a bench-mark system is used to evaluate the overall performance of the emulator. Therefore, a physical hardware setup is performed in order to test the basic aspects of the emulators operation. This evaluation is not meant as an exhaustive analysis of the emulator, but aims to highlight the overall performance of the emulated system against a typical physical system setup.
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Daniil, Nickolaos. "Battery emulator operating in a power hardware-in-the-loop simulation : the concept of hybrid battery emulator." Thesis, University of Bristol, 2017. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.723517.
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O'Rourke, Colm Joseph. "Design of a hardware solar emulator for an experimental microgrid." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99852.
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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 67-68).
Microgrids are regions where local generation and loads are clustered together. Students from the LEES group at MIT are currently developing an experimental microgrid. This will enable various studies in the area of microgrid dynamics. The setup consists of a variety of modules that emulate both conventional and renewable sources. In this thesis, we focus on the design of one of these modules: the solar PV emulator. The complete design of a solar PV emulator will be described. Firstly, AC and DC models of a solar cell are introduced. These models specify design constraints for the power electronic circuitry. They also indicate a desired performance for the feedback control system. The controller design is discussed and the effect of load type on the closed-loop dynamics are considered. This is especially interesting for the grid-connected case. The design methodology culminates in the construction of an experimental prototype of the hardware solar PV emulator. The modular design approach is outlined as are its benefits to the overall construction of the microgrid. A Generic Controller board that can be used for all future power electronic modules in the microgrid is also designed and fabricated. The results of simulations and experiments are discussed and it is shown that it is possible for a buck converter to emulate the steady state dynamics associated with solar PV panels.
by Colm Joseph O'Rourke.
S.M.
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Petucco, Andrea. "Hardware in the loop, all-electronic wind turbine emulator for grid compliance testing." Doctoral thesis, Università degli studi di Padova, 2017. http://hdl.handle.net/11577/3422321.
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During the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be
submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through
(LVRT) certitication due to the following resons:
• The standards specify it must be performed ad different power levels. For this reasons it is necessary to wait for the right atmospheric conditions.
• It requires a voltage sag generator which is usually expensive and bulky.
• The voltage sag generator needs to be cabled between the grid and the wind
turbine.
• The voltage sag generator causes disturbances and perturbation on the power
grid, for this reasons agreements with the distributor operator are needed.
For all these reasons a laboratory test bench to perform the LVRT certification tests on wind turbines would be a more controlled and inexpensive alternative to the classic
testing methodology. The research presented in this thesis is focused on the design and the realization of a test bench to perform certification tests on energy converters
for wind turbines in laboratory. More specifically, the possibility of performing LVRT certification tests directly in laboratory over controlled conditions would allow faster testing procedures and less certification overall costs. The solution presented in this
thesis is based on a power hardware in the loop implementing a digitally-controlled, power electronics-based emulation of a wind turbine. This emulator is used to drive the electronic wind energy converter (WEC) under test. A grid emulator is used to
apply voltage sags to the wind turbine converter and perform LVRT certification tests.
In this solution AC power supplies are used to emulate both the wind turbine and the grid emulator. For this reason the test bench power rating is limited to the AC supplies one. Two working versions of the test bench has been realized and successfully tested.
The work here presented has evolved through the following phases:
• Study of the grid code requirements and the state of the art.
• Modeling of the parts of a wind turbine and complete system simulations.During the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through (LVRT) certitication due to the following resons: • The standards specify it must be performed ad different power levels. For this reasons it is necessary to wait for the right atmospheric conditions. • It requires a voltage sag generator which is usually expensive and bulky. • The voltage sag generator needs to be cabled between the grid and the wind turbine. • The voltage sag generator causes disturbances and perturbation on the power grid, for this reasons agreements with the distributor operator are needed. For all these reasons a laboratory test bench to perform the LVRT certification tests on wind turbines would be a more controlled and inexpensive alternative to the classic testing methodology. The research presented in this thesis is focused on the design and the realization of a test bench to perform certification tests on energy converters for wind turbines in laboratory. More specifically, the possibility of performing LVRT certification tests directly in laboratory over controlled conditions would allow faster testing procedures and less certification overall costs. The solution presented in this thesis is based on a power hardware in the loop implementing a digitally-controlled, power electronics-based emulation of a wind turbine. This emulator is used to drive the electronic wind energy converter (WEC) under test. A grid emulator is used to apply voltage sags to the wind turbine converter and perform LVRT certification tests. In this solution AC power supplies are used to emulate both the wind turbine and the grid emulator. For this reason the test bench power rating is limited to the AC supplies one. Two working versions of the test bench has been realized and successfully tested. The work here presented has evolved through the following phases: • Study of the grid code requirements and the state of the art. • Modeling of the parts of a wind turbine and complete system simulations.
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Adnan, Muhammad Wasif. "Implementation of an FPGA based Emulator for High Speed Power Electronic Systems." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175752.
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During development of control systems for power electronic systems, it is desirable to test the controller in real-time, by interfacing it with an emulator device. In this context, this work comprises the development of an emulator that can model accurately the dynamics of high speed power electronic systems and provides interfaces that are compatible with the real hardware. The realtime state calculations, based on discrete models, were performed on custom logic, implemented on an FPGA. The realized system allows to emulate Linear Parameter Varying (LPV) systems, achieving sampling rates up to 12MHz using a low cost Xilinx FPGA. As a result, power electronic systems with very high switching frequencies can be modeled. In addition, the FPGA incorporates a soft-core processor that allows a designer to easily re-configure the system model through software. The emulator system has been validated for a multiphase DC-DC converter, by comparing its results with the real hardware setup.
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Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Dresden TUDpress, 2008. http://d-nb.info/991847423/04.
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Shadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.
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The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into the statistics of a channel emulator and analyzes its effects on a particular decoder.
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Oliveira, José Rodrigo de. "Emulador de turbina eólica : uma ferramenta para o estudo experimental e computacional /." Bauru, 2019. http://hdl.handle.net/11449/191354.
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Orientador: André Luiz AndreoliResumo: As fontes renováveis de energia apresentam-se como solução para problemas relacionados ao aumento da demanda por energia elétrica e crescimento dos níveis de emissão de gás carbônico, uma vez que são não poluentes, limpas e abundantes. Aproveitamentos eólicos se mostram como uma das mais promissoras fontes de energia renovável, e por essa razão as pesquisas envolvendo este tipo de aproveitamento têm despertado grande interesse na comunidade científica. Este trabalho apresenta o desenvolvimento de um emulador de turbina eólica (ETE), uma ferramenta de apoio às investigações experimentais capaz de reproduzir o comportamento mecânico dinâmico de uma turbina eólica através de uma malha de controle digital em configuração de hardware-in-the-loop atuando sobre um acionamento eletrônico de uma máquina de indução Operando como fonte de força motriz, o ETE torna mais fácil a avaliação dinâmica de geradores e seus sistemas de controle associados voltados às aplicações envolvendo energia eólica. A pesquisa apresenta uma revisão bibliográfica sobre o estado da arte, a modelagem e a implementação experimental de um emulador de turbina eólica utilizando um motor de indução trifásico (MIT) acionado por um inversor de frequência. Para isso, é implementado um controle em malha fechada de conjugado e velocidade. Este controle faz com que o acionamento eletromecânico representado pelo MIT e inversor de frequência apresente em seu eixo o comportamento de uma turbina eólica conforme os parâmetros... (Resumo completo, clicar acesso eletrônico abaixo)
Mestre
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Tomaro, Emiliano. "Simulations and automated tests of battery management system control strategies and diagnosis on hardware in the loop system." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2019. http://amslaurea.unibo.it/19241/.
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The aim of this master’s degree thesis is to describe the activities performed during a four months internship in Magneti Marelli Powertrain, Bologna. The role I covered in this period was Validation Engineer for Hybrid & Electric systems in Hardware in the Loop (HIL) environment, the main activity was to develop automated tests in python involving software and control strategies.
A first focus of this thesis is on the Battery Management System functionalities, Hardware in the Loop system and Test Automation.
The second part of the thesis describes the experimental activity of the interniship: the development of a cells' emulator in order to simulate battery packs in HIL environment.
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Thornes, Tobias. "Investigating the potential for improving the accuracy of weather and climate forecasts by varying numerical precision in computer models." Thesis, University of Oxford, 2018. http://ora.ox.ac.uk/objects/uuid:038874a3-710a-476d-a9f7-e94ef1036648.
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Accurate forecasts of weather and climate will become increasingly important as the world adapts to anthropogenic climatic change. Forecasts' accuracy is limited by the computer power available to forecast centres, which determines the maximum resolution, ensemble size and complexity of atmospheric models. Furthermore, faster supercomputers are increasingly energy-hungry and unaffordable to run. In this thesis, a new means of making computer simulations more efficient is presented that could lead to more accurate forecasts without increasing computational costs. This 'scale-selective reduced precision' technique builds on previous work that shows that weather models can be run with almost all real numbers represented in 32 bit precision or lower without any impact on forecast accuracy, challenging the paradigm that 64 bits of numerical precision are necessary for sufficiently accurate computations. The observational and model errors inherent in weather and climate simulations, combined with the sensitive dependence on initial conditions of the atmosphere and atmospheric models, renders such high precision unnecessary, especially at small scales. The 'scale-selective' technique introduced here therefore represents smaller, less influential scales of motion with less precision. Experiments are described in which reduced precision is emulated on conventional hardware and applied to three models of increasing complexity. In a three-scale extension of the Lorenz '96 toy model, it is demonstrated that high resolution scale-dependent precision forecasts are more accurate than low resolution high-precision forecasts of a similar computational cost. A spectral model based on the Surface Quasi-Geostrophic Equations is used to determine a power law describing how low precision can be safely reduced as a function of spatial scale; and experiments using four historical test-cases in an open-source version of the real-world Integrated Forecasting System demonstrate that a similar power law holds for the spectral part of this model. It is concluded that the scale-selective approach could be beneficially employed to optimally balance forecast cost and accuracy if utilised on real reduced precision hardware.
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Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
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Williams, Steve. "Advanced Hardware-in-the-Loop Testing Assures RF Communication System Success." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/604299.
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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, CaliforniaRF Communication (COMMS) systems where receivers and transmitters are in motion must be proven rigorously over an array of natural RF link perturbations such as Carrier Doppler shift, Signal Doppler shift, delay, path loss and noise. These perturbations play significant roles in COMMS systems involving satellites, aircraft, UAVs, missiles, targets and ground stations. In these applications, COMMS system devices must also be tested against increasingly sophisticated intentional and unintentional interference, which must result in negligible impact on quality of service. Field testing and use of traditional test and measurement equipment will need to be substantially augmented with physics-compliant channel emulation equipment that broadens the scope, depth and coverage of such tests, while decreasing R&D and test costs and driving in quality. This paper describes dynamic link emulation driven by advanced antenna and motion modeling, detailed propagation models and link budget methods for realistic, nominal and worst-case hardware-in-the-loop test and verification.
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Sedaghat, Maman Reza. "Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping /." [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.
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Ford, Gregory Fick. "Hardware Emulation of Sequential ATPG-Based Bounded Model Checking." Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.
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Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Doctoral thesis, Universitätsbibliothek Chemnitz, 2013. http://nbn-resolving.de/urn:nbn:de:bsz:ch1-qucosa-115411.
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Der vorliegende Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Optimierung von Hardware Emulatoren durch die Anwendung von Methoden der partiellen Laufzeitrekonfiguration. An aktuelle Schaltkreis- und Systementwürfe werden zunehmend divergente Anforderungen gestellt. Einer sehr kurzen Entwicklungszeit für eine schnelle Markteinführung steht, um teure und aufwändige Re-Desings zu verhindern, eine möglichst umfangreiche Testabdeckung des Entwurfs gegenüber. Um die Zeit für die Tests zu reduzieren, kommen überwiegend FPGA-basierte HW-Emulatoren zum Einsatz. Durch den Einfluss der steigenden Komplexität aktueller Entwürfe auf die Emulator-Plattform reduziert sich jedoch signifikant die Performance der Emulatoren. Die in Emulatoren eingesetzten FPGAs sind aber zunehmend partiell zur Laufzeit rekonfigurierbar. Der in der vorliegenden Arbeit umgesetzte Ansatz behandelt die Anwendung von Methoden der Laufzeitrekonfiguration auf dem Gebiet der Hardware-Emulation. Dafür ist zunächst eine Partitionierung des zu testenden Entwurfs in möglichst funktional unabhängige Systemteile notwendig. Für eine optimierte und ressourceneffiziente Platzierung der einzelnen HW-Module während der Emulation, ist ein ebenfalls auf dem FPGA platziertes Kommunikationsnetzwerk implementiert. Der vorgestellte Ansatz wird an verschiedenen Beispielen anschaulich illustriert. So kann der Leser die Mächtigkeit der entwickelten Methodik nachvollziehen und wird motiviert, das Verfahren auch auf weitere Anwendungsfälle zu übertragenCurrent circuit and system designs consist a lot of gate numbers and divergent requirements. In contrast to a short development and time to market schedule, the needs for perfect test coverage and quality are rising. One approach to cover this problem is the FPGA based functional test of electronic circuits. State of the art FPGA platforms doesn't consist enough gates to support fully custom designs. The thesis catches this problem and gives some approaches to use partial dynamic reconfiguration to solve the size problem. A fully automated design flow demonstrates partial partitioning of designs, modifications to use dynamic reconfiguration and its schedule. At the end of the work, some examples demonstrates the power of the approach
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Almeida, Filipe Afonso de. "Parallel software emulation of multi-processor dataflow machines on transputer networks." Thesis, University of Kent, 1992. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.315170.
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Wells, George James. "Hardware emulation and real-time simulation strategies for the concurrent development of microsatellite hardware and software." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ62899.pdf.
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Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." TUDpress, 2008. https://monarch.qucosa.de/id/qucosa%3A19914.
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Der vorliegende Band der wissenschaftlichen Schriftenreihe Eingebettete Selbstorganisierende Systeme widmet sich der Optimierung von Hardware Emulatoren durch die Anwendung von Methoden der partiellen Laufzeitrekonfiguration.
An aktuelle Schaltkreis- und Systementwürfe werden zunehmend divergente Anforderungen gestellt. Einer sehr kurzen Entwicklungszeit für eine schnelle Markteinführung steht, um teure und aufwändige Re-Desings zu verhindern, eine möglichst umfangreiche Testabdeckung des Entwurfs gegenüber. Um die Zeit für die Tests zu reduzieren, kommen überwiegend FPGA-basierte HW-Emulatoren zum Einsatz. Durch den Einfluss der steigenden Komplexität aktueller Entwürfe auf die Emulator-Plattform reduziert sich jedoch signifikant die Performance der Emulatoren.
Die in Emulatoren eingesetzten FPGAs sind aber zunehmend partiell zur Laufzeit rekonfigurierbar. Der in der vorliegenden Arbeit umgesetzte Ansatz behandelt die Anwendung von Methoden der Laufzeitrekonfiguration auf dem Gebiet der Hardware-Emulation.
Dafür ist zunächst eine Partitionierung des zu testenden Entwurfs in möglichst funktional unabhängige Systemteile notwendig. Für eine optimierte und ressourceneffiziente Platzierung der einzelnen HW-Module während der Emulation, ist ein ebenfalls auf dem FPGA platziertes Kommunikationsnetzwerk implementiert.
Der vorgestellte Ansatz wird an verschiedenen Beispielen anschaulich illustriert. So kann der Leser die Mächtigkeit der entwickelten Methodik nachvollziehen und wird motiviert, das Verfahren auch auf weitere Anwendungsfälle zu übertragen.Current circuit and system designs consist a lot of gate numbers and divergent requirements. In contrast to a short development and time to market schedule, the needs for perfect test coverage and quality are rising. One approach to cover this problem is the FPGA based functional test of electronic circuits. State of the art FPGA platforms doesn't consist enough gates to support fully custom designs. The thesis catches this problem and gives some approaches to use partial dynamic reconfiguration to solve the size problem. A fully automated design flow demonstrates partial partitioning of designs, modifications to use dynamic reconfiguration and its schedule. At the end of the work, some examples demonstrates the power of the approach.
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Päivänsäde, V. (Ville). "Dynamic power estimation with a hardware emulation acquired switching activity model." Master's thesis, University of Oulu, 2016. http://urn.fi/URN:NBN:fi:oulu-201609082736.
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This thesis is a study of dynamic power estimation at register-transfer level using an activity model acquired with a hardware emulator. The thesis consists of a practical part that presents the studied flow and the testing work related to it and a theory part that supports the topics of the practical part. In the theory part, the common sources of power consumption in complementary metal-oxide-semiconductor logic are studied, along with brief introductions about their reduction techniques. The electronic design automation tool methodologies, commonly used for power estimation and analysis, are discussed as well. In the practical part, a dynamic power estimation electronic design automation tool flow is presented. The flow estimates a floorplan model of the design from a register-transfer level hardware description with fast synthesis and acquires a simulative activity model with a hardware emulator. The studied power estimation tool was the Joules RTL Power Solution and the hardware emulation system was the Palladium XP II Verification Computing Platform, both by Cadence Design Systems. The overall quality of the flow was analyzed with a test vehicle hardware description as a design model, three different test cases as activity models and an existing gate-level dynamic power analysis flow as a reference model. The variation between the studied register-transfer level flow and the gate-level reference flow was 4,4 % on average in the three test cases. The run time for the full estimation flow, with the fast synthesis step and single frame average computation, was slightly over an hour, while an incremental run without the synthesis step executed in about 15 minutesTässä työssä tutkitaan dynaamista tehonkulutuksen estimointia rekisterinsiirtotasolla laitteistoemuloinnilla tuotetulla aktiivisuusmallilla. Työ koostuu käytännön osuudesta, jossa esitellään tutkittua vuota ja siihen liittyvää testaustyötä, ja teoriaosuudesta, jonka tarkoitus on tukea käytännön osuudessa käsiteltyjä aiheita. Teoriaosuudessa käsitellään CMOS-logiikkaan perustuvien mikropiiritekniikoiden yleisimpiä tehonkulutusmekanismeja ja lyhyesti niiden vähennystekniikoita. Lisäksi osiossa käsitellään elektroniikan suunnittelun automaatiotyökalujen yleisimpiä tehonkulutuksen estimointi- ja analyysimetodologioita. Käytännön osuudessa esitellään yhden elektroniikan automaatiotyökalun dynaaminen tehonkulutuksen estimointivuo. Vuossa suunnitelman pohjapiirros estimoidaan rekisterinsiirtotason laitteistokuvauskielisestä mallista nopean synteesin avulla ja aktiivisuusmalli tuotetaan laitteistoemuloinnilla. Tutkittu tehonkulutuksen estimointityökalu oli Joules RTL Power Solution ja laitteistoemulointijärjestelmä oli Palladium XP II Verification Computing Platform, molemmat Cadence Design Systemssiltä. Vuon lopullinen laadukkuus arvioitiin käyttäen laitteistokuvauskielistä testisuunnitelmamallia, kolmea erilaista testitapausta aktiivisuusmalleina ja olemassaolevaa porttitason dynaamista tehonkulutuksen analyysivuota referenssimallina. Esitellyn rekisterinsiirtotason vuon ja porttitason referenssivuon välinen ero oli keskimäärin 4,4 % kolmessa tutkitussa testitapauksessa. Täyden keskiarvoistetun estimointivuon ajoaika oli hieman yli tunnin, kun taas inkrementaalinen ajo ilman nopeaa synteesiä kesti noin 15 minuuttia
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Driscoll, Scott Crawford. "The Design and Qualification of a Hydraulic Hardware-in-the-Loop Simulator." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7132.
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The goal of this work was to design and evaluate a hydraulic Hardware-in-the-Loop (HIL) simulation system based around electric and hydraulic motors. The idea behind HIL simulation is to install real hardware within a physically emulated environment, so that genuine performance can be assessed without the expense of final assembly testing. In this case, coupled electric and hydraulic motors were used to create the physical environment emulation by imparting flows and pressures on test hardware. Typically, servo-valves are used for this type of hydraulic emulation, and one of the main purposes of this work was to compare the effectiveness of using motors instead of the somewhat standard servo-valve. Towards this end, a case study involving a Sauer Danfoss proportional valve and emulation of a John Deere backhoe cylinder was undertaken. The design of speed and pressure controllers used in this emulation is presented, and results are compared to data from a real John Deere backhoe and proportional valve. While motors have a substantially lower bandwidth than servo-valves due to their inertia, they have the ability to control pressure at zero and near-zero flows, which is fundamentally impossible for valves. The limitations and unique capabilities of motors are discussed with respect to characteristics of real hydraulic systems.
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Hanono, Silvina Zimi. "InnerView hardware debugger : a logic analysis tool for the Virtual Wires emulation system." Thesis, Massachusetts Institute of Technology, 1995. http://hdl.handle.net/1721.1/11855.
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Marko, Vekić. "Нови поступак за развој управљачких склопова енергетске електронике заснован на емулацији у стварном времену." Phd thesis, Univerzitet u Novom Sadu, Fakultet tehničkih nauka u Novom Sadu, 2014. http://dx.doi.org/10.2298/NS20131223VEKIC.
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У тези je предложен поступак развоја управљачких склопова енергетскеелектронике заснован на технологији Hardware In the Loop. Подробно јеописан предложени емулатор са нагласком на специфичноммоделовању погодном за извршење у стварном времену што јепредуслов веродостојности. Сама веродостојност је проверенапоређењем резултата са симулацијом, као и са измереним резултатимау неколико стварних погона. Затим је поступак развоја управљачкихсклопова подробно објашњен на примеру развоја и испитивања једногновог контролног алгоритма за повезивање синхроног генератора наелектричну мрежу.U tezi je predložen postupak razvoja upravljačkih sklopova energetskeelektronike zasnovan na tehnologiji Hardware In the Loop. Podrobno jeopisan predloženi emulator sa naglaskom na specifičnommodelovanju pogodnom za izvršenje u stvarnom vremenu što jepreduslov verodostojnosti. Sama verodostojnost je proverenapoređenjem rezultata sa simulacijom, kao i sa izmerenim rezultatimau nekoliko stvarnih pogona. Zatim je postupak razvoja upravljačkihsklopova podrobno objašnjen na primeru razvoja i ispitivanja jednognovog kontrolnog algoritma za povezivanje sinhronog generatora naelektričnu mrežu.
This paper proposes development of Power Electronics controllers based onthe Hardware In the Loop technology. Proposed emulator is describied indetail where emphasis was set on specific methods of modeling which issuitable for real time emulations in order to obtain emulation faithfulness.Fidelity itself was checked through comparison with off-line simulations andresults of real drives. Procedure of controllers development was presentedthrough development and testing of one new control algorithm for connectionof the permanent magnet synchronous generator to the electrical grid.
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Noon, John Patrick. "Development of a Power Hardware-in-the-Loop Test Bench for Electric Machine and Drive Emulation." Thesis, Virginia Tech, 2020. http://hdl.handle.net/10919/101498.
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This work demonstrates the capability of a power electronic based power hardware-inthe-
loop (PHIL) platform to emulate electric machines for the purpose of a motor drive
testbench with a particular focus on induction machine emulation. PHIL presents advantages
over full-hardware testing of motor drives as the PHIL platform can save space and
cost that comes from the physical construction of multiple electric machine test configurations.
This thesis presents real-time models that were developed for the purpose of PHIL
emulation. Additionally, real-time modeling considerations are presented as well as the modeling
considerations that stem from implementing the model in a PHIL testbench. Next, the
design and implementation of the PHIL testbench is detailed. This thesis describes the
design of the interface inductor between the motor drive and the emulation platform. Additionally,
practical implementation challenges such as common mode and ground loop noise
are discussed and solutions are presented. Finally, experimental validation of the modeling
and emulation of the induction machine is presented and the performance of the machine
emulation testbench is discussed.Master of Science
According to the International Energy Agency (IEA), electric power usage is increasing across all sectors, and particularly in the transportation sector [1]. This increase is apparent in one's daily life through the increase of electric vehicles on the road. Power electronics convert electricity in one form to electricity in another form. This conversion of power is playing an increasingly important role in society because examples of this conversion include converting the dc voltage of a battery to ac voltage in an electric car or the conversion of the ac power grid to dc to power a laptop. Additionally, even within an electric car, power converters transform the battery's electric power from a higher dc voltage into lower voltage dc power to supply the entertainment system and into ac power to drive the car's motor. The electrification of the transportation sector is leading to an increase in the amount of electric energy that is being consumed and processed through power electronics. As was illustrated in the previous examples of electric cars, the application of power electronics is very wide and thus requires different testbenches for the many different applications. While some industries are used to power electronics and testing converters, transportation electrification is increasing the number of companies and industries that are using power electronics and electric machines. As industry is shifting towards these new technologies, it is a prime opportunity to change the way that high power testing is done for electric machines and power converters. Traditional testing methods are potentially dangerous and lack the flexibility that is required to test a wide variety of machines and drives. Power hardware-in-the-loop (PHIL) testing presents a safe and adaptable solution to high power testing of electric machines. Traditionally, electric machines were primarily used in heavy industry such as milling, processing, and pumping applications. These applications, and other applications such as an electric motor in a car or plane are called motor drive systems. Regardless of the particular application of the motor drive system, there are generally three parts: a dc source, an inverter, and the electric machine. In most applications, other than cars which have a dc battery, the dc source is a power electronic converter called a rectifier which converts ac electricity from the grid to dc for the motor drive. Next, the motor drive converts the dc electricity from the first stage to a controlled ac output to drive the electric machine. Finally, the electric machine itself is the final piece of the electrical system and converts the electrical energy to mechanical energy which can drive a fan, belt, or axle. The fact that this motor drive system can be generalized and applied to a wide range of applications makes its study particularly interesting. PHIL simplifies testing of these motor drive systems by allowing the inverter to connect directly to a machine emulator which is able to replicate a variety of loads. Furthermore, this work demonstrates the capability of PHIL to emulate both the induction machine load as well as the dc source by considering several rectifier topologies without any significant adjustments from the machine emulation platform. This thesis demonstrates the capabilities of the EGSTON Power Electronics GmbH COMPISO System Unit to emulate motor drive systems to allow for safer, more flexible motor drive system testing. The main goal of this thesis is to demonstrate an accurate PHIL emulation of a induction machine and to provide validation of the emulation results through comparison with an induction machine.
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Schmitt, Alexander [Verfasser]. "Hochdynamische Power Hardware-in-the-Loop Emulation hoch ausgenutzter Synchronmaschinen mit einem Modularen-Multiphasen-Multilevel Umrichter / Alexander Schmitt." Karlsruhe : KIT Scientific Publishing, 2017. http://www.ksp.kit.edu.
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Serdar, Usenmez. "Design Of An Integrated Hardware-in-the-loop Simulation System." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/2/12612051/index.pdf.
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This thesis aims to propose multiple methods for performing a hardware-in-the-loop simulation, providing the hardware and software tools necessary for design and execution. For this purpose, methods of modeling commonly encountered dynamical system components are explored and techniques suitable for calculating the states of the modeled system are presented. Modules and subsystems that enable the realization of a hardware-in-the-loop simulation application and its interfacing with external controller hardware are explained. The thesis also presents three different simulation scenarios. Solutions suitable for these scenarios are provided along with their implementations. The details and specifications of the developed software packages and hardware platforms are given. The provided results illustrate the advantages and disadvantages of the approaches used in these solutions.
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Levrini, Giacomo. "Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020. http://amslaurea.unibo.it/22105/.
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In the next 10 years, a radical upgrade is expected for the Large Hadron Collider focused in achieving the highest values in the instantaneous and integrated luminosity. Both the subdetectrors of the experiments and their data acquisition systems will need an
upgrade.
For the Phase-II upgrade of the Trigger and Data Acquisition System (TDAQ) of the ATLAS experiment a common platform has been created to share the common firmware, software and tools that are ongoing and that will come in the next years
within the ATLAS TDAQ collaboration. The environment includes a set of design procedures, a virtual machine as repository for the firmware and some automatic tools for the continuous integration and versioning. The platform is under testing, as the firmware will be tested on the TDAQ upgraded, it will also be used for the prototype cards that will be produced as demonstrator for the ATLAS Hardware Tracking for the Trigger (HTT) system. For the HTT project a physical environment is being prepared, exploiting Peripheral Component Interconnect express (PCIe)
and ACTA crates. My personal work has been the design of a part of track-fitting algorithms, in particular the one using the Hough Transform. This implementation has been required by the ATLAS experiment as an alternative solution to the baseline proposal accepted and described in the TDAQ Upgrade Technical Design Report (TDR). I have developed and tested a set of pattern vectors used not only in the simulation and validation of the algorithm, but also in the hadware integration on a FPGA based hardware accelerator. The used technology is based on high-performance Xilinx Ultrascale+ FPGA, implemented on VCU1525 board. This work is going to be validated by the ATLAS collaboration very soon, so to understand how we can proceed in the future upgrade. Bologna is the only Italian institute which participates in the integration of a tracking algorithm in the ATLAS trigger upgrade, using high performance FPGA-based hardware.
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Varais, Andy. "Modèles à échelle réduite en similitude pour l'ingénierie système et l'expérimentation simulée "temps compacté" : application à un microréseau incluant un stockage électrochimique." Thesis, Toulouse, INPT, 2019. http://www.theses.fr/2019INPT0007/document.
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Cette thèse a été réalisée en collaboration avec la société SCLE SFE (Groupe ENGIE) et le laboratoire Laplace. Elle porte sur le développement d’une méthodologie permettant d’élaborer des modèles dits « en similitude », à échelle de puissance et de temps réduites. Ces modèles peuvent servir pour l’analyse des systèmes mais ils sont en particulier utiles pour l’expérimentation en temps réel des systèmes énergétiques. En effet, les expérimentations sont très souvent menées à échelle réduite pour des questions de taille, de coût,… Certaines parties de ces expérimentations peuvent être « émulées » (simulées physiquement par des dispositifs de puissance) d’autres étant constitués de composants physiques : on parle alors de procédure Hardware in the Loop (HIL). Même si, à la base, la démarche de réduction d’échelle a une portée générale, notre gamme d’application principale concerne les micro réseaux avec intégration de sources renouvelables intermittentes couplées à des composants de stockage. En conséquence,nos travaux se focalisent sur la mise en œuvre de modèles de similitudes en puissance/énergie/temps de sources ENR et de stockeurs. La notion de réduction de temps, nous parlerons de « temps virtuel compacté », est un des concepts clés de ces travaux. Une attention particulière est portée sur le développement d’un émulateur physique de batterie électrochimique.En effet, le stockage d’énergie est un point clé dans un micro réseau. De plus, cet élément présente de fortes non-linéarités dont la mise en similitude doit impérativement tenir compte et n’est pas triviale. Une fois ces modèles développés, on les éprouve via la mise en œuvre d’essais en expérimentation simulée par émulateurs physiques à échelle de puissance réduite et en temps virtuel compacté. Ces essais permettent par ailleurs de confronter les notions d’émulateurs «copie-modèle », pour lequel un modèle est utilisé pour reproduire le comportement du système, et d’émulateurs « copie-image », où le comportement du système est reproduit à partir d’un de ses composants réels (par exemple une cellule pour la batterie)This thesis was carried out in collaboration with SCLE SFE (ENGIE Group) and the Laplacelaboratory. It focuses on the establishment of a methodology allowing the “similarity” modelsdevelopment, with reduced power and time scale. These models can be used for systems analysisbut they are particularly useful for real-time experimentation of energy systems. Indeed, theexperiments are often carried out on a small scale for issues of size, cost, … Some parts of theseexperiments can be "emulated" (physically simulated by power devices) while others consist ofphysical components: this is called the Hardware in the Loop (HIL) procedure. Although, initially,the downscaling approach is broad in scope, our main field of application is microgrids withintegration of intermittent renewable sources coupled with storage components. As a result, ourwork focuses on the implementation of power / energy / time similarity models of ENR sources andstorage facilities. The concept of time reduction, we will talk about "compacted virtual time", is oneof the key concepts of this work. Particular attention is paid to the development of a physicalemulator of electrochemical battery. Indeed, energy storage is a key point in microgrid. In addition,this element has strong nonlinearities whose scaling in similarity must imperatively take intoaccount and is not trivial. Once these models have been developed, they are tested through theimplementation of simulated experiments using physical emulators with reduced power scale andcompacted virtual time. These tests also make it possible to compare the concepts of "copymodel" emulators, for which a model is used to reproduce the behavior of the system, and "copyimage" emulators, where the behavior of the system is reproduced from of one of its realcomponents (for example a cell for the battery)
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MONTEIRO, Heron Aragão. "Emulação de circuitos quânticos em Placa FPGA." Universidade Federal de Campina Grande, 2012. http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/1368.
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Com o avanço da nanotecnologia, a computação quântica tem recebido grande destaque no meio científico. Utilizando os fundamentos da mecânica quântica, têm sido propostos diversos algoritmos quânticos. E, até então, os mesmos têm apresentado ganhos significativos com relação às suas versões clássicas. Na intenção de poder ser verificada a eficiência dos algoritmos quânticos, diversos simuladores vêm sendo desenvolvidos, visto que a confecção de um computador quântico ainda não foi possível. Há duas grandes vertentes de simuladores: os simuladores por software e os simuladores por hardware, chamados de emuladores. Na primeira classe se encontram os programas desenvolvidos em um computador clássico, procurando implementar os fundamentos da mecânica quântica, fazendo uso das linguagens de programação clássicas. Na segunda, são utilizados recursos que não estejam vinculados à plataforma do computador clássico. Dentre os emuladores, particularmente, estudos têm sido realizados fazendo uso de hardware dedicado (mais especificamente, FPGAV). O presente trabalho propõem a verificação da real utilidade da plataforma FPGA, com a intenção de se desenvolver um emulador universal, que permita a emulação de qualquer classe de circuitos, e que os mesmos possam ser implementados com um maior número de q-bits em relação aos circuitos tratados nos trabalhos anteriores.
With the progress of nanotechnology, quantum computing has received great emphasis in scientific circles. Using the basis of quantum mechanics, different quantum algorithms have been proposed. And so far, they have presented significant gains with respect to its classic versions. In order to verify the efficiency of quantum algorithms, several simulators have been developed, since the construction of a quantum computer is not yet possible. There are two major classes of simulators, simulators via software and via hardware. The latter being also called emulators. In the first class, programs are developed in a classical computer, attempting to implement the fundamentais of quantum mechanics, making use of classic programming languages. In the second, resources are used that are not related to the classic computer platform. Among the emulators, in particular, studies have been made using dedicated hardware (more specifically, FPGA's2). The present work proposes the use of the FPGA boards in emulation of quantum circuits aiming a gain scale in relation to the alternatives presented so far. The present work proposes checking the usefulness of the FPGA with the intention of developing an universal emulator that is able to emulate any type of circuit, and that they can be implemented with a larger number of q-bit in respect to the circuits treated in the previous works.
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Beckert, René [Verfasser], Wolfram [Gutachter] Hardt, Ulrich [Gutachter] Heinkel, Christophe [Gutachter] Bobda, Wolfram [Akademischer Betreuer] Hardt, and Ulrich [Akademischer Betreuer] Heinkel. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration / René Beckert ; Gutachter: Wolfram Hardt, Ulrich Heinkel, Christophe Bobda ; Wolfram Hardt, Ulrich Heinkel." Dresden : TUDpress, 2013. http://d-nb.info/1214245722/34.
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Mehrnoosh, Behzad. "Comparing Analog and Digital Non-Linear Sonic Signatures : an Investigation on Creative Application and Subjective Perception using the Universal Audio 1176 FET Compressor." Thesis, Luleå tekniska universitet, Institutionen för ekonomi, teknik, konst och samhälle, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-84598.
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Historically, compression was primarily used as a preventative measure to reduce the risk of clipping or overloading equipment in the recording signal chain. Research on the topic has revealed that modern production applications more commonly include utilizing compression as a creative effect, to impart distortion, manipulate timbre, and modify transients, rather than to control the dynamic range of audio signals. It has also been found that specific compressors are regularly chosen for the sonic signatures that they impart onto audio material. To evaluate the quality of a digitally modeled emulation plugin of a classic compressor, an analog and digital version of the Universal Audio 1176 FET compressor was tested in this study. 20 experienced listeners participated in a MUSHRA-style listening test during which processed sounds were rated based on four attributes. The result of the listening test verifies previous findings on the sonic signature of the 1176, and evidence presented suggests that the plugin can be used for the same creative purposes as the analog device. However, it was also found that intuitive methods could not be used when trying to match the processing of the hardware. Instead, critical listening and user experience seem to be important factors when trying to achieve the same creative effects when using the software plugin.
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Santos, Vitor Alexandre. "Caso de estudo de sistema de emulação em hardware para aplicação com controlador lógico programável." Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/2720.
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Este trabalho consiste em um caso de estudo de um emulador de planta industrial implementado em FPGA (Field Programmable Gate Array), a fim de simulação de sistemas em conjunto com um CLP (Controlador Lógico Programável). Com isso, fundamentado na indústria de manufatura, são confrontados resultados práticos de um protótipo de processo industrial com os resultados de um modelo aplicado em FPGA. Dessa maneira, tem-se como objetivo o auxílio em testes em níveis de validação de aplicação em desenvolvimento, aproximação de condições de chão de fábrica, otimização de controle de processo e treinamento em automação industrial baseada em CLP. Como proposta para os modelos, a pesquisa utiliza características de um sistema em malha fechada de controle de velocidade de esteira e a partir desse, um processo de sistema discreto, o qual utiliza como base um processo manufatureiro. Inicialmente a revisão bibliográfica apresenta trabalhos em torno de simulação de sistemas e emuladores baseados em hardware reconfigurável. Também são revisados temas relacionados à indústria de manufatura com a aplicação do CLP, assim como a técnica de modelagem GRAFCET. Em seguida, são apresentadas questões referentes à lógica reconfigurável em torno dos dispositivos FPGA. Na sequência da explanação do tema, é realizada a descrição dos protótipos utilizados, assim como os modelos desenvolvidos em FPGA para o emulador, e assim a realização das comparações dos dados. Com a apresentação dos resultados é possível a verificação da semelhança entre os dois sistemas, físico e modelado na FPGA. As pequenas diferenças detectadas nos resultados obtidos, em alguns pontos da simulação, são discutidas no final do trabalho.This work is a case study of an industrial plant emulator implemented in FPGA (Field Programmable Gate Array), to simulate systems together with a PLC (Programmable Logic Controller). Based in manufacturing industry, practical results of an industrial process prototype are confronted with the results of an applied model in FPGA. The objective is to assist in testing application validation levels in development, approximation of factory floor conditions, optimization of control process and training in industrial automation based on PLC. As a proposal for the models, the research use characteristics of a closed loop speed control system and from this, a discrete system process, which uses as a basis a manufacturing process. Initially the bibliographic review presents works around simulation of systems and emulators based on reconfigurable hardware. Also are reviewed topics related to the manufacturing industry with the application of PLC, beside the GRAFCET modeling technique. Next, questions will set out questions about reconfigurable logic around FPGA devices. Following the explanation of the theme, we describe the used prototypes and the developed models developed in FPGA for the emulator. Finally the obtained data are compared. With the presentation of the results is possible to verify the similarity between the two systems, physical and modeling in the FPGA. The small differences detected in the results obtained, in some points of the simulation, are discussed at the end of the work.
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Souza, Igor Dias Neto de. "Controle digital com malha dupla de tensão aplicado a um conversor formador de rede." Universidade Federal de Juiz de Fora (UFJF), 2017. https://repositorio.ufjf.br/jspui/handle/ufjf/4083.
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Esta dissertação apresenta um estudo de um conversor emulador de rede (CER) que faz parte de uma estrutura Power-Hardware-in-the-Loop (PHIL). O PHIL será futuramente utilizado para verificar os impactos causados pela integração de sistemas de geração fotovoltaico (PV) à rede elétrica, assim como a operação do sistema PV frente a distúrbios na rede. O CER, composto por um conversor fonte de tensão (VSC) de dois níveis e filtro de saída LC, é responsável por alimentar cargas isoladas emulando uma rede elétrica. A modelagem do conversor emulador de rede é feita no sistema de coordenadas estacionário (αβ0), fornecendo um sistema de equações diferenciais usado para descrever o comportamento dinâmico do sistema. O conversor é controlado no modo de tensão, através da estratégia de modulação vetorial. Duas malhas de controle em cascata são projetadas. A malha interna utiliza compensadores em avanço digitais para amortecer a ressonância do filtro LC sem a necessidade de uma realimentação interna de corrente. Já a externa utiliza controladores ressonantes digitais modificados para rejeitar distúrbios harmônicos e garantir a qualidade da forma de onda da tensão no ponto de acoplamento comum. Os controladores ressonantes são conectados em série e o projeto é baseado no amortecimento dos zeros. Resultados experimentais, obtidos com o protótipo de laboratório, cujos controladores foram implementados em um processador digital de sinais TMS320F28335 da Texas Instruments, são usados para validar as estratégias de controle propostas.
This dissertation presents a study on a grid-former converter (GFC) which is a part of a Power-Hardware-in-the-Loop (PHIL) structure. The PHIL will be used to verify the impacts caused by the integration of photovoltaic (PV) generation systems into grid, as well as to study the PV operation under grid disturbances. The GFC, composed by a two-level voltage source converter with a LC output filter, is responsible to feed isolated loads emulating an electrical grid. The modeling of the grid-former converter is done in the stationary frame (αβ0), providing a set of differential equations that describes the dynamical behavior of the system. The converter is controlled in voltage mode by means of the space vector modulation (SVM) strategy. Two control loops are designed to control the static converter. At the inner loop a novel discrete-time active damping technique is proposed in order to damp the filter resonance without the need of current feedback. The method is based on an inner feedback loop with digital lead compensator on the feedback path while the external loop uses a discretetime integrator and a modified digital resonant controller to guarantee a decreasing frequency response and ensure the quality of the voltage waveform at the point of common coupling, respectively. The resonant controllers are connected in series and the design is based on its zeros damping. Experimental results obtained with the prototype, which controllers were implemented in a Texas Instruments TMS320F28335 are used to validate the proposed control strategies.
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Guimarães, Marcelo Alves. "Transporte TDM em redes GPON." Universidade de São Paulo, 2011. http://www.teses.usp.br/teses/disponiveis/18/18155/tde-07042011-152547/.
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Neste trabalho analisamos e propomos a utilização de TDM (Time Division Multiplexing) nativo canalizado/estruturado em redes PON (Passive Optical Network) com padrão GPON (Gigabit Passive Optical Network), com ênfase na estrutura de transmissão do legado das redes de telefonia. O objetivo principal é obter um aumento na eficiência de banda transmitida através da fragmentação de sinais E1 sem que seja necessário o uso de técnicas de emulação de circuito (que reduzem a eficiência de banda devido à adição de cabeçalhos). Inicialmente, é descrito o transporte TDM em redes GPON, como efetuado pelos equipamentos comerciais atuais através de duas técnicas: CES - Circuit Emulation Service e TDM nativo não estruturado. Em seguida, é introduzido o conceito de comutação digital visando sua aplicação no transporte TDM nativo estruturado em redes GPON. Nesta etapa, é proposta uma solução para este transporte, é descrito o protocolo utilizado bem como seu funcionamento. Por fim, como prova de conceito, é apresentada uma implementação em HDL (Hardware Description Language) para FPGA (Field Programmable Gate Array).In this work we analyze and propose the use of native channeled /structured TDM (Time Division Multiplexing) in GPON (Gigabit Passive Optical Network), with emphasis on the structure for transmission of the telephone network legacy. The main target is to achieve an increase in transmitted bandwidth efficiency by fragmenting E1 signals, thus avoiding the use of circuit emulation techniques (which reduce the bandwidth efficiency due to overhead addition). Initially, it is described in TDM transport in GPON networks, as it is performed in present commercial equipment by two techniques: CES - Circuit Emulation Service and Native TDM - unstructured. Next, we introduce the concepts of digital switching aiming its application on the transport of native and structured TDM in GPON. At this stage, we propose a transport solution, describe its protocol and functionalities. Finally, for concept proof, we present an implementation in HDL (Hardware Description Language) meant to FPGA (Field Programmable Gate Array) application.
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BOUKADIDA, Yassine. "The i-motor: a system for end-of-line testing of electric drives for vehicles." Doctoral thesis, Università degli studi di Cassino, 2021. http://hdl.handle.net/11580/83957.
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This work is developed within a current trend aimed at time simulation-based testing systems, especially those dedicated to complex process where different sub-processes interact with different dynamics. The Hardware in the loop (HIL) is currently considered as a viable candidate to fulfill the requirements of real time simulation for the testing of complex systems. Within this trend, a HIL simulation system dedicated to the testing of a variable speed traction drive is developed. It incorporates a power system made up of two DC-AC converters connected through their AC sides by a three phase inductor, and a control system built around a NI PXI interface in which is embedded a real-time simulation HIL system. The implemented control scheme considers a current-regulated voltage source inverter fed permanent magnet synchronous motor under a vector control strategy. The analysis the test results obtained considering the emulation of different accelerating and braking cycles, have clearly proven the potentialities of the developed system.
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Li, Ming-You, and 李明祐. "Hardware Implementation of Analog Emulator Based on Wave Digital Filters." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/46414417801929081152.
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碩士國立中央大學
電機工程學系
105
Modern System-on-Chip (SOC) designs usually contain analog and digital circuits. However, it is difficult to simulate them together because the design and verification processes are quite different for analog and digital circuits in traditional design flow. In order to provide a rapid and reliable verification method, we adopt Wave Digital Filter (WDF) theory to map resistors, capacitors, inductors and voltage source to wave domain one-by-one and connect them with serial or parallel adaptors. By this way, analog circuits can be transformed to digital circuits and verified in digital environment together. In this thesis, we focus on studying how to implement the WDF structures on FPGA. With the built-in IEEE 754 floating point circuits in the FPGA software, we can implement all computation elements of WDF rapidly. According to the emulation results, it demonstrates that the WDF theory is possible to be implemented with real hardware, and its behavior is consistent with the simulation results of HSPICE.
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"Digital implementation of an upstream DOCSIS QAM modulator and channel emulator." Thesis, 2014. http://hdl.handle.net/10388/ETD-2015-06-1783.
Full textAbstract:
The concept of cable television, originally called community antenna television (CATV), began in the 1940's. The information and services provided by cable operators have changed drastically since the early days. Cable service providers are no longer simply providing their customers with broadcast television but are providing a multi-purpose, two-way link to the digital world. Custom programming, telephone service, radio, and high-speed internet access are just a few of the services offered by cable service providers in the 21st century.
At the dawn of the internet the dominant mode of access was through telephone lines. Despite advances in dial-up modem technology, the telephone system was unable to keep pace with the demand for data throughput. In the late 1990's an industry consortium known as Cable Television Laboratories, Inc. developed a standard protocol for providing high-speed internet access through the existing CATV infrastructure. This protocol is known as Data Over Cable Service Interface Specification (DOCSIS) and it helped to usher in the era of the information superhighway.
CATV systems use different parts of the radio frequency (RF) spectrum for communication to and from the user. The downstream portion (data destined for the user) consumes the bulk of the spectrum and is located at relatively high frequencies. The upstream portion (data destined to the network from the user) of the spectrum is smaller and located at the low end of the spectrum. This lower frequency region of the RF spectrum is particularly prone to impairments such as micro-reflections, which can be viewed as a type of multipath interference. Upstream data transfer in the presence of these impairments is therefore problematic and requires complex signal correction algorithms to be employed in the receiver.
The quality of a receiver is largely determined by how well it mitigates the signal impairments introduced by the channel. For this reason, engineers developing a receiver require a piece of equipment that can emulate the channel impairments in any permutation in order to test their receiver. The conventional test methodology uses a hardware RF channel emulator connected between the transmitter and the receiver under test. This method not only requires an expensive RF channel emulator, but a functioning analog front-end as well. Of these two problems, the expense of the hardware emulator is likely less important than the delay in development caused by waiting for a functional analog front-end. Receiver design is an iterative, time consuming process that requires the receiver's digital signal processing (DSP) algorithms be tested as early as possible to reduce the time-to-market.
This thesis presents a digital implementation of a DOCSIS-compliant channel emulator whereby cable micro-reflections and thermal noise at the analog front-end of the receiver are modelled digitally at baseband. The channel emulator and the modulator are integrated into a single hardware structure to produce a compact circuit that, during receiver testing, resides inside the same field programmable gate array (FPGA) as the receiver. This approach removes the dependence on the analog front-end allowing it to be developed concurrently with the receiver's DSP circuits, thus reducing the time-to-market.
The approach taken in this thesis produces a fully programmable channel emulator that can be loaded onto FPGAs as needed by engineers working independently on different receiver designs. The channel emulator uses 3 independent data streams to produce a 3-channel signal, whereby a main channel with micro-reflections is flanked on either side by adjacent channels. Thermal noise normally generated by the receiver's analog front-end is emulated and injected into the signal. The resulting structure utilizes 43 dedicated multipliers and 401.125 KB of RAM, and achieves a modulation error ratio (MER) of 55.29 dB.
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Πρίσκας, Θεόδωρος. "Σχεδίαση ενός 8-bit μικροεπεξεργαστή (του μP 8085) σε VHDL και υλοποίηση σε FPGAs." Thesis, 2012. http://hdl.handle.net/10889/5575.
Full textAbstract:
Ο σκοπός της παρούσας Διπλωματικής Εργασίας είναι η μελέτη και η υλοποίηση ενός 8085 προσομοιωτή σε FPGAs με τη χρήση VHDL.
H υλοποίηση έγινε με την βοήθεια του περιβάλλοντος εξομοίωσης του Quartus v7.2 της ALTERA, με την χρήση της γλώσσας VHDL [8],[10].Η εργασία αυτή χωρίζεται σε 12 κεφάλαια:
Στο πρώτο κεφάλαιο γίνεται αναφορά στο μικροεπεξεργαστή και στα τεχνικά του γνωρίσματα [1], [2], [4].
Στο δεύτερο κεφάλαιο γίνεται μια εκτενής αναφορά στη γλώσσα VHDL [3], [10].
Στο τρίτο κεφάλαιο παρουσιάζεται η αναπτυξιακή πλατφόρμα DE2 της εταιρίας ALTERA. Παρουσιάζονται αναλυτικά οι δυνατότητες και τα σχεδιαστικά χαρακτηριστικά της αναπτυξιακής κάρτας DE2 της ALTERA καθώς και τεχνική απεικόνισης video με τη χρήση FPGA [3], [9], [14].
Στο τέταρτο κεφάλαιο αναλύεται η λειτουργία του πρώτου μεγάλου τμήματος του μικροεπεξεργαστή, της ALU. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [6], [12], [13].
Στο πέμπτο κεφάλαιο αναλύεται η λειτουργία του register file. Πρόκειται για το τμήμα των καταχωρητών, το οποίο είναι υπεύθυνο για την μεταφορά δεδομένων και την λειτουργία των διαύλων διευθύνσεων. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [11], [13], [14].
Στο έκτο κεφάλαιο αναλύεται η λειτουργία του τμήματος ελέγχου διακοπών. Πρόκειται για το τμήμα το οποίο εξυπηρετεί οποιαδήποτε αίτηση για διακοπή και το οποίο έχει οριστεί να είναι υπεύθυνο και για την σειριακή επικοινωνία. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [1], [12], [13].
Στο έβδομο κεφάλαιο γίνεται μια πρώτη απόπειρα σύνδεσης των τριών πρώτων μεγάλων τμημάτων του μικροεπεξεργαστή [12], [13].
Στο όγδοο κεφάλαιο αναλύεται η λειτουργία της control unit ως μονάδα ελέγχου και διαχείρισης των σημάτων ελέγχου του όλου κυκλώματος του μικροεπεξεργαστή. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του κυκλώματος, η λειτουργία κάθε επιμέρους τμήματος καθώς και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [5], [7], [12], [13].
Στο ένατο κεφάλαιο παρουσιάζεται το κύκλωμα του μικροεπεξεργαστή μέσα από την σύνδεση των επιμέρους τμημάτων του. Παρουσιάζεται η αρχιτεκτονική υλοποίησης του και ο αναλυτικός κώδικας εξομοίωσης του. Η πιστοποίηση της ορθής λειτουργίας του κυκλώματος γίνεται με την βοήθεια του waveform editor του προγράμματος [7], [12], [13].
Στο δέκατο κεφάλαιο παρουσιάζεται ο μικροπρογραμματισμός της microprogram ROM της control unit. Αναλύεται διεξοδικά η λειτουργία των σημάτων ελέγχου των τμημάτων του μικροεπεξεργαστή για την εκτέλεση κάθε μιας εντολής του 8085 [7], [12], [13].
Στο ενδέκατο κεφάλαιο γίνεται εξομοίωση ορισμένων προγραμμάτων για τον έλεγχο της ορθής λειτουργίας των εντολών και των σημάτων ελέγχου και εξόδου του μικροεπεξεργαστή 8085 [1], [12], [13].
Στο δωδέκατο κεφάλαιο παρουσιάζεται η υλοποίηση του μικροεπεξεργαστή στην αναπτυξιακή πλατφόρμα DE2 της εταιρείας ALTERA [3], [14].
Τελειώνοντας θα ήθελα να ευχαριστήσω τον επιβλέποντα της προσπάθειας αυτής Αναπληρωτή Καθηγητή κ. Ευάγγελο Ζυγούρη, η καθοδήγηση του οποίου υπήρξε καθοριστική.The purpose of this thesis is the design of an 8085 emulator in FPGAs using VHDL. The implementation was done with the simulation environment of ALTERA Quartus v7.2, using VHDL. The project is divided into 12 chapters: The first chapter refers to the 8085 microprocessor and it’s technical features [1], [2], [4]. The second chapter is a detailed presentation of the VHDL language [3], [10]. The third chapter presents DE2 development board of Altera. Capabilities and design features of DE2 board are presented and vga video display generation using FPGAs is explained [3], [9], [14]. The fourth chapter analyzes the operation of the first large section of the microprocessor, ALU. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [6], [12], [13]. The fifth chapter presents the operation of the register file. Register File is responsible for data transfer and operation of the address bus. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [11], [13], [14]. The sixth chapter presents microprocessor 's interrupts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [1], [12], [13]. The seventh chapter is a first attempt to link the first three major sections of the microprocessor [12], [13]. The eighth chapter presents the operation of the control unit. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [5], [7], [12], [13]. The ninth chapter presents the circuit of the microprocessor through the connection of all individual parts. The architecture of the circuit, the function and the detailed code is presented. The verification of the circuit is done by using the Quartus waveform editor program [7], [12], [13]. The tenth chapter presents the microprogramming of microprogram ROM of the control unit. It analyzes in detail the operation of the control signals of the parts of the microprocessor to perform each of 8085 command [7], [12], [13]. The eleventh chapter presents the simulation of microprocessor through assembly programs written in RAM memory of 8085 microprocessor [1], [12], [13]. The twelfth chapter presents the implementation of microprocessor in FPGAs using DE2 development board of Altera [3], [14].
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Lee, Chao-Cheng, and 李朝丞. "Emulation-Based Open-Hardware Course Design." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/by735u.
Full textAbstract:
碩士國立臺灣師範大學
資訊教育研究所
107
This study developed task-specific software to emulate the behaviors of an open-hardware. Students could test-run their programs on the emulation software before transmit it into the hardware. The Quasi-experimental design was implemented and the participants were a class of 8th graders in a class with a total of 45 students. Among them, 23 students served as the experiment group using emulation in programming, whereas the other 22 students served as the control group without using emulation. The experiment lasted for five weeks with a total of 5 hours. Data collected for analysis including students’ achievement test, International Bebras Contest, attitude questionnaire, and class observation record. The findings show that the emulation-based open-hardware activities: (1) significantly improved students’ performance in problem decomposition, (2) had no effects on students’ performance in programming and their attitudes toward the learning activities, and (3) benefited students’ computational thinking. Future studies should extend the length of experiment time and design proper computational thinking evaluation tools.
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Wieler, Richard. "Emulation systems based on reconfigurable hardware devices." 1995. http://hdl.handle.net/1993/19040.
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Peng, Fei, and 彭飛. "OpenCL 2.0 Enabled HSA Hardware Platform Emulation." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/38981095842033467767.
Full textAbstract:
碩士國立清華大學
資訊工程學系
103
Heterogeneous System Architecture (HSA) is an open industry standard that tightly coupled the CPU with variety accelerators and also designed to support data-parallel programming models. Although there is a HSA-compatible machine, it is still not the HSA fully supported machine. A lot of software components using HSA is in development, so it is useful by providing an emulation environment for verifying HSA software components and tool-chains In this paper, we introduce a HSA emulation platform that can support OpenCL 2.0, which is based on HSAemu framework. HSA emulation platform provides a plat-form that combines OpenCL 2.0 with Heterogeneous System Architecture, using Shared Virtual Memory in HSA to achieve the same feature in OpenCL 2.0, and sup-ply with other new features such as Generic Address Space, Device Enqueue, Pipe, C11 atomic. Programmers can verify whether the program written in OpenCL can leverage the Heterogeneous System Architecture. In our preliminary experiments, the HSAemu has been validated by those extra features mentioned above. It can help developers to verify the program results and performances.
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LI, MENG-LIN, and 李孟霖. "Resource Optimization for Hardware Generation of WDF-based Circuit Emulators." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/r29jm6.
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碩士國立中央大學
電機工程學系
107
With the advance of semiconductor technologies, the design of Very-Large-Scale Integration (VLSI) circuits becomes more complex. System-on-Chip (SOC) has become the main stream of VLSI design style . Because SOC designs usually contain both analog and digital circuits, it is important to have an Analog/Mixed-Signal (AMS) verification flow for chip development. In this thesis, we adopt Wave Digital Filter(WDF) theorem to map analog circuits into digital circuits for emulating analog circuits. This method uses incident and reflected waves to model circuit characteristics. Each analog component can be transformed into digital component in WDF framework to support the co-simulation with digital circuits. Based on the previous studies for the simulation process of WDF architectures, this thesis presents an automatic environment for converting analog circuits into WDF structures. Using the sensitivity-based method, the change of γ value at each adaptor becomes a formula related to the input voltage, This approach successfully avoids long calculation time by replacing the look-up table and interpolation method. In order to minimize hardware resource, integer linear programming algorithm is used to obtain the minimum number of required adaptors, The affine arithmetic model is also applied to calculate the minimum bit length with certain precision. As shown in the experimental results combining the proposed methods, the generated WDF circuits are greatly improve in terms of speed and area. The automation environment also improves the convenience for users to do analog emulation
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Sá, José Pedro Patrício Gonçalves de. "Emulador em hardware de floppy disk drive com acesso sem fios." Master's thesis, 2011. http://hdl.handle.net/10216/63317.
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Sá, José Pedro Patrício Gonçalves de. "Emulador em hardware de floppy disk drive com acesso sem fios." Dissertação, 2011. http://hdl.handle.net/10216/63317.
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Lee, Tsing Gen, and 李清根. "EMPAR: An Interactive Design Environment for Hardware Emulation Applications." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/45774630746461439061.
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Wu, Cheng-Chang, and 吳誠昌. "A Real-Time Emulation Hardware Platform for Channel Decoder." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/65843466950607930475.
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碩士國立清華大學
電機工程學系
91
ABSTRACT In modern communication systems, the interference of the channel noise is unavoidable when we transmit data. To overcome this problem, many theories about channel coding have been developed. Firstly, the data in the transmitter is coded, and then transmitted to the receiver via channel. Though it may be corrupted by the channel interference, the decoder can still get the decoded data that is like the original data. The most commonly used error control coding is the convolutional code in communication systems. The Viterbi algorithm is a Maximan-likelihood decoding algorithm for the convolutional code. When developing the channel decoder without hardware support, we can only use software tools such as Xilinx ISE, Synplify Pro, or ModelSim to synthesize and simulate the decoder. In this thesis, we first design a PCI-based emulation hardware and host GUI system that utilizes a Xilinx FPGA XCV1000E for fast design realization and real-time emulation for channel decoder. Users can compiler their decoder circuit and use the system to program decoder circuit into the FPGA quickly. The system can generate convolutional code continuously, add the simulated channel noise, and then transmit data to decoder circuit by PCI interface. The system can then analyze the results from the FPGA decoder to test and verify if the design is correct. Besides, a flexible IP builder is designed which enables experimenting different aspects of Viterbi decoders by changing (n,k,m) parameters. The builder can generate the VHDL code of different parameter according to our need. Afterward, the real-time hardware emulation of the decoder can be performed. The field test of the developed PCI-based FPGA hardware emulation platform illustrates the effectiveness and usefulness of the system. It can also be used as a general fast hardware emulation platform for designing other circuits and applications.
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Frauenschläger, Jens. "Hardware-Debugging durch die Kombination von Emulation und Simulation." 2002. https://ul.qucosa.de/id/qucosa%3A16537.
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'...Zugriffsfehler im Modul xyz...' - solche oder ähnliche Fehlermeldungen sehen Benutzer von Computern meist dann, wenn sie versuchen mit einem Programm Operationen auszuführen, die fehlerhaft programmiert wurden. Die Ursachen für derartige Fehler sind dabei recht vielfältig. Oftmals sind sie bereits in der benutzten Programmiersprache zu suchen, dazu kommen zusätzlich Fehler in den Compilern, Beschränkungen in dem Betriebssystem sowie Seiteneffekte anderer Programme, wie z.B. falsches Speichermanagement. Angeführt wird die Liste möglicher Fehlerquellen allerdings vom Menschen selbst. Wobei auch hier noch zu unterscheiden ist, ob der Mensch einen Fehler aus Unwissenheit gemacht hat, oder ob er dessen Relevanz einfach unterschätzt hat. In beiden Fällen wird es immer schwer sein in einem Endprodukt die genaue Ursache eines Fehlverhaltens zu lokalisieren. Ähnlich wie es zu Problemen bei der Erstellung von Software kommen kann, treten natürlich auch während der Entwicklung einer Schaltung grundlegende Schwierigkeiten auf...
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Todd, Michael Gordon. "Hardware Emulation of a Secure Passive Rfid Sensor System." 2010. https://scholarworks.umass.edu/theses/528.
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Passively powered radio frequency (RFID) tags are a class of devices powered via harvested ultra high frequency (UHF) radiation emitted by a reader device. Currently, these devices are relegated to little more than a form of wireless barcode, but could be used in a myriad of applications from simple product identification to more complex applications such as environmental sensing. Because these devices are intended for large scale deployment and due to the limited power that can be harvested from RF energy, hardware and cost constraints are extremely tight.
The Electronic Product Code (EPC) Global Class 1 Generation 2 (Gen2) specification [EPC08] is currently the de facto communication standard for passively powered RFID. One issue restricting deployment and a cause for some privacy concerns is a lack of security in the Gen2 protocol. We will demonstrate a potential solution to this problem by using a novel block cipher designed for low power and area constrained devices to encrypt and transmit sensor data. This will be done while maintaining backward compatibility with the original standard and will require no substantial changes to the reader. Our solution will also provide one way authentication, data integrity checking and will provide security against replay attacks.
In this thesis we will demonstrate an FPGA emulation of a Gen2 compatible RFID tag which will serve as a test bed for several novel features. We will leverage prior work involving several aspects of a tag [QL09] [PP07] as well as incorporate a novel low power encryption cipher [AB07] and external temperature sensor. Demonstrated in [CT08], FPGA emulation will allow for the independent verification of several components. This thesis will provide insight into the future of RFID and will provide insight into tag design as well as possible future updates to the Gen2 standard.
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Lin, Li-Te, and 林俐德. "Hardware Emulation and System Prototyping of Embedded Digital Signal Processor." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/90758127535700247190.
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碩士國立交通大學
電機資訊學院碩士在職專班
94
In the development procedure of embedded DSP, to verify the functionality of DSP is a very important step and it usually takes a lot of time. Designers can use software simulation, formal verification, or hardware emulation to complete the verification of DSP. Unfortunately, software simulation is a very inefficient way considering the simulation time. Formal verification could shorten verification time, but can’t handle large-scale circuitry. Although hardware emulation could emulate complex circuitry, its shortcoming is the lack of debugging ability. In this thesis, we use hardware emulation to shorten the development procedure of DSP. In order to overcome the shortcoming of hardware emulator - the lack of debugging ability, we propose a new embedded In-Circuit Emulator (ICE) architecture, in which we use DSP ready-made hardware to reduce the time demand of verification. At the same time, we use the instruction set and hardware interrupts of DSP to reduce extra debugging hardware. We integrate this emulator into a DSP – Pica DSP (Packed Instruction and Cluster Architecture). We also rely on FPGA to implement and verify the system prototype of Pica DSP. The result of implementation shows that Pica DSP integrates ICE could be easily verified and debugged. The hardware overhead of Pica DSP is 1.53% after we integrate embedded ICE.