Relevant bibliographies by topics / Hardware Emulator

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Hardware Emulator'

Author: Grafiati
Published: 6 September 2023

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Hardware Emulator.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "Hardware Emulator"

1

Chaves, Ricardo, Carlos Senna, Miguel Luís, Susana Sargento, André Moreira, Diogo Recharte, and Ricardo Matos. "EmuCD: An Emulator for Content Dissemination Protocols in Vehicular Networks." Future Internet 12, no. 12 (December 21, 2020): 234. http://dx.doi.org/10.3390/fi12120234.

Full text
Abstract:
The development of protocols for mobile networks, especially for vehicular ad-hoc networks (VANETs), presents great challenges in terms of testing in real conditions. Using a production network for testing communication protocols may not be feasible, and the use of small networks does not meet the requirements for mobility and scale found in real networks. The alternative is to use simulators and emulators, but vehicular network simulators do not meet all the requirements for effective testing. Aspects closely linked to the behaviour of the network nodes (mobility, radio communication capabilities, etc.) are particularly important in mobile networks, where a delay tolerance capability is desired. This paper proposes a distributed emulator, EmuCD, where each network node is built in a container that consumes a data trace that defines the node’s mobility and connectivity in a real network (but also allowing the use of data from simulated networks). The emulated nodes interact directly with the container’s operating system, updating the network conditions at each step of the emulation. In this way, our emulator allows the development and testing of protocols, without any relation to the emulator, whose code is directly portable to any hardware without requiring changes or customizations. Using the facilities of our emulator, we tested InterPlanetary File System (IPFS), Sprinkler and BitTorrent content dissemination protocols with real mobility and connectivity data from a real vehicular network. The tests with a real VANET and with the emulator have shown that, under similar conditions, EmuCD performs closely to the real VANET, only lacking in the finer details that are extremely hard to emulate, such as varying loads in the hardware.
APA, Harvard, Vancouver, ISO, and other styles
2

Kirei, Botond Sandor, Calin-Adrian Farcas, Cosmin Chira, Ionut-Alin Ilie, and Marius Neag. "Hardware Emulation of Step-Down Converter Power Stages for Digital Control Design." Electronics 12, no. 6 (March 10, 2023): 1328. http://dx.doi.org/10.3390/electronics12061328.

Full text
Abstract:
This paper proposes a methodology of delivering the emulation hardware of several step-down converter power stages. The generalized emulator design methodology follows these steps: first, the power stage is described using an ordinary differential equation system; second, the ordinary differential equation system is solved using Euler’s method, and thus an accurate time-domain model is obtained; next, this time-domain model can be described using either general-purpose programming language (MATLAB, C, etc.) or hardware description language (VHDL, Verilog, etc.). As a result, the emulator has been created; validation of the emulator may be carried out by comparing it to SPICE transient simulations. Finally, the validated emulator can be implemented on the preferred target technology, either in a general-purpose processor or a field programmable gate array. As the emulator relies on the ordinary differential equation system of the power stage, it has better behavioral accuracy than the emulators based on average state space models. Moreover, this paper also presents the design methodology of a manually tuned proportional–integrative–derivative controller deployed on a field programmable gate array.
APA, Harvard, Vancouver, ISO, and other styles
3

Ganapathy, Apoorva, and Taposh Kumar Neogy. "Artificial Intelligence Price Emulator: A Study on Cryptocurrency." Global Disclosure of Economics and Business 6, no. 2 (December 31, 2017): 115–22. http://dx.doi.org/10.18034/gdeb.v6i2.558.

Full text
Abstract:
The cryptocurrency Artificial intelligence price emulator is a software programmed to collect cryptocurrency market data, analyze the data and predict the market price using the collected data. Computer emulators are programmed to mimic and copy behaviors or other software/hardware. The reason for emulation is to get to a particular result as quickly as possible. Machine learning is the ability of computers to read and process data while learning from the data with human interference or influence. This work focused majorly on how cryptocurrency market prices can be emulated using Artificial Intelligence with machine learning abilities. It also looked into the advantages of using the software for crypto investors. Some of which is the reduced time of research, reduction of risk, among others.
APA, Harvard, Vancouver, ISO, and other styles
4

Ozawa, Felipe, Marco Rocha, Guilherme Lucas, Wallace Souza, and Andre Andreoli. "Application of Torque Transducer and Rotary Encoder in a Hardware-in-the-Loop Wind Turbine Emulation." Proceedings 42, no. 1 (November 14, 2019): 55. http://dx.doi.org/10.3390/ecsa-6-06633.

Full text
Abstract:
Wind energy is one of the most promising forms of renewable energy. For the constant evolution of power generation technology, the use of sensors is fundamental to the development of wind turbine emulators. A wind turbine emulator allows tests and evaluations of a wind power system, regardless of weather conditions. Therefore, to further improve this technology, this work focuses on the application of a torque transducer and a rotary encoder for the implementation of a closed-loop wind turbine emulator. The sensors provide the torque and speed feedback signals to the computational model so that the model could plot the power curves and produce the set point voltage used by a variable-frequency drive (VFD) to control a three-phase induction motor (TIM). The emulator was implemented using a control algorithm designed on LabVIEW, with an NI 6211 for the data acquisition. Finally, the system emulates the behaviour of a wind turbine, considering the variations in wind speed, aerodynamic phenomena, load effects, and pitch angle. Experimental results demonstrated the effectiveness of using the TIM-VFD assembly for emulating a wind turbine since the wind turbine emulator behaved like a wind turbine in real-time.
APA, Harvard, Vancouver, ISO, and other styles
5

Ye, Zhijing, Fei Hu, Lin Zhang, Zhe Chu, and Zheng O'Neill. "A Low-Cost Experimental Testbed for Energy-Saving HVAC Control Based on Human Behavior Monitoring." International Journal of Cyber-Physical Systems 2, no. 1 (January 2020): 33–55. http://dx.doi.org/10.4018/ijcps.2020010103.

Full text
Abstract:
Heating, ventilation, and cooling (HVAC) is the largest source of residential energy consumption. Occupancy sensors' data can be used for HVAC control since they indicate the number of people in the building. HVAC/sensor interactions show the essential features of a typical cyber-physical system (CPS). However, there are communication protocol incompatibility issues in the CPS interface between the sensors and the building HVAC server. Through either wired or wireless communication links, the server always needs to understand the communication schedule to receive occupant values from sensors. This paper proposes two hardware-based emulators to investigate the use of wired/wireless communication interfaces for occupancy sensor-based building CPS control. The interaction scheme between sensors and HVAC server will be discussed. The authors have built two hardware/software emulation platforms to investigate the sensor/HVAC integration strategies. The first emulator demonstrates the residential building's energy control by using sensors and Raspberry pi boards to emulate the functions/responses of a static thermostat. In this case, room HVAC temperature settings could be changed in real-time with a high resolution based on the collected sensor data. The second emulator is built to show the energy control in commercial building by transmitting the sensor data and control signals via BACnet in HVAC system. Both emulators discussed above are portable (i.e., all hardware units can be easily taken to a new place) and have extremely low cost. This research tests the whole system with YABE (Yet Another BACnet Explorer) and WebCTRL.
APA, Harvard, Vancouver, ISO, and other styles
6

Díaz, Edel, Raúl Mateos, Emilio J. Bueno, and Rubén Nieto. "Enabling Parallelized-QEMU for Hardware/Software Co-Simulation Virtual Platforms." Electronics 10, no. 6 (March 23, 2021): 759. http://dx.doi.org/10.3390/electronics10060759.

Full text
Abstract:
Presently, the trend is to increase the number of cores per chip. This growth is appreciated in Multi-Processor System-On-Chips (MPSoC), composed of more cores in heterogeneous and homogeneous architectures in recent years. Thus, the difficulty of verification of this type of system has been great. The hardware/software co-simulation Virtual Platforms (VP) are presented as a perfect solution to address this complexity, allowing verification by simulation/emulation of software and hardware in the same environment. Some works parallelized the software emulator to reduce the verification times. An example of this parallelization is the QEMU (Quick EMUlator) tool. However, there is no solution to synchronize QEMU with the hardware simulator in this new parallel mode. This work analyzes the current software emulators and presents a new method to allow an external synchronization of QEMU in its parallelized mode. Timing details of the cores are taken into account. In addition, performance analysis of the software emulator with the new synchronization mechanism is presented, using: (1) a boot Linux for MPSoC Zynq-7000 (dual-core ARM Cortex-A9) (Xilinx, San Jose, CA, USA); (2) an FPGA-Linux co-simulation of a power grid monitoring system that is subsequently implemented in an industrial application. The results show that the novel synchronization mechanism does not add any appreciable computational load and enables parallelized-QEMU in hardware/software co-simulation virtual platforms.
APA, Harvard, Vancouver, ISO, and other styles
7

Modares, Jalil, Nicholas Mastronarde, and Karthik Dantu. "Simulating unmanned aerial vehicle swarms with the UB-ANC Emulator." International Journal of Micro Air Vehicles 11 (January 2019): 175682931983766. http://dx.doi.org/10.1177/1756829319837668.

Full text
Abstract:
Recent advances in multi-rotor vehicle control and miniaturization of hardware, sensing, and battery technologies have enabled cheap, practical design of micro air vehicles for civilian and hobby applications. In parallel, several applications are being envisioned that bring together a swarm of multiple networked micro air vehicles to accomplish large tasks in coordination. However, it is still very challenging to deploy multiple micro air vehicles concurrently. To address this challenge, we have developed an open software/hardware platform called the University at Buffalo’s Airborne Networking and Communications Testbed (UB-ANC), and an associated emulation framework called the UB-ANC Emulator. In this paper, we present the UB-ANC Emulator, which combines multi-micro air vehicle planning and control with high-fidelity network simulation, enables practitioners to design micro air vehicle swarm applications in software and provides seamless transition to deployment on actual hardware. We demonstrate the UB-ANC Emulator’s accuracy against experimental data collected in two mission scenarios: a simple mission with three networked micro air vehicles and a sophisticated coverage path planning mission with a single micro air vehicle. To accurately reflect the performance of a micro air vehicle swarm where communication links are subject to interference and packet losses, and protocols at the data link, network, and transport layers affect network throughput, latency, and reliability, we integrate the open-source discrete-event network simulator ns-3 into the UB-ANC Emulator. We demonstrate through node-to-node and end-to-end measurements how the UB-ANC Emulator can be used to simulate multiple networked micro air vehicles with accurate modeling of mobility, control, wireless channel characteristics, and network protocols defined in ns-3.
APA, Harvard, Vancouver, ISO, and other styles
8

Ma, Chao-Tsung, Zhen-Yu Tsai, Hung-Hsien Ku, and Chin-Lung Hsieh. "Design and Implementation of a Flexible Photovoltaic Emulator Using a GaN-Based Synchronous Buck Converter." Micromachines 12, no. 12 (December 20, 2021): 1587. http://dx.doi.org/10.3390/mi12121587.

Full text
Abstract:
In order to efficiently facilitate various research works related to power converter design and testing for solar photovoltaic (PV) generation systems, it is a great merit to use advanced power-converter-based and digitally controlled PV emulators in place of actual PV modules to reduce the space, cost, and time to obtain the required scenarios of solar irradiances for various functional tests. This paper presents a flexible PV emulator based on gallium nitride (GaN), a wide-bandgap (WBG) semiconductor, and a based synchronous buck converter and controlled with a digital signal processor (DSP). With the help of GaN-based switching devices, the proposed emulator can accurately mimic the dynamic voltage-current characteristics of any PV module under normal irradiance and partial shading conditions. With the proposed PV emulator, it is possible to closely emulate any PV module characteristic both theoretically, based on manufacturer’s datasheets, and experimentally, based on measured data from practical PV modules. A curve fitting algorithm is used to handle the real-time generation of control signals for the digital controller. Both simulation with computer software and implementation on 1 kW GaN-based experimental hardware using Texas Instruments DSP as the controller have been carried out. Results show that the proposed emulator achieves efficiency as high as 99.05% and exhibits multifaceted application features in tracking various PV voltage and current parameters, demonstrating the feasibility and excellent performance of the proposed PV emulator.
APA, Harvard, Vancouver, ISO, and other styles
9

Zhu, Qiuming, Wei Huang, Kai Mao, Weizhi Zhong, Boyu Hua, Xiaomin Chen, and Zikun Zhao. "A Flexible FPGA-Based Channel Emulator for Non-Stationary MIMO Fading Channels." Applied Sciences 10, no. 12 (June 17, 2020): 4161. http://dx.doi.org/10.3390/app10124161.

Full text
Abstract:
In this paper, a discrete non-stationary multiple-input multiple-output (MIMO) channel model suitable for the fixed-point realization on the field-programmable gate array (FPGA) hardware platform is proposed. On this basis, we develop a flexible hardware architecture with configurable channel parameters and implement it on a non-stationary MIMO channel emulator in a single FPGA chip. In addition, an improved non-stationary channel emulation method is employed to guarantee accurate channel fading and phase, and the schemes of other key modules are also illustrated and implemented in a single FPGA chip. Hardware tests demonstrate that the output statistical properties of proposed channel emulator, i.e., the probability density function (PDF), cross-correlation function (CCF), Doppler power spectrum density (DPSD), and the power delay profile (PDP) agree well with the corresponding theoretical ones.
APA, Harvard, Vancouver, ISO, and other styles
10

Verani, Alessandro, Roberto Di Rienzo, Niccolò Nicodemo, Federico Baronti, Roberto Roncella, and Roberto Saletti. "Modular Battery Emulator for Development and Functional Testing of Battery Management Systems: Hardware Design and Characterization." Electronics 12, no. 5 (March 4, 2023): 1232. http://dx.doi.org/10.3390/electronics12051232.

Full text
Abstract:
Battery Management Systems are essential for safe and effective use of Lithium-Ion batteries. The increasing complexity of the control and estimation algorithms requires deeper functional testing and validation phases of BMSs. However, the use of real batteries in such phases leads to hazards and safety risks. Battery emulators and the Hardware-in-the-Loop approach can instead speed-up and increase the safety of the functional testing and algorithm validation phases. This work describes the design and the characterization of a low-cost modular multi-cell battery emulator which provides a complete emulation of cell voltage, temperature, and current. This platform can be used to carry out Hardware-in-the-Loop tests on custom and commercial Battery Management Systems. The paper describes the platform design constraints derived from the most diffused Battery Management System architectures, the main design and implementation choices, and the platform characterization results. The proposed emulation platform is compared with literature and commercial ones showing a very good trade-off between performance and cost. This characteristic makes it appealing for small-size laboratories that develop and test Battery Management Systems. The project has therefore been made available to the scientific community as a freely downloadable open hardware platform.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "Hardware Emulator"

1

Persson, Robert. "PPS5000 Thruster Emulator Architecture Development & Hardware Design." Thesis, Luleå tekniska universitet, Rymdteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:ltu:diva-72827.

Full text
Abstract:
This Master's Thesis handles prestudy work and early hardware development that resulted in architectural definitions and prototype hardware of electronic ground support equipment. This equipment is destined to emulate the electric power consumption of the PPS5000 Hall Effect Thruster (HET), for use in satellite end-to-end tests of the all-electric Geostationary Satellite Electra, developed at OHB Sweden AB. The Thruster Emulator (TEM) was defined through a resulting compilation of intricate interdependent components that interface the satellite power system and the thruster, which yielded an architecture development to support some basic predefined emulator requirements. This architecture was then analyzed to form a base-line conceptual function of the emulator system, which incorporates the entire HET functionality. Six primary HET impedances were defined, of which the three most complex impedances were investigated fully. For the primary thruster discharge, research is shown of the complexity of implementing advanced electronic load hardware directly to the satellite's 5kW power system with respect to the transient primary plasma discharge during thruster start up, and with limitations on the electronic load reducing emulator-thruster similarities. Additionally, a fully functional plasma ignition emulator prototype circuit board was built to be used in the final hardware of the TEM to emulate the external HET cathode start-up functionality. Finally, a feasibility study for designing a possible solution for the large PPS5000 electromagnet impedance was performed, resulting in the manufacture of two prototype inductors with unsatisfying performance results according to the design requirements.
APA, Harvard, Vancouver, ISO, and other styles
2

Stanley, Berdenia Walker. "Hierarchical multiway partitioning strategy with hardware emulator architecture intelligence." Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/13360.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Witkowsky, Jason. "A hardware emulator testbed for a software-defined radio." Thesis, Peninsula Technikon, 2003. http://hdl.handle.net/20.500.11838/1170.

Full text
Abstract:
Submitted in fulfillment of the requirement for the Masters degree of Technology (MTech): Electrical Engineering, 2003
Contemporary software-defined radio (SDR) is continuously changing and challenging the way traditional RF systems operate. Having more of a radio system’s operation in software enables further flexibility through the use of software manipulation. Due to practical limitations, however, it is not always feasible to have the entire radio system’s operations performed using software. Practical limitations, therefore, require that a SDR employs some form of RF front-end in order to interface the antenna signals and the signals prior to the data converters. As technology grows in support of SDR development, this hardware interface is becoming increasingly smaller. The problem with the rapid rate at which SDR developments are occurring is that RF hardware needs to change accordingly. Therefore, the RF hardware front-end can be seen as a non-standardised piece of equipment. To the designer, this means having to prototype in hardware in order to experiment with various types of SDR hardware front-ends. One of a SDR’s main attractions is the inherent property of software testability. Taking this fact into account, this thesis investigates the design and operation of a basic softwaredriven RF front-end emulator for a SDR. Basic prototype software models are identified and developed in order to test their performance within the emulator. The focus of the thesis, however, is geared toward the development of a software architecture that enables a high degree of interchangeability amongst the underlying modelled components. In the case of a SDR, the advantage of prototyping in software is in predicting the behaviour of a system prior to having to perform any physical developments. This property of software testability in the emulator can only fully be appreciated if a bench-mark system is used to evaluate the overall performance of the emulator. Therefore, a physical hardware setup is performed in order to test the basic aspects of the emulators operation. This evaluation is not meant as an exhaustive analysis of the emulator, but aims to highlight the overall performance of the emulated system against a typical physical system setup.
APA, Harvard, Vancouver, ISO, and other styles
4

Daniil, Nickolaos. "Battery emulator operating in a power hardware-in-the-loop simulation : the concept of hybrid battery emulator." Thesis, University of Bristol, 2017. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.723517.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

O'Rourke, Colm Joseph. "Design of a hardware solar emulator for an experimental microgrid." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/99852.

Full text
Abstract:
Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 67-68).
Microgrids are regions where local generation and loads are clustered together. Students from the LEES group at MIT are currently developing an experimental microgrid. This will enable various studies in the area of microgrid dynamics. The setup consists of a variety of modules that emulate both conventional and renewable sources. In this thesis, we focus on the design of one of these modules: the solar PV emulator. The complete design of a solar PV emulator will be described. Firstly, AC and DC models of a solar cell are introduced. These models specify design constraints for the power electronic circuitry. They also indicate a desired performance for the feedback control system. The controller design is discussed and the effect of load type on the closed-loop dynamics are considered. This is especially interesting for the grid-connected case. The design methodology culminates in the construction of an experimental prototype of the hardware solar PV emulator. The modular design approach is outlined as are its benefits to the overall construction of the microgrid. A Generic Controller board that can be used for all future power electronic modules in the microgrid is also designed and fabricated. The results of simulations and experiments are discussed and it is shown that it is possible for a buck converter to emulate the steady state dynamics associated with solar PV panels.
by Colm Joseph O'Rourke.
S.M.
APA, Harvard, Vancouver, ISO, and other styles
6

Petucco, Andrea. "Hardware in the loop, all-electronic wind turbine emulator for grid compliance testing." Doctoral thesis, Università degli studi di Padova, 2017. http://hdl.handle.net/11577/3422321.

Full text
Abstract:
During the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through (LVRT) certitication due to the following resons: • The standards specify it must be performed ad different power levels. For this reasons it is necessary to wait for the right atmospheric conditions. • It requires a voltage sag generator which is usually expensive and bulky. • The voltage sag generator needs to be cabled between the grid and the wind turbine. • The voltage sag generator causes disturbances and perturbation on the power grid, for this reasons agreements with the distributor operator are needed. For all these reasons a laboratory test bench to perform the LVRT certification tests on wind turbines would be a more controlled and inexpensive alternative to the classic testing methodology. The research presented in this thesis is focused on the design and the realization of a test bench to perform certification tests on energy converters for wind turbines in laboratory. More specifically, the possibility of performing LVRT certification tests directly in laboratory over controlled conditions would allow faster testing procedures and less certification overall costs. The solution presented in this thesis is based on a power hardware in the loop implementing a digitally-controlled, power electronics-based emulation of a wind turbine. This emulator is used to drive the electronic wind energy converter (WEC) under test. A grid emulator is used to apply voltage sags to the wind turbine converter and perform LVRT certification tests. In this solution AC power supplies are used to emulate both the wind turbine and the grid emulator. For this reason the test bench power rating is limited to the AC supplies one. Two working versions of the test bench has been realized and successfully tested. The work here presented has evolved through the following phases: • Study of the grid code requirements and the state of the art. • Modeling of the parts of a wind turbine and complete system simulations.
During the last years the distribution of renewable energy sources is continuously increasing and their influence on the distribution grid is becoming every year more relevant. As the increasing integration of renewable resources is radically changing the grid scenario, grid code technical requirements as are needed to ensure the grid correct behavior. To be standard compliant wind turbines need to be submitted to certification tests which usually must be performed on the field. One of the most difficult tests to be performed on the field is the low voltage ride through (LVRT) certitication due to the following resons: • The standards specify it must be performed ad different power levels. For this reasons it is necessary to wait for the right atmospheric conditions. • It requires a voltage sag generator which is usually expensive and bulky. • The voltage sag generator needs to be cabled between the grid and the wind turbine. • The voltage sag generator causes disturbances and perturbation on the power grid, for this reasons agreements with the distributor operator are needed. For all these reasons a laboratory test bench to perform the LVRT certification tests on wind turbines would be a more controlled and inexpensive alternative to the classic testing methodology. The research presented in this thesis is focused on the design and the realization of a test bench to perform certification tests on energy converters for wind turbines in laboratory. More specifically, the possibility of performing LVRT certification tests directly in laboratory over controlled conditions would allow faster testing procedures and less certification overall costs. The solution presented in this thesis is based on a power hardware in the loop implementing a digitally-controlled, power electronics-based emulation of a wind turbine. This emulator is used to drive the electronic wind energy converter (WEC) under test. A grid emulator is used to apply voltage sags to the wind turbine converter and perform LVRT certification tests. In this solution AC power supplies are used to emulate both the wind turbine and the grid emulator. For this reason the test bench power rating is limited to the AC supplies one. Two working versions of the test bench has been realized and successfully tested. The work here presented has evolved through the following phases: • Study of the grid code requirements and the state of the art. • Modeling of the parts of a wind turbine and complete system simulations.
APA, Harvard, Vancouver, ISO, and other styles
7

Adnan, Muhammad Wasif. "Implementation of an FPGA based Emulator for High Speed Power Electronic Systems." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-175752.

Full text
Abstract:
During development of control systems for power electronic systems, it is desirable to test the controller in real-time, by interfacing it with an emulator device. In this context, this work comprises the development of an emulator that can model accurately the dynamics of high speed power electronic systems and provides interfaces that are compatible with the real hardware. The realtime state calculations, based on discrete models, were performed on custom logic, implemented on an FPGA. The realized system allows to emulate Linear Parameter Varying (LPV) systems, achieving sampling rates up to 12MHz using a low cost Xilinx FPGA. As a result, power electronic systems with very high switching frequencies can be modeled. In addition, the FPGA incorporates a soft-core processor that allows a designer to easily re-configure the system model through software. The emulator system has been validated for a multiphase DC-DC converter, by comparing its results with the real hardware setup.
APA, Harvard, Vancouver, ISO, and other styles
8

Beckert, René. "Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration." Dresden TUDpress, 2008. http://d-nb.info/991847423/04.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Shadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.

Full text
Abstract:
The purpose of a channel emulator is to emulate a communication channel in real-life use case scenario. These emulators are often used in the domains of research in digital and wireless communication. One such area is error correction coding, where transmitted data bits over a channel are decoded and corrected to prevent data loss. A channel emulator that does not follow the properties of the channel it is intended to replicate can lead to mistakes while analyzing the performance of an error-correcting decoder. Hence, it is crucial to validate an emulator for a particular communication channel. This work delves into the statistics of a channel emulator and analyzes its effects on a particular decoder.
APA, Harvard, Vancouver, ISO, and other styles
10

Oliveira, José Rodrigo de. "Emulador de turbina eólica : uma ferramenta para o estudo experimental e computacional /." Bauru, 2019. http://hdl.handle.net/11449/191354.

Full text
Abstract:
Orientador: André Luiz Andreoli
Resumo: As fontes renováveis de energia apresentam-se como solução para problemas relacionados ao aumento da demanda por energia elétrica e crescimento dos níveis de emissão de gás carbônico, uma vez que são não poluentes, limpas e abundantes. Aproveitamentos eólicos se mostram como uma das mais promissoras fontes de energia renovável, e por essa razão as pesquisas envolvendo este tipo de aproveitamento têm despertado grande interesse na comunidade científica. Este trabalho apresenta o desenvolvimento de um emulador de turbina eólica (ETE), uma ferramenta de apoio às investigações experimentais capaz de reproduzir o comportamento mecânico dinâmico de uma turbina eólica através de uma malha de controle digital em configuração de hardware-in-the-loop atuando sobre um acionamento eletrônico de uma máquina de indução Operando como fonte de força motriz, o ETE torna mais fácil a avaliação dinâmica de geradores e seus sistemas de controle associados voltados às aplicações envolvendo energia eólica. A pesquisa apresenta uma revisão bibliográfica sobre o estado da arte, a modelagem e a implementação experimental de um emulador de turbina eólica utilizando um motor de indução trifásico (MIT) acionado por um inversor de frequência. Para isso, é implementado um controle em malha fechada de conjugado e velocidade. Este controle faz com que o acionamento eletromecânico representado pelo MIT e inversor de frequência apresente em seu eixo o comportamento de uma turbina eólica conforme os parâmetros... (Resumo completo, clicar acesso eletrônico abaixo)
Mestre
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "Hardware Emulator"

1

Zeljko, Zilic, and SpringerLink (Online service), eds. Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring. Dordrecht: Springer Science + Business Media B.V, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
2

Beckert, René. Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration. Dresden: TUDpress, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
3

Beckert, René. Untersuchungen zur Kostenoptimierung für Hardware-Emulatoren durch Anwendung von Methoden der partiellen Laufzeitrekonfiguration. Dresden: TUDpress, 2008.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Wells, George James. Hardware emulation and real-time simulation strategies for the concurrent development of microsatellite hardware and software. Toronto: Department of Aerospace Engineering, University of Toronto, 2001.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
5

Commission, United States International Trade. In the matter of certain hardware logic emulation systems and components thereof. Washington, DC: U.S. International Trade Commission, 1998.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
6

Commission, United States International Trade. In the matter of certain hardware logic emulation systems and components thereof. Washington, DC: U.S. International Trade Commission, 1996.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Calvert, W. T. A hardware emulation system for a spectrometer fitted with anintegrated multichannel detector. Manchester: UMIST, 1993.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Zilic, Zeljko, and Marc Boulé. Generating Hardware Assertion Checkers: For Hardware Verification, Emulation, Post-Fabrication Debugging and On-Line Monitoring. Springer, 2010.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
9

Davis, Mark Bradley. Hardware Acceleration for Software Emulation of PCI Express Compliant Devices: United States Patent 9996484. Independently Published, 2020.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
10

In the matter of certain hardware logic emulation systems and components thereof: Modification of temporary exclusion order. Washington, DC: U.S. International Trade Commission, 1997.

Find full text
APA, Harvard, Vancouver, ISO, and other styles

Book chapters on the topic "Hardware Emulator"

1

Skubiszewski, Marcin. "A Hardware Emulator for Binary Neural Networks." In International Neural Network Conference, 555–58. Dordrecht: Springer Netherlands, 1990. http://dx.doi.org/10.1007/978-94-009-0643-3_2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Marchal, Pierre, Pascal Nussbaum, Christian Piguet, and Moshe Sipper. "Speeding-up digital ecologies evolution using a hardware emulator: Preliminary results." In Evolvable Systems: From Biology to Hardware, 107–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63173-9_41.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Ye, Zhijing, Zheng O’Neill, Lin Zhang, Fei Hu, and Zhe Chu. "Hardware-Based Emulator for Building Energy Cyber-Physical Control with Occupancy Sensing." In Advances in Intelligent Systems and Computing, 493–99. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-43020-7_65.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Capriglione, Domenico, Gianni Cerro, Luigi Ferrigno, and Gianfranco Miele. "The Effect of Hardware/Software Features on the Performance of an Open–Source Network Emulator." In Lecture Notes in Computer Science, 233–45. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30523-9_19.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Kühner, Jens. "Hardware Emulation." In Expert .NET Micro Framework, 367–412. Berkeley, CA: Apress, 2009. http://dx.doi.org/10.1007/978-1-4302-2388-7_12.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Helaihel, Rachid, and Kunle Olukotun. "Emulation and Prototyping Of Digital Systems." In Hardware/Software Co-Design, 339–66. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2_14.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Rosenstiel, Wolfgang. "Prototyping and Emulation." In Hardware/Software Co-Design: Principles and Practice, 75–112. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-2649-7_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Martínez, Fredy H., and Jesús Alberto Delgado. "Hardware Emulation of Bacterial Quorum Sensing." In Lecture Notes in Computer Science, 329–36. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-14922-1_41.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Mierau, Caspar Clemens. "›There is no Hardware‹. Reanimation durch Emulation." In Re-Animationen, 311–28. Köln: Böhlau Verlag, 2012. http://dx.doi.org/10.7788/boehlau.9783412215538.311.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Scherer, Klaus, and Oliver Rettig. "Rapid Prototyping mikroelektronischer Hardware-Software-Systeme durch Emulation." In Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme, 285–96. Berlin, Heidelberg: Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/978-3-642-84304-4_24.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "Hardware Emulator"

1

Boutillon, Emmanuel, Yangyang Tang, Cedric Marchand, and Pierre Bomel. "Hardware Discrete Channel Emulator." In Simulation (HPCS). IEEE, 2010. http://dx.doi.org/10.1109/hpcs.2010.5547099.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Rosa, Vagner S., Vitor I. Gervini, Sebastiao C. P. Gomes, and Sergio Bampi. "A hardware DC motor emulator." In 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS). IEEE, 2010. http://dx.doi.org/10.1109/lascas.2010.7410216.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Zhang, Rong, and Andrew G. Alleyne. "Dynamic Emulation Using a Resistive Control Input." In ASME 2002 International Mechanical Engineering Congress and Exposition. ASMEDC, 2002. http://dx.doi.org/10.1115/imece2002-39323.

Full text
Abstract:
Dynamic load emulation using a resistive control input is a key topic of Hardware-In-The-Loop implementation. Three control configurations are available to design a load emulator. When the bandwidth of the reference system is low enough compared to the bandwidth of the actuator, a one degree-of-freedom (DOF) feedback emulator can be successful. When the reference loop has a very large bandwidth compared to the actuator, the one-DOF feedback design yields poor performance with a possible loss of stability. In this case, if accurate plant model parameters or, alternatively, online adaptation is available, a one-DOF feed forward design can secure stability and improve the performance; otherwise, a two-DOF emulator is the choice to utilize both feedback and feed forward signals and to obtain robust stability and robust performance. To emulate the load dynamics, the usage of a resistance as the control input imposes some fundamental limitations to the closed-loop performance. This paper presents the following: (i) Generalization of load emulation problems and control configurations, (ii) Analysis of performance limitations for resistively controlled systems, and (iii) Design examples including simulation and experimental results.
APA, Harvard, Vancouver, ISO, and other styles
4

Peter, Cleber S., Lucas Penning, Alexandra Zimpeck, Felipe Marques, Jorge Barbosa, and Adenauer Yamin. "SOTARU: Abordagem Baseada em Blockchain de Consórcio para Atualização Remota de Firmware no Cenário da IoT." In Seminário Integrado de Software e Hardware. Sociedade Brasileira de Computação - SBC, 2022. http://dx.doi.org/10.5753/semish.2022.223110.

Full text
Abstract:
Devido à elasticidade requerida, prover o armazenamento e distribuição das atualizações para os dispositivos que compõem a Internet das Coisas (IoT) tem se mostrado um elevado desafio para as infraestruturas de rede. Neste cenário, este artigo apresenta uma nova abordagem, denominada SOTARU, que propõe a utilização de uma Blockchain de consórcio entre os fabricantes de sistemas embarcados para fornecer uma infraestrutura compartilhada e descentralizada, mas também segura. A proposta foi implantada sobre os nodos do middleware EXEHDA e através do emulador de redes distribuídas Common Open Research Emulator (CORE) foi possível avaliar também a sua segurança e robustez. Como resultado, verificou-se que a SOTARU se sobressai em termos de segurança quando comparada às demais abordagens propostas pela literatura, bem como se mostra funcional mesmo em cenários de alta latência.
APA, Harvard, Vancouver, ISO, and other styles
5

Ulaganathan, M., and D. Devaraj. "Hardware and Software Co-emulation Technique based Solar Photovoltaic Sources Emulator." In 2019 IEEE International Conference on Intelligent Techniques in Control, Optimization and Signal Processing (INCOS). IEEE, 2019. http://dx.doi.org/10.1109/incos45849.2019.8951330.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Muntean, Nicolae, Lucian Tutelea, Diana Petrila, and Ovidiu Pelan. "Hardware in the loop wind turbine emulator." In 2011 International Aegean Conference on Electrical Machines and Power Electronics (ACEMP) and Electromotion Joint Conference. IEEE, 2011. http://dx.doi.org/10.1109/acemp.2011.6490568.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Zhang, Jingyao, Yi Tang, Sachin Hirve, Srikrishna Iyer, Patrick Schaumont, and Yaling Yang. "A software-hardware emulator for sensor networks." In 2011 8th Annual IEEE Communications Society Conference on Sensor, Mesh and Ad Hoc Communications and Networks (SECON). IEEE, 2011. http://dx.doi.org/10.1109/sahcn.2011.5984928.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Ruuskanen, Vesa, Joonas Koponen, Antti Kosonen, Markku Niemela, Jero Ahola, and Risto Tiainen. "Hardware-in-loop emulator for water electrolysers." In IECON 2016 - 42nd Annual Conference of the IEEE Industrial Electronics Society. IEEE, 2016. http://dx.doi.org/10.1109/iecon.2016.7794072.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Liu, Keren, Erik Börjeson, Christian Häger, and Per Larsson-Edefors. "FPGA-based Optical Kerr Effect Emulator." In Signal Processing in Photonic Communications. Washington, D.C.: Optica Publishing Group, 2022. http://dx.doi.org/10.1364/sppcom.2022.spth1i.2.

Full text
Abstract:
We propose a digital emulator of the optical Kerr effect, suitable for FPGA implementation. In addition, we study a combined PMD and Kerr emulator implementation with respect to DSP hardware aspects such as fixed-point performance.
APA, Harvard, Vancouver, ISO, and other styles
10

Patel, Harsh Vinod, S. S. Rathod, and Payal Hitesh Shah. "An FPGA based Hardware Emulator for Neuromorphic Chip." In 2020 International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2020. http://dx.doi.org/10.1109/icesc48915.2020.9155822.

Full text
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'Hardware Emulator' for particular source types:
Journal articles Dissertations / Theses
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography