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Books on the topic 'Hardware Construction Languages (HCLs)'

Author: Grafiati

Published: 25 May 2024

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1

Alain, Vachoux, ed. Analog and mixed-signal hardware description languages. Boston: Kluwer Academic Publishers, 1997.

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2

IFIP WG10.2 International Symposium on Computer Hardware Description Languages and their Applications (9th 1989 Washington, D. C.). Computer hardware description languages and their applications: Proceedings of theIFIP WG 10.2 Ninth International Symposium on Computer Hardware Description Languages and their Applications : Washington, D. C., U.S.A., 19-21 June, 1989. Amsterdam: North-Holland, 1990.

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3

Carlos, Delgado Kloos, and Damm Werner, eds. Practical formal methods for hardware design. Berlin: Springer, 1997.

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4

Jean-Michel, Mermet, ed. Electronic chips & systems design languages. Boston: Kluwer Academic Publishers, 2001.

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5

1950-, Smailagic Asim, ed. Digital systems design and prototyping: Using field programmable logic and hardware description languages. 2nd ed. Boston: Kluwer Academic, 2000.

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6

IFIP WG 10.2 International Conference on Computer Hardware Description Languages and their Applications (7th 1985 Tokyo). Computer hardware description languages and their applications: Proceedings of the IFIP WG 10.2 Seventh International Conference on Computer Hardware Description Languages and their Applications : Tokyo, Japan, 29-31 August, 1985. Amsterdam: North-Holland, 1985.

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7

Formal specification and verification of digital systems. London: McGraw-Hill, 1994.

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8

(2003), FDL'03. Languages for system specification: Selected contributions on UML, SystemC, System Verilig, mixed-signal systems, and property specification from FDL'03. Boston: Kluwer Academic Publishers, 2004.

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9

Simon, Davidmann, and Flake Peter, eds. SystemVerilog for design: A guide to using SystemVerilog for hardware design and modeling. Norwell, Mass: Kluwer, 2004.

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10

Anne, Mignotte, Villar Eugenio, and Horobin Lynn, eds. System on chip design languages: Extended papers : best of FDL'01 and HDLCon'01. Boston: Kluwer Academic Publishers, 2002.

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11

Philippe, Coussy, and Morawiec Adam, eds. High-level synthesis: From algorithm to digital circuit. [New York]: Springer, 2008.

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12

VHDL and FPLDs in digital systems design, prototyping and customization. Boston: Kluwer Academic Publishers, 1998.

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13

Eduard, Cerny, ed. Hierarchical annotated action diagrams: An interface-oriented specification and verification method. Boston: Kluwer Academic Publishers, 1998.

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14

Hoffmann, Andreas. Architecture exploration for embedded processors with LISA. Boston: Kluwer Academic Publishers, 2002.

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15

Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Boston: Kluwer Academic Publishers, 2001.

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16

Bening, Lionel. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. 2nd ed. Boston: Kluwer Academic Publishers, 2001.

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17

1956-, Foster Harry, ed. Principles of verifiable RTL design: A functional coding style supporting verification processes in Verilog. Norwell, Mass: Kluwer Academic Publishers, 2000.

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18

Chonlameth, Arpnikanondt, ed. A platform-centric approach to system-on-chip (SoC) design. New York: Springer, 2005.

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19

Moto-Oka, T., and C. J. Koomen. Computer Hardware Description Languages and Their Applications. Elsevier Science & Technology, 1985.

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20

Wecker, Dieter. Prozessorentwurf Mit VHDL: Modellierung und Synthese Eines 12-Bit-Mikroprozessors. de Gruyter GmbH, Walter, 2018.

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21

Wecker, Dieter. Prozessorentwurf Mit VHDL: Modellierung und Synthese Eines 12-Bit-Mikroprozessors. de Gruyter GmbH, Walter, 2018.

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22

Wecker, Dieter. Prozessorentwurf Mit VHDL: Modellierung und Synthese Eines 12-Bit-Mikroprozessors. de Gruyter GmbH, Walter, 2018.

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23

Palnitkar, Samir. Design Verification with e. Prentice Hall PTR, 2003.

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24

Design Verification with e. Prentice Hall PTR, 2003.

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25

Villar, Eugenio, and Jean Mermet. System Specification and Design Languages: Best of FDL'02. Springer, 2010.

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26

(Editor), Peter J. Ashenden, J. Mermet (Editor), and Ralf Seepold (Editor), eds. System-on-Chip Methodologies & Design Languages (The Chdl Series). Springer, 2001.

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27

Introduction to Logic Synthesis Using Verilog HDL (Synthesis Lectures on Digital Circuits and Systems). Morgan and Claypool Publishers, 2007.

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28

(Editor), Eugenio Villar, and J. Mermet (Editor), eds. System Specification and Design Languages: Best of FDL'02 (The Chdl Series). Springer, 2003.

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29

Morawiec, Adam, and Philippe Coussy. High-Level Synthesis: From Algorithm to Digital Circuit. Coussy Philippe Morawiec Adam, 2010.

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30

Languages for Embedded Systems and Their Applications Lecture Notes in Electrical Engineering. Springer, 2009.

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31

Sutherland, Stuart, Simon Davidmann, and Peter Flake. SystemVerilog For Design: A Guide to Using SystemVerilog for Hardware Design and Modeling. Springer, 2003.

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32

(Editor), Anne Mignotte, Eugenio Villar (Editor), and Lynn Horobin (Editor), eds. System on Chip Design Languages - Extended Papers: Best of FDL'01 and HDLCon'01. Springer, 2002.

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33

Morawiec, Adam, and Philippe Coussy. High-Level Synthesis: From Algorithm to Digital Circuit. Springer, 2008.

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34

Schliebusch, Oliver, Heinrich Meyr, and Rainer Leupers. Optimized ASIP Synthesis from Architecture Description Language Models. Springer, 2007.

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35

Schliebusch, Oliver, Heinrich Meyr, and Rainer Leupers. Optimized ASIP Synthesis from Architecture Description Language Models. Springer, 2010.

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36

Optimized ASIP Synthesis from Architecture Description Language Models. Springer, 2007.

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37

Vachoux, A. Applications of Specification and Design Languages for SoCs: Selected papers from FDL 2005. Springer, 2010.

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38

Vachoux, A. Applications of Specification and Design Languages for Socs: Selected Papers from FDL 2005. Springer London, Limited, 2006.

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39

Applications of Specification and Design Languages for SoCs: Selected papers from FDL 2005 (Chdl). Springer, 2006.

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40

Boulet, Pierre. Advances in Design and Specification Languages for Socs: Selected Contributions from FDL'04. Springer London, Limited, 2006.

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41

Boulet, Pierre. Advances in Design and Specification Languages for SoCs: Selected Contributions from FDL'04. Springer, 2014.

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42

Advances in Design and Specification Languages for SoCs: Selected Contributions from FDL'04 (Chdl). Springer, 2005.

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43

Cerny, Eduard, Bachir Berkane, Pierre Girodias, and Karim Khordoc. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method. Springer, 1998.

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44

Hoffmann, Andreas, Heinrich Meyr, and Rainer Leupers. Architecture Exploration for Embedded Processors with LISA. Springer London, Limited, 2013.

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45

Hoffmann, Andreas, Heinrich Meyr, and Rainer Leupers. Architecture Exploration for Embedded Processors with LISA. Springer, 2010.

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46

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design: A functional coding style supporting verification processes in Verilog. Springer, 2013.

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47

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design Second Edition - A Functional Coding Style Supporting Verification Processes in Verilog. 2nd ed. Springer, 2001.

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48

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog. Springer London, Limited, 2007.

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49

Bening, Lionel, and Harry D. Foster. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog. Springer, 2013.

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50

Hilgurt, S. Ya, and O. A. Chemerys. Reconfigurable signature-based information security tools of computer systems. PH “Akademperiodyka”, 2022. http://dx.doi.org/10.15407/akademperiodyka.458.297.

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Abstract:

The book is devoted to the research and development of methods for combining computational structures for reconfigurable signature-based information protection tools for computer systems and networks in order to increase their efficiency. Network security tools based, among others, on such AI-based approaches as deep neural networking, despite the great progress shown in recent years, still suffer from nonzero recognition error probability. Even a low probability of such an error in a critical infrastructure can be disastrous. Therefore, signature-based recognition methods with their theoretically exact matching feature are still relevant when creating information security systems such as network intrusion detection systems, antivirus, anti-spam, and wormcontainment systems. The real time multi-pattern string matching task has been a major performance bottleneck in such systems. To speed up the recognition process, developers use a reconfigurable hardware platform based on FPGA devices. Such platform provides almost software flexibility and near-ASIC performance. The most important component of a signature-based information security system in terms of efficiency is the recognition module, in which the multipattern matching task is directly solved. It must not only check each byte of input data at speeds of tens and hundreds of gigabits/sec against hundreds of thousand or even millions patterns of signature database, but also change its structure every time a new signature appears or the operating conditions of the protected system change. As a result of the analysis of numerous examples of the development of reconfigurable information security systems, three most promising approaches to the construction of hardware circuits of recognition modules were identified, namely, content-addressable memory based on digital comparators, Bloom filter and Aho–Corasick finite automata. A method for fast quantification of components of recognition module and the entire system was proposed. The method makes it possible to exclude resource-intensive procedures for synthesizing digital circuits on FPGAs when building complex reconfigurable information security systems and their components. To improve the efficiency of the systems under study, structural-level combinational methods are proposed, which allow combining into single recognition device several matching schemes built on different approaches and their modifications, in such a way that their advantages are enhanced and disadvantages are eliminated. In order to achieve the maximum efficiency of combining methods, optimization methods are used. The methods of: parallel combining, sequential cascading and vertical junction have been formulated and investigated. The principle of multi-level combining of combining methods is also considered and researched. Algorithms for the implementation of the proposed combining methods have been developed. Software has been created that allows to conduct experiments with the developed methods and tools. Quantitative estimates are obtained for increasing the efficiency of constructing recognition modules as a result of using combination methods. The issue of optimization of reconfigurable devices presented in hardware description languages is considered. A modification of the method of affine transformations, which allows parallelizing such cycles that cannot be optimized by other methods, was presented. In order to facilitate the practical application of the developed methods and tools, a web service using high-performance computer technologies of grid and cloud computing was considered. The proposed methods to increase efficiency of matching procedure can also be used to solve important problems in other fields of science as data mining, analysis of DNA molecules, etc. Keywords: information security, signature, multi-pattern matching, FPGA, structural combining, efficiency, optimization, hardware description language.

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