Dissertations / Theses on the topic 'Hardware circuits'
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Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.
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Thesis (M.S.)--University of Missouri--Rolla, 2007.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).
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Kalganova, Tatiana. "Evolvable hardware design of combinational logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4341.
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Evolvable Hardware (EHW), as an alternative method for logic design, became more attractive recently, because of its algebra-independent techniques for generating selfadaptive self-reconfigurable hardware. This thesis investigates and relates both evaluation and evolutionary processes, emphasizing the need to address problems arising from data complexity. Evaluation processes, capable of evolving cost-optimised fully functional circuits are investigated. The need for an extrinsic EHW approach (software models) independent of the concerns of any implementation technologies is emphasized. It is also shown how the function description may be adapted for use in the EHW approach. A number of issues of evaluation process are addressed: these include choice of optimisation criteria, multi-objective optimisation tedmiques in EHW and probabilistic analysis of evolutionary processes. The concept of self-adaptive extrinsic EHW method is developed. This approach emphasizes the circuit layout evolution together with circuit functionality. A chromosome representation for such system is introduced, and a number of genetic operators and evolutionary algorithms in support of this approach are presented. The genetic operators change the genetic material at the different levels of chromosome representation. Furthermore, a chromosome representation is adapted to the function-level EHW approach. As a result, the modularised systems are evolved using multi-output building blocks. This chromosome representation overcomes the problem of long string chromosome. Together, these techniques facilitate the construction of systems to evolve logic functions of large number of variables. A method for achieving this using bidirectional incremental evolution is documented. It is demonstrated that the integration of a dynamic evaluation process and self-adaptive function-level EHW approach allows the bidirectional incremental evolution to successfully evolve more complex systems than traditionally evolved before. Thereby it provides a firm foundation for the evolution of complex systems. Finally, the universality of these techniques is proved by applying them to multivalued combinational logic design. Empirical study of this application shows that there is no fundamental difference in approach for both binary and multi-valued logic design problems.
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Singh, Satnam. "Analysis of hardware descriptions." Thesis, University of Glasgow, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.390451.
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Sandiford, Richard. "Hardware compilation based on communicating processes." Thesis, Imperial College London, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246769.
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Thompson, Adrian. "Hardware evolution : automatic design of electronic circuits in reconfigurable hardware by artificial evolution." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360588.
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Desai, Avinash R. "Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23756.
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Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property
(IP) core or to inject malicious alterations is a major concern. First, offshore chip manufac-
turing allows the design secrets of the IP cores to be transparent to the foundry and other
entities along the production chain. Second, small malicious modifications to the design
may not be detectable after fabrication without anti-tamper mechanisms. Counterfeit Inte-
grated Circuits (ICs) also have become an important security issue in recent years, in which
counterfeit ICs that perform incorrectly or sub-par to the expected can lead to catastrophic
consequences in safety and/or mission-critical applications, in addition to the tremendous
economic toll they incur to the semiconductor industry. Some techniques have been devel-
oped in the past to improve the defense against such attacks but they tend to fall prey to
the increasing power of the attacker. We present a new way to protect against tampering
by a clever obfuscation of the design, which can be unlocked with a specific, dynamic path
traversal. Hence, the functional mode of the controller is hidden with the help of obfuscated
states, and the functional mode is made operational only on the formation of a specific
interlocked Code-Word during state transition. A novel time-stamp is proposed that can
provide the date at which the IC was manufactured for counterfeit detection. Furthermore,
we propose a second layer of tamper resistance to the time-stamp circuit to make it even
more difficult to modify. Results show that methods proposed offer higher levels of security
with small area overhead. A side benefit is that any small alteration will be magnified via
the obfuscated design proposed in these methods.Master of Science
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Basak, Abhishek. "INFRASTRUCTURE AND PRIMITIVES FOR HARDWARE SECURITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=case1458787036.
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Blum, Thomas. "Modular exponentiation on reconfigurable hardware." Digital WPI, 1999. http://www.wpi.edu/Pubs/ETD/Available/etd-090399-090413/unrestricted/thesis.pdf.
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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.
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Staunstrup, Jørgen. "A formal approach to hardware design /." Boston [u.a.] : Kluwer Acad. Publ, 1994. http://www.loc.gov/catdir/enhancements/fy0820/93043582-d.html.
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He, Ji. "Formal specification and analysis of digital hardware circuits in LOTOS." Thesis, University of Stirling, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.322097.
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Layzell, Paul. "Hardware evolution : on the nature of artificially evolved electronic circuits." Thesis, University of Sussex, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.393208.
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Dutta, Sumit Ph D. Massachusetts Institute of Technology. "Magnetic logic circuits with high bit resolution for hardware acceleration." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/111997.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 109-120).
The ever-increasing demand for high-performance and low-power computing warrants an investigation of technologies beyond conventional digital transistor circuits. We explore a logic device based on magnetic domain walls, which are electrically movable boundaries between oppositely magnetized domains of a wire, for applications to hardware acceleration. A domain wall logic device takes current on the input, which moves a magnetic domain wall to a position in a ferromagnetic wire, and this position is the nonvolatile data token read as an output current through a magnetic tunnel junction. The spatial resolution of discrete magnetic domain wall positions in domain wall logic devices is studied to guide memory and logic applications. Theory, numerical modeling, and experiments on in-plane and perpendicularly magnetized materials demonstrate that the bit resolution, or analog information capacity, of a magnetic nanowire with a single domain wall is limited by the self-affine statistics of the wire edge roughness. The domain wall logic device is extended further into functional design implementations, including a logic-in-memory architecture to perform deep convolutional neural network operations in a hybrid process with magnetic devices and 45 nm CMOS. A 3-terminal magnetic logic device is designed to have a 3-bit resolution, and is used in conjunction with transistors in circuit designs for an ecient logic-in-memory system that can process convolutional neural networks 10 faster than conventional digital CMOS implementations.
by Sumit Dutta.
Ph. D.
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Gohil, Nikhil N. "Design of DPA-Resistant Integrated Circuits." University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1516622822794541.
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Pietkiewicz-Koutny, Marta. "Relating formal models of concurrency for the modelling of asynchronous digital hardware." Thesis, University of Newcastle Upon Tyne, 2000. http://hdl.handle.net/10443/1817.
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This Thesis investigates formal models of concurrency that are often used in the process of the design of asynchronous circuits, namely transition systems and Petri nets. The aim of the Thesis is to relate various classes of transition systems and nets, so that different models can be used at different design stages. We characterise three classes of transition systems: the sequential Semi-elementary Transition Systems, and two classes of step transition systems, where arcs are labelled by sets of concurrently executed events: TSENI and TSENIapost Transition Systems. All three classes can be employed to describe the behaviour of safe Petri nets used in circuit design. Semi-elementary Transition Systems are generated by Semi-elementary Net Systems, which are basically Elementary Net Systems with added self-loops. TSENI (TSENIapost ) Transition Systems are step transition systems generated by Elementary Net Systems with Inhibitor Arcs executed according to the a- priori (resp. a-posteriori) semantics, and called ENI-systems (resp. ENIapost -systems). The relationship between each class of transition systems and nets is established via the notion of a region in the process of solving the synthesis problem for the appropriate class of nets. The Thesis compares the three classes of transition systems and gives examples of their use in the specification of asynchronous circuits behaviour.
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Hu, Jhy-Fang 1961. "AUTOMATIC HARDWARE COMPILER FOR THE CMOS GATE ARRAY." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/276948.
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Patel, Mayank Raman. "HARDWARE COMPILER DRIVEN HEURISTIC SEARCH FOR DIGITAL IC TEST SEQUENCES." Thesis, The University of Arizona, 1985. http://hdl.handle.net/10150/275246.
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Stamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
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The introduction of new technologies such as Field Programmable Gate Arrays (FPGAs) with high gate counts and embedded memory Applications Specific Integrated Circuits (ASICs) gives greater scope to the design of computer graphics hardware. This thesis investigates the features of the current generation of FPGAs and complex programmable logic devices (CPLD) and assesses their suitability as replacements for ASIC technologies, and as prototyping tools for their verification prior to fabrication. The traditional methodologies and techniques used for digital systems are examined for application to FPGA devices and novel design flow and implementation techniques are proposed. The new methodology and design flow uses a contemporary top down approach using hardware description languages and combines the flexibility of those methods with the efficiency of detailed low level design techniques. As an example of this methodology, a set of floating point arithmetic units consisting of a adder/subtraction, multiplication and division were designed using novel alternative algorithms that significantly outperformed algorithms designed with traditional methods in terms of both size and performance.T hese techniquesu sed were used to form a ToolKit that can accelerateth e design of systems that use floating point units for computer graphics systems. This ToolKit, in combination with a precision investigation methods can be used to generate floating point arithmetic units that have the required precision with minimum required hardware resources. Another emerging technology is that of embedded memory. Recent advancements in semiconductor fabrication processes make it feasible to integrate large amounts of DRAM, SRAM and logic on a single silicon die. This thesis will show the changes in the design flow that are require to take advantage of this new technology. A new embedded logic ToolKit was created that facilitates the exploitation of this technology. Finally, as an example to this methodology, a novel processor oriented towards 3D graphics was designedA. n architecturale xploration driven by novel trace-drivenp erformancea nalysism ethods is detailed that was used to model and tune the processor for the execution of global illumination computer graphics algorithms. The adaptation of these algorithms for execution in our processor is demonstrateda nd the performancea dvantagesth at can be extracteda re shown
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Ryan, Christopher A. "Parallel hardware accelerated switch level fault simulation." Diss., This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-10022007-145318/.
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Kuyucu, Tuze. "Evolution of circuits in hardware and the evolvability of artificial development." Thesis, University of York, 2010. http://etheses.whiterose.ac.uk/1020/.
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Automatic design of digital electronic circuits via evolutionary algorithms is a promising area of research. When evolved intrinsically on real hardware, evolved circuits are guaranteed to work and the emergence of novel and unconventional circuits is likely. However, evolution of digital circuits on real hardware can cause various reliability issues. Thus, key mechanisms that produce reliable evolution of digital circuits on a hardware platform are developed and explained in the first part of this thesis. On the other hand, the evolution of complex and scalable designs without any assistance is thwarted due to increasingly large genomes. Using traditional circuit design knowledge to assist evolutionary algorithms, the evolution of scalable circuits becomes feasible, but the results found in such experiments are neither novel anymore nor are they competitive with engineered designs. A novel, biologically inspired gene regulatory network based multicellular artificial developmental model is introduced in this thesis. This developmental model is evolved to build digital circuits that can automatically scale to larger designs. However, the results achieved still remain inferior to engineered digital circuit designs. Evolving a developmental system for the design of engineering systems or computational paradigms provides a variety of desirable properties, such as fault tolerance, adaptivity, and scalable designs automation. However, developmental systems in their role as computational networks are as yet poorly understood. Many mechanisms and parameters that a developmental system comprises are based on various assumptions, their biological counterparts, or educated guesses. There is a lack of understanding of the roles of these mechanisms and parameters in forming an evolvable platform for evolutionary computation. Initially, various experiments are shown to demonstrate the evolvability of the new developmental system. A thorough investigation is then undertaken in order to obtain large amounts of empirical data that yields a better understanding of some of the crucial developmental mechanisms and parameters on the evolvability of multicellular developmental systems.
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Meana, Richard William Piper. "Approximate Sub-Graph Isomorphism For Watermarking Finite State Machine Hardware." Scholar Commons, 2013. http://scholarcommons.usf.edu/etd/4728.
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We present a method of mitigating theft of sequential circuit Intellectual Property hardware designs through means of watermarking. Hardware watermarking can be performed by selectively embedding a watermark in the state encoding of the Finite State Machine. This form of watermarking can be achieved by matching a directed graph representation of the watermark with a sub-graph in state transition graph representation of the FSM. We experiment with three approaches: a brute force method that provides a proof of concept, a greedy algorithm that provides excellent runtime with a drawback of sub-optimal results, and finally a simulated annealing method that provides near optimal solutions with runtimes that meet our performance goals. The simulated annealing approach when applied on a ten benchmarks chosen from IWLS 93 benchmark suite, provides watermarking results with edge overhead of less than 6% on average with runtimes not exceeding five minutes.
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Kim, Kwanghyun. "An expert system for self-testable hardware design." Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54216.
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BIDES (A BIST Design Expert System) is an expert system for incorporating BIST into a digital circuit described with VHDL. BIDES modifies a circuit to produce a self-testable circuit by inserting BIST hardware such as pseudorandom pattern generators and signature analysis registers. In inserting BIST hardware, BIDES not only makes a circuit self-testable, but also incorporates the appropriate type of BIST structure so that a set of user-specified constraints on hardware overhead and testing time can be satisfied. This flexibility comes from the formulation of the BIST design problem as a search problem. A satisfactory BIST structure is explored through an iterative process of evaluation and regeneration of BIST structure. The process of regeneration is performed by a problem solving technique called hierarchical planning. In order to apply a hierarchical planning technique, we introduce an abstraction hierarchy in BIST design. Using the abstraction hierarchy, the knowledge of the BIST design process is represented with several operators defined on the abstraction levels. This type of knowledge representation in conjunction with hierarchical planning led to an easy implementation of the system and results in an easily modifiable system.
In this dissertation, we also study a BIST scheme called cascade testing. ln cascade testing, a signature analysis register is used concurrently as a test pattern generator in order to reduce the overall testing time by improving testing parallelism. The characteristics of the patterns generated by the signature analysis register are investigated through analysis as well as experiments. lt is shown that the patterns generated by signature analysis registers are rarely repeated when the number of patterns generated is relatively small compared to the number of all possible patterns. It is also shown that the patterns generated by signature analysis registers are almost random. Therefore, signature analysis registers can be used effectively as pseudorandom pattern generators. The practicality of cascade testing is investigated by fault simulation experiments using an example circuit.Ph. D.
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Goulart, Sobrinho Edilton Furquim [UNESP]. "Uma ferramenta alternativa para síntese de circuitos lógicos usando a técnica de circuito evolutivo." Universidade Estadual Paulista (UNESP), 2007. http://hdl.handle.net/11449/87253.
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Neste trabalho descreve-se uma metodologia para síntese e otimização de circuitos digitais, usando a teoria de algoritmos evolutivos e como plataforma os dispositivos reconfiguráveis, denominada Hardware Evolutivo do inglês- Evolvable Hardware - EHW. O EHW, tornou-se viável com o desenvolvimento em grande escala dos dispositivos reconfiguráveis, Programmable Logic Devices (PLD s), cuja arquitetura e função podem ser determinadas por programação. Cada circuito pode ser representado como um indivíduo em um processo evolucionário, evoluindo-o através de operações genéticas para um resultado desejado. Como algoritmo evolutivo, aplicou-se o Algoritmo Genético (AG), uma das técnicas da computação evolutiva que utiliza os conceitos da genética e seleção natural. O processo de síntese aplicado neste trabalho, inicia por uma descrição do comportamento do circuito, através de uma tabela verdade para circuitos combinacionais e a tabela de estados para os circuitos seqüenciais. A técnica aplicada busca o arranjo correto e minimizado do circuito que desempenhe uma função proposta. Com base nesta metodologia, são implementados alguns exemplos em duas diferentes representações (mapas de fusíveis e matriz de portas lógicas).
In this work was described a methodology for optimization and synthesis of digital circuits, which consist of evolving circuits through evolvable algorithms using as platforms reconfigurable devices, denominated Evolvable Hardware (EHW). It was became viable with the large scale development of reconfigurable devices, whose architecture and function can be determined by programming. Each circuit can be represented as an individual within an evolutionary process, evolving through genetic operations to desire results. Genetic Algorithm (GA) was applied as evolutionary algorithm where this technique evolvable computation as concepts of genetics and natural selection. The synthesis process applied in this work starts from a description from the circuits behavior. Trust table for combinatorial circuits and state transition table for sequential circuits were used for synthesis process. This technic applied search the correct arrange and minimized circuit which response the propose function. Based on this methodology, some examples are implemented in two different representations (fuse maps and logic gate matrices).
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Tobar, Edgar Leonardo Romero. "Contribuições à verificação funcional ajustada por cobertura para núcleos de hardware de comunicação e multimídia." Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-20082010-160736/.
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Tornar a verificação funcional mais eficiente, em termos de gasto de recursos de computação e tempo, é necessário para a contínua evolução dos sistemas digitais. A verificação funcional com geração de casos de teste aleatória ajustada por cobertura é uma das alternativas identificadas nos últimos anos para acelerar a execução de testbenches. Várias abordagens têm sido testadas com sucesso na verificação funcional de núcleos de hardware, no domínio de aplicação dos processadores de propósito geral, porém, influenciada por características específicas do domínio, dos modelos de cobertura e do espaço possível de casos de teste. Por outro lado, pouca atenção tem sido dispensada à verificação ajustada por cobertura em outros domínios de aplicação como nos de sistemas de comunicação e de sistemas multimídia. Estes casos são tratados no presente estudo, com os fatores específicos que influenciam os resultados dos testbenches com geração ajustada. Entre os fatores relevantes para isto, foram identificados o tamanho do espaço de casos de teste e a distribuição da ocorrência dos eventos de cobertura, sendo necessária para o desenvolvimento do presente trabalho, a realização de várias alterações na construção de testbenches com ajuste. A geração de casos de teste ajustada por cobertura é realizada a partir da realimentação da informação do estado da cobertura, para se determinar os casos de teste necessários para tornar o progresso da cobertura mais rápido. Esta realimentação depende da criação, por aprendizado automático, de modelos que relacionem os casos de teste com as ocorrências dos eventos de cobertura. Com núcleos de hardware realistas e de grande porte, neste trabalho, foram aplicadas as técnicas de aprendizado de redes Bayesianas e data mining com árvores de classificação, já utilizados em outras pesquisas mais específicas. Estas técnicas se caracterizam por requerer processos de maximização local para seu funcionamento. Neste trabalho, foi avaliada também a adoção da técnica de Support Vector Machine (SVM), por se basear em um processo de maximização global. Os resultados demonstram que as técnicas de geração de casos de teste ajustadas por cobertura precisam ser adaptadas às características do domínio de aplicação, para conseguir acelerar a execução dos testbenches.Making functional verification more efficient in terms of computational and time resources is mandatory in order to maintain the evolution of digital systems. Coverage driven verification is one of the recently used alternatives for speeding up the execution of testbenches. Many approaches have been successfully applied to the functional verification of cores in the application domain of general purpose processors, however, being influenced by the specific coverage and testcase dimensionality characteristics of this domain. Furthermore, little attention has been given to the use of coverage driven verification in other domains, such as communication systems and multimedia systems. These domains have been considered in the present study, together with the specific factors that have influenced the coverage driven testbench results. Among these factors, one has identified the size of the testcase space and the distribution of the coverage events; making it necessary to the development of this work, several changes regarding the construction of the coverage driven testbenches. Coverage driven testecase generation is performed by feedbacking the coverage status information and selecting those testcases that lead to the improvement of the coverage progression rate. This feedback depends on the construction of a model, by automatic learning, which relates testcases and the observations of coverage events. During this work, realistic large IP cores were verified with the following coverage driven techniques: Bayesian networks and classification tree data mining. These techniques, previously used in specific research works, adopt local optimization in their processing. In the present work, coverage driven verification with support vector machine learning, is tested due to the fact that this technique is based in a global optimization process. Results of this work have shown the need of adaptation of the coverage driven verification to the application domain characteristics, in order to obtain meaningful acceleration in testbench execution.
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Cozzi, Maxime. "Infrared Imaging for Integrated Circuit Trust and Hardware Security." Thesis, Montpellier, 2019. http://www.theses.fr/2019MONTS046.
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La généralisation des circuits intégrés et plus généralement de l'électronique à tous les secteurs d'activité humaine, nécessite d'assurer la sécurité d'un certain nombre de systèmes critiques (militaire, finance, santé, etc). Aujourd'hui, l'intégrité de ces systèmes repose sur un éventail d'attaques connues, pour lesquelles des contremesures ont été développées.Ainsi, la recherche de nouvelles attaques contribue fortement à la sécurisation des circuits électroniques. La complexité toujours croissante des circuits, permise par les progrès dans les technologies silicium, a pour conséquence l'apparition de circuits occupant de plus en plus de surface. La retro-ingénierie est donc une étape souvent obligatoire menée en amont d'une attaque afin de localiser les périphériques et autres régions d'intérêts au sein du circuit visé. Dans cet objectif, l'étude présenté dans ce document propose de nouvelles méthodes d'imagerie infrarouge. En particulier, il est démontré que l'analyse statistique des mesures infrarouge permet d'automatiser la localisation des régions électriquement active d'un circuit. Aussi, une nouvelle méthode de comparaison statistique d'image infrarouge est proposée. Enfin, ces résultats sont acquis au moyen d'une plateforme de mesure faible cout, permettant de détecter toute activité électrique possédant une consommation supérieure à 200µWThe generalization of integrated circuits and more generally electronics to everyday life systems (military, finance, health, etc) rises the question about their security. Today, the integrity of such circuits relies on a large panel of known attacks for which countermeasures have been developed. Hence, the search of new vulnerabilities represents one of the largest contribution to hardware security. The always rising complexity of dies leads to larger silicon surfaces.Circuit imaging is therefore a popular step among the hardware security community in order to identify regions of interest within the die. In this objective, the work presented here proposes new methodologies for infrared circuit imaging. In particular, it is demonstrated that statistical measurement analysis can be performed for automated localization of active areas in an integrated circuit.Also, a new methodology allowing efficient statistical infrared image comparison is proposed. Finally, all results are acquired using a cost efficient infrared measurement platform that allows the investigation of weak electrical source, detecting power consumption as low as 200 µW
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Taesopapong, Somboon. "A VLSI-nMOS hardware implementation of a high speed parallel adder." Ohio : Ohio University, 1986. http://www.ohiolink.edu/etd/view.cgi?ohiou1183379787.
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Láník, Jan. "La réduction de consommation dans les circuits digitaux." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAM016/document.
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Le sujet de cette thèse est la réduction de consommation dans les circuits digitaux, et plus particulièrement dans ce cadre les méthodes basées sur la réduction de la fréquence de commutation moyenne, au niveau transistor. Ces méthodes sont structurelles, au sens où elles ne sont pas liées à l’optimisation des caractéristiques physique du circuit mais sur la structure de l’implémentation logique, et de ce fait parfaitement indépendantes de la technologie considérée. Nous avons développé dans ce cadre deux méthodes nouvelles. La première est basée sur l’optimisation de la structure de la partie combinatoire d’un circuit pendant la synthèse logique. La seconde est centrée sur la partie séquentielle du circuit. Elle consiste en la recherche de conditions permettant de détecter qu’un sous-circuit devient inactif, de sorte à pouvoir désactiver ce sous-circuit en coupant la branche correspondante de l’arbre d’horloge, et utilise des méthodes formelles pour prouver que la fonctionnalité du circuit n’en serait pas affectéeThe topic of this thesis are methods for power reduction in digital circuits by reducing average switching on the transistor level. These methods are structural in the sense that they are not related to tuning physical properties of the circuitry but to the internal structure of the implemented logic an d therefore independent on the particular technology. We developed two novel methods. One is based on optimizing the structure of the combinatorial part of a circuit during synthesis. The second method is focused on sequential part of the circuit. It looks for clock gating conditions that can be used to disable idle parts of a circuit and uses formal methods to prove that the function of the circuit will not be altered
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Chenard, Jean-Samuel. "Hardware-based temporal logic checkers for the debugging of digital integrated circuits." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106282.
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Integrated circuit complexity is ever increasing and the debug process of modern devices pose important technical challenges and cause delays in production. A comprehensive Design-for-Debug methodology is therefore rapidly becoming a necessity. This thesis presents a comprehensive system-level approach to debugging based on insilicon hardware checkers. The proposed approach leverages existing assertion-based verification libraries by translating useful temporal logic statements into efficient hardware circuits. Those checker circuits are then integrated in the device as part of the memory map, so they can provide on-line monitoring and debug assistance in addition to accelerating the integration of performance monitoring counters. The thesis presents a set of enhancements to the translation process from temporal language to hardware, targeted such that an eventual debug process is made more efficient. Automating the integration of the checker's output and control structures is covered along with a practical method that allow transparent access to the resulting registers within a modern (Linux) operating system. Finally, a method of integration of the hardware checkers in future Network-on-Chip systems is proposed. The use of a quality metric encompassing test, monitoring and debug considerations is defined along with the necessary tool flow required to support theprocess.La complexité des circuits intégrés augmente sans cesse et à un tel point que le procéssus de déboggage pose de nombreux problèmes techniques et engendre des retards dans la production. Une approche d'ensemble de conception pour le déboggage (Design-for-Debug) devient donc rapidement une nécessité. Cette thèse propose une approche détaillée de niveau système, intégrant des circuits de surveillance sur puce. L'approche proposée s'appuie sur la réutilisation de déclarations écrites en language de logique temporelle afin de les transformer en circuits digitaux efficaces. Ces derniers seront intégrés à la puce à travers son interface d'image mémoire afin qu'ils puissent servir au processus de déboggage ainsi qu'à une utilisation dans le système lorsque la puce est intégrée dans son environement. Cette thèse présente une série d'ajout au procéssus de transformation d'instructions de logique temporelle de manière à faciliter le procéssus de déboggage. Une méthode qui automatise l'intégration des sorties et du contrôle des circuits de surveillance est présentée ainsi que la manière dont une utilisation de ces circuits peut être accomplie dans le contexte d'un système d'exploitation moderne (Linux). Finalement, une méthode globale d'intégration des circuits de vérification dans le contexte de systèmes basés sur les réseaux-sur-puce est présentée, accompagnée de la chaine d'outils requise pour supporter ce nouveau processus de conception. Cette méthode propose l'utilisation de facteurs de qualité de test, de surveillance et de déboggage (Test, Monitoring and Debug) permettant une meilleure sélection des circuits ainsi qu'une intégration plus efficace au niveau des resources matérielles.
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Batts, William Merle. "Modeling of a hardware VLSI placement system : accelerating the simulated annealing algorithm /." Link to online version, 2005. https://ritdml.rit.edu/dspace/handle/1850/1015.
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Khairullah, Shawkat Sabah. "Toward Biologically-Inspired Self-Healing, Resilient Architectures for Digital Instrumentation and Control Systems and Embedded Devices." VCU Scholars Compass, 2018. https://scholarscompass.vcu.edu/etd/5671.
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Digital Instrumentation and Control (I&C) systems in safety-related applications of next generation industrial automation systems require high levels of resilience against different fault classes. One of the more essential concepts for achieving this goal is the notion of resilient and survivable digital I&C systems. In recent years, self-healing concepts based on biological physiology have received attention for the design of robust digital systems. However, many of these approaches have not been architected from the outset with safety in mind, nor have they been targeted for the automation community where a significant need exists. This dissertation presents a new self-healing digital I&C architecture called BioSymPLe, inspired from the way nature responds, defends and heals: the stem cells in the immune system of living organisms, the life cycle of the living cell, and the pathway from Deoxyribonucleic acid (DNA) to protein. The BioSymPLe architecture is integrating biological concepts, fault tolerance techniques, and operational schematics for the international standard IEC 61131-3 to facilitate adoption in the automation industry. BioSymPLe is organized into three hierarchical levels: the local function migration layer from the top side, the critical service layer in the middle, and the global function migration layer from the bottom side. The local layer is used to monitor the correct execution of functions at the cellular level and to activate healing mechanisms at the critical service level. The critical layer is allocating a group of functional B cells which represent the building block that executes the intended functionality of critical application based on the expression for DNA genetic codes stored inside each cell. The global layer uses a concept of embryonic stem cells by differentiating these type of cells to repair the faulty T cells and supervising all repair mechanisms. Finally, two industrial applications have been mapped on the proposed architecture, which are capable of tolerating a significant number of faults (transient, permanent, and hardware common cause failures CCFs) that can stem from environmental disturbances and we believe the nexus of its concepts can positively impact the next generation of critical systems in the automation industry.
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Bodnar, Michael Richard. "The implementation of a hardware accelerator for the full-wave analysis of electronic circuits." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 63 p, 2007. http://proquest.umi.com/pqdweb?did=1338919461&sid=3&Fmt=2&clientId=8331&RQT=309&VName=PQD.
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Koelmans, Albertus Maria. "STRICT : a language and tool set for the design of very large scale integrated circuits." Thesis, University of Newcastle Upon Tyne, 1996. http://hdl.handle.net/10443/2076.
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An essential requirement for the design of large VLSI circuits is a design methodology which would allow the designer to overcome the complexity and correctness issues associated with the building of such circuits. We propose that many of the problems of the design of large circuits can be solved by using a formal design notation based upon the functional programming paradigm, that embodies design concepts that have been used extensively as the framework for software construction. The design notation should permit parallel, sequential, and recursive decompositions of a design into smaller components, and it should allow large circuits to be constructed from simpler circuits that can be embedded in a design in a modular fashion. Consistency checking should be provided as early as possible in a design. Such a methodology would structure the design of a circuit in much the same way that procedures, classes, and control structures may be used to structure large software systems. However, such a design notation must be supported by tools which automatically check the consistency of the design, if the methodology is to be practical. In principle, the methodology should impose constraints upon circuit design to reduce errors and provide' correctness by construction' . It should be possible to generate efficient and correct circuits, by providing a route to a large variety of design tools commonly found in design systems: simulators, automatic placement and routing tools, module generators, schematic capture tools, and formal verification and synthesis tools.
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Ahmed, Mohammad Abrar. "Early Layout Design Exploration in TSV-based 3D Integrated Circuits." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3617.
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Through silicon via (TSV) based 3D integrated circuits have inspired a novel design paradigm which explores the vertical dimension, in order to alleviate the performance and power limitations associated with long interconnects in 2D circuits. TSVs enable vertical interconnects across stacked and thinned dies in 3D-IC designs, resulting in reduced wirelength, footprint, faster speed, improved bandwidth, and lesser routing congestion. However, the usage of TSVs itself gives rise to many critical design challenges towards the minimization of chip delay and power consumption. Therefore, realization of the benefits of 3D ICs necessitates an early and realistic prediction of circuit performance during the early layout design stage.
The goal of this thesis is to meet the design challenges of 3D ICs by providing new capabilities to the existing floorplanning framework [87]. The additional capabilities included in the existing floorplanning tool is the co-placement of TSV islands with circuit blocks and performing non-deterministic assignment of signals to TSVs. We also replace the wirelength and number of TSVs in the floorplanning cost function with the total delay in the nets. The delay-aware cost function accounts for RC delay impact of TSVs on the delay of individual signal connection, and obviates the efforts required to balance the weight contributions of wirelength and TSVs in the wirelength-aware floorplanning. Our floorplanning tool results in 5% shorter wirelength and 21% lesser TSVs compared to recent approaches. The delay in the cost function improves total delay in the interconnects by 10% - 12% compared to wirelength-aware cost function.
The influence of large coupling capacitance between TSVs on the delay, power and coupling noise in 3D interconnects also offers serious challenges to the performance of 3D-IC. Due to the degree of design complexity introduced by TSVs in 3D ICs, the importance of early stage evaluation and optimization of delay, power and signal integrity of 3D circuits cannot be ignored. The unique contribution of this work is to develop methods for accurate analysis of timing, power and coupling noise across multiple stacked device layers during the floorplanning stage. Incorporating the impact of TSV and the stacking of multiple device layers within floorplanning framework will help to achieve 3D layouts with superior performance.
Therefore, we proposed an efficient TSV coupling noise model to evaluate the coupling noise in the 3D interconnects during floorplanning. The total coupling noise in 3D interconnects is included in the cost function to optimize positions of TSVs and blocks, as well as nets-to-TSVs assignment to obtain floorplans with minimized coupling noise. We also suggested diagonal TSV arrangement for larger TSV pitch and nonuniform pitch arrangement for reducing worst TSV-to-TSV coupling, thereby minimizing the coupling noise in the interconnects.
This thesis also focuses on more realistic evaluation and optimization of delay and power in TSV based 3D integrated circuits considering the interconnect density on individual device layers. The floorplanning tool uses TSV locations and delay, non-uniform interconnect density across multiple stacked device layers to assess and optimize the buffer count, delay, and interconnect power dissipation in a design. It is shown that the impact of non-uniform interconnect density, across the stacked device layers, should not be ignored, as its contribution to the performance of the 3D interconnects is consequential.
A wire capacitance-aware buffer insertion scheme is presented that determines the optimal distance between adjacent buffers on the individual device layers for nonuniform wire density between stacked device layers. The proposed approach also considers TSV location on a 3D wire to optimize the buffer insertion around TSVs. For 3D designs with uniform wire density across stacked device layers, we propose a TSV-aware buffer insertion approach that appropriately models the TSV RC delay impact on interconnect delay to determine the optimum interval between adjacent buffers for individual 3D nets. Moreover, our floorplanning tool help achieve 3D layouts with superior performance by incorporating the impact of nonuniform density on the delay, power and coupling noise in the interconnects during floorplanning.
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Chu, Ming-Cheung. "Hazard detection with VHDL in combinational logic circuits with fixed delays." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020040/.
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Andrade, Junior Antonio de Quadros. "Planejamento de teste de sistemas baseados em núcleos de hardware de sinal misto usando bist." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/8296.
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Atualmente, os sistemas eletrônicos integrados seguem o paradigma do projeto baseado em núcleos de hardware. Além de núcleos digitais, tais sistemas podem incluir núcleos analógicos, que, neste caso, dominam os requisitos de teste, como tempo de teste e número adicional de pinos. Consequentemente, há um aumento do custo total de manufatura do dispositivo. O presente trabalho propõe o uso de técnicas de autoteste integrado (BIST) analógico, baseado no reuso de núcleos digitais presentes no mesmo sistema, com objetivo de reduzir os custos relativos ao teste do sistema. Além disso, uma estratégia satisfatória requer um adequado planejamento de teste, de forma a melhor explorar as possibilidades de teste simultâneo de mais de um núcleo e o escalonamento do teste de cada um destes, diminuindo custos associados ao teste. Adaptando uma ferramenta computacional voltada ao planejamento de sistemas compostos exclusivamente de núcleos digitais para o universo dos sistemas mistos e considerando a possibilidade do uso de BIST, pode-se avaliar o impacto da estratégia proposta em termos de tempo de teste, acréscimo de área em virtude das estruturas de teste e pinos extras. Restrições de dissipação de potência também são consideradas. Para validação das hipóteses levantadas, sistemas mistos foram descritos a partir de benchmarks industriais e acadêmicos puramente digitais, através da inclusão de núcleos analógicos. Os resultados obtidos através de simulações com a ferramenta apontam para uma redução no tempo de teste e otimização de custos de pinos e área, além da redução no custo de equipamentos automatizados de teste (ATE), para o caso de teste de produção. Com isso, uma redução no custo total do procedimento de teste de tais sistemas pode ser alcançada.Currently, integrated electronic systems follow the core-based design paradigm. Such systems include not only digital circuits as internal blocks, but also analog circuits, which dominate test resources, such as testing time, extra pins and overhead area, thus increasing the total manufacture cost of these devices. The present work proposes the application of analog Built-in Self Test (BIST) techniques based on the reuse of available digital cores within the same integrated system, aiming to reduce the test costs of the analog cores. Moreover, a satisfactory strategy requires an adequate test planning, so that the design space is better explored. By adapting a software tool, which was originally designed for test planning of exclusively digital SOC, to consider analog cores, as well as the possibility of BIST, one can evaluate the impact of the proposed strategy in terms of test application time, area overhead due to test structures added and extra pins. Power dissipation restrictions may also be taken into account. In order to validate the hypotheses considered, mixed-signal systems are described from digital industrial and academic benchmarks, just adding analog cores. Through simulation with the adapted tool, the obtained results point to a decrease in the system test time, as well as a reduction in the cost of Automatic Test Equipment (ATE), in case of a production test. Thus, a reduction in the overall cost of the test procedure for such devices can be achieved.
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Thulasi, Raman Sudheer Ram. "Logic Encryption of Sequential Circuits." University of Cincinnati / OhioLINK, 2019. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1553251689992143.
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Ba, Papa-Sidy. "Détection et prévention de Cheval de Troie Matériel (CTM) par des méthodes Orientées Test Logique." Thesis, Montpellier, 2016. http://www.theses.fr/2016MONTT271/document.
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Pour réduire le coût des Circuits Intégrés (CIs), les entreprises de conception se tournent de plus en plus vers des fonderies basées dans des pays à faible coût de production (outsourcing). Cela a pour effet d’augmenter les menaces sur les circuits. En effet, pendant la fabrication,le CI peut être altéré avec l’insertion d’un circuit malicieux, appelé cheval de Troie Matériel (CTM). Ceci amène les vendeurs de CI à protéger leurs produits d’une potentielle insertion d’un CTM, mais également, d’en assurer l’authenticité après fabrication (pendant la phase de test).Cependant, les CTMs étant furtifs par nature, il est très difficile, voire impossible de les détecter avec les méthodes de test conventionnel, et encore moins avec des vecteurs de test aléatoires. C’est pourquoi nous proposons dans le cadre de cette thèse, des méthodes permettant de détecter et de prévenir l’insertion de CTM dans les CIs pendant leur fabrication.Ces méthodes utilisent des approches orientées test logique pour la détection de CTM aussi bien en phase de test (après fabrication du CI) qu’en fonctionnement normal (run-time).De plus, nous proposons des méthodes de prévention qui elles aussi s’appuient sur des principes de test logique pour rendre difficile, voire impossible l’insertion de CTM aussi bien au niveau netlist qu’au niveau layoutIn order to reduce the production costs of integrated circuits (ICs), outsourcing the fabrication process has become a major trend in the Integrated Circuits (ICs) industry. As an inevitable unwanted side effect, this outsourcing business model increases threats to hardware products. This process raises the issue of un-trusted foundries in which, circuit descriptions can be manipulated with the aim to possibly insert malicious circuitry or alterations, referred to as Hardware Trojan Horses (HTHs). This motivates semiconductor industries and researchers to study and investigate solutions for detecting during testing and prevent during fabrication, HTH insertion.However, considering the stealthy nature of HTs, it is quite impossible to detect them with conventional testing or even with random patterns. This motivates us to make some contributions in this thesis by proposing solutions to detect and prevent HTH after fabrication (during testing).The proposed methods help to detect HTH as well during testing as during normal mode(run-time), and they are logic testing based.Furthermore, we propose prevention methods, which are also logic testing based, in order tomake harder or quasi impossible the insertion of HTH both in netlist and layout levels
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Taber, Caleb N. "Conversion of Digital Circuits Labs." Digital Commons @ East Tennessee State University, 2016. https://dc.etsu.edu/honors/395.
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The engineering technology department at ETSU currently lacks a modern method to teach digital circuits. The aim of this thesis is to convert our current digital circuits labs to equivalent labs suited to run on the Basys 3. The Basys has several advantages over the aging NI Elvis boards (and now just breadboards) currently in use. The first advantage is that the Basys gives students a taste of FPGA programming without being overwhelmingly; like the systems currently in place for the digital signal processing class. The Basys is also a more modern system; our current integrated circuit and breadboard system is from the 70’s and has little to do with the modern world of electronics.
There are several major difficulties with moving towards the Basys 3. It requires several tweaks to the current computer security setting of the lab computers. The other issue to be solved is that very few people in the department have even an inkling of how to program in VHDL and most of them are outgoing students. This lack of skills could be a threat to the class but I have included an appendix and a few recommendations for books on the subject to ensure that system development can continue.
The other objective of this project was to see if there were ways to incorporate new educational techniques into the engineering technology curriculum. While there have been no actual tests on students, the groundwork has been laid to use some new ideas in the classroom. All of these new systems are designed to get students to think about how devices actually work and develop models to help them fully understand what is being taught.
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Zaveri, Jainish K. "Asic Design of RF Energy Harvester Using 0.13UM CMOS Technology." DigitalCommons@CalPoly, 2018. https://digitalcommons.calpoly.edu/theses/1940.
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Recent advances in wireless sensor nodes, data acquisition devices, wearable and implantable medical devices have paved way for low power (sub 50uW) devices. These devices generally use small solid state or thin film batteries for power supply which need replacement or need to be removed for charging. RF energy harvesting technology can be used to charge these batteries without the need to remove the battery from the device, thus providing a sustainable power supply. In other cases, a battery can become unnecessary altogether. This enables us to deploy wireless network nodes in places where regular physical access to the nodes is difficult or cumbersome.
This thesis proposes a design of an RF energy harvesting device able to charge commercially available thin film or solid-state batteries. The energy harvesting amplifier circuit is designed in Global Foundry 0.13um CMOS technology using Cadence integrated circuit design tools. This Application Specific Integrated Circuit (ASIC) is intended to have as small a footprint as possible so that it can be easily integrated with the above-mentioned devices. While a dedicated RF power source is a direct solution to provide sustainable power to the harvesting circuit, harvesting ambient RF power from TV and UHF cellular frequencies increases the possibilities of where the harvesting device can be placed. The biggest challenge for RF energy harvesting technology is the availability of adequate amount of RF power. This thesis also presents a survey of available RF power at various ultra-high frequencies in San Luis Obispo, CA.The idea is to determine the frequency band which can provide maximum RF power for harvesting and design a harvester for that frequency band.
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Moseley, Ralph. "Transcending static deployment of circuits : dynamic run-time systems and mobile hardware processes for FPGAs." Thesis, University of Kent, 2002. https://kar.kent.ac.uk/13733/.
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The usefulness of reconfigurable hardware has been shown in research and commercial applications. Unquestionably, this has and will lead to, unique avenues of thought within computer science being explored. The interest by researchers in some specific areas has led to manufacturers developing devices which were enhanced in their ability to dynamically be configured within a run-time context. These improvements are on-going and rapid progress is being made, producing high density, system-on-a-chip capable devices, with fast run-time reconfiguration. The advancements in this technology have particularly led to a convergence between software and hardware domains, in the sense that algorithms can be implemented in either; the choice being dependent only in terms of efficiency within the medium itself. Older methods for development with these devices have become rapidly dated and inflexible. Very few suitable tools exist, for example, which are capable of fully utilising the inherent capabilities of such hardware. The approach taken here allows the division between hardware and software to be diminished. Component designs, which may be hardware description language (HDL) based or synthesised algorithms, become easily manipulated and interacted with through a run-time engine, that can deploy elements at will to local or distributed devices. Such entities are essentially hybrid in nature, possessing both hardware and software functionality. These processes are sufficiently self-supporting, to be capable of being used outside of the run-time system within a normal Java development environment. This work explores how hardware entities can become as dynamic as memory based algorithms within conventional von Neumann based systems, providing the means for extending the software programming paradigm into such areas. It analyses the possibilities of applying object-oriented and occam/Communicating Sequential Processes (CSP) based concurrency philosophies to these highly mobile, hardware processes.
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Schaeffer, Ben. "Synthesis of Linear Reversible Circuits and EXOR-AND-based Circuits for Incompletely Specified Multi-Output Functions." PDXScholar, 2017. https://pdxscholar.library.pdx.edu/open_access_etds/3783.
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At this time the synthesis of reversible circuits for quantum computing is an active area of research. In the most restrictive quantum computing models there are no ancilla lines and the quantum cost, or latency, of performing a reversible form of the AND gate, or Toffoli gate, increases exponentially with the number of input variables. In contrast, the quantum cost of performing any combination of reversible EXOR gates, or CNOT gates, on n input variables requires at most O(n2/log2n) gates. It was under these conditions that EXOR-AND-EXOR, or EPOE, synthesis was developed.
In this work, the GF(2) logic theory used in EPOE is expanded and the concept of an EXOR-AND product transform is introduced. Because of the generality of this logic theory, it is adapted to EXOR-AND-OR, or SPOE, synthesis. Three heuristic spectral logic synthesis algorithms are introduced, implemented in a program called XAX, and compared with previous work in classical logic circuits of up to 26 inputs. Three linear reversible circuit methods are also introduced and compared with previous work in linear reversible logic circuits of up to 100 inputs.
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Imvidhaya, Ming. "VHDL simulation of the implementation of a costfunction circuit." Thesis, Monterey, California : Naval Postgraduate School, 1990. http://handle.dtic.mil/100.2/ADA240430.
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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, September 1990.Thesis Advisor(s): Lee, Chin-Hwa. Second Reader: Butler, Jon T. "September 1990." Description based on title screen as viewed on December 29, 2009. DTIC Identifier(s): Computerized simulation, computer aided design, logic circuits, subroutines, theses, integrated circuits. Author(s) subject terms: VHDL, costfunction, hardware description language. Includes bibliographical references (p. 77). Also available in print.
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Norrod, Forrest Eugene. "The E-algorithm: an automatic test generation algorithm for hardware description languages." Thesis, Virginia Tech, 1988. http://hdl.handle.net/10919/43260.
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Traditional test generation techniques for digital circuits have been rendered inadequate by the increasing levels of integration achieved by VLSI technology. This thesis presents a test generation algorithm, the E-algorithm, that generates tests for circuits described using the VHDL Hardware Description Language. A fault model has been developed that addresses data path faults, faults in control structures, and faults in functional operators. The E-algorithm is able to generate tests for all modeled fault types, and handles a wide variety of circuit types, including sequential circuits. The algorithm has been implemented; preliminary results are given.Master of Science
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Lynch, Elizabeth Whitaker. "Hardware acceleration for conservative parallel discrete event simulation on multi-core systems." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39506.
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Multi-core architectures are becoming more common and core counts continue to increase. There are six- and eight-core chips currently in production, such as Intel Gulftown, and many-core chips with dozens of cores, such as the Intel Teraflops 80-core chip, are projected in the next five years. However, adding more cores often does not improve the performance of applications. It would be desirable to take advantage of the multi-core environment to speed up parallel discrete event simulation. The current bottleneck for many parallel simulations is time synchronization. This is especially true for simulations of wireless networks and on-chip networks, which have low lookahead. Message passing is also a common simulation bottleneck. In order to address the issue of time synchronization, we have designed hardware at a functional level that performs the time synchronization for parallel discrete event simulation asynchronously and in just a few clock cycles, eliminating the need for global communication with message passing or lock contention for shared memory. This hardware, the Global Synchronization Unit, consists of 3 register files, each the size of the number of cores, and is accessed using 5 new atomic instructions. In order to reduce the simulation overhead from message passing, we have also designed two independent pieces of hardware at a functional level, the Atomic Shared Heap and Atomic Message Passing, which can be used to perform lock-free, zero-copy message passing on a multi-core system. The impact of these specialized hardware units on the performance of parallel discrete event simulation is assessed and compared to traditional shared-memory techniques.
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Vamja, Harsh. "Reverse Engineering of Finite State Machines from Sequential Circuits." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1530267556456191.
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Brown, Michelle M. "Hardware study on the H.264/AVC video stream parser /." Online version of thesis, 2008. http://hdl.handle.net/1850/7766.
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Ahderom, Selam T. "Opto-VLSI based WDM multifunction device." Thesis, Edith Cowan University, Research Online, Perth, Western Australia, 2004. https://ro.ecu.edu.au/theses/772.
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The tremendous expansion of telecommunication services in the past decade, in part due to the growth of the Internet, has made the development of high-bandwidth optical net-works a focus of research interest. The implementation of Dense-Wavelength Division Multiplexing (DWDM) optical fiber transmission systems has the potential to meet this demand. However, crucial components of DWDM networks – add/drop multiplexers, filters, gain equalizers as well as interconnects between optical channels – are currently not implemented as dynamically reconfigurable devices. Electronic cross-connects, the traditional solution to the reconfigurable optical networks, are increasingly not feasible due to the rapidly increasing bandwidth of the optical channels. Thus, optically transparent, dynamically reconfigurable DWDM components are important for alleviating the bottleneck in telecommunication systems of the future. In this study, we develop a promising class of Opto-VLSI based devices, including a dynamic multi-function WDM processor, combining the functions of optical filter, channel equalizer and add-drop multiplexer, as well as a reconfigurable optical power splitter. We review the technological options for all optical WDM components and compare their advantages and disadvantages. We develop a model for designing Opto-VLSI based WDM devices, and demonstrate experimentally the Opto-VLSI multi-function WDM device. Finally, we discuss the feasibility of Opto-VLSI WDM components in meeting the stringent requirements of the optical communications industry.
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Ardeishar, Raghu. "Automatic verification of VHDL models." Thesis, This resource online, 1990. http://scholar.lib.vt.edu/theses/available/etd-03032009-040338/.
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Selvakumaran, Dinesh Kumar. "ENERGY-EFFICIENT AND SECURE HARDWARE FOR INTERNET OF THINGS (IoT) DEVICES." UKnowledge, 2018. https://uknowledge.uky.edu/ece_etds/132.
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Internet of Things (IoT) is a network of devices that are connected through the Internet to exchange the data for intelligent applications. Though IoT devices provide several advantages to improve the quality of life, they also present challenges related to security. The security issues related to IoT devices include leakage of information through Differential Power Analysis (DPA) based side channel attacks, authentication, piracy, etc. DPA is a type of side-channel attack where the attacker monitors the power consumption of the device to guess the secret key stored in it. There are several countermeasures to overcome DPA attacks. However, most of the existing countermeasures consume high power which makes them not suitable to implement in power constraint devices. IoT devices are battery operated, hence it is important to investigate the methods to design energy-efficient and secure IoT devices not susceptible to DPA attacks. In this research, we have explored the usefulness of a novel computing platform called adiabatic logic, low-leakage FinFET devices and Magnetic Tunnel Junction (MTJ) Logic-in-Memory (LiM) architecture to design energy-efficient and DPA secure hardware. Further, we have also explored the usefulness of adiabatic logic in the design of energy-efficient and reliable Physically Unclonable Function (PUF) circuits to overcome the authentication and piracy issues in IoT devices.
Adiabatic logic is a low-power circuit design technique to design energy-efficient hardware. Adiabatic logic has reduced dynamic switching energy loss due to the recycling of charge to the power clock. As the first contribution of this dissertation, we have proposed a novel DPA-resistant adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL). EE-SPFAL based circuits are energy-efficient compared to the conventional CMOS based design because of recycling the charge after every clock cycle. Further, EE-SPFAL based circuits consume uniform power irrespective of input data transition which makes them resilience against DPA attacks.
Scaling of CMOS transistors have served the industry for more than 50 years in providing integrated circuits that are denser, and cheaper along with its high performance, and low power. However, scaling of the transistors leads to increase in leakage current. Increase in leakage current reduces the energy-efficiency of the computing circuits,and increases their vulnerability to DPA attack. Hence, it is important to investigate the crypto circuits in low leakage devices such as FinFET to make them energy-efficient and DPA resistant. In this dissertation, we have proposed a novel FinFET based Secure Adiabatic Logic (FinSAL) family. FinSAL based designs utilize the low-leakage FinFET device along with adiabatic logic principles to improve energy-efficiency along with its resistance against DPA attack.
Recently, Magnetic Tunnel Junction (MTJ)/CMOS based Logic-in-Memory (LiM) circuits have been explored to design low-power non-volatile hardware. Some of the advantages of MTJ device include non-volatility, near-zero leakage power, high integration density and easy compatibility with CMOS devices. However, the differences in power consumption between the switching of MTJ devices increase the vulnerability of Differential Power Analysis (DPA) based side-channel attack. Further, the MTJ/CMOS hybrid logic circuits which require frequent switching of MTJs are not very energy-efficient due to the significant energy required to switch the MTJ devices. In the third contribution of this dissertation, we have investigated a novel approach of building cryptographic hardware in MTJ/CMOS circuits using Look-Up Table (LUT) based method where the data stored in MTJs are constant during the entire encryption/decryption operation.
Currently, high supply voltage is required in both writing and sensing operations of hybrid MTJ/CMOS based LiM circuits which consumes a considerable amount of energy. In order to meet the power budget in low-power devices, it is important to investigate the novel design techniques to design ultra-low-power MTJ/CMOS circuits. In the fourth contribution of this dissertation, we have proposed a novel energy-efficient Secure MTJ/CMOS Logic (SMCL) family. The proposed SMCL logic family consumes uniform power irrespective of data transition in MTJ and more energy-efficient compared to the state-of-art MTJ/ CMOS designs by using charge sharing technique.
The other important contribution of this dissertation is the design of reliable Physical Unclonable Function (PUF). Physically Unclonable Function (PUF) are circuits which are used to generate secret keys to avoid the piracy and device authentication problems. However, existing PUFs consume high power and they suffer from the problem of generating unreliable bits. This dissertation have addressed this issue in PUFs by designing a novel adiabatic logic based PUF. The time ramp voltages in adiabatic PUF is utilized to improve the reliability of the PUF along with its energy-efficiency. Reliability of the adiabatic logic based PUF proposed in this dissertation is tested through simulation based temperature variations and supply voltage variations.
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Balog, Michael Rosen Warren A. "The automated compilation of comprehensive hardware design search spaces of algorithmic-based implementations for FPGA design exploration /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1770.
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