Relevant bibliographies by topics / Hardware circuits

Academic literature on the topic 'Hardware circuits'

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Published: 14 March 2023

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Journal articles on the topic "Hardware circuits"

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Raman, Karthik, and Andreas Wagner. "The evolvability of programmable hardware." Journal of The Royal Society Interface 8, no. 55 (June 9, 2010): 269–81. http://dx.doi.org/10.1098/rsif.2010.0212.

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In biological systems, individual phenotypes are typically adopted by multiple genotypes. Examples include protein structure phenotypes, where each structure can be adopted by a myriad individual amino acid sequence genotypes. These genotypes form vast connected ‘neutral networks’ in genotype space. The size of such neutral networks endows biological systems not only with robustness to genetic change, but also with the ability to evolve a vast number of novel phenotypes that occur near any one neutral network. Whether technological systems can be designed to have similar properties is poorly understood. Here we ask this question for a class of programmable electronic circuits that compute digital logic functions. The functional flexibility of such circuits is important in many applications, including applications of evolutionary principles to circuit design. The functions they compute are at the heart of all digital computation. We explore a vast space of 10 45 logic circuits (‘genotypes’) and 10 19 logic functions (‘phenotypes’). We demonstrate that circuits that compute the same logic function are connected in large neutral networks that span circuit space. Their robustness or fault-tolerance varies very widely. The vicinity of each neutral network contains circuits with a broad range of novel functions. Two circuits computing different functions can usually be converted into one another via few changes in their architecture. These observations show that properties important for the evolvability of biological systems exist in a commercially important class of electronic circuitry. They also point to generic ways to generate fault-tolerant, adaptable and evolvable electronic circuitry.
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D'Ari, Richard, and René Thomas. "Hardware (DNA) circuits." Comptes Rendus Biologies 326, no. 2 (February 2003): 215–17. http://dx.doi.org/10.1016/s1631-0691(03)00066-0.

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Li, Zeyu, Junjie Wang, Zhao Huang, Nan Luo, and Quan Wang. "Towards Trust Hardware Deployment of Edge Computing: Mitigation of Hardware Trojans based on Evolvable Hardware." Applied Sciences 12, no. 13 (June 29, 2022): 6601. http://dx.doi.org/10.3390/app12136601.

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Hardware Trojans (HTs) are malicious hardware components designed to leak confidential information or cause the chip/circuit on which they are integrated to malfunction during operation. When we deploy such hardware platforms for edge computing, FPGA-based implementations of Coarse-Grained Reconfigurable Array (CGRA) are also currently falling victim to HT insertion. However, for CGRA, an evolvable hardware (EHW) platform, which has the ability to dynamically change its configuration and behavioral characteristics based on inputs from the environment, provides us with a new way to mitigate HT attacks. In this regard, we investigate the feasibility of using EHW to mitigate HTs that disrupt normal functionality in CGRA in this paper. When it is determined that HT is inserted into certain processing elements (PEs), the array autonomously reconfigures the circuit structure based on an evolutionary algorithm (EA) to avoid the use of HT-infected (HT-I) PEs. We show that the proposed approach is applicable to: (1) hardware platforms that support coarse-grained reconfiguration; and (2) pure combinatorial circuits. In a simulation environment built in Python, this paper reports experimental results for two target evolutionary circuits and outlines the effectiveness of the proposed method.
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Kerschbaumer, Ricardo, Robson R. Linhares, Jean M. Simão, Paulo C. Stadzisz, and Carlos R. Erig Lima. "Notification-Oriented Paradigm to Implement Digital Hardware." Journal of Circuits, Systems and Computers 27, no. 08 (April 12, 2018): 1850124. http://dx.doi.org/10.1142/s0218126618501244.

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The growing demand for high-performance digital circuits, mainly involving FPGAs, increases the demand for high-level synthesis (HLS) tools. Traditional Hardware Description Languages (HDLs) are complex and depend on low-level abstractions, thereby requiring hardware detailed knowledge from developers. In turn, the current HLS tools are based on proprietary or C/C[Formula: see text] derived languages, which allow easier circuit description but decrease performance. This work presents an alternative solution for designing digital circuits, which arises from the Notification-Oriented Paradigm (NOP). The NOP is an alternative computing solution based upon a set of predefined interconnected entities whose collaborations are performed through precise notifications. The NOP, when targeted to digital hardware (DH), allows the developer to describe the circuit behavior just by connecting and parameterizing elements. The result is a VHDL file that can be compiled for any platform from any manufacturer. In order to check the functionality of this approach, sorting circuits were built both with usual VHDL and with the NOP VHDL aiming to compare the resulting circuits in terms of operating frequency and resource use. The results show that the NOP VHDL approach facilitates the build of digital circuits when compared to the VHDL usual approach without limiting the operating frequency or increasing the use of resources.
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Pawase, Ramesh, and N. P. Futane. "MEMS Seismic Sensor with FPAA Based Interface Circuit for Frequency-Drift Compensation using ANN." International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no. 2 (May 28, 2018): 120. http://dx.doi.org/10.11591/ijres.v6.i2.pp120-126.

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<p>Electrochemical MEMS seismic sensor is limited by its non-ideality of frequency dependent characteristics hence interface circuits for compensation is necessary. The conventional compensation circuits are limited by high power consumption, bulky external hardware circuitry. In these methods digital circuits are also limited by inherent analog to digital conversion and vice versa which consumes significant power, acquires more size and limits speed. A Field programmable analog array (FPAA) overcomes these limitations and gives fast, simple and user friendly development platform with less development speed comparable to ASIC. Recently FPAA becoming popular for rapid prototyping. The proposed system presents FPAA (Anadigm AN231E04) based hardware implementation of ANN model. Using this FPAA based compensation circuit, the error in frequency drift have been minimized in the range of 3.68% to about 0.64% as compared to ANN simulated results in the range of 23.07% to 0.99 %. This single neuron consumes of power of 206.62 mW. and has minimum block wise resource utilization. The proposed hardware uses all analog blocks which remove the requirement of ADC and DAC reducing significant power and size of interface circuit. This work gives the SMART MEMS seismic sensor with reliable output and ANN based intelligent interface circuit implemented in FPAA hardware.<strong></strong></p>
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PARK, SUNGWOO, and HYEONSEUNG IM. "A calculus for hardware description." Journal of Functional Programming 21, no. 1 (November 19, 2010): 21–58. http://dx.doi.org/10.1017/s0956796810000249.

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AbstractIn efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a calculus, called lλ (linear lambda), which may serve as an intermediate functional language just above netlists in the hierarchy of hardware description languages. In order to support higher-order functions, lλ uses a linear type system, which enforces the linear use of variables of function type. The translation of lλ into structural descriptions of hardware circuits is sound and complete in the sense that it maps expressions only to realizable hardware circuits, and that every realizable hardware circuit has a corresponding expression in lλ. To illustrate the use of lλ as a practical intermediate language for hardware description, we design a simple hardware description language that extends lλ with polymorphism, and use it to implement a fast Fourier transform circuit and a bitonic sorting network.
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Li, Chun Feng, Ke Ming Li, and Xiang Zhang. "Research on Circuit Design for Speed Adjusting Hardware of Brushless DC Motor Based on the Two-Dimensional Fuzzy Controller." Advanced Materials Research 705 (June 2013): 509–15. http://dx.doi.org/10.4028/www.scientific.net/amr.705.509.

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The essay first establishes the general design for intelligent rotary speed system of the brushless DC motors, then based on the general design scheme, two-dimensional fuzzy controller, adaptive current adjustor and mainly used hardware circuits are designed. The mainly used hardware circuit design includes the circuit design of current detecting circuit, voltage detecting circuit, high-speed optocoupler, motor driver circuit, zero-crossing comparator circuit, etc. At last the designed controller and hardware circuits are tested to achieve optimum effects for rotary speed control through validation of experimental devices.
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Shibata, Tadashi, and Tadahiro Ohmi. "Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors." Journal of Robotics and Mechatronics 8, no. 6 (December 20, 1996): 508–15. http://dx.doi.org/10.20965/jrm.1996.p0508.

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The primary objective of this article is not to present integrated circuit implementation of neural networks in the sense that neurophysiological models are constructed in electronic circuits, but to describe new-architecture intelligent electronic circuits built using a neuron-like high-functionality transistor as a basic circuit element. This has greatly reduced the VLSI hardware/software burden in carrying out intelligent data processing and would find promising applications in robotics. The transistor is a multiple-input-gate thresholding device called a neuron MOSFET (neuMOS or νMOS) due to its functional similarity to a simple neuron model. vMOS circuits are characterized by a high degree of parallelism in hardware computation, large flexibility in the hardware configuration, and a dramatic reduction in circuit complexity compared to conventional integrated circuits. As a result, a number of new-concept circuits has been developed. Examples include a real-time reconfigurable logic circuit called flexware and associative memory conducting a fully parallel search for the most similar targets. A simple hardware model for self-learning systems is also presented. The enhancement in functionality at a very elemental transistor level is critical to building human-like intelligent systems on silicon.
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Katoh, Yusuke, Hironari Yoshiuchi, Yoshio Murata, and Hironori Nakajo. "Scalable Hardware Mechanism for Partitioned Circuits Operation." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 12, no. 2 (December 16, 2018): 90–97. http://dx.doi.org/10.37936/ecti-cit.2018122.142511.

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For designing hardware with a high-level synthesis tool using a programming language such as C or Java, its large size of logic circuit makes it difficult to implement the design in a single FPGA. In such a case, partitioning the logic circuit and implementing in multiple FPGAs is a commonly used approach. We propose the Scalable Hardware Mechanism, which enables the operation of a partitioned circuit to prevent the degradation of clock frequency by minimizing its dependence on the usage and the type of FPGA. Our mechanism provides a reduced delay by the collective signal transmission with the partitioned AES code generation circuit and the character string edit distance calculation circuit as partitioned circuits. The collective signal transmission has attained 1.27 times improvement in the speed for the AES code generation circuit and 3.16 times improvement for the character string edit distance calculation circuit compared with the circuit by the conventional method.
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Odame, K., and P. E. Hasler. "Nonlinear Circuit Analysis via Perturbation Methods and Hardware Prototyping." VLSI Design 2010 (March 18, 2010): 1–8. http://dx.doi.org/10.1155/2010/687498.

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Nonlinear signal processing is necessary in many emerging applications where form factor and power are at a premium. In order to make such complex computation feasible under these constraints, it is necessary to implement the signal processors as analog circuits. Since analog circuit design is largely based on a linear systems perspective, new tools are being introduced to circuit designers that allow them to understand and exploit circuit nonlinearity for useful processing. This paper discusses two such tools, which represent nonlinear circuit behavior in a graphical way, making it easy to develop a qualitative appreciation for the circuits under study.
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Dissertations / Theses on the topic "Hardware circuits"

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Mallepalli, Samarsen Reddy. "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication." Diss., Rolla, Mo. : University of Missouri-Rolla, 2007. http://scholarsmine.umr.edu/thesis/pdf/Mallepalli_09007dcc803c4eec.pdf.

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Thesis (M.S.)--University of Missouri--Rolla, 2007.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).
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Kalganova, Tatiana. "Evolvable hardware design of combinational logic circuits." Thesis, Edinburgh Napier University, 2000. http://researchrepository.napier.ac.uk/Output/4341.

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Evolvable Hardware (EHW), as an alternative method for logic design, became more attractive recently, because of its algebra-independent techniques for generating selfadaptive self-reconfigurable hardware. This thesis investigates and relates both evaluation and evolutionary processes, emphasizing the need to address problems arising from data complexity. Evaluation processes, capable of evolving cost-optimised fully functional circuits are investigated. The need for an extrinsic EHW approach (software models) independent of the concerns of any implementation technologies is emphasized. It is also shown how the function description may be adapted for use in the EHW approach. A number of issues of evaluation process are addressed: these include choice of optimisation criteria, multi-objective optimisation tedmiques in EHW and probabilistic analysis of evolutionary processes. The concept of self-adaptive extrinsic EHW method is developed. This approach emphasizes the circuit layout evolution together with circuit functionality. A chromosome representation for such system is introduced, and a number of genetic operators and evolutionary algorithms in support of this approach are presented. The genetic operators change the genetic material at the different levels of chromosome representation. Furthermore, a chromosome representation is adapted to the function-level EHW approach. As a result, the modularised systems are evolved using multi-output building blocks. This chromosome representation overcomes the problem of long string chromosome. Together, these techniques facilitate the construction of systems to evolve logic functions of large number of variables. A method for achieving this using bidirectional incremental evolution is documented. It is demonstrated that the integration of a dynamic evaluation process and self-adaptive function-level EHW approach allows the bidirectional incremental evolution to successfully evolve more complex systems than traditionally evolved before. Thereby it provides a firm foundation for the evolution of complex systems. Finally, the universality of these techniques is proved by applying them to multivalued combinational logic design. Empirical study of this application shows that there is no fundamental difference in approach for both binary and multi-valued logic design problems.
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Singh, Satnam. "Analysis of hardware descriptions." Thesis, University of Glasgow, 1991. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.390451.

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Sandiford, Richard. "Hardware compilation based on communicating processes." Thesis, Imperial College London, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.246769.

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Thompson, Adrian. "Hardware evolution : automatic design of electronic circuits in reconfigurable hardware by artificial evolution." Thesis, University of Sussex, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.360588.

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Desai, Avinash R. "Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23756.

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Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First, offshore chip manufac- turing allows the design secrets of the IP cores to be transparent to the foundry and other entities along the production chain. Second, small malicious modifications to the design may not be detectable after fabrication without anti-tamper mechanisms. Counterfeit Inte- grated Circuits (ICs) also have become an important security issue in recent years, in which counterfeit ICs that perform incorrectly or sub-par to the expected can lead to catastrophic consequences in safety and/or mission-critical applications, in addition to the tremendous economic toll they incur to the semiconductor industry. Some techniques have been devel- oped in the past to improve the defense against such attacks but they tend to fall prey to the increasing power of the attacker. We present a new way to protect against tampering by a clever obfuscation of the design, which can be unlocked with a specific, dynamic path traversal. Hence, the functional mode of the controller is hidden with the help of obfuscated states, and the functional mode is made operational only on the formation of a specific interlocked Code-Word during state transition. A novel time-stamp is proposed that can provide the date at which the IC was manufactured for counterfeit detection. Furthermore, we propose a second layer of tamper resistance to the time-stamp circuit to make it even more difficult to modify. Results show that methods proposed offer higher levels of security with small area overhead. A side benefit is that any small alteration will be magnified via the obfuscated design proposed in these methods.
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Basak, Abhishek. "INFRASTRUCTURE AND PRIMITIVES FOR HARDWARE SECURITY IN INTEGRATED CIRCUITS." Case Western Reserve University School of Graduate Studies / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=case1458787036.

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Blum, Thomas. "Modular exponentiation on reconfigurable hardware." Digital WPI, 1999. http://www.wpi.edu/Pubs/ETD/Available/etd-090399-090413/unrestricted/thesis.pdf.

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Wang, Xiao-Lin 1955. "A TRANSLATER OF CLOCK MODE VHDL HARDWARE DESCRIPTION LANGUAGE." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/291295.

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Staunstrup, Jørgen. "A formal approach to hardware design /." Boston [u.a.] : Kluwer Acad. Publ, 1994. http://www.loc.gov/catdir/enhancements/fy0820/93043582-d.html.

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Books on the topic "Hardware circuits"

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Computer hardware diagnostics for engineers. New York: McGraw-Hill, 1995.

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PC hardware projects. Indianapolis, IN: Prompt Publications, 1997.

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Thompson, Adrian. Hardware evolution: Automatic design of electronic circuits in reconfigurable hardware by Artificial Evolution. London: Springer, 1998.

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A formal approach to hardware design. Boston: Kluwer Academic Publishers, 1994.

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Wang, Li-Guo. Abstraction of hardware construction. Edinburgh: LFCS, Dept. of Computer Science, University of Edinburgh, 1995.

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Singh, Gaurav. Low power hardware synthesis from concurrent action-oriented specifications. New York: Springer, 2010.

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Abraham, Kandel, and Langholz Gideon, eds. Fuzzy hardware: Architectures and applications. Boston: Kluwer Academic Publishers, 1998.

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Hardware design verification: Simulation and formal method-based approaches. Upper Saddle River, NJ: Prentice Hall Professional Technical Reference, 2005.

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Luís, Gomes, Lavagno Luciano 1959-, and Yakovlev Alex, eds. Hardware design and petri nets. Boston: Kluwer Academic, 2000.

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Kropf, Thomas. Introduction to Formal Hardware Verification. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999.

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Book chapters on the topic "Hardware circuits"

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Tehranipoor, Mark, Ujjwal Guin, and Domenic Forte. "Hardware IP Watermarking." In Counterfeit Integrated Circuits, 203–22. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-11824-6_10.

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Sekanina, Lukáš. "Principles and Applications of Polymorphic Circuits." In Evolvable Hardware, 209–24. Berlin, Heidelberg: Springer Berlin Heidelberg, 2015. http://dx.doi.org/10.1007/978-3-662-44616-4_8.

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Tehranipoor, Mark, Nitin Pundir, Nidish Vashistha, and Farimah Farahmandi. "Hardware Camouflaging in Integrated Circuits." In Hardware Security Primitives, 171–84. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-19185-5_10.

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Wei, Shaojun, Leibo Liu, Jianfeng Zhu, and Chenchen Deng. "Hardware Architectures and Circuits." In Software Defined Chips, 77–196. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6994-2_3.

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Galindez Olascoaga, Laura Isabel, Wannes Meert, and Marian Verhelst. "Hardware-Aware Probabilistic Circuits." In Hardware-Aware Probabilistic Machine Learning Models, 81–110. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-74042-9_5.

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Froehlich, Saman, Daniel Große, and Rolf Drechsler. "Approximate Hardware Generation Using Formal Techniques." In Approximate Circuits, 155–74. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-99322-5_8.

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Joyce, Jeffrey J. "Generic Specification of Digital Hardware." In Designing Correct Circuits, 68–91. London: Springer London, 1991. http://dx.doi.org/10.1007/978-1-4471-3544-9_4.

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Sanchez, Eduardo. "Field programmable gate array (FPGA) circuits." In Towards Evolvable Hardware, 1–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61093-6_1.

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Lee, Seogoo, and Andreas Gerstlauer. "Approximate High-Level Synthesis of Custom Hardware." In Approximate Circuits, 205–23. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-99322-5_10.

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Hanif, Muhammad Abdullah, Muhammad Usama Javed, Rehan Hafiz, Semeen Rehman, and Muhammad Shafique. "Hardware–Software Approximations for Deep Neural Networks." In Approximate Circuits, 269–88. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-99322-5_13.

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Conference papers on the topic "Hardware circuits"

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Miller, J. F., and P. Thomson. "Discovering novel digital circuits using evolutionary techniques." In IEE Colloquium Evolvable Hardware Systems. IEE, 1998. http://dx.doi.org/10.1049/ic:19980207.

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Knichel, David, and Amir Moradi. "Low-Latency Hardware Private Circuits." In CCS '22: 2022 ACM SIGSAC Conference on Computer and Communications Security. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3548606.3559362.

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Venturelli, Davide, Minh Do, Eleanor Rieffel, and Jeremy Frank. "Temporal Planning for Compilation of Quantum Approximate Optimization Circuits." In Twenty-Sixth International Joint Conference on Artificial Intelligence. California: International Joint Conferences on Artificial Intelligence Organization, 2017. http://dx.doi.org/10.24963/ijcai.2017/620.

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We investigate the application of temporal planners to the problem of compiling quantum circuits to emerging quantum hardware. While our approach is general, we focus our initial experiments on Quantum Approximate Optimization Algorithm (QAOA) circuits that have few ordering constraints and thus allow highly parallel plans. We report on experiments using several temporal planners to compile circuits of various sizes to a realistic hardware architecture. This early empirical evaluation suggests that temporal planning is a viable approach to quantum circuit compilation.
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Catelan, Daniela, Ricardo Santos, and Liana Duenha. "Accuracy and Physical Characterization of Approximate Arithmetic Circuits." In XXI Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2020. http://dx.doi.org/10.5753/wscad.2020.14065.

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With the end of Dennard&apos;s scale, designers have been looking for new alternatives and approximate computing (AC) has managed to attract the attention of researchers, by offering techniques ranging from the application level to the circuit level. When applying approximate circuit techniques in hardware design, the program user may speed up the application while a designer may save area and power dissipation at the cost of less accuracy on the operations results. This paper discusses the compromise between accuracy versus physical efficiency by presenting a set of experiments and results of tailor-made approximate arithmetic circuits on Field-Programmable Gate Array (FPGA) platforms. Our results reveal that an approximate circuit with accuracy control could not be useful if the goal is to save circuit area or even power dissipation. Even for circuits that seem to have power efficiency, we should care about the size and prototyping platform where the hardware will be used.
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Rose, G. S., J. Rajendran, N. McDonald, R. Karri, M. Potkonjak, and B. Wysocki. "Hardware security strategies exploiting nanoelectronic circuits." In 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013). IEEE, 2013. http://dx.doi.org/10.1109/aspdac.2013.6509623.

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"Verification of hardware systems and circuits." In IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society. IEEE, 2013. http://dx.doi.org/10.1109/iecon.2013.6700422.

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Liu, Siting, and Jie Han. "Hardware ODE Solvers using Stochastic Circuits." In DAC '17: The 54th Annual Design Automation Conference 2017. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3061639.3062258.

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Yamakawa. "Fuzzy logic hardware systems." In 1993 Symposium on VLSI Circuits. IEEE, 1989. http://dx.doi.org/10.1109/vlsic.1989.1037460.

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Shanthi, A. P., P. Muruganandam, and R. Parthasarathi. "Enhancing the development based evolution of digital circuits." In 2004 NASA/DoD Conference on Evolvable Hardware. IEEE, 2004. http://dx.doi.org/10.1109/eh.2004.1310815.

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Dally, William J., C. Thomas Gray, John Poulton, Brucek Khailany, John Wilson, and Larry Dennison. "Hardware-Enabled Artificial Intelligence." In 2018 IEEE Symposium on VLSI Circuits. IEEE, 2018. http://dx.doi.org/10.1109/vlsic.2018.8502368.

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Reports on the topic "Hardware circuits"

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Di, Jia. Towards Trustable Embedded Systems: Hardware Threat Modeling for Integrated Circuits. Fort Belvoir, VA: Defense Technical Information Center, October 2008. http://dx.doi.org/10.21236/ada501149.

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Chung, Moon Jung. Parallel Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) Simulation for Performance Modeling. Fort Belvoir, VA: Defense Technical Information Center, March 1999. http://dx.doi.org/10.21236/ada372678.

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Mills, Michael T. A Key Element Toward Concurrent Engineering of Hardware and Software: Binding Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) with Ada 95. Fort Belvoir, VA: Defense Technical Information Center, October 1994. http://dx.doi.org/10.21236/ada294469.

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Mills, Michael T. Proposed Object Oriented Programming (OOP) Enhancements to the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). Fort Belvoir, VA: Defense Technical Information Center, August 1993. http://dx.doi.org/10.21236/ada274004.

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Wachen, John, and Steven McGee. Qubit by Qubit’s Four-Week Quantum Computing Summer School Evaluation Report for 2021. The Learning Partnership, September 2021. http://dx.doi.org/10.51420/report.2021.4.

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Qubit by Qubit’s Quantum Computing Summer School is a four-week summer course for high school and university students in their first or second year of studies. The aim of the summer school is to introduce the field of Quantum Information Sciences and Engineering (QISE), specifically quantum computing. Through the course, students learn about quantum mechanics, quantum computation and information (quantum gates, circuits, and algorithms and protocols, including Grover’s Algorithm and Quantum Key Distribution), applications of quantum computing, and quantum hardware. Students also learn how to program in Qiskit and basic mathematics for quantum, including matrices and vectors. The Quantum Computing Summer School program enrolled a diverse population of high school and undergraduate students with 48% of participants identifying at female or non-binary, 20% of students identifying as Hispanic, 17% identifying as Black, and 38% identifying as Asian. The program substantially increased participants’ knowledge about quantum computing, as exhibited by large gains on a technical assessment that was administered at the beginning and end of the program. On a survey of student motivation, students in the program showed a statistically significant increase in their expectancy of being successful in quantum computing and valuing quantum computing. From the beginning of the program to the end of the program, there was a statistically significant increase in students’ reported sense of belonging in quantum. Participation in the program increased students’ interest in pursuing additional coursework and careers in STEM generally and in quantum specifically.
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