Relevant bibliographies by topics / Hardware

Academic literature on the topic 'Hardware'

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Published: 4 June 2021
Last updated: 29 July 2024

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Journal articles on the topic "Hardware"

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Choi, Jin-Suk, and Young-Sam Lee. "The Implementation of a Hardware-In-The-Loop Simulator for an Inverted Pendulum System Using Open-Source Hardware." Journal of Institute of Control, Robotics and Systems 23, no. 2 (February 28, 2017): 117–25. http://dx.doi.org/10.5302/j.icros.2017.17.0002.

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Blegvad, Peter. "Hardware." Chicago Review 45, no. 3/4 (1999): 126. http://dx.doi.org/10.2307/25304426.

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Brixius, Elizabeth. "Hardware." College English 51, no. 6 (October 1989): 588. http://dx.doi.org/10.2307/377953.

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Monterrubio Hernández, Elias. "Hardware." Con-Ciencia Serrana Boletín Científico de la Escuela Preparatoria Ixtlahuaco 6, no. 11 (January 5, 2024): 6–8. http://dx.doi.org/10.29057/ixtlahuaco.v6i11.11967.

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Hardware elemento fundamental de un ordenador o sistema informático que es formado por componentes electrónicos y mecánicos, tales como circuitos memorias, discos rígidos, dispositivos de comunicación y otros materiales en estado físico que es altamente necesario para que un sistema tecnológico funcione de la manera correcta. Este apartado permite conocer de conceptos donde se comprueba, aumenta y desplaza los conocimientos por medio de la información que brindan diversos puntos y entre ellos conceptos de gran interés e importancia.
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Chin, S. K., and E. P. Stabler. "Synthesis of arithmetic hardware using hardware metafunctions." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9, no. 8 (1990): 793–803. http://dx.doi.org/10.1109/43.57787.

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Karri, Ramesh, Jeyavijayan Rajendran, Kurt Rosenfeld, and Mohammad Tehranipoor. "Trustworthy Hardware: Identifying and Classifying Hardware Trojans." Computer 43, no. 10 (October 2010): 39–46. http://dx.doi.org/10.1109/mc.2010.299.

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Sengupta, Anirban. "Hardware Security of CE Devices [Hardware Matters]." IEEE Consumer Electronics Magazine 6, no. 1 (January 2017): 130–33. http://dx.doi.org/10.1109/mce.2016.2614552.

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DINU, Alexandru, Adrian CRĂCIUN, and Marian ALEXANDRU. "HARDWARE RECONFIGURATION OF A SOC." Review of the Air Force Academy 16, no. 1 (August 1, 2018): 55–64. http://dx.doi.org/10.19062/1842-9238.2018.16.1.8.

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Bethuna, Bethuna. "Hardware Implementation Of Iris Matching." International Journal of Scientific Research 1, no. 6 (June 1, 2012): 46–48. http://dx.doi.org/10.15373/22778179/nov2012/16.

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Sommerville, Matthew. "Radical Hardware." Afterimage 17, no. 6 (January 1, 1990): 20–21. http://dx.doi.org/10.1525/aft.1990.17.6.20.

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Dissertations / Theses on the topic "Hardware"

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Chilingirian, Berj Krikor. "Hashing hardware : identifying hardware during boot-time system verification." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/112837.

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Thesis: M. Eng., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Cataloged from student-submitted PDF version of thesis.
Includes bibliographical references (pages 85-90).
Modern systems measure the software loaded at boot-time to ensure the machine starts in a trusted state. Such measurements, however, do not include any information about the underlying hardware of the machine. Recent DRAM-based attacks and the growing complexity of the supply chain attest to the importance of measuring hardware at boot. In this thesis, we propose a technique for designing measurement schemes for hardware components. We then apply this technique to designing and implementing a hardware measurement scheme for DRAM on a real system without hardware modifications. Finally, we evaluate our DRAM hardware measurement scheme and demonstrate that it achieves 89% accuracy in mapping a DRAM measurement to the manufacturing process from which that DRAM was produced.
by Berj Krikor Chilingirian.
M. Eng.
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Figueiredo, Boneti Carlos Santieri de. "Exploring coordinated software and hardware support for hardware resource allocation." Doctoral thesis, Universitat Politècnica de Catalunya, 2009. http://hdl.handle.net/10803/6018.

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Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the prioritization of tasks done by the software.
This thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.
It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.
In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
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Desai, Avinash R. "Anti-Counterfeit and Anti-Tamper Hardware Implementation using Hardware Obfuscation." Thesis, Virginia Tech, 2013. http://hdl.handle.net/10919/23756.

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Tampering and Reverse Engineering of a chip to extract the hardware Intellectual Property (IP) core or to inject malicious alterations is a major concern. First, offshore chip manufac- turing allows the design secrets of the IP cores to be transparent to the foundry and other entities along the production chain. Second, small malicious modifications to the design may not be detectable after fabrication without anti-tamper mechanisms. Counterfeit Inte- grated Circuits (ICs) also have become an important security issue in recent years, in which counterfeit ICs that perform incorrectly or sub-par to the expected can lead to catastrophic consequences in safety and/or mission-critical applications, in addition to the tremendous economic toll they incur to the semiconductor industry. Some techniques have been devel- oped in the past to improve the defense against such attacks but they tend to fall prey to the increasing power of the attacker. We present a new way to protect against tampering by a clever obfuscation of the design, which can be unlocked with a specific, dynamic path traversal. Hence, the functional mode of the controller is hidden with the help of obfuscated states, and the functional mode is made operational only on the formation of a specific interlocked Code-Word during state transition. A novel time-stamp is proposed that can provide the date at which the IC was manufactured for counterfeit detection. Furthermore, we propose a second layer of tamper resistance to the time-stamp circuit to make it even more difficult to modify. Results show that methods proposed offer higher levels of security with small area overhead. A side benefit is that any small alteration will be magnified via the obfuscated design proposed in these methods.
Master of Science
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Acosta, Roberto S. M. Massachusetts Institute of Technology. "Open source hardware." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/55201.

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Thesis (S.M.)--Massachusetts Institute of Technology, System Design and Management Program, 2009.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 82-83).
Open source software development models have created some of the most innovative tools and companies in the industry today modifying the way value is created and businesses developed. The purpose of this thesis is to analyze open source hardware in its current state and its potential impact at several stages of the value chain. Existing examples of open source hardware at different stages of the value chain are analyzed in terms of their innovation and potential impact to existing players in the value chain. An Ethernet framer is develop through the use of traditional development and benchmarked against a design developed based on open source hardware cores. The research concludes with an examination of business models established around open source hardware.
by Roberto Acosta.
S.M.
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Lamy, M. F., and D. H. Ellis. "CAIS AIRBORNE HARDWARE." International Foundation for Telemetering, 1992. http://hdl.handle.net/10150/608890.

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International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California
The Common Airborne Instrumentation System (CAIS) is designed as a general purpose system for flight test applications into the next century. The system has an open architecture which readily permits the addition of new equipment as the need arises. This paper describes the current complement of airborne hardware as well as the approach to the design of the open architecture. This paper is presented as a companion to the CAIS overview prepared for this conference.
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Martínez, Miguel, and Berral Miguel Gámez. "OPEN HARDWARE AGV." Thesis, Högskolan i Skövde, Institutionen för ingenjörsvetenskap, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:his:diva-20010.

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The versatility of open source technologies could grant them an intriguing place in the industry. Moreparticularly, an open source hardware automated guided vehicle (AGV) might show up as an idealsolution for low-scale logistic process, as well as a useful development and didactic tool. What is more,a modular vehicle with interchangeable components would comply even better with this philosophy.Hereafter, besides from a literature review including research related to the many subjects that thisproject attempts to orchestrate, an open source hardware methodology has been followed, acomparison analysis of each component and structure performed and configurations of possible AGVsselected, in order to shed light on the viability of conducting this sort of project in reality. Plus, a modularframe has been designed and tested with computer-aided and simulation tools. The conclusions showthat constructing an open source-based industrial vehicle is to a high extent feasible, although theprecise economic outcomes are not clear and building a real model is a future requisite to give evidence.

There are other digital material (eg. film, imgage or audio files) or models/artifacts that belongs to the thesis and need to be archived.

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Vlach, Jiří. "Zabezpečovací ústředna - hardware." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2010. http://www.nusl.cz/ntk/nusl-218368.

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This work deals with the design and realization of a modular security central unit's hardware positioned in familial houses. As an operating component of the central unit is used Module Rabbit 3365 with an integrated Ethernet interface. Based on user's requirements and general requirements for electronic security system, circuit diagrams of the central unit's motherboard and power supply with a function of backup power supply are designed. The work also includes layout of a keyboard and LCD display. Printed circuit boards are designed, produced and assembled. The device is set to work. The last part concerns programming of the module Rabbit 3365 in Dynamic C. Gradually, set of operating functions for individual components of the security central unit are implemented.
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Lee, Justin Alexander. "Morphogenetic evolvable hardware." Thesis, Queensland University of Technology, 2006. https://eprints.qut.edu.au/16231/1/Justin_Lee_Thesis.pdf.

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Evolvable hardware (EHW) uses simulated evolution to generate an electronic circuit with specific characteristics, and is generally implemented on Field Programmable Gate Arrays (FPGAs). EHW has proven to be successful at producing small novel circuits for applications such as robot control and image processing, however, traditional approaches, in which the FPGA configuration is directly encoded on the chromosome, have not scaled well with increases in problem and FPGA architecture complexity. One of the methods proposed to overcome this is the incorporation of a growth process, known as morphogenesis, into the evolutionary process. However, existing approaches have tended to abstract away the underlying architectural details, either to present a simpler virtual FPGA architecture, or a biochemical model that hides the relationship between the cellular state and the underlying hardware. By abstracting away the underlying architectural details, EHW has moved away from one of its key strengths, that being to allow evolution to discover novel solutions free of designer bias. Also, by separating the biological model from the target FPGA architecture, too many assumptions and arbitrary decisions need to be made, which are liable to lead to the growth process failing to produce the desired results. In this thesis a new approach to applying morphogenesis to gate-level FPGA- based EHW is presented, whereby circuit growth is closely tied to the underlying gate-level architecture, with circuit growth being driven largely by the state of gate-level resources of the FPGA. An investigation into the applicability of biological processes, structures and mechanisms to morphogenetic EHW (MGEHW) is conducted, and the resulting design elaborated. The developed MGEHW system is applied to solving a signal routing problem with irregular and severe constraints on routing resources. It is shown that the morphogenetic approach outperforms a traditional EHW approach using a direct encoding, and importantly, is able to scale to larger, more complex, signal routing problems without any significant increase in the number of generations required to find an optimal solution. With the success of the MGEHW system in solving primarily structural prob- lems, it is then applied to solving a combinatorial function problem, specifically a one-bit full adder, with a more complete set of FPGA resources. The results of these experiments, together with the previous experiments, has provided valuable information that when analysed has enabled the identification of the critical factors that determine the likelihood of an EHW problem being solvable. In particular this has highlighted the importance of effective fitness feedback for guiding evolution towards its desired goal. Results indicate that the gate-level morphogenetic approach is promising. The research presented here is far from complete; many avenues for future research have opened. The MGEHW system that has been developed allows further research in this area to be explored experimentally. Some of the most fruitful directions for future research are described.
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Lee, Justin Alexander. "Morphogenetic evolvable hardware." Queensland University of Technology, 2006. http://eprints.qut.edu.au/16231/.

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Evolvable hardware (EHW) uses simulated evolution to generate an electronic circuit with specific characteristics, and is generally implemented on Field Programmable Gate Arrays (FPGAs). EHW has proven to be successful at producing small novel circuits for applications such as robot control and image processing, however, traditional approaches, in which the FPGA configuration is directly encoded on the chromosome, have not scaled well with increases in problem and FPGA architecture complexity. One of the methods proposed to overcome this is the incorporation of a growth process, known as morphogenesis, into the evolutionary process. However, existing approaches have tended to abstract away the underlying architectural details, either to present a simpler virtual FPGA architecture, or a biochemical model that hides the relationship between the cellular state and the underlying hardware. By abstracting away the underlying architectural details, EHW has moved away from one of its key strengths, that being to allow evolution to discover novel solutions free of designer bias. Also, by separating the biological model from the target FPGA architecture, too many assumptions and arbitrary decisions need to be made, which are liable to lead to the growth process failing to produce the desired results. In this thesis a new approach to applying morphogenesis to gate-level FPGA- based EHW is presented, whereby circuit growth is closely tied to the underlying gate-level architecture, with circuit growth being driven largely by the state of gate-level resources of the FPGA. An investigation into the applicability of biological processes, structures and mechanisms to morphogenetic EHW (MGEHW) is conducted, and the resulting design elaborated. The developed MGEHW system is applied to solving a signal routing problem with irregular and severe constraints on routing resources. It is shown that the morphogenetic approach outperforms a traditional EHW approach using a direct encoding, and importantly, is able to scale to larger, more complex, signal routing problems without any significant increase in the number of generations required to find an optimal solution. With the success of the MGEHW system in solving primarily structural prob- lems, it is then applied to solving a combinatorial function problem, specifically a one-bit full adder, with a more complete set of FPGA resources. The results of these experiments, together with the previous experiments, has provided valuable information that when analysed has enabled the identification of the critical factors that determine the likelihood of an EHW problem being solvable. In particular this has highlighted the importance of effective fitness feedback for guiding evolution towards its desired goal. Results indicate that the gate-level morphogenetic approach is promising. The research presented here is far from complete; many avenues for future research have opened. The MGEHW system that has been developed allows further research in this area to be explored experimentally. Some of the most fruitful directions for future research are described.
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Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation." Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.

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Books on the topic "Hardware"

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Barnes, Linda. Hardware. Thorndike, Me: Thorndike Press, 1995.

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Barnes, Linda. Hardware. New York: Delacorte Press, 1995.

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Barnes, Linda. Hardware. London: Hodder & Stoughton, 1995.

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Canada. Industry, Science and Technology Canada. Hardware. Ottawa: Industry, Science and Technology Canada, 1991.

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Barnes, Linda. Hardware. New York: Delacorte Press, 1995.

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Ayala, Danny. Audiovisual hardware. Nashville, Tenn: Convention Press, 1994.

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Trebor. Emotional hardware. 2nd ed. San Francisco, Calif: Terrapin Press, 1993.

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Aubuchon, Bernard W. Aubuchon Hardware. Charleston, SC: Arcadia Pub., 2008.

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Krieg, Christian, Adrian Dabrowski, Heidelinde Hobel, Katharina Krombholz, and Edgar Weippl. Hardware Malware. Cham: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-031-02338-5.

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Thompson, Adrian. Hardware Evolution. London: Springer London, 1998. http://dx.doi.org/10.1007/978-1-4471-3414-5.

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Book chapters on the topic "Hardware"

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Gansterer, Wilfried, and Christoph Überhuber. "Hardware." In Hochleistungsrechnen mit HPF, 1–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-642-59503-5_1.

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Antenucci, John C., Kay Brown, Peter L. Croswell, Michael J. Kevany, and Hugh Archer. "Hardware." In Geographic Information Systems, 133–60. Boston, MA: Springer US, 1991. http://dx.doi.org/10.1007/978-1-4615-3934-6_7.

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Borgeest, Kai. "Hardware." In Elektronik in der Fahrzeugtechnik, 111–76. Wiesbaden: Vieweg+Teubner, 2010. http://dx.doi.org/10.1007/978-3-8348-9337-6_6.

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Klaus, Dembowski. "Hardware." In Raspberry Pi – Das Handbuch, 55–94. Wiesbaden: Springer Fachmedien Wiesbaden, 2013. http://dx.doi.org/10.1007/978-3-658-03167-1_4.

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Alex, Wulf, and Gerhard Bernör. "Hardware." In UNIX, C und Internet, 15–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 1994. http://dx.doi.org/10.1007/978-3-662-10707-2_2.

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Strobel, Stefan, Rainer Maurer, and Stefan Middendorf. "Hardware." In Linux Universe, 15–22. New York, NY: Springer New York, 1997. http://dx.doi.org/10.1007/978-1-4612-1868-5_4.

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French, Richard Mark. "Hardware." In Technology of the Guitar, 295–316. Boston, MA: Springer US, 2012. http://dx.doi.org/10.1007/978-1-4614-1921-1_8.

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Gmehlich, Rainer, and Heinrich Rust. "Hardware." In Mehr als nur Programmieren…, 87–98. Wiesbaden: Vieweg+Teubner Verlag, 1993. http://dx.doi.org/10.1007/978-3-322-85940-2_3.

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Houghton, A. "Hardware." In Error Coding for Engineers, 147–64. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4615-1509-8_10.

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Schrödel, Tobias. "Hardware." In Hacking für Manager, 219–25. Wiesbaden: Gabler Verlag, 2012. http://dx.doi.org/10.1007/978-3-8349-7128-9_14.

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Conference papers on the topic "Hardware"

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Nantian, Wang, Qian Yanling, Li Yue, Zhuo Qingqi, and Li Tingpeng. "Survey on evolvable hardware and embryonic hardware." In 2013 IEEE 11th International Conference on Electronic Measurement & Instruments (ICEMI). IEEE, 2013. http://dx.doi.org/10.1109/icemi.2013.6743207.

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Martin, Kevin. "Session 2: Hardware, FPGAs, and reconfigurable hardware." In 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP). IEEE, 2014. http://dx.doi.org/10.1109/dasip.2014.7115602.

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Unknown. "DIY hardware." In ACM SIGGRAPH ASIA 2009 Art Gallery & Emerging Technologies: Adaptation. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1665137.1665186.

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Gautron, Pascal. "Hardware implementation." In ACM SIGGRAPH 2008 classes. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1401132.1401220.

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"Hardware architectures." In Second IEEE International Conference on Computational Cybernetics, 2004. ICCC 2004. IEEE, 2004. http://dx.doi.org/10.1109/icccyb.2004.1437662.

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Friedman, Batya, Peter H. Kahn, and Jennifer Hagman. "Hardware companions?" In the conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/642611.642660.

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Casto, Matthew. "Hardware Assurance." In GLSVLSI '18: Great Lakes Symposium on VLSI 2018. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3194554.3194555.

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Tyanev, Dimitar, and Yulka Petkova. "Hardware Divider." In CompSysTech'18: 19th International Conference on Computer Systems and Technologies. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3274005.3274009.

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Brassil, Jack, Jonathan Smith, Flavio Bonomi, Keren Bergman, Paul Congdon, Ivan Seskar, and Steve Muir. "Networking hardware." In the 5th ACM/IEEE Symposium. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1882486.1882488.

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Sekanina, Lukas. "Evolvable hardware." In the 2007 GECCO conference companion. New York, New York, USA: ACM Press, 2007. http://dx.doi.org/10.1145/1274000.1274127.

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Reports on the topic "Hardware"

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Ku, David C., and Giovanni De Micheli. Hardware C - A Language for Hardware Design. Fort Belvoir, VA: Defense Technical Information Center, August 1988. http://dx.doi.org/10.21236/ada207317.

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Elesina, S. I. Computer hardware. OFERNIO, June 2018. http://dx.doi.org/10.12731/ofernio.2018.23687.

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Lloyd, G., and Peter Lindstrom. ZFP Hardware Implementation. Office of Scientific and Technical Information (OSTI), June 2020. http://dx.doi.org/10.2172/1642491.

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Souppaya, Murugiah. Hardware-Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320b.

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Souppaya, Murugiah. Hardware-Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2022. http://dx.doi.org/10.6028/nist.ir.8320c.ipd.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2023. http://dx.doi.org/10.6028/nist.ir.8320d.ipd.

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Bartock, Michael. Hardware Enabled Security:. Gaithersburg, MD: National Institute of Standards and Technology, 2024. http://dx.doi.org/10.6028/nist.ir.8320d.

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Buford, James A., and Kenneth R. Letson. THAAD Hardware-in-the-Loop Signal Injection Hardware Technical Description. Fort Belvoir, VA: Defense Technical Information Center, March 1998. http://dx.doi.org/10.21236/ada341751.

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Allen, C. W. PEP-II Hardware Reliability. Office of Scientific and Technical Information (OSTI), April 2005. http://dx.doi.org/10.2172/839818.

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