Journal articles: 'GHz low-power receivers'

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Malika Begum, N., and W. Yasmeen. "A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers." International Journal of Engineering & Technology 7, no. 3.6 (July 4, 2018): 84. http://dx.doi.org/10.14419/ijet.v7i3.6.14944.

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This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.

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Ceolin, Giovana, and Lucas Compassi Severo. "0.4 V Active Biased LNA for 2.4 GHz Low Energy RF Receivers." Journal of Integrated Circuits and Systems 17, no. 2 (September 17, 2022): 1–8. http://dx.doi.org/10.29292/jics.v17i2.559.

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To meet low power requirements for Internet of Things (IoT) applications, the power dissipation of RF transceivers must be very low. As the Low Noise Amplifier (LNA) is one of the most energy consuming parts of an RF receiver, its power optimization is necessary for modern IoT devices. This work presents a 170 $\mu$W LNA capable of operating at 2.4 GHz when powered by a 0.4 V source. It is based on an inverter-based amplifier with improved gate bias voltage and automatic forward bulk biasing to operate at the moderated channel inversion level. A biasing metric is explored to analyze the best dimensions and bulk bias voltages for the NMOS transistor. Post-layout simulation results shown a 2.8 dB noise and competitive specification values compared to the state-of-the-art low-voltage LNAs.

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FRITZ, KARL E., BARBARA A. RANDALL, GREGG J. FOKKEN, MICHAEL J. DEGERSTROM, MICHAEL J. LORSUNG, JASON F. PRAIRIE, ERIC L. H. AMUNDSEN, et al. "HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY." International Journal of High Speed Electronics and Systems 13, no. 01 (March 2003): 221–37. http://dx.doi.org/10.1142/s0129156403001582.

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Under the auspices of Defense Advanced Research Project Agency's Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

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Abbasi, Arash, and Frederic Nabki. "A Design Methodology for Wideband Current-Reuse Receiver Front-Ends Aimed at Low-Power Applications." Electronics 11, no. 9 (May 6, 2022): 1493. http://dx.doi.org/10.3390/electronics11091493.

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This work gives a design perspective on low-power and wideband RF-to-Baseband current-reuse receivers (CRR). The proposed CRR architecture design shares a single supply and biasing current among both LNTA and baseband circuits to reduce power consumption. The work discusses topology selection and a suitable design procedure of the low noise transconductance amplifier (LNTA), down-conversion passive-mixer, active-inductor (AI) and TIA circuits. Layout considerations are also discussed. The receiver was simulated in 130 nm CMOS technology and occupies an active area of 0.025 mm2. It achieves a wideband input matching of less than −10 dB from 0.8 GHz to 3.4 GHz. A conversion-gain of 39.5 dB, IIP3 of −28 dBm and a double-sideband (DSB) NF of 5.6 dB is simulated at a local-oscillator (LO) frequency of 2.4 GHz and an intermediate frequency (IF) of 10 MHz, while consuming 1.92 mA from a 1.2 V supply.

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Zhang, Xin, Chunhua Wang, Yichuang Sun, and Haijun Peng. "A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers." Journal of Circuits, Systems and Computers 27, no. 03 (October 30, 2017): 1850047. http://dx.doi.org/10.1142/s0218126618500470.

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This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18[Formula: see text][Formula: see text]m Complementary Metal-Oxide-Semiconductor (CMOS) technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8[Formula: see text]dB. The input and output reflection coefficients both are lower than [Formula: see text][Formula: see text]dB over 2.5–11.5[Formula: see text]GHz. The input third-order intercept point (IIP3) is 5.6[Formula: see text]dBm at 8[Formula: see text]GHz and the noise figure (NF) is lower than 4.0[Formula: see text]dB. The LNA consumes 5.4[Formula: see text]mW power under a 1[Formula: see text]V supply voltage.

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Touati, F., and M. Loulou. "High-Performance BiCMOS Transimpedance Amplifiers for Fiber-Optic Receivers." Journal of Engineering Research [TJER] 4, no. 1 (December 1, 2007): 69. http://dx.doi.org/10.24200/tjer.vol4iss1pp69-74.

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High gain, wide bandwidth, low noise, and low-power transimpedance amplifiers based on new BiCMOS common- base topologies have been designed for fiber-optic receivers. In particular a design approach, hereafter called "A more- FET approach", added a new dimension to effectively optimize performance tradeoffs inherent in such circuits. Using conventional silicon 0.8 μm process parameters, simulated performance features of a total-FET transimpedance amplifier operating at 7.2 GHz, which is close to the technology fT of 12 GHz, are presented. The results are superior to those of similar recent designs and comparable to IC designs using GaAs technology. A detailed analysis of the design architecture, including a discussion on the effects of moving toward more FET-based designs is presented.

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Kumar Vishnoi, Manoj, and Satya Sai Srikant. "Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 160. http://dx.doi.org/10.11591/ijres.v7.i3.pp160-166.

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This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

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Kumar Vishnoi, Manoj, and Satya Sai Srikant. "Design Considerations of Reconfigurable CMOS Mixers for Multi-Standard Communication Receiver Systems." International Journal of Reconfigurable and Embedded Systems (IJRES) 7, no. 3 (November 1, 2018): 166. http://dx.doi.org/10.11591/ijres.v7.i3.pp166-172.

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This paper has been carried out the study of reconfigurable wide-band mixers that can do the frequency conversion and gain variation standards with low noise and high linearity used in multi-mode and multi-standard receivers. Over the last few years reconfigurability has become very popular in adopting technology to meet the wideband wireless communication specifications that is compatible with multi-standards like GPS (1.57 GHz), WLAN (2.4 GHz - 5.9 GHz), Bluetooth (2.402 – 2.483 GHz) and ZigBee (0.784 - 0.915 GHz) in low power consumption environment. The reconfigurability can be achieved between low and high band modes through power switching in RF frequency mixers. It can be achieved by flipping the input RF signal between gate and source terminal of input transistor and altering the trans-impedance stage output. With the concept of reconfigurable transistor pair with open and short circuit stubs, one can not only find the configurable gain with center frequencies 7.355, 8.65, 11.35 and 12.65 GHz but also with high power efficiency. Tow Thomas Bi-Quad Topology other than the traditional current commuting technique for the second order trans-impedance amplifier stage, works as a current mode filter over a tunable bandwidth. The active Gilbert mixers are used widely in most of communication system, due to its significance gain, perfect isolation, and linearity in response.

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9

Deyun Cai, Yang Shang, Hao Yu, and Junyan Ren. "Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS." IEEE Transactions on Microwave Theory and Techniques 61, no. 9 (September 2013): 3360–72. http://dx.doi.org/10.1109/tmtt.2013.2268738.

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10

D'Amico, Stefano, Annachiara Spagnolo, Andrea Donno, Vincenzo Chironi, Piet Wambacq, and Andrea Baschirotto. "A Low-Power Analog Baseband Section for 60-GHz Receivers in 90-nm CMOS." IEEE Transactions on Microwave Theory and Techniques 62, no. 8 (August 2014): 1724–35. http://dx.doi.org/10.1109/tmtt.2014.2332877.

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11

Li, Chen-Ming, Ming-Tsung Li, Kuang-Chi He, and Jenn-Hwan Tarng. "A Low-Power Self-Forward-Body-Bias CMOS LNA for 3–6.5-GHz UWB Receivers." IEEE Microwave and Wireless Components Letters 20, no. 2 (February 2010): 100–102. http://dx.doi.org/10.1109/lmwc.2009.2038526.

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12

Tiwari, Shitesh, Sumant Katiyal, and Parag Parandkar. "Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications." International Journal of Emerging Research in Management and Technology 6, no. 8 (June 25, 2018): 53. http://dx.doi.org/10.23956/ijermt.v6i8.118.

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Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage. Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation.

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Pascual, Juan Pablo, Beatriz Aja, Enrique Villa, Jose Vicente Terán, Luisa de la Fuente, and Eduardo Artal. "Performance Assessment of W-Band Radiometers: Direct versus Heterodyne Detections." Electronics 10, no. 18 (September 21, 2021): 2317. http://dx.doi.org/10.3390/electronics10182317.

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W-Band radiometers using intermediate frequency down-conversion (super-heterodyne) and direct detection are compared. Both receivers consist of two W-band low noise amplifiers and an 80-to-101 GHz filter, which conforms to the reception frequency band, in the front-end module. The back-end module of the first receiver comprises a subharmonic mixer, intermediate frequency (IF) amplification and a square-law detector. For direct detection, a W-Band detector replaces the mixer and the intermediate frequency detection stages. The performance of the whole receivers has been simulated requiring special techniques, based on data from the experimental characterization of each subsystem. In the super-heterodyne implementation a local oscillator at 27.1 GHz (with 8 dBm) with a x3 frequency multiplier is used, exhibiting an overall conversion gain around 48 dB, a noise figure around 4 dB, and an effective bandwidth over 10 GHz. In the direct detection scheme, slightly better noise performance is obtained, with a wider bandwidth, around 20 GHz, since there is no IF bandwidth limitation (~15 GHz), and even using the same 80-to-101 GHz filter, the detector can operate through the whole W-band. Moreover, W-band detector has higher sensitivity than the IF detector, increasing slightly the gain. In both cases, the receiver performance is characterized when a broadband noise input signal is applied. The radiometer characteristics have been obtained working as a total power radiometer and as a Dicke radiometer when an optical chopper is used to modulate the incoming signal. Combining this particular super-heterodyne or direct detection topologies and total power or Dicke modes of operation, four different cases are compared and discussed, achieving similar sensitivities, but better performances in terms of equivalent bandwidth and noise for the direct detection radiometer. It should be noted that this conclusion comes from a particular set of components, which we could consider as typical, but we cannot exclude other conclusions for different components, particularly for different mixers and detectors.

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REZAUL HASAN, S. M. "A LOW-VOLTAGE SCALABLE (1.8 V–0.75 V) CMOS FOLDED-CASCODE LC QUADRATURE VCO FOR RF RECEIVERS." Journal of Circuits, Systems and Computers 19, no. 04 (June 2010): 835–57. http://dx.doi.org/10.1142/s0218126610006475.

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This paper presents a scalable low voltage CMOS folded-cascode quadrature voltage controlled oscillator (QVCO) design for radio-frequency (RF) applications using the TSMC 0.18 μm 6M1P CMOS process technology. The simulated startup behavior of this proposed QVCO topology indicates that, the QVCO is free from bi-modal oscillation (frequency ambiguity). The QVCO provided extended voltage swing with the supply voltage scalable in the range of 1.8 V to 0.75 V. The QVCO operates in the frequency range of 4 GHz to 3 GHz (corresponding to supply voltage scaling in the range of 1.8 V to 0.75 V) with around 11.7% tuning range and low quadrature error. The QVCO had a power consumption under 10 mW within the specified supply voltage scaling range. Phase noise simulations using the Monte Carlo analysis provide an approximate phase noise estimate of ≈ -150 dBc/Hz at an offset of 600 KHz from the center frequency (@3.7 GHz) for operation using the 1.8 V supply voltage, using moderate inductor-Q values. Monte Carlo simulations were also carried out to determine the effects of the process, voltage and temperature variations.

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Yaghoobi, Majid, Mohammad Yavari, and Hassan Ghafoorifard. "A 17-to-24 GHz Low-Power Variable-Gain Low-Noise Amplifier in 65-nm CMOS for Phased-Array Receivers." Circuits, Systems, and Signal Processing 38, no. 12 (June 17, 2019): 5448–66. http://dx.doi.org/10.1007/s00034-019-01169-z.

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Singh, Priya, Vandana Niranjan, and Ashwni Kumar. "Design and Simulation of Low Power Differential Transimpedance Amplifier Using Degenerations Capacitors." Journal of Nanoelectronics and Optoelectronics 17, no. 10 (October 1, 2022): 1370–78. http://dx.doi.org/10.1166/jno.2022.3306.

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In today’s internet-connected culture, high-speed data transmission techniques are in high demand. Optical communication is most used techniques for data transmission with speed. High-speed amplifiers are needed, nevertheless, to obtain high gains and transform current signals into voltage gains. This is accomplished via transimpedance amplifiers, a crucial component of optical receivers. In this work, a high-speed transimpedance amplifier with negative degeneration capacitors and complete differential operation is built. The proposed design has a transimpedance gain of approximately 52.4 dB at 19.8 GHz and an average input-referred noise current of roughly 23.3 pA/√Hz. The suggested circuit also has an high gain, and low input-referred noise, excellent bandwidth all of which contribute to its low power consumption of roughly 215 uW. This makes it appropriate for Internet of Things (IoT) devices, smart devices, mobile phones, laptops, and other computer peripherals.

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Bolli, P., A. Orlati, L. Stringhetti, A. Orfei, S. Righini, R. Ambrosini, M. Bartolini, et al. "Sardinia Radio Telescope: General Description, Technical Commissioning and First Light." Journal of Astronomical Instrumentation 04, no. 03n04 (December 2015): 1550008. http://dx.doi.org/10.1142/s2251171715500087.

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In the period 2012 June–2013 October, the Sardinia Radio Telescope (SRT) went through the technical commissioning phase. The characterization involved three first-light receivers, ranging in frequency between 300[Formula: see text]MHz and 26[Formula: see text]GHz, connected to a Total Power back-end. It also tested and employed the telescope active surface installed in the main reflector of the antenna. The instrument status and performance proved to be in good agreement with the expectations in terms of surface panels alignment (at present 300[Formula: see text][Formula: see text]m[Formula: see text]rms to be improved with microwave holography), gain ([Formula: see text]0.6[Formula: see text]K/Jy in the given frequency range), pointing accuracy (5 arcsec at 22[Formula: see text]GHz) and overall single-dish operational capabilities. Unresolved issues include the commissioning of the receiver centered at 350[Formula: see text]MHz, which was compromised by several radio frequency interferences, and a lower-than-expected aperture efficiency for the 22-GHz receiver when pointing at low elevations. Nevertheless, the SRT, at present completing its Astronomical Validation phase, is positively approaching its opening to the scientific community.

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Abbasi, Arash, and Frederic Nabki. "Wideband Cascaded and Stacked Receiver Front-Ends Employing an Improved Clock-Strategy Technique." Journal of Low Power Electronics and Applications 13, no. 1 (February 2, 2023): 14. http://dx.doi.org/10.3390/jlpea13010014.

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A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.

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AVRAMOV, IVAN D. "HIGH-PERFORMANCE SURFACE TRANSVERSE WAVE RESONATORS IN THE LOWER GHz FREQUENCY RANGE." International Journal of High Speed Electronics and Systems 10, no. 03 (September 2000): 735–92. http://dx.doi.org/10.1142/s0129156400000635.

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Since the first successful surface transverse wave (STW) resonator was demonstrated by Bagwell and Bray in 1987, STW resonant devices on temperature stable cut orientations of piezoelectric quartz have enjoyed a spectacular development. The tremendous interest in these devices is based on the fact that, compared to the widely used surface acoustic waves (SAW), the STW acoustic mode features some unique properties which makes it very attractive for low-noise microwave oscillator applications in the 1.0 to 3.0 GHz frequency range in which SAW based or dielectric resonator oscillators (DRO) fail to provide satisfactory performance. These STW properties include: high propagation velocity, material Q-values exceeding three times those of SAW and bulk acoustic waves (BAW) on quartz, low propagation loss, unprecedented 1/f device phase noise, extremely high power handling ability, as well as low aging and low vibration sensitivity. This paper reviews the fundamentals of STW propagation in resonant geometries on rotated Y-cuts of quartz and highlights important design aspects necessary for achieving desired STW resonator performance. Different designs of high- and low-Q, low-loss resonant devices and coupled resonator filters (CRF) in the 1.0 to 2.5 GHz range are characterized and discussed. Design details and data on state-of-the-art STW based fixed frequency and voltage controlled oscillators (VCO) with low phase noise and high power efficiency are presented. Finally, several applications of STW devices in GHz range data transmitters, receivers and sensors are described and discussed.

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Schrüfer, Daniel, Jürgen Röber, Timo Mai, and Robert Weigel. "A Low-Power Squaring Circuit with Regulated Output and Improved Settling Time in 180 nm CMOS for 3–5 GHz IR-UWB Applications." Advances in Radio Science 19 (December 17, 2021): 79–84. http://dx.doi.org/10.5194/ars-19-79-2021.

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Abstract. This paper demonstrates a low-power squaring circuit for 3–5 GHz non-coherent Impulse-Radio Ultra-Wideband (IR-UWB) receivers for Pulse Position Modulation (PPM) in a low-cost 180 nm CMOS technology. The squaring, which is the key element in typical IR-UWB receivers, is performed exploiting the non-linear transfer function of a MOS transistor. For a high gain at low power consumption the transistor is biased in the moderate inversion region, where the second-order derivative of the transconductance gm and, as a result, the quadratic term in the transfer function reaches a maximum. A control loop was implemented to set the dc output voltage to a defined value and thus to allow a comparison of the squarer output signal with a defined threshold voltage, which can easily be set and adjusted (e.g. by a DAC). To speed up the settling time of the output and hence to reach higher data rates, a novel slew-rate booster is implemented at the output. Thereby, the squarer is capable of data rates of up to 15.6 Mbit s−1, which is more than two times higher compared to the circuit without the slew-rate booster, while only consuming 72.4 µW in addition. In the extracted post-layout simulations the whole circuitry consumes 724 µA at a 1.8 V power supply, resulting in a power consumption of 1.3 mW.

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A. Kareem, Thaar, and Hatem Trabelsi. "A Broadband High Gain, Noise-Canceling Balun LNA with 3–5 GHz UWB Receivers for Medical Applications." International Journal of Online and Biomedical Engineering (iJOE) 18, no. 03 (March 8, 2022): 60–71. http://dx.doi.org/10.3991/ijoe.v18i03.28009.

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The Ultra-Wideband Wireless Body Area Network (UWB-WBAN) has been identified to provide an efficient, low-power, and improved wireless communication between sensor nodes worn by the human body to monitor physiological signals. The first part of the UWB receiver is a low noise amplifier (LNA). This article describes an upgrade to a sort of balun LNA that is entirely transistor-based and devoid of inductors for medical worn communication service. The balun LNA uses common gate and a common source configuration which cancels the noise generated by the common gate. This work uses the transistors in place of resistors to minimize the integrated circuit's area, as well as finding the best values for the dimensions of the transistor to minimize energy consumption, achieve a high gain and good linearity. This reduces the noise figure. The designed system utilizes the UWB frequency range of 3-5 GHz and a voltage supply of 1.8V. The designed balun LNA is able to achieve a peak gain of 25.5 dB and noise figure (NF) less than 3.2-3.5 dB using 180µm TSMC CMOS technology. The IIP3 is quite high at 2 dBm, whereas the IIP2 maximum is 21 dBm. The entire power consumption is less than 7.2 mW.

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Gu, Cheng Jie, Xiang Ning Fan, Kuan Bao, and Zai Jun Hua. "Design of a Reconfigurable Mixer for Multi-Mode Multi-Standard Receivers." Applied Mechanics and Materials 618 (August 2014): 553–57. http://dx.doi.org/10.4028/www.scientific.net/amm.618.553.

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This paper reports a reconfigurable wideband passive mixer for direct conversion multimode multi-standard receivers. Different from the traditional current-commutating passive mixers, transconductor stage of this design is variable. And the TIA stage is a second-order low-pass transimpedance amplifiers based on Tow-Thomas biquad topology, working as a current mode filter. The mixer is controlled by a 4-bit control word to realize the flexible gain and variable intermediate frequency bandwidth. Other characteristics such as power consumption, NF, and linearity is also reconfigurable according to different communication standard. Circuit is implementing in 0.18μm CMOS technology. Post-simulation results show that, with the radio frequency ranges from 700 MHz to 2.6 GHz, it provides four voltage conversion gains (10/16/22/28dB) and three-3 dB intermediate frequency bandwidth (5/7.5/10MHz). Under the maximum gain, the double sideband NF of the mixer is 8.4 dB. And under the minimum gain, IIP3 is 13 dBm. The chip occupies an area of 0.248 mm2 and drains a current of 8.5mA from a 1.8 V supply when the mixer has highest gain.

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Braun, S., A. Frech, and P. Russer. "Measurement of electromagnetic interference in time-domain." Advances in Radio Science 6 (May 26, 2008): 311–13. http://dx.doi.org/10.5194/ars-6-311-2008.

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Abstract. Time-domain EMI measurement systems allow measurement time to be reduced by several orders of magnitude. In this paper a novel real-time operating time-domain EMI measurement system is presented. By the use of several analog-to-digital converters the dynamic range requested by the international EMC standards is achieved. A real-time operating digital signal processing unit is presented. The frequency band that is investigated is subdivided into several sub-bands. A novel implementation of the 9 kHz IF filter for the frequency 150 kHz to 1 GHz is presented. By this way the measurement time has been reduced by a factor of 8000 in comparison to conventional EMI receivers. During emission measurements performed with a modelled IF-bandwidth of 9 kHz the noise floor is decreased to −19 dBµV in the average detector mode by the implemented low noise power splitter. Measurements have been performed with the improved measurement system in the frequency range 30 MHz–1 GHz.

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Kojima, T., S. Masui, W. Shan, and Y. Uzawa. "Characterization of a low-noise superconductor–insulator–superconductor-based microwave amplifier with local oscillator phase-adjusting architecture." Applied Physics Letters 122, no. 7 (February 13, 2023): 072601. http://dx.doi.org/10.1063/5.0134595.

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This paper describes a low-noise microwave amplifier based on up- and down-frequency-conversion processes in quasiparticle superconductor–insulator–superconductor (SIS) tunnel junctions. The SIS amplifier was configured with two SIS frequency-converter modules and a cryogenic millimeter-wave isolator inserted between them. Moreover, a local oscillator (LO) using millimeter-wave attenuators and a phase shifter was considered. This setup allowed the control of individual LO power and differential phase in these SIS frequency converters to optimize the amplifier performance. The SIS amplifier showed noise temperatures as low as 11 K and a 6–8 dB gain from nearly DC to 5 GHz. The attained microwave performance is promising for obtaining large-format arrays, such as multibeam heterodyne receivers. Moreover, this two-frequency-converter concept based on SIS junctions might enable microwave applications, such as wideband non-reciprocal circuits in isolators, gyrators, and circulators, which are essential devices in the quantum computing and radio astronomy fields.

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Huo, Dongquan, Luhong Mao, Liji Wu, and Xiangmin Zhang. "A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology." Electronics 9, no. 9 (August 24, 2020): 1369. http://dx.doi.org/10.3390/electronics9091369.

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Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

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Deal, W. R., Kevin Leong, Alex Zamora, Wayne Yoshida, Mike Lange, Ben Gorospe, Khanh Nguyen, and Gerry X. B. Mei. "A Low-Power 670-GHz InP HEMT Receiver." IEEE Transactions on Terahertz Science and Technology 6, no. 6 (November 2016): 862–64. http://dx.doi.org/10.1109/tthz.2016.2614264.

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Cai, Wei, and Frank Shi. "2.4 GHZ HETERODYNE RECEIVER FOR HEALTHCARE APPLICATION." International Journal of Pharmacy and Pharmaceutical Sciences 8, no. 2 (September 17, 2016): 22. http://dx.doi.org/10.22159/ijpps.2016v8s2.15214.

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<p class="lead">The objective of this research was to design a basic 2.4 GHz heterodyne receiver for healthcare on a 130um CMOS process. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design. In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The second part of this thesis presents a low power 2.4 GHz down conversion Gilbert Cell mixer. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology. In the first part, a low noise amplifier (LNA) design reaches the NF of 2 dB, has a power consumption of 2.2 mW, and has a gain of 20dB. The second part of this proposal presents a low power 2.4 GHz down conversion Gilbert Cell mixer. The obtained result shows a conversion gain of 14.6 dB and power consumption of 8.2 mW at a 1.3V supply voltage. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The final simulation of the phase noise is-128 dBc/Hz, and the tuning range is 2.3 GHz-2.5 GHz while the total power consumption is 3.25 mW.<strong> </strong>The performance of the receiver meets the specification requirements of the desired standard.</p>

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Royer, Alain, Alexandre Roy, Sylvain Jutras, and Alexandre Langlois. "Review article: Performance assessment of radiation-based field sensors for monitoring the water equivalent of snow cover (SWE)." Cryosphere 15, no. 11 (November 4, 2021): 5079–98. http://dx.doi.org/10.5194/tc-15-5079-2021.

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Abstract. Continuous and spatially distributed data of snow mass (water equivalent of snow cover, SWE) from automatic ground-based measurements are increasingly required for climate change studies and for hydrological applications (snow hydrological-model improvement and data assimilation). We present and compare four new-generation sensors, now commercialized, that are non-invasive and based on different radiations that interact with snow for SWE monitoring: cosmic-ray neutron probe (CRNP), gamma ray monitoring (GMON) scintillator, frequency-modulated continuous-wave radar (FMCW radar) at 24 GHz and global navigation satellite system (GNSS) receivers (GNSSr). All four techniques have relatively low power requirements, provide continuous and autonomous SWE measurements, and can be easily installed in remote areas. A performance assessment of their advantages, drawbacks and uncertainties is discussed from experimental comparisons and a literature review. Relative uncertainties are estimated to range between 9 % and 15 % when compared to manual in situ snow surveys that are also discussed. Results show the following. (1) CRNP can be operated in two modes of functioning: beneath the snow, it is the only system able to measure very deep snowpacks (> 2000 mm w.e.) with reasonable uncertainty across a wide range of measurements; CRNP placed above the snow allows for SWE measurements over a large footprint (∼ 20 ha) above a shallow snowpack. In both cases, CRNP needs ancillary atmospheric measurements for SWE retrieval. (2) GMON is the most mature instrument for snowpacks that are typically up to 800 mm w.e. Both CRNP (above snow) and GMON are sensitive to surface soil moisture. (3) FMCW radar needs auxiliary snow-depth measurements for SWE retrieval and is not recommended for automatic SWE monitoring (limited to dry snow). FMCW radar is very sensitive to wet snow, making it a very useful sensor for melt detection (e.g., wet avalanche forecasts). (4) GNSSr allows three key snowpack parameters to be estimated simultaneously: SWE (range: 0–1000 mm w.e.), snow depth and liquid water content, according to the retrieval algorithm that is used. Its low cost, compactness and low mass suggest a strong potential for GNSSr application in remote areas.

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Zolfaghari, A., and B. Razavi. "A low-power 2.4-GHz transmitter/receiver CMOS IC." IEEE Journal of Solid-State Circuits 38, no. 2 (February 2003): 176–83. http://dx.doi.org/10.1109/jssc.2002.807580.

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Homayoun, Aliakbar, and Behzad Razavi. "A Low-Power CMOS Receiver for 5 GHz WLAN." IEEE Journal of Solid-State Circuits 50, no. 3 (March 2015): 630–43. http://dx.doi.org/10.1109/jssc.2014.2386900.

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Ma, Heping, Hua Xu, Bei Chen, and Yin Shi. "An ISM 2.4 GHz low power low-IF RF receiver front-end." Journal of Semiconductors 36, no. 8 (August 2015): 085002. http://dx.doi.org/10.1088/1674-4926/36/8/085002.

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Vouilloz, A., M. Declercq, and C. Dehollain. "A low-power CMOS super-regenerative receiver at 1 GHz." IEEE Journal of Solid-State Circuits 36, no. 3 (March 2001): 440–51. http://dx.doi.org/10.1109/4.910483.

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Chang, Tien-Hung, Chang-Zhi Chen, Yo-Sheng Lin, and Guo-Wei Huang. "A low-power low-phase-noise 48-GHz CMOS LC VCO for 60-GHz dual-conversion receiver." Microwave and Optical Technology Letters 51, no. 4 (April 2009): 997–1000. http://dx.doi.org/10.1002/mop.24256.

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Weinan, Li, Huang Yumei, and Hong Zhiliang. "A low power 3–5 GHz CMOS UWB receiver front-end." Journal of Semiconductors 30, no. 3 (March 2009): 035005. http://dx.doi.org/10.1088/1674-4926/30/3/035005.

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Cha, Minyeon, and Ickjin Kwon. "A low-power 5-GHz CMOS RF receiver for WLAN applications." Microwave and Optical Technology Letters 54, no. 4 (February 16, 2012): 842–47. http://dx.doi.org/10.1002/mop.26700.

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Ha, Min-Cheol, Byung-Jun Park, Young-Jin Park, and Yun-Seong Eo. "A Low Power Single-End IR-UWB CMOS Receiver for 3~5 GHz Band Application." Journal of Korean Institute of Electromagnetic Engineering and Science 20, no. 7 (July 31, 2009): 657–63. http://dx.doi.org/10.5515/kjkiees.2009.20.7.657.

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LIU, WEIYANG, JINGJING CHEN, HAIYONG WANG, and NANJIAN WU. "A LOW POWER 2.4 GHz RF TRANSCEIVER FOR ZIGBEE APPLICATIONS." Journal of Circuits, Systems and Computers 22, no. 09 (October 2013): 1340007. http://dx.doi.org/10.1142/s0218126613400070.

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This paper presents a low power RF transceiver for 2.4 GHz ZigBee applications. The current reused inductor-less-load balun low noise amplifier (LNA) with quadrature mixer is proposed for area and power saving for low-IF receiver. The transmitter adopts power efficient power amplifier (PA) to improve transmitting efficiency. This RF transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves 6.5 dB noise figure (NF) and 20 dB conversion gain. The transmitter delivers maximum +3 dBm output power with PA efficiency of 30%. The receiver and transmitter front-end dissipate 1.9 mW and 5.3 mW at 1.8 V supply, respectively. The whole die area is 0.95 mm2.

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Ellinger, Frank, David Fritsche, Gregor Tretter, Jan Dirk Leufker, Uroschanit Yodprasit, and C. Carta. "Review of Millimeter-Wave Integrated Circuits With Low Power Consumption for High Speed Wireless Communications." Frequenz 71, no. 1-2 (January 1, 2017): 1–9. http://dx.doi.org/10.1515/freq-2016-0119.

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Abstract In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

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Li, Dongze, Qingzhen Xia, Jiawei Huang, Jinwei Li, Hudong Chang, Bing Sun, and Honggang Liu. "A 24 GHz Direct Conversion Receiver for FMCW Ranging Radar Based on Low Flicker Noise Mixer." Electronics 10, no. 6 (March 18, 2021): 722. http://dx.doi.org/10.3390/electronics10060722.

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In this paper, a 24 GHz direct conversion receiver (DCR) for frequency-modulated continuous-wave (FMCW) ranging radar based on low flicker noise mixer in 90 nm silicon-on-insulator (SOI) CMOS technology is presented. A low-noise and low-power low-noise-amplifier (LNA) adopting simultaneous noise and input matching (SNIM) method is designed. Neutralized technology and boost inductor are introduced to improve performance. The measurement results of standalone LNA show that the peak gain is 17.2 dB at 23.8 GHz and the −3 dB bandwidth is around 2.2 GHz from 22.8 GHz to 25 GHz. The LNA achieves an average 3 dB NF within the 24 GHz band. A current-bleeding mixer is used to lower noise and the factors influencing flicker noise have been discussed. Proper element values and local oscillator (LO) power have been chosen to make the mixer low-noise. Measurement results illustrate that the receiver exhibits 20.3 dB peak gain, 7 dB SSB noise figure (NF) and −22 dBm IP1dB. Flicker noise of the mixer and the receiver are measured respectively and the noise knee-point of receiver is observed 60 kHz. The receiver consumes only 16 mW with chip area of 0.65 mm2 including pads. The results demonstrate that the proposed receiver can be a promising candidate for FMCW ranging radar.

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Bergveld, H. J., K. M. M. van Kaam, D. M. W. Leenaerts, K. J. P. Philips, A. W. P. Vaassen, and G. Wetkzer. "A low-power highly digitized receiver for 2.4-GHz-band GFSK applications." IEEE Transactions on Microwave Theory and Techniques 53, no. 2 (February 2005): 453–61. http://dx.doi.org/10.1109/tmtt.2004.840756.

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Miao, Yannan, Jian-Wei Zhang, and Cun-Lu Yin. "Passive mixer with 24-GHz LO signal generator for low-power receiver." International Journal of Electronics Letters 2, no. 4 (October 2013): 197–202. http://dx.doi.org/10.1080/21681724.2013.841086.

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Lin, Yu-Tso, Yo-Sheng Lin, and Shey-Shi Lu. "A low-power 2.4-GHz receiver front-end for wireless sensor networks." Microwave and Optical Technology Letters 51, no. 12 (September 23, 2009): 3021–24. http://dx.doi.org/10.1002/mop.24812.

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Ulusoy, Ahmet Çağrı, Gang Liu, Andreas Trasser, and Hermann Schumacher. "Hardware efficient receiver for low-cost ultra-high rate 60 GHz wireless communications." International Journal of Microwave and Wireless Technologies 3, no. 2 (March 3, 2011): 121–29. http://dx.doi.org/10.1017/s1759078711000110.

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This paper presents a hardware efficient receiver architecture, to be used in low-cost, ultra-high rate 60 GHz wireless communication systems. The receiver utilizes a simple, feed-forward carrier recovery concept, performing phase and frequency synchronization in the analog domain. This enables 1-bit baseband processing without a need of ultra-high speed and high precision analog-to-digital conversion, offering a strong simplification of the system architecture and comparatively low power consumption. In a first prototype implementation, the receiver is realized in a low-cost SiGe technology as two separate ICs: the 60 GHz/5 GHz downconverter, and the intermediate frequency synchronous demodulator. The simple synchronous reception concept is experimentally validated for up to 3.5 Gbit/s data rate, which constituted the limit of the existing experimental setup. Furthermore, the downconverter demonstrates that low-cost technologies (fop/fmax ~ 0.75) can be used to realize short-range data links at 60 GHz, with low-noise amplifiers in a more performant technology as needed.

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Manjula, S., M. Malleshwari, and M. Suganthy. "Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver." International Journal of Engineering & Technology 7, no. 2.24 (April 25, 2018): 448. http://dx.doi.org/10.14419/ijet.v7i2.24.12132.

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This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance. For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.

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Kraemer, Michael, Daniela Dragomirescu, and Robert Plana. "Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology." International Journal of Microwave and Wireless Technologies 3, no. 2 (March 8, 2011): 131–38. http://dx.doi.org/10.1017/s1759078711000067.

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The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

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Huang, Shuigen, Min Lin, Zongkun Zhou, and Xiaoyun Li. "An ultra-low-power 2.4 GHz RF receiver in CMOS 55 nm process." IEICE Electronics Express 15, no. 5 (2018): 20180016. http://dx.doi.org/10.1587/elex.15.20180016.

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Do, Aaron V., Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, and Alper Cabuk. "An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications." IEEE Transactions on Circuits and Systems I: Regular Papers 57, no. 10 (October 2010): 2675–84. http://dx.doi.org/10.1109/tcsi.2010.2047750.

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Li, Huanbo, Jixin Chen, Peigen Zhou, Jiayang Yu, Pinpin Yan, Debin Hou, and Wei Hong. "Compact low‐power 154 GHz receiver front‐end in 0.13 µm SiGe BiCMOS." IET Microwaves, Antennas & Propagation 14, no. 9 (May 15, 2020): 955–59. http://dx.doi.org/10.1049/iet-map.2019.0511.

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Kwon, Ickjin, and Minkyung Lee. "An integrated 8‐mW 2.4‐GHz CMOS RF receiver for low‐power WPAN." Microwave and Optical Technology Letters 50, no. 9 (September 2008): 2345–48. http://dx.doi.org/10.1002/mop.23652.

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Weikle, Robert M., N. Scott Barker, Arthur W. Lichtenberger, Matthew F. Bauwens, and Naser Alijabbari. "Heterogeneous Integration and Micromachining Technologies for Terahertz Devices and Components." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 002041–81. http://dx.doi.org/10.4071/2015dpc-tha31.

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Terahertz electronics has been a topic of research and development for many years, motivated largely by the technological needs of the radio astronomy and remote sensing scientific communities. Over the past decade, however, this field has experienced dramatic growth and intense, renewed interest from academic researchers and federal agencies, as well as from industry. This interest has arisen, in part, from recent funding initiatives from the federal government (such as DARPA's Terahertz Electronics Program), but is also largely due to the establishment of a commercial infrastructure that has made test and measurement instrumentation available to the engineers and scientists working at these frequencies. Moreover, the emergence of CMOS as a potential submillimeter-wave device technology has greatly expanded access to this spectral region by providing circuit designers with a platform for realizing terahertz circuits without need for specialized fabrication facilities or processes. The recent and rapid progress in terahertz electronics has created a demand for improved approaches to packaging and integration, as well as a need for new measurement instrumentation for characterizing emerging terahertz devices. This paper focuses on two recent research developments aimed at addressing these needs and broadening the technology base for both terahertz system implementation and terahertz metrology. These developments include (1) the development of a direct-contact probe technology that permits on-wafer scattering-parameter characterization and measurement of planar integrated devices at frequencies to 1 THz and beyond, and (2) the establishment of processing technologies that permit fabrication of highly-integrated submillimeter-wave diode-based circuits, such as heterodyne receivers and frequency multipliers, that are based on heterogeneous integration of III-V semiconductor devices with thin silicon membranes as a support and integration substrate. The technical foundation for each of these efforts is micromachining of silicon that allow the formation of mechanically-robust and low-loss membrane carriers to support terahertz devices and circuitry. Two examples of heterogeneous integration with silicon as an approach to packaging terahertz components are detailed in this paper. These include development of micromachined probes for on-wafer measurements of devices and circuits in the WR-1.0 waveguide band (0.75 – 1.1 THz). The probe design concept will be presented and methods for characterizing the probe described. Measurements demonstrate that the probes exhibit an insertion loss of less than 7 dB and return loss of greater than 15 dB over 750—1100 GHz band, yielding the first demonstration of on-wafer probe operating above 1 THz. In addition, an example of heterogeneous integration/packaging of a submillimeter-wave frequency quadrupler operating at 160 GHz with efficiency of 30% and corresponding output power of 70 mW will be discussed. The quadrupler design includes two frequency doubler stages in cascade and is based on a balanced circuit architecture that addresses degradation issues often arising from impedance mismatches between multiplier stages. A unique quasi-vertical diode fabrication process consisting of transfer of GaAs epitaxy to the thin silicon support substrate is used to implement the quadrupler, resulting in an integrated drop-in chip module that incorporates 18 varactors, matching networks and beamleads for mounting.

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Journal articles on the topic 'GHz low-power receivers'

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