Dissertations / Theses on the topic 'Gate oxide reliability'
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Owens, Gethin Lloyd. "Design of a reliability methodology : modelling the influence of temperature on gate oxide reliability." Thesis, Durham University, 2007. http://etheses.dur.ac.uk/2695/.
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An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models. Each model is based on a physics of failure approach and includes on the effects of temperature. At all stages the models are verified experimentally on modern deep sub-micron devices. The research provides the foundations of a tool which gives the user the opportunity to make appropriate trade-offs between performance and reliability, and that can be implemented in the early stages of product development.
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Zeng, Xu, and 曾旭. "Electrical reliability of N-Mos devices with N2O-based oxides as gate dielectrics." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 1996. http://hub.hku.hk/bib/B31235475.
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Zeng, Xu. "Electrical reliability of N-Mos devices with N2O-based oxides as gate dielectrics /." Hong Kong : University of Hong Kong, 1996. http://sunzi.lib.hku.hk/hkuto/record.jsp?B1966980X.
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Jayaraman, Rajsekhar. "Reliability and 1/f noise properties of MOSFETs with nitrided oxide gate dielectrics." Thesis, Massachusetts Institute of Technology, 1988. http://hdl.handle.net/1721.1/41582.
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Yan, Liang. "Characterisation of gate oxide and high-k dielectric reliability in strained si and sige cmos transistors." Thesis, University of Newcastle Upon Tyne, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.506541.
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Kutty, Karan. "CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY." Master's thesis, University of Central Florida, 2010. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2703.
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This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
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MA, JUN. "STUDY OF GATE OXIDE BREAKDOWN AND HOT ELECTRON EFFECT ON CMOS CIRCUIT PERFORMANCES." Doctoral diss., University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3547.
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In the modern semiconductor world, there is a significant scaling of the transistor dimensions--The transistor gate length and the gate oxide thickness drop down to only several nanometers. Today the semiconductor industry is already dominated by submicron devices and other material devices for the high transistor density and performance enhancement. In this case, the semiconductor reliability issues are the most important thing for commercialization. The major reliability issues caused by voltage are hot carrier effects (HCs) and gate oxide breakdown (BD) effects. These issues are recently more important to industry, due to the small size and high lateral field in short-channel of the device will cause high electrical field and other reliability issues. This dissertation primarily focuses on the study of the CMOS device gate oxide breakdown effect on different kinds of circuits performance, also some HC effects on circuit's performance are studied. The physical mechanisms for BD have been presented. A practical and accurate equivalent breakdown circuit model for the CMOS device was studied to simulate the RF performance degradation on the circuit level. The BD location effect has been evaluated. Furthermore, a methodology was developed to predict the BD effects on the circuit's performances with different kinds of BD location. It also provides guidance for the reliability considerations of the digital, analog, and RF circuit design. The BD effects on digital circuits SRAM, analog circuits Sample&Hold, and RF building blocks with the nanoscale device--low noise amplifier, LC oscillator, mixer, and power amplifier, have been investigated systematically. Finally 90 nm device will be used to study the HC effect on the circuit's performance.
The contributions of this dissertation include: Providing a thorough study of the gate oxide breakdown issues caused by the voltage stress on the device--from device level to circuit level; Studying real voltage stress case--high frequency (950 MHz) dynamic stress, and comparing with the traditional DC stress; A simple, practical, and analytical method is derived to study the gate oxide breakdown effect including breakdown location effect and soft / hard breakdown on the digital, analog and RF circuits performances. A brief introduction and simulation for 90 nm device HC effect provide some useful information and helpful data for the industry. The gate oxide breakdown effect is the most common device reliability issue. The successful results of this dissertation, from device level to circuit level, provide an insight on how the BD affects the circuit's performance, and also provide some useful data for the circuit designers in their future work.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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Matsumoto, Takashi. "Impact of Bias Temperature Instability and Random Telegraph Noise on CMOS Logic Circuits." 京都大学 (Kyoto University), 2015. http://hdl.handle.net/2433/199461.
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松本, 高士. "バイアス温度不安定性とランダムテレグラフノイズがCMOS論理回路特性に及ぼす影響." Kyoto University, 2015. http://hdl.handle.net/2433/199558.
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Boyer, Ludovic. "Analyse des propriétés de l'oxyde de grille des composants semi-conducteurs de puissance soumis à des contraintes électro-thermiques cycliques : vers la définition de marqueurs de vieillissement." Thesis, Montpellier 2, 2010. http://www.theses.fr/2010MON20028/document.
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Les composants semi-conducteurs de puissance sont aujourd'hui au c?ur des systèmes de conversion d'énergie et sont de plus en plus employés dans le domaine des transports, notamment dans des applications critiques induites par l'émergence des véhicules hybrides et d'avions plus électriques. Durant l'exploitation des systèmes de conversion d'énergie, des contraintes significatives sont imposées aux composants semi-conducteurs de puissance, dégradant ainsi leur fonctionnement. Dans une application critique, ces dégradations peuvent activer la défaillance d'un système électrique et ainsi avoir des conséquences graves d'un point de vue économique et de sécurité. Il existe alors une forte demande concernant une compréhension des modes de défaillances et des mécanismes de vieillissement des composants semi-conducteurs de puissance. Il en est de même pour le développement de nouvelles techniques de caractérisations pour le suivi de leur vieillissement. Le suivi de l'évolution de paramètres de l'oxyde de grille de véhicules tests par le biais de la méthode Capacité-Tension ou C(V) - couramment employée en micro-électronique - et de la méthode de l'onde thermique ou MOT - développée au sein du Groupe Énergie et Matériaux de l'IES -, ainsi que leur adaptation à des composants semi-conducteurs de puissance, constituent l'essentiel du travail de cette thèse. Le couplage de la MOT à la C(V) a permis de localiser sommairement les charges injectées dans l'oxyde de grille des véhicules tests lorsqu'ils ont été soumis à des contraintes électriques similaires à celles subies dans les systèmes de conversion d'énergiePower semi-conductor devices are increasingly used as key parts of embedded power conversion systems in critical applications such as aerospace industry and ground transport. In such critical applications, these devices are submitted to harsh electrical, thermal and mechanical environments stresses which may significantly alter their reliability. An embedded power conversion system failure due to a power semi-conductor device breakdown may induce catastrophic results in terms of human safety, as well as economical dimensions. There is, indeed, a continuous demand on an increasing knowledge concerning the failure modes and the ageing mechanisms of power semi-conductor devices, as well as for development of new characterization techniques for ageing monitoring. The greatest part of the present work is focused on the monitoring of gate oxide properties evolutions of samples structures using the Capacitance-Voltage method (C-V method) -mainly employed in microelectronics- and the Thermal Step Method (TSM) -developed in Energy and Materials Group of IES-, as well as applying them to power semi-conductor devices. Coupling TSM and C-V method has allowed to approximately locate injected charges in the gate oxide of sample devices when submitted to electrical stresses comparable to the ones submitted to power semi-conductor devices
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Kumar, Pushpendra. "Impact of 14/28nm FDSOI high-k metal gate stack processes on reliability and electrostatic control through combined electrical and physicochemical characterization techniques." Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT114/document.
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Cette thèse concerne l’étude des procédés de fabrication des grilles HKMG des technologies FDSOI 14 et 28 nm sur les performances électriques des transistors MOS. Elle a porté spécifiquement sur l'aspect fiabilité et la maîtrise du travail de sortie effectif (WFeff), au travers de la diffusion des additifs comme le lanthane (La) et l’aluminium (Al). Ce travail combine des techniques de caractérisation électriques et physico-chimiques et leur développement. L'effet de l'incorporation de ces additifs sur la fiabilité et la durée de vie du dispositif a été étudié. Le lanthane dégrade les performances de claquage TDDB et de dérives suite aux tests aux tensions négatives. L’introduction d’aluminium améliore le claquage TDDB, mais dégrade les dérives aux tensions positives. Ces comportements ont été reliés à des mécanismes physiques. Par ailleurs, la diffusion de ces additifs dans l’empilement de grille a été étudiée pour différents matériaux high-k en fonction de la température et de la durée de recuit de diffusion. Les doses d’additifs ont pu être ainsi mesurées, comparées et corrélées au décalage de travail de sortie effectif de grille. On a également étudié, les influences des paramètres du procédé de dépôt de grille TiN sur leur microstructure et les propriétés électriques du dispositif, identifiant certaines conditions à même de réduire la taille de grain ou la dispersion d’orientation cristalline. Toutefois, les modulations obtenues sur le travail de sortie effectif de grille dépendent plus du ratio Ti/N, suggérant un changement du dipôle à l'interface SiO2 / high-k. Enfin, une technique éprouvée de mesure de spectroscopie à rayon X sous tension a pu être mise en place grâce des dispositifs spécifiques et une méthodologie adaptée. Elle permet de mesurer les positions relatives des bandes d’énergie à l'intérieur de l’empilement de grille. Cette technique a démontré que le décalage du travail de sortie effectif induits par des additifs (La or Al) ou par des variations d'épaisseur de grille métallique TiN provient de modifications du dipôle à l'interface SiO2/ high-kThis Ph.D. thesis is focused on the impact of the 14 and 28 nm FDSOI technologies HKMG stack processes on the electrical performance of MOS transistors. It concerns specifically the reliability aspect and the engineering of effective workfunction (WFeff ), through diffusion of lanthanum (La) and aluminum (Al) additives. This work combines electrical and physicochemical characterization techniques, and their development. The impact of La and Al incorporation, in the MOS gate stack, on reliability and device lifetime has been studied. La addition has a significant negative impact on device lifetime related to both NBTI and TDDB degradations. Addition of Al has a significant negative impact on lifetime related to PBTI, but on the contrary improves the lifetime for TDDB degradation. These impacts on device lifetime have been well correlated to the material changes inside the gate oxides. Moreover, diffusion of these additives into the HKMG stack with annealing temperature and time has been studied on different high-k materials. The diffused dose has been compared with the resulting shift in effective workfunction (WFeff), evidencing clear correlation. In addition, impact of TiN metal gate RF-PVD parameters on its crystal size and orientation, and device electrical properties has been studied. XRD technique has been used to obtain the crystal size and orientation information. These properties are significantly modulated by TiN process, with a low grain size and a unique crystal orientation obtained in some conditions. However, the WFeff modulations are rather correlated to the Ti/N ratio change, suggesting a change in the dipole at SiO2/high-k interface. Lastly, using specific test structures and a new test methodology, a robust and accurate XPS under bias technique has been developed to determine the relative band energy positions inside the HKMG stack of MOS devices. Using this technique, we demonstrated that WFeff shift induced by La and Al or by variations in gate thickness originates due to modifications of the dipole at SiO2/high-k interface
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Chen, Chang-Chih. "System-level modeling and reliability analysis of microprocessor systems." Diss., Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/53033.
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Frontend and backend wearout mechanisms are major reliability concerns for modern microprocessors. In this research, a framework which contains modules for negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), hot carrier injection (HCI), gate-oxide breakdown (GOBD), backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze the impact of each wearout mechanism on state-of-art microprocessors and to accurately estimate microprocessor lifetimes due to each wearout mechanism. Taking into account the detailed thermal profiles, electrical stress profiles and a variety of use scenarios, composed of a fraction of time in operation, a fraction of time in standby, and a fraction of time when the system is off, this work provides insight into lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units for a system. This enables circuit designers to know if their designs will achieve an adequate lifetime and further make any updates in the designs to enhance reliability prior to committing the designs to manufacture.
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Mamy, Randriamihaja Yoann. "Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors." Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4781/document.
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L'étude de la fiabilité représente un enjeu majeur de la qualification des technologies de l'industrie de la microélectronique. Elle est traditionnellement étudiée en suivant la dégradation des paramètres des transistors au cours du temps, qui sert ensuite à construire des modèles physiques expliquant le vieillissement des transistors. Nous avons fait le choix dans ces travaux d'étudier la fiabilité des transistors à l'échelle microscopique, en nous intéressant aux mécanismes de ruptures de liaisons atomiques à l'origine de la création des défauts de l'oxyde de grille. Nous avons tout d'abord identifié la nature des défauts et modéliser leurs dynamiques de capture de charges afin de pouvoir reproduire leur impact sur des mesures électriques complexes. Cela nous a permis de développer une nouvelle méthodologie de localisation des défauts, le long de l'interface Si-SiO2, ainsi que dans le volume de l'oxyde. La mesure des dynamiques de créations de défauts pour des stress de type porteurs chauds et menant au claquage de l'oxyde de grille nous a permis de développer des modèles de dégradation de l'oxyde, prédisant les profils de défauts créés à l'interface et dans le volume de l'oxyde. Nous avons enfin établi un lien précis entre l'impact de la dégradation d'un transistor sur la perte de fonctionnalité d'un circuit représentatif du fonctionnement d'un produit digital.L'étude et la modélisation de la fiabilité à l'échelle microscopique permet d'avoir des modèles plus physiques, offrant ainsi une plus grande confiance dans les extrapolations de durées de vie des transistors et des produitsReliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation
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Pomès, Emilie. "Amélioration et suivi de la robustesse et de la qualité de MOSFETs de puissance dédiés à des applications automobiles micro-hybrides." Thesis, Toulouse, INSA, 2012. http://www.theses.fr/2012ISAT0039/document.
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Dans le contexte écologique actuel, les équipementiers automobiles européens sont dans l’obligation de développer des systèmes innovants afin de réduire les rejets de gaz à effet de serre des véhicules. Les nouvelles applications électroniques micro-hybrides exigent le développement de stratégies quant à l’intégration des systèmes et la réduction des pertes. Ainsi, une proposition a consisté à réaliser des modules de puissance constitués de transistors MOSFETs basse tension fort courant. L’application de type alterno-démarreur plus communément nommée « Stop & Start »exige des composants toujours plus robustes et fiables du fait de la sollicitation en mode d’avalanche sous des températures pouvant atteindre 175°C.Les travaux de recherche présentés dans cette thèse portent donc sur l’aspect d’optimisation de la robustesse et de la fiabilité des composants. Tout d’abord, il était essentiel de comprendre l’avalanche et ses enjeux pour la technologie. Ensuite dans ce contexte, le procédé notamment autour de l’oxyde de grille a été amélioré afin de garantir la tenue en mode de sollicitation grille-source et grille-drain pour satisfaire les exigences de fiabilité. En outre, le développement d’un test innovant de la puce, dérivé du QBD, a permis d’évaluer précisément les modifications apportées sur le procédé de fabrication et d’être corrélé avec les résultats des essais de fiabilité. Enfin, le cycle de vie d’un MOSFET nécessite un suivi qualité précis qui se compose de deux aspects essentiels. En premier lieu, le suivi des paramètres électriques et de leur dérive par une analyse statistique « postprocessing». En second lieu, la mise en place d’un outil de traçabilité du module à la puce pour traquer les éventuels rejets dans l’application finale et remonter à la cause d’origine. Toutes les innovations présentées, dans ce mémoire, s’inscrivent dans une démarche novatrice de l’amélioration continue de la qualité des composants de type MOSFET de puissanceIn the current ecologic context, the European automotive suppliers have to develop innovating systems inorder to reduce greenhouse gas rejects produce by vehicles. The new mild-hybrid electronic applications require the development of new strategies due to their integration and the reduction of power losses.Thereby, a proposition consisted in creating power modules constituted by MOSFETs characterized by alow blocking voltage under high current. The starter alternator reversible application also named “Stop &Start” requires robust and reliable components in order to support a high current solicitation in avalanche mode for temperatures up to 175°C.Research work presented in this thesis concerns the robustness and reliability enhancement of MOSFET components. First of all, the important part is about avalanche mode understanding and their issues. Inthis context, the fabrication process is a main part for quality and reliability requirements. Then, the workis focused on gate oxide process quality in order to hold gate-source and gate-drain stress modes.Moreover, the development of an innovating test at wafer level derivate from QBD test, allowed the precise evaluation of process modification thanks to the correlation with reliability campaign results. Finally, theMOSFET life cycle needs a quality monitoring constituted by two main steps. The first one is the monitoring of electrical parameters in time with a post-processing statistical analysis. The second one is the use of a traceability tool between the power module and the silicon die in order to highlight possible defects in the final starter alternator application, and understand failure root causes. The innovations presented in this thesis are included in the continued improvement approach for MOSFETs quality and robustness enhancement
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Sadik, Diane-Perle. "On Reliability of SiC Power Devices in Power Electronics." Doctoral thesis, KTH, Elkraftteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-207763.
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Silicon Carbide (SiC) is a wide-bandgap (WBG) semiconductor materialwhich has several advantages such as higher maximum electric field, lowerON-state resistance, higher switching speeds, and higher maximum allowablejunction operation temperature compared to Silicon (Si). In the 1.2 kV - 1.7kV voltage range, power devices in SiC are foreseen to replace Si Insulatedgatebipolar transistors (IGBTs) for applications targeting high efficiency,high operation temperatures and/or volume reductions. In particular, theSiC Metal-oxide semiconductor field-effect transistor (MOSFET) – which isvoltage controlled and normally-OFF – is the device of choice due to the easeof its implementation in designs using Si IGBTs.In this work the reliability of SiC devices, in particular that of the SiCMOSFET, has been investigated. First, the possibility of paralleling two discreteSiC MOSFETs is investigated and validated through static and dynamictests. Parallel-connection was found to be unproblematic. Secondly, drifts ofthe threshold voltage and forward voltage of the body diode of the SiC MOSFETare investigated through long-term tests. Also these reliability aspectswere found to be unproblematic. Thirdly, the impact of the package on thechip reliability is discussed through a modeling of the parasitic inductancesof a standard module and the impact of those inductances on the gate oxide.The model shows imbalances in stray inductances and parasitic elementsthat are problematic for high-speed switching. A long-term test on the impactof humidity on junction terminations of SiC MOSFETs dies and SiCSchottky dies encapsulated in the same standard package reveals early degradationfor some modules situated outdoors. Then, the short-circuit behaviorof three different types (bipolar junction transistor, junction field-effect transistor,and MOSFET) of 1.2 kV SiC switching devices is investigated throughexperiments and simulations. The necessity to turn OFF the device quicklyduring a fault is supported with a detailed electro-thermal analysis for eachdevice. Design guidelines towards a rugged and fast short-circuit protectionare derived. For each device, a short-circuit protection driver was designed,built and validated experimentally. The possibility of designing diode-lessconverters with SiC MOSFETs is investigated with focus on surge currenttests through the body diode. The discovered fault mechanism is the triggeringof the npn parasitic bipolar transistor. Finally, a life-cycle cost analysis(LCCA) has been performed revealing that the introduction of SiC MOSFETsin already existing IGBT designs is economically interesting. In fact,the initial investment is saved later on due to a higher efficiency. Moreover,the reliability is improved, which is beneficial from a risk-management pointof-view. The total investment over 20 years is approximately 30 % lower fora converter with SiC MOSFETs although the initial converter cost is 30 %higher.Kiselkarbid (SiC) är ett bredbandgapsmaterial (WBG) som har flera fördelar,såsom högre maximal elektrisk fältstyrka, lägre ON-state resitans, högreswitch-hastighet och högre maximalt tillåten arbetstemperatur jämförtmed kisel (Si). I spänningsområdet 1,2-1,7 kV förutses att effekthalvledarkomponenteri SiC kommer att ersätta Si Insulated-gate bipolar transistorer(IGBT:er) i tillämpningar där hög verkningsgrad, hög arbetstemperatur ellervolymreduktioner eftersträvas. Förstahandsvalet är en SiC Metal-oxidesemiconductor field-effect transistor (MOSFET) som är spänningsstyrd ochnormally-OFF, egenskaper som möjliggör enkel implementering i konstruktionersom använder Si IGBTer.I detta arbete undersöks tillförlitligheten av SiC komponenter, specielltSiC MOSFET:en. Först undersöks möjligheten att parallellkoppla tvådiskretaSiC MOSFET:ar genom statiska och dynamiska prov. Parallellkopplingbefanns vara oproblematisk. Sedan undersöks drift av tröskelspänning ochbody-diodens framspänning genom långtidsprov. Ocksådessa tillförlitlighetsaspekterbefanns vara oproblematiska. Därefter undersöks kapslingens inverkanpåchip:et genom modellering av parasitiska induktanser hos en standardmoduloch inverkan av dessa induktanser pågate-oxiden. Modellen påvisaren obalans mellan de parasitiska induktanserna, något som kan varaproblematiskt för snabb switchning. Ett långtidstest av inverkan från fuktpåkant-termineringar för SiC-MOSFET:ar och SiC-Schottky-dioder i sammastandardmodul avslöjar tidiga tecken pådegradering för vissa moduler somvarit utomhus. Därefter undersöks kortslutningsbeteende för tre typer (bipolärtransistor,junction-field-effect transistor och MOSFET) av 1.2 kV effekthalvledarswitchargenom experiment och simuleringar. Behovet att stänga avkomponenten snabbt stöds av detaljerade elektrotermiska simuleringar för allatre komponenter. Konstruktionsriktlinjer för ett robust och snabbt kortslutningsskyddtas fram. För var och en av komponenterna byggs en drivkrets medkortslutningsskydd som valideras experimentellt. Möjligheten att konstrueradiodlösa omvandlare med SiC MOSFET:ar undersöks med fokus påstötströmmargenom body-dioden. Den upptäckta felmekanismen är ett oönskat tillslagav den parasitiska npn-transistorn. Slutligen utförs en livscykelanalys(LCCA) som avslöjar att introduktionen av SiC MOSFET:ar i existerandeIGBT-konstruktioner är ekonomiskt intressant. Den initiala investeringensparas in senare pågrund av en högre verkningsgrad. Dessutom förbättrastillförlitligheten, vilket är fördelaktigt ur ett riskhanteringsperspektiv. Dentotala investeringen över 20 år är ungefär 30 % lägre för en omvandlare medSiC MOSFET:ar även om initialkostnaden är 30 % högre.
QC 20170524
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Gay, Roméric. "Développement de composants analogiques embarqués dans des microcontrôleurs destinés à l'Internet des Objets (loT)." Electronic Thesis or Diss., Aix-Marseille, 2022. http://www.theses.fr/2022AIXM0218.
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L’objectif de ces travaux de thèse a été d'améliorer les performances, le coût et la surface de silicium occupés par un microcontrôleur fabriqué sur la base d’une technologie mémoire embarquée CMOS (eNVM) 40 nm. Ces améliorations ont été réalisées grâce au développement de nouvelles architectures de transistors adaptées au besoin du marché de l’IoT. Dans une première partie, le contexte dans lequel s’inscrit cette thèse est exposé par la présentation des limites technologiques et économiques de technologie CMOS. Dans une deuxième partie, le procédé de fabrication eNVM ainsi que l’architecture et le mode de fonctionnement d’un nouveau composant, appelé transistor triple grille, ont été présentés. Sur la base de cette nouvelle architecture, composée de grilles de contrôle indépendantes, différents transistors multigrilles ont été fabriqués. Par la même occasion, leur comportement électrique a été analysé. Dans la continuité, des études de fiabilité, portant notamment sur les oxydes de grilles, ont été menées. L’objectif de ces études a été d’étudier l’impact d’une contrainte électrique, appliquée sur une grille du transistor, sur les autres grilles non soumises à cette même contrainte. Des caractérisations électriques ainsi que des simulations TCAD, ont permis d’améliorer la compréhension des résultats obtenus. Finalement, la structure du transistor triple grille a été modélisée à l’aide d’un modèle compact de transistor de type PSP. Cette modélisation a pour objectif de permettre l’évaluation du comportement et des performances électriques de ce transistor au niveau circuitThe aim of this work is to improve the performance, cost and area of a microcontroller manufactured in a 40 nm CMOS embedded memory technology (eNVM), by developing new transistor architectures suitable for the IoT market. The context is first presented with a focus on the technological and economical limitations of the CMOS technology. In a second part, the eNVM manufacturing process as well as the architecture and operation mode of a new component called triple gate transistor are presented. Based on this new architecture which provides independent control gates, various multigate transistors are manufactured and their electrical behaviour is analysed. Reliability studies are then carried out, to assess the reliability of the gate’s oxides. The objective is to study the impact of an electrical stress applied to one transistor gate on the gates not subject to this same stress. Electrical characterizations and TCAD simulations are also conducted to improve the understanding. Finally, the structure of the triple gate transistor is modelled using a compact PSP transistor model. The aim is to evaluate the behaviour but also the electrical performance of this transistor at the circuit level
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Molin, Quentin. "Contribution à l’étude de la robustesse des MOSFET-SiC haute tension : Dérive de la tension de seuil et tenue aux courts-circuits." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI111.
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Ce manuscrit est une contribution à l’étude de la fiabilité et de la robustesse des composants MOSFET sur carbure de silicium, matériau semi-conducteur grand gap qui possède des caractéristiques bien meilleures que le silicium. Ces nouveaux interrupteurs de puissances permettent d’obtenir entre autres propriétés remarquables, des fréquences de commutations et des tenues en tension plus élevées dans les systèmes de conversions de puissance. Ils sont particulièrement mis en avant depuis un peu plus d’une dizaine d’années pour les gains en performances, diminution des tailles et poids qu’ils apportent à certaines topologies de convertisseurs pour les réseaux haute tension à courant continu. Puis sont répertoriés les principaux mécanismes de défaillances de ces MOSFET SiC induits par la faiblesse de la grille. Toutes les mesures nécessaires au suivi des paramètres clés lors des prochains vieillissements sont présentées. Les résultats de nos tests sur l’instabilité de la tension de seuil sont aussi détaillés et un modèle empirique pour valider le comportement de relaxation observé est proposé. Celui-ci nous aidera par la suite à établir un protocole de mesure rigoureux de la tension de seuil. Les tests expérimentaux et résultats de vieillissement en statique et dynamique sur les composants 1,7 kV vont permettre de se rendre compte de l’importance de la dérive de la tension de seuil sur 1000 h. Dans le cas d’un vieillissement statique, il y a environ 7 % de dérive positive du VTH et un pourcentage équivalent pour les tests dynamiques. Des analyses supplémentaires (C-V et pompage de charge) sur l’oxyde de grille en cours de vieillissement sont proposées pour une meilleure compréhension des mécanismes mis en jeu dans la dégradation de l’oxyde. Enfin, les derniers tests présentés seront focalisés sur le comportement en court-circuit et courts-circuits répétitifs des mêmes composants. Avec une énergie critique évaluée autour de 1,5 J nos tests sur les MOSFET 1,7 kV montrent les limites de la robustesse de ces composants, avec une tenue en court-circuit bien inférieure à 10 µs et une incapacité à résister à plus de 150 courts-circuits successifs. L’influence de la tension entre drain et source y est notamment étudiée, et montre que l’énergie critique supportée par le composant diminue avec l’augmentation de cette tensionThis manuscript is a contribution to reliability and robustness study of MOSFET components on silicon carbide “SiC”, wide band gap semiconductor with better characteristics compared to silicon “Si” material. Those new power switches can provide better switching frequencies or voltage withstanding for example in power converter. SiC MOSFET are the results of approximately 10 years of research and development and can provide increased performances and weight to some converter topology for high voltage direct current networks. Others power switches available are still introduced and an introduction to reliability is explaining why such work on this new power switches is important. Transition from Si technologies to SiC ones require a lot of work regarding its robustness. Before showing reliability and robustness results is presented I give a lot of details regarding to the measurement and monitoring of key parameters used in the next chapters. The results of our tests on the threshold voltage instability are presented and how we validated an empirical model on this drift. This was used to propose an enhanced measurement protocol on the threshold voltage. Static and dynamic experimental results presented next will show if the voltage drift during ageing is significant or not. Further analysis is proposed to add more insight on the understanding of the oxide degradation mechanisms through C-V and charge pumping measurements. Finally, the ageing results presented on 1,7 kV SiC MOSFET are focused on the short-circuit and repetitive short-circuit behavior of the same components. Drain to source voltage influence on critical energy during this particular and stressful operation mode is studied. This time, the results are worrying.The last chapter is confidential
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Kempf, Thibault. "Caractérisation et fiabilité des mémoires embarquées non volatiles pour les nœuds technologiques 40nm et 28nm." Electronic Thesis or Diss., Université Côte d'Azur (ComUE), 2019. http://www.theses.fr/2019AZUR4093.
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Les technologies mémoires 1.5Tr proposent des améliorations non négligeables en termes de performance et de fiabilité pour les microcontrôleurs visant les marchés florissants de l’automobile et de l’internet des objets. Dans cette thèse, une mémoire unique en son genre et innovante basé sur un transistor de sélection vertical et enterré et appelé « embedded Select Trench Memory » (eSTM) est présenté. Après un état de l'art concis, un chapitre est consacré à la présentation d'outils pour améliorer la caractérisation et l'analyse du transistor mémoire unitaire ou intégré dans une macrocell. Plus précisément des outils pour analyser les bitmaps des macrocell sont proposés afin d’évaluer et d'optimiser la fiabilité et la variabilité de la mémoire. Ces outils sont ensuite utilisés dans un chapitre sur la performance et la fiabilité intrinsèque de l'eSTM. Le mode de programmation résultant de la topologie de la cellule est décrit afin de comprendre les dépendances du mécanisme de programmation et les moyens de l'optimiser. L'amélioration de la fiabilité de l'oxyde tunnel est aussi étudié en tant que clé de la performance en cyclage et en rétention de l'eSTM. Enfin les limites et avantages de la miniaturisation de l'eSTM sont discutés. Dans le chapitre suivant, la variabilité extrinsèque de l'eSTM est étudiée sur la macrocell. Chacune des sources de variabilité est évaluée pour extraire leurs origines liées soit au procédé de fabrication ou au design du microcontrôleur. Ce chapitre se clot sur la relation entre la fiabilité et la variabilité de la cellule mémoire. L'importance de l'étude statistique par des moyens adéquates comme la macrocell est mise en valeur par le lien direct de cause à effet entre la variabilité et la fiabilité ce qui peut affecter la fiabilité du produit, et donc sa durée de vie ou son rendementSplit-gate memory technologies propose non negligible improvement of the performance and reliability of embedded non-volatile memory in microcontroller products targeting growing market such as automotive or Internet of Things. In this thesis, a unique and innovative split-gate memory based on a trench select transistor, called embedded Select Trench Memory (eSTM) is presented. After a concise state of art, a chapter is devoted to the presentation of several tools to improve the characterization and analysis of the memory from single cell to testchip. Especially tools to analyze the testchip's bitmap are proposed for the memory reliability and variability evaluation and optimization. These methodologies are then deployed in a chapter focusing on the eSTM intrinsic performance and reliability. The unique programming scheme due to the cell topology is described to understand the dependency of the programming mechanisms and the way to improve it. Then the tunnel oxide reliability improvement is studied as a key to eSTM cycling and retention. Finally, the limitations and advantages of the eSTM shrinking are discussed. In the following chapter, the extrinsic variability of the eSTM is studied based on the testchip. Each sources of variability are outsourced, and studied to extract their root causes which are either process-related, or design/layout related. This chapter closes on the relation between the reliability weaknesses and the memory variability. It highlights the importance of statistics study through adapted device such as testchip and the causal connection between the variability and the reliability that can affect the product reliability, lifetime and yield
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Jahan, Carine. "Étude des mécanismes de défaillance des diélectriques de grille minces pour les technologies CMOS avancées." Grenoble INPG, 1998. http://www.theses.fr/1998INPG0137.
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Ce memoire presente les resultats consacres a l'etude des mecanismes de degradation et de claquage de l'oxyde de grille pour une gamme d'epaisseur variant de 7 a 3. 5 nm, correspondant aux technologies cmos 0. 35 a 0. 18 m. Cette etude a d'abord necessite un important travail d'optimisation des techniques de caracterisation de l'oxyde de grille mince et en particulier de tenir compte du comportement quantique des porteurs pres de l'interface pour avoir une extraction fiable des parametres de la structure mos. Dans la gamme d'epaisseur d'oxyde etudiee, la degradation du dielectrique se manifeste principalement par des courants de fuite a faible champs electriques, communement appeles silc (stress induced leakage current) : ce phenomene peut etre considere comme une conduction tunnel assistee par pieges des electrons a travers l'oxyde. L'etude de l'evolution du silc avec l'epaisseur d'oxyde et les conditions de contrainte permet de proposer une modelisation originale de la generation du silc : celle-ci, basee sur le modele d'injection de trous chauds de l'anode, introduit a l'origine pour expliquer le claquage, permet de decrire avec succes les resultats experimentaux. Nous en concluons que les courants de trous injectes de l'anode interviennent a la fois dans les mecanismes de creation du silc et du claquage. Neanmoins, si le silc et le claquage correspondent tous deux a un processus relie a des defauts generes lors de la contrainte, nous montrons que le claquage du dielectrique n'est pas provoque par un nombre critique des pieges a l'origine du silc : ceci indique que les defauts a l'origine du silc et du claquage sont de nature differente. La derniere partie de ce memoire complete l'etude de la fiabilite de l'oxyde de grille en evaluant l'impact des differentes agressions technologiques subies par l'oxyde au cours de la fabrication du composant : en particulier la diffusion du bore des grilles p+ affecte l'oxyde en augmentant le silc et en diminuant la charge au claquage. Cette diffusion peut etre partiellement reduite par l'incorporation d'azote dans l'oxyde par un procede de nitruration. Enfin, contrairement au processus menant au claquage, le silc est un phenomene reversible dans certaines conditions de temperature et d'atmosphere, ce qui confirme que le silc et le claquage ne sont pas provoques par les memes defauts.
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Candelier, Philippe. "Contribution à l'amélioration de la fiabilité des mémoires non volatiles de type flash EEPROM." Université Joseph Fourier (Grenoble ; 1971-2015), 1997. http://www.theses.fr/1997GRE10245.
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L'augmentation continue de la densite d'integration des memoires non-volatiles de type flash eeprom passe par la comprehension des mecanismes de degradation intervenant dans le cadre du fonctionnement de ces memoires. Nous avons pu correler les degradations observees sur des dispositifs elementaires (transistors et capacites) aux derives des caracteristiques de la cellule flash. Cette etude demontre que de nouveaux modes de fonctionnement devront etre envisages. Le mode d'effacement par la source, habituellement utilise, pose des problemes d'optimisation technologique pour les cellules de faible longueur de grille (generation de trous chauds difficile a controler). Il devra vraisemblablement etre remplace par l'effacement fn qui est plus fiable pour les criteres d'endurance et de retention apres endurance. Parmi les degradations observees, le probleme principal est l'augmentation de la perte de charge avec l'amincissement des dielectriques et avec la degradation de l'oxyde de grille lors des cycles ecriture/effacement. Face au premier probleme, la mise en place d'une fonction de rafraichissement periodique semble necessaire. Face au second probleme, l'effacement fn a ete optimise en minimisant le champ electrique dans l'oxyde de grille par l'utilisation d'impulsions trapezoidales. Des progres technologiques importants (dielectriques interpolysilicium deposes, isolation laterale de type box) ont ensuite ete introduits dans le procede de fabrication afin permettre une integration plus poussee. La validation de ces evolutions technologiques ouvre les portes de la generation de cellules flash 0. 25 m. Finalement, face au probleme d'augmentation de la densite d'integration, la programmation multi-niveaux est une solution simple dont la fiabilite a ete amelioree grace a la realisation d'un systeme de programmation convergente. La faisabilite d'un doublement de capacite memoire a alors ete demontree.
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Lin, Y. B., and 林宜斌. "The Reliability of Ultra-thin Gate Oxide." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/06213704889877444052.
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碩士中華大學
電機工程研究所
86
The key issue for ultra-thin oxide film integrity reliability is the presence of native oxide, thickness uniformity, interface smoothness, leakage current, stress-induced leakage current and reliability. In out study, we have designed a leak-tight oxidation furnace that can desorb native oxide removed in-situ prior to oxidation. By using HF-vapor treatment and H2-bake process, atomically smooth interface of oxide/Si was observed by high resolution TEM for oxide thickness from 11 tp 38A. We have observed that the presence of native oxide will degrade the eletrical characteristics, interface roughness, gate oxide leakage current and hole trap generation after stress. Much improved reliability, as pbserved from the slow leakage, SILC and ble soft-breakdown is also obrained by using this atomically smooth oxide with native oxide free. Therefore the above process can achieve excellent oxide integrity and can be applied to ULSI process.
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Huang, Shin-Duen, and 黃信惇. "Gate oxide reliability of advance CMOS device." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/51931041390158072911.
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碩士國立成功大學
微電子工程研究所碩博士班
91
In this thesis, the sample is an 8inch wafer for 0.15μm technology n-MOSFET’s and p-MOSFET’s and we researched on oxide reliability. As devices scaling down, the device operational voltage and some characteristic still decreases slowly. The area and the thickness of the device oxide layer also decreased that varied the characteristic representation. So the dielectric oxide layer in MOSFET is to pay much attention to people. My experiment focuses on the difference between thin and thick oxide layer and finds the difference of the characteristic between before breakdown and after breakdown. First, I use ramp voltage test and constant voltage test to confer the difference of the I-V changes. Then I use the past breakdown definition to analyze the I-V curve. I want to find what influence on device between thin and thick oxide layer. Besides, I try to generalize it has the more accurate way to define the device breakdown. In these experiments, we used ICS (Interactive Characterization Software) to control HP4155B (Semiconductor Parameter Analyzer) produced by Agilent Technologies and 4200-SCS system produced by Keithley to finish various researches.
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Chen, Chi-Chun, and 陳啟群. "Studies of Process-Related Oxide Reliability in Ultra-Thin Gate Oxides." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/12540224544709691803.
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博士國立交通大學
電子工程系
88
Ultrathin gate oxide, which is essential for low supply voltage and high driving capability, is indispensable for the continued scaling of ULSI technologies towards smaller and faster devices. Needless to say, the reliability of ultrathin oxide is of major concerns in the manufacturing of the state-of-the-art metal-oxide-semiconductor devices. In this thesis, the reliability issues regarding ultrathin gate oxide for present and future ULSI technologies are extensively investigated and discussed. Firstly, we start with a review of the present understanding of general reliability issues, their mutual relationship, effects on gate oxide integrity (GOI) and the consequences for oxide thickness scaling. Issues relating quantum mechanical tunneling current, determination of ultrathin oxide thickness, time-dependent dielectric breakdown characteristics, characteristics of soft-breakdown and its impacts on device reliability, effects of temperature, stressing polarity and oxide thickness dependences of ultrathin oxide breakdown, and evaluation of ultrathin oxide reliability is comprehensively demonstrated. Secondly, plasma-induced charging damage in thin gate oxides with thickness ranging from 8.7 to 2.5 nm is investigated and analyzed by subjecting antenna devices to a photoresist ashing step after metal pad definition. Oxide thickness dependence of charging damage is discussed and the evaluation of charging damage in ultrathin gate oxides (Tox < 4 nm) is also demonstrated. The charging damage characteristics induced in nMOS and pMOS devices are also compared. Our experimental results show that pMOS devices are more sensitive to plasma charging and more susceptible to positive charging damage. Possible mechanism responsible for these phenomena is also discussed. Thirdly, the effects of fluorine and nitrogen incorporation on ultrathin gate oxide integrity (GOI) are investigated by introducing N2O-nitrided oxide as gate dielectric and by implanting fluorine and nitrogen into poly gate or Si substrate. Multiple oxide thickness, which is essential for achieving system-on-a-chip (SOC) technology, by fluorine and nitrogen implant, is first introduced. Improved immunity of plasma charging damage in nitrided oxide and fluorinated oxide is then investigated. It is observed that charging damage can be significantly suppressed for nitrided oxide and fluorinated oxide. Finally, improved CMOS GOI, even for p-channel devices, is actually achieved for the first time with medium-dose fluorine implantation, without causing noticeably worsened boron penetration. Process-induced oxide degradation in ultrathin gate oxides is then presented. Issues including effects of polysilicon doping concentration, boron penetration, and polysilicon etching damage on ultrathin oxide reliability are investigated comprehensively. We found that while oxide reliability shows a noticeable improvement with increasing doping concentration, plasma-induced charging damage is actually aggravated with increasing doping concentration. Effects of boron penetration on device characteristics and its impacts on charging damage are also discussed. Finally, plasma etching-induced damage is investigated by subjecting various devices to TCP (Transform Coupled Plasma) poly etcher (e.g., LAM TCP 9400) with different over-etching durations. Gate oxides and poly re-oxidation are thermally grown in either pure O2 or N2O ambient in order to compare the damage in various oxides. Followed by a comprehensive study on the plasma process induced damage in sputtered TiN metal-gate capacitors with 4nm N2O-nitrided oxide. A significant reduction in the effective oxide thickness extracted from C-V measurement is observed for the metal-gated devices. The effects of post-deposition RTA temperature on the flat-band voltage (Vfb) and interface state density (Dit) are studied. In addition, charging damage due to the additional plasma processes in metal gate process flow is analyzed. Finally, post-metal plasma treatments are studied for suppressing the gate leakage current of metal-gate devices. Finally, a modified percolation model for ultrathin gate oxide breakdown is proposed. We start with investigating the post-breakdown characteristics of ultra-thin oxides. The pre- and post-breakdown characteristics of MOS devices are compared and a strong dependence on the breakdown spot locations is observed. The location of breakdown spot can be identified according to post-breakdown drain current characteristics and further verified by the photo-emission analysis. In order to find some clues for explaining the evolution and different stages of oxide degradation, effects of oxide breakdown on device''s characteristics are investigated in detail. In addition to the well-known soft-breakdown and hard-breakdown, a new breakdown mode, which we named as "partial breakdown" (PBD), is observed and identified. The corresponding physical origin and mechanism are then demonstrated. Accordingly, a new technique for probing the intrinsic traps near the gate/oxide interface of MOS structure is proposed. Effects of nitridation and fluorination on oxide breakdown are also compared and discussed.
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Lin, Yung-Hao, and 林永豪. "Analysis of Gate Oxide Reliability and Gate Engineering Applied in Surface-Channel PMOSFETs." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/76356245674211509002.
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Krishnan, Siddarth A. "Characterization and reliability of HFO₂ and hfsion gate dielectrics with tin metal gate." Thesis, 2005. http://hdl.handle.net/2152/2255.
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Chang, Wen Tsung, and 張文聰. "The Electrical and Reliability Characteristics of Dysprosium Oxide and Holmium Oxide Gate Dielectrics." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/99786063321036846002.
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碩士長庚大學
電子工程學研究所
97
In this thesis, we selected two high-k materials as the gate dielectric of metal-oxide-semiconductor capacitors. One is dysprosium oxide (Dy2O3) and the other is holmium oxide (Ho2O3). Through PDA treatment, we analyzed its physical properties. We use X-ray diffraction (XRD), X-ray photoelectron Spectroscopy (XPS), and Atomic Force Microscopy (AFM) to identify the oxide film crystallization, chemical composition, and surface morphology. After using Al as gate electrode, we investigated its electrical and reliability characteristics. The analyses of electrical properties have C-V curves, hysteresis phenomenon, interface state density, and leakage current. We found dysprosium oxide and holmium oxide have a larger capacitance value when the annealing temperature is 600℃ and exhibited a lower hysteresis voltage. And, we also explored the reliability of dysprosium oxide and holmium oxide. In dysprosium oxide, we discuss charge-to-breakdown (QBD) and time-dependent-dielectric-breakdown (TDDB) in gate oxide reliability. The Weibull slope is almost independent of current stress, gate area, and temperature for Dy2O3 in QBD. The Weibull slope is almost independent of stress voltage for Dy2O3 in TDDB. In holmium oxide, we discuss charge-to-breakdown (QBD) in gate oxide reliability. The Weibull slope is almost independent of current stress, gate area, and temperature for Ho2O3 in QBD. We found the oxide breakdown for these two high-k material belonged to intrinsic breakdown. It means the oxide breakdown is caused by stress-induced charge traps. Finally, we used the cell-base analytic model to extract the defect size of Dy2O3 thin film. The defect size of Dy2O3 is 4.5 nm for α=0.6 and 7.5 nm for α=1.
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Chang, Long, and 張國郎. "A Study on Reliability of Ultrathin Gate oxide for MOS devices." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/46881182579596083070.
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Shen-Xiang, Lin, and 林信翔. "The Improvement in the Reliability of Gate Oxide and Silicide by the Stacked Poly-Si Gate." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/82783055239431198839.
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碩士國立交通大學
電子工程系
88
In this thesis, we have first presented a systematic study of the physics characteristics of Ni- and Co-silicides formed on different Si substrates to recognize the effects on the thermal stability. The four point probe was used to measure the sheet resistance of Ni- and Co-silicides with various silicidation temperatures. The X-ray diffraction (XRD) was carried out for phase identification. We have found that the thermal stability of the silicide is affected by thickness, microstructure, and dopant type of the underlying poly-Si film. Additionally, the stacked poly-Si film structures are found to have better thermal stability. NiSi and CoSi2 formed on a thinner poly-Si film can improve the thermal stability. The thermal annealing also has influences on the thermal stability and the morphological changes of the Ni-silicide regardless the dopant type in the underlying poly-Si film. Moreover, the stacked poly-Si sample can suppress the agglomeration of NiSi2 formed on undoped Si substrates with 950℃ recrystallization. The transmission electron microscopy (TEM) micrographs reveal that the bottom poly-Si film is still in good shape, but the Ni-silicide layer is discontinuous and broken up into isolated islands at the top poly-Si film. Secondly, we proposed disilane-silane (DS), and disilane-amorphous (DA) stacked poly-Si gate to improve the gate oxide reliability. For capacitors with Al gate electrode, capacitors with the stacked poly-Si gate have better electrical characteristics, such as higher dielectric breakdown field (Ebd), smaller electron trapping rate, and higher charge to breakdown (Qbd). For capacitors with the gate electrode of CoSi2 and NiSi, even though after 950℃ and 800℃ silicidation for 30s respectively, the capacitors with the stacked poly-Si gate were still highly reliable while the conventional one was degraded seriously.
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Du, Long J., and 杜隆杰. "Reliability Modeling of Ultra-thin Gate Oxide Device for Circuit Functionality Evaluation." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/21649806869009536583.
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碩士國立清華大學
電子工程研究所
90
The reliability of ultra-thin gate oxide has been researched for many years since the development of the VLSI technology into the sub-micron regime. Most of the studies following the conventional analysis of thicker gate oxide layer focus on the dielectric breakdown and the lifetime of a “single” device. Gradually, not only various degradation in device characteristics are observed but the physical mechanisms leading to these results are also well understood. However, the practical situation of the device when it is used in circuit configurations and the impacts of these degrading characteristics on circuits need to be studied or modeled. This thesis focuses on extending the reliability research from a device level onto a circuit level, i.e. the reliability of the device operating in circuits. This work will establish resistance models to simulate the degradation of the circuit performance resulting from devices’, and predict the reliability of the circuit, moreover, to provide different sets of the “Design Rule” for different applications.
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Huang, Cheng-Chuan, and 黃正權. "A Study of Fluorine and Nitrogen on Ultra-Thin Gate Oxide Reliability." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/81450298866558750195.
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碩士國立交通大學
電子工程系
88
The effects of fluorine and nitrogen incorporation on ultra-thin gate oxide integrity (GOI) were investigated by implanting fluorine and nitrogen into poly gate or Si substrate. The transconductance (Gm) and subthreshold swing (S.S) of fluorinated devices were better than that of nitrided devices. The hot carrier reliability test also showed that fluorinated oxide was more resistant to hot electron injection. For area dependence of charge-to-breakdown, the fluorine atoms pile up at the poly-Si/SiO2 interface may be responsible for degradation in large gate area devices. It is observed that fluorine and nitrogen implantation into Si substrate prior to oxidation can be used to obtain multiple oxide thickness, albeit its effectiveness is drastically reduced for N2O-nitrided oxide. Gate leakage measurements performed on antenna devices show that charging damage can be significantly reduced for fluorine- or nitrogen- implanted devices with O2 oxide. On the other hand, fluorine-alone implant is useful to reduce the gate leakage of antenna devices with N2O oxide. Finally, the possible model for immunity to plasma charging damage was proposed.
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Lai, Jiu-Meng, and 賴久盟. "The Study of Gate Oxide Reliability with Nickel Silicides and Stacked Structures." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/m4jdpk.
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碩士國立交通大學
電子工程系所
92
As the dimension of device scaling down, the short channel effects are more severe. Then, in order to control threshold voltage, it is needed to use heavy channel doping. However, the carrier mobility will be reduced and device performance will be degraded, too. For this reason, the single metal gate with suitable work function will be used to control the threshold voltage in the future. However, metal gate got integration difficulties with the self-aligned process. Recently, the FUll SIlicide (FUSI) NiSi gate is investigated as an alternative metal-gate. The nickel silicide gate has several advantages, such as low resistivity, elimination of PDE, tunable work function, and better process compatibility. However, whether the gate oxide reliability is affected by nickel or not is a concern. In this thesis, we have studied the gate oxide reliability with the NiSi gate. The NiSi gate was carried out with different temperature and structures. For the undoped poly-Si and a-Si gate, the amounts of nickel diffusion into the gate oxide increased with temperature, and the oxide was degraded severely after 800oC annealing. For the in situ doped n+ NiSi gate, the gate oxide reliability is still acceptable even with 800oC annealing. The interaction between impurity and nickel is believed a reason of retarded nickel diffusion into gate-oxide. In TEM images of NiSi films, better uniformity and larger grains were observed while with higher RTA temperature. And, from the flat-band voltage shifts, we found the n+ NiSi work function changed with different RTA temperatures. We also used the n+ a-Si/poly-Si and poly-Si/n+ a-Si stacked structures to form NiSi gate, and the gate oxide reliability was affected at high temperature. The interface between a-Si and poly-Si doesn’t seem to affect the nickel diffusion much. Nevertheless, all the samples treated by low temperature annealing sustained the gate oxide reliability well. Thus, FUSI NiSi gate still possesses potential to be used in low temperature process in the future.
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Chen, Chieh-Chuang, and 陳志強. "Impact of Plasma Charging Damage and Metal Impurities on Thin Gate Oxide Reliability." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/51043656126006598399.
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Chen, Wen-Yi, and 陳穩義. "Design of On-Chip ESD Protection Circuits with Consideration of Gate-Oxide Reliability." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65542208357281098872.
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Rahman, Mohammad Shahriar. "Reliability of advanced dielectrics in gate oxide and device level packaging in MEMS." 2009. http://hdl.handle.net/10106/2014.
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Onishi, Katsunori. "A study of the performance and reliability characteristics of HfO₂ MOSFET's with polysilicon gate electrodes." Thesis, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3110668.
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Lin, Chung-Hsun, and 林崇勳. "A Comprehensive Study of Electrical Property and Deuterium-Enhanced Reliability of Ultrathin Gate Oxide." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/85685308449056004514.
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碩士國立臺灣大學
電機工程學研究所
89
Abstract In this thesis, we investigate the mechanisms of inversion gate tunneling current and ultrathin gate oxide degradation in metal-oxide-silicon (MOS) tunneling diode. Besides, the enhanced reliability of oxide and electroluminescence (EL) by novel deuterium incorporation is proposed. First, The gate current of MOS tunneling diodes biased at inversion region with different substrate doping is investigated. For p-type substrate (1-5Ω-cm) devices, the tunneling diode works in the deep depletion region and the inversion current is dominated by the thermal generation rate of minority electrons via traps at Si/SiO2 interface and in the deep depletion region. The activation energy is approximately equal to half of the silicon bandgap independent of gate voltage. For devices on p+ substrate (0.01-0.05Ω-cm), the band-to-traps tunneling and band-to-band tunneling are dominating current components at inversion bias, and reveal a strong field dependence and a weak temperature dependence. The band-to-traps and band-to-band current components are even more significant in the devices on the p++ substrate (0.001-0.0025Ω-cm). MOS tunneling diodes with Si/SiO2 interface passivated by hydrogen or deuterium are stressed under various constant current conditions to investigate oxide degradation mechanism. For NMOS tunneling diode, when the energy of injected electrons exceeds a threshold value (~3eV), both hydrogen and deuterium passivated devices reveal similar soft breakdown behaviors. On the contrary, when the injected electrons with low energy (<3eV) at high current density stress, a giant isotope effect is observed in the deuterated devices due to the resonance between the Si-D bond bending mode and the transverse optical phonon of bulk silicon. Therefore, hydrogen release model is suggested as the possible mechanism of oxide degradation in NMOS tunneling diode. For PMOS tunneling diode, unlike previous results in NMOS devices, there is no isotope effect in deuterium-treated PMOS tunneling diodes. When stressed at high positive gate voltage, both hydrogen-treated and deuterium-treated PMOS tunneling diodes reveal soft breakdown. The tunneling-hole-induced traps in bulk oxide are responsible for this soft breakdown. However, when stressed at lower positive voltage, both hydrogen-treated and deuterium-treated devices maintain intact even after 2000 sec stress at 100 μA (a fluence of 660 C/cm2), since the holes do not have sufficient energy to be trapped in bulk oxide. A resonant capture model based on quantum mechanics is given to explain the hole trapping in the oxide. The reliability of EL from MOS tunneling diodes is improved by the incorporation of deuterium, which is implemented by deuterium prebake and the post-oxidation deuterium anneal. At constant current stress of 100mA, a deuterium-treated NMOS tunneling light-emitting diode shows that the integrated light emission intensity increases slightly about 6% after 10000 sec operation, while the hydrogen-treated device shows a 30 % decrease of the integrated light emission intensity. The hydrogen release by the electrons tunneling from the gate electrode to Si and the formation of interface defects are responsible for the degradation of light-output in the hydrogen-treated samples. An annealing model is also given to explain the slight increase of light-output for the deuterium-treated samples. Finally, the deuterium enhanced oxide reliability by novel deuterium incorporation methods is proposed, which includes very high vacuum prebake, deuterium prebake, and deuterium post-oxidation anneal. The deuterium distributes not only at Si/SiO2 interface but also in the bulk oxide. The deuterium incorporation shows the improvement on soft breakdown characteristics and the degradation reduction of interface state density after stress. Surface roughness enhanced oxide reliability is also discussed.
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Chen, Yi-Feng, and 陳宜鋒. "The Studies of Process-Related Reliability Issue on Ultra-Thin Gate Oxide CMOS Devices." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/56100845463098228787.
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碩士國立臺北科技大學
機電整合研究所
90
In this thesis study, we propose a furnace N2O oxidation process to improve the reliability of ultra-thin gate oxide grown in rapid thermal oxidation (RTO). Base on Weibull slope β, we find, for the first time, degradation on the reliability of the thick-oxide with dual-oxidation in modern CMOS technology. In order to improve this problem, varied gate oxide thicknesses are grown with nitrogen-ion implantation on substrate, and degradation on thick-oxide is improved. In addition, we study on the stress-induced-VTH-shift of 0.15um PMOS device and the stress-induced-VTH-shift of furnace N2O oxides is compared with oxides grown in RTO. It is discovered that the threshold voltage shift is improved by furnace N2O oxidation. Furthermore, the BF2 implantation of S/D engineering is used to improve stress-induced-VTH-shift of advanced PMOS devices. The same results can be found during the reliability testing of negative bias temperature instability (NBTI).
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Choi, Rino Lee Jack Chung-Yeung. "Processing and reliability studies on hafnium oxide and hafnium silicate for the advanced gate dielectric application." 2004. http://repositories.lib.utexas.edu/bitstream/handle/2152/1907/choir042.pdf.
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Choi, Rino. "Processing and reliability studies on hafnium oxide and hafnium silicate for the advanced gate dielectric application." Thesis, 2004. http://hdl.handle.net/2152/1907.
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Kim, Young-Hee Lee Jack Chung-Yeung. "Interface engineering and reliability characteristics of HfO₂ with poly Si gate and dual metal (Ru-Ta alloy, Ru) gate electrode for beyond 65nm technology." 2004. http://repositories.lib.utexas.edu/bitstream/handle/2152/2044/kimy042.pdf.
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Kim, Young-Hee. "Interface engineering and reliability characteristics of HfO₂ with poly Si gate and dual metal (Ru-Ta alloy, Ru) gate electrode for beyond 65nm technology." Thesis, 2004. http://hdl.handle.net/2152/2044.
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Kao, Shih-Hsing, and 高世興. "Reliability Comparison of Metal-Oxide-Semiconductor Capacitors with TiSi2 and NiSi as Gate Electrode Materials." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/49750696231618958165.
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碩士國立暨南國際大學
電機工程學系
94
Most of metal silicide papers in the literature discuss only their thermal stability and the low resistance characteristics, rarely focus on the influence of different metal silicide materials used on the oxide reliability of MOS devices. This thesis studies the reliability issues including those related to radiation resistance and electrical stress resistance of oxide in MOS devices with Titanium silicide (TiSi2) and Nickel silicide (NiSi) as gate electrode materials. In this thesis, constant current stress, constant voltage stress, as well as Co-60 gamma-ray irradiation were applied to the MOS capacitors to see the changes in C-V and I-V characteristics. From our experimental results, we found that the flat band voltage of TiSi2 sample shifted to negatively along the voltage axis and the amount of shifting is larger than that of NiSi sample when both the constant voltage stress and constant current stress were applied to the samples with gate biased negatively. When constant voltage stress or constant current stress applied to both TiSi2 and NiSi samples with gate biased positively, no obvious flat-band voltage shift were observed. Therefore , we concluded that stress resistance of NiSi sample is better than that of TiSi2 sample under constant current stress and constant voltage stress with negative polarity. On the other hand, poly-depletion effect were found in the low frequency capacitor-voltage curve (QSCV) of TiSi2 sample, but not in NiSi sample. Since poly-depletion effect increases the effective thickness of oxide and degrades the device performance, therefore, MOS devices with NiSi gate electrode outperformance that with TiSi2 electrode. The C-V curves of TiSi2 samples shifted negatively along the voltage axis when subjected to 1 Mrad Co-60 gamma-ray irradiation, but no obvious flat-band voltage shift was observed for NiSi samples. Hence, MOS devices used NiSi as gate electrode has better radiation hardness than does the TiSi2 samples.
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Tsai, Hui-Wen, and 蔡惠雯. "Design for Mixed-Voltage I/O Buffer against Hot-Carrier Degradation and Gate-Oxide Reliability." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/95264719758204512138.
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碩士國立交通大學
電子工程系所
97
Rapid development of complementary metal oxide semiconductor (CMOS) techniques desires the transistor dimension to scale down with lower supply voltage continually for reducing chip area, increasing operating speed, and diminishing power consumption. When thickness of gate oxide becomes much thinner and the length of MOS transistor becomes shorter corresponding to smaller device size, the decreasing maximum tolerable voltage across the transistor terminals makes the design of mixed-voltage I/O buffer facing reliability problems such as gate-oxide reliability, hot-carrier degradation, and undesired circuit leakage paths with input signal higher than the voltage level of supply voltage. In this thesis, a new 2xVDD-tolerant I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is presented. The new proposed 2xVDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2xVDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application. Performances as power consumption and the robustness for hot-carrier degradation and gate-oxide overstress are also compared with a few conventional designs.
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Lin, Ching-Chung, and 林清淳. "Bias and Temperautre Dependent Reliability for Dual Gate CMOS Devices Fabricated Using Multi-Oxide Technology." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/99430765143150727808.
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碩士國立交通大學
電子工程系
89
System-on-a-chip (SoC) has received considerable attention for the future dual gate CMOS technology. One of the major technological requirements of SoC is the ability to grow multi-gate oxide thickness, and then multiple supply voltages are used on one chip. To optimize the circuit performance, both circuit architecture and reliability are merged for the design consideration of integration. However, with high density of integrated circuits and an increase of power dissipation, the lifetime prediction is not sufficient by considering only the hot carrier reliability at room temperature for SoC. The temperature effect is of cirtical importance. Although the hot carrier (HC) effect is weak in PMOSFET, negative bias temperature instability (NBTI) is more pronounced at higher operation temperature and a lower operation voltage. In this thesis, we investigated the bias and temperature dependent reliability for the SoC with 7 kinds of stress conditions. This SoC includes two generation of devices with 0.35µm gate length, 65Å gate oxide and 0.18µm gate length, 32Å gate oxide. They were fabricated using multi-oxide technology. For NMOSFET, the stress at IB,MAX and room temperature dominates the device lifetime for 0.35µm devices, while the stress at VG=VD and high temperature dominates the device lifetime for 0.18µm devices. In contrast, the stress at VG=VD and high temperature was shown to dominate the device lifetime for both 0.18µm and 0.35µm PMOSFET in SoC. In particular, for the first time, a new mechanism called enhanced NBTI effect has been proposed. Experimental results show that in addition to the HC effect and NBTI in PMOSFET, we have seen an enhanced degradation caused by the energetic holes in PMOSFET. Therefore, this is a very important factor for reliability test of PMOSFET’s.
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Lai, Ming-Yen, and 賴明彥. "Reliability Comparison of Metal-Oxide-Semiconductor Capacitors with TiSi2 and CoSi2 as Gate Electrode Materials." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/28225613425768717898.
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碩士國立暨南國際大學
電機工程學系
93
Abstract Metal silicide has been used as source/drain and gate contact materials of metal-oxide-semiconductor (MOS) devices in integrated circuit manufacturing to lower the contact resistance. Tungsten silicide is one of the most commonly used one among the various metal silicide materials. Titanium silicide and cobalt silicide are also chosen for their ability to provide lower contact resistance as the device size is shrunk. Most of the metal silicide papers in the literature discuss only their thermal stability and the low resistance characteristics, rarely focus on the influences of different metal silicide materials used on the oxide reliability of MOS devices. This thesis studies the reliability issue of oxide in MOS devices using titanium silicide (TiSi2) and cobalt silicide (CoSi2) as gate electrode materials. Low-frequency capacitance-voltage (C-V) was adopted as the evaluation tool for investigating the reliability of MOS capacitors with TiSi2 and CoSi2 as gate electrode by applying constant voltage/current stresses with either polarity to the devices. When compared with TiSi2 samples, larger low-frequency C-V shift was found in CoSi2 samples when a negative electric stress was applied on it. In the negative stress case, both the flat-band voltage shift and stress-induced interface trap density in CoSi2 samples were larger than those in TiSi2 samples. Under positive stress case, only little difference between the CoSi2 and TiSi2 samples was observed. We think that there exist a high resistance depletion region metal silicide structure which reduces the current flowing through the samples when a large positive stress applied to the CoSi2 and TiSi2 samples. Since the initial flat-band voltage and interface trap density in CoSi2 samples is a little bit higher than that in TiSi2 samples, we believe that some sort of process-induced interface stress has already been generated at the SiO2/Si interface stress during the preparation of the samples. Therefore, the oxide quality of CoSi2 samples is worse than that of TiSi2 samples.
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Shiue, Jao-Hsian, and 薛兆軒. "A Study on Reliability of Ultra-thin Gate Oxide in MOS Devices for ULSI Applications." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/05753940326306732380.
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碩士國立清華大學
電機工程研究所
86
In this thesis, four types of devices are fabricated:NMOS and PMOS with 4-nm gate-oxide grown in either O2 or NO2 atmosphere. Gate leakage current, threshold voltage shift, mobility degradation, oxidetrapped charge(Qot) and interface-trapped charge (Qit) generated after different electrical stresses are studied. Both Qot and Qit cause stress-induced threshold voltage shift and mobility degradation. For 4nm gate-oxide MOSFETs, the generated Dit after VG<0 Fowler-Nordheim stress of a IG=80mA/cm2 at 50 sec is 1.3×1011cm-2 .The generated Qot is 2.5×1010cm-2 .Qit is therefore more dominant than Qot for the both issues by. The generation of Qit by different stresses is studied. It is conchuded that the energy released in the impact ionization event is one of the primary reasons for interface-trap generation by VG<0 FN stress. Hot holes impacting the interface is another. The stress-induced Qit of gate-oxides grown with N2O and O2 are compared in this work. N2O-grown gate-oxide has better hole-injection prevention than O2-grown oxide. For PMOS, hot holes generate less interface traps at N2O-grown gate-oxide. Beside, N2O-grown gate-oxide has good boron-penetration prevention and better polysilicon depletion prevention.In the future, N2O-grown gate-oxide will be the trend for VLSI gate-oxide process.
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Nieh, Renee Elizabeth. "An evaluation of the electrical, material, and reliability characteristics and process viability of ZrO₂ and ZrOxNy for future generation MOS gate dielectric." Thesis, 2002. http://wwwlib.umi.com/cr/utexas/fullcit?p3099506.
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Shen, Wan-Yi, and 沈宛儀. "Design of Charge Pump Circuit in Low-Voltage CMOS Process With Consideration on Gate-Oxide Reliability." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/34686375138211905989.
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碩士國立交通大學
電子工程系所
94
Recent applications like USB OTG (On-The-Go) require not only the high voltage level but also high current drivability. The internal charge pump circuit of the USB On-The-Go dual-role transceiver supplies VBUS power and signaling that is required by the transceiver. In this thesis, two kinds of design of charge pump circuit in low-voltage CMOS process with consideration on gate-oxide reliability are presented. The two designs of charge pump circuit can also provide high voltage level and high current drivability. In order to enhance the pumping gain of each stage, it is necessary that charge transfer switches must be used in the two proposed charge pump circuits. We use new clock control signals to implement the two kinds of charge pump circuits in thesis. This method may not only dealing the gate-oxide reliability but also solving the back leakage effect in the rise or fall time of the clock signals in the old charge pump design. In order to deal the variation of the output voltage value causing by the change of the output current loading, we will add the feedback loop to the charge pump circuit. By controlling the frequency of the voltage-controlled oscillator (VCO) in the feedback loop, we will tune the output voltage of the charge pump circuit to the voltage level we want. During the initial pumping state, the voltage value of output is very small, so we let the frequency of the voltage-controlled oscillator circuit to be fast. This method can speed up the pumping progress and let the output voltage achieve the level we want quickly. After the pumping progress, the voltage value of output might be higher than we want, so we let the frequency of the voltage-controlled oscillator circuit to be slow. This method can lower the pumping efficiency let the output voltage maintain the level we want. If the voltage value of output is lower than what we want, we will let the frequency of the voltage-controlled oscillator circuit to be fast. And we can know that this circulation will last constantly when there exist the variation of the output voltage.
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Rhee, Se Jong. "Electrical and material characteristics of hafnium-based multi-metal high-k gate dielectrics for future scaled CMOS technology: physics, reliability, and process development." Thesis, 2005. http://hdl.handle.net/2152/2287.
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Akbar, Mohammad Shahariar Lee Jack Chung-Yeung. "Process development, characterization, transient relaxation, and reliability study of HfO₂ and HfSi(x)O(y) gate oxide for 45nm technology and beyond." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1495/akbarm58099.pdf.
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