Dissertations / Theses on the topic 'GATE LEVEL SIMULATION'

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 42).
In the last several years, parallel computing on multicore processors has transformed from a niche discipline relegated primarily to scientific computing into a standard component of highperformance personal computers. At the same time, simulating processors prior to manufacture has become increasingly time-consuming due to the increasing number of gates on a single chip. However, writing parallel programs in a way that significantly improves performance can be a difficult task. In this thesis, I outline principles that must be considered when running good gate-level circuit simulations in parallel. I also analyze a test circuit's performance in order to quantitatively demonstrate the benefit of considering these principles in advance of running simulations.
by Jacinda R. Shelly.
M.Eng.

As a consequence of Moore's law, the size of integrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. Consequently, parallel simulation has emerged as an approach which can be both fast and cost effective. In this thesis, we examine the performance of a parallel Verilog simulator, VXTW, on four large, real designs using an optimistic synchronization scheme named Time Warp. As previous work has made use of either relatively small benchmarks or synthetic circuits, the use of these circuits is far more realistic. Because of the low computational granularity of a gate level simulation and because the computational and communication loads vary throughout the course of the simulation, the performance of Time Warp can be severely degraded or can even be unstable. Dynamic load balancing algorithms for balancing the computational and communication loads during the simulation are described in this thesis. Like all load balancing algorithms, the proposed algorithms have some tuning parameters which must be optimized. In addition, in order to avoid the simulation from being too optimistic, we make use of a time window. In the thesis, we make use of learning techniques from artificial intelligence (N-armed Bandit, Multi-state Q-learning) and heuristic searches (Genetic Algorithm, Simulated Annealing) to tune the parameters of the dynamic load balancing algorithms and to determine the size of the time window. we evaluated the performance of these algorithms on open source Sparc and Leon processor designs and on two Viterbi decoder designs and observed up to a 70% improvement in simulation time using these approaches.
Une des conséquences de la loi de Moore est la croissance significative de lataille des circuits intégrés; il en résulte que la simulation est devenue le goulot d'étranglement majeur dans le processus de conception de tels circuits. Conséquemment, la simulation parallèle se veut une approche qui a le potentiel d'être à la fois rapide etrentable. Dans cette thèse, nous examinerons la performance d'un simulateur Verilog parallèle appelé VXTW sur quatre conceptions de processeurs réelles de grande taille, en utilisant un algorithme de synchronisation optimiste appelé Time Warp. Puisque les travaux précédents ont utilisé des circuits synthétiques ou des tests de performance de taille relativement petite, l'utilisation de ces circuits est beaucoup plus réaliste. Puisque les simulations au niveau des portes logiques impliquent une granularité calculatoire peu élevée, et puisque les charges calculatoires et de communication varient au cours de la simulation, la performance de Time Warp peut se dégrader sévèrement ou devenir instable. Dans cette thèse, nous décrivons des algorithmes dynamiques d'équilibrage de charge visant à équilibrer les charges calculatoires et de communicationdurant la simulation. Comme tous les algorithmes d'équilibrage de charge, les algorithmes proposés comportent des paramètres de réglage qui doivent être optimisés. De plus, nous utilisons une fenêtre de temps pour éviter que la simulation ne soit trop optimiste. Dans cette thèse, nous utilisons des techniques d'apprentissage provenant du domaine de l'intelligence artificielle (machine à sous à leviers multiples, Q-learning avec plusieurs agents) et des recherches heuristiques (algorithmes génétiques, méthode du circuit simulé) pour régler les paramètres des algorithmes dynamiques d'équilibrage des charges, ainsi que pour déterminer la taille de la fenêtre de temps. Nous évaluons la performance de ces algorithmes sur des conceptions de processeurs Sparc et Leon libres de droits, ainsi que sur deux décodeurs Viterbi, et nous avons pu observer une amélioration du temps de simulation de 70% en utilisant ces approches.

This thesis introduces a new methodology for energy estimation in asynchronous circuits. Unlike existing probabilistic methods, this is the first simulative work for energy estimation in all types of asynchronous circuits. The new simulative methodology is based on Petri net modeling. A real delay model is incorporated to capture both gate delays and interconnect delays. The switching activity at each gate is captured to measure the average dynamic energy consumed per request/acknowledge handshaking pair. The new type of Petri net is called Hierarchical Colored Asynchronous Hardware Petri net (HCAHPN). The HCAHPN is able to capture the temporal and spatial correlations of signals within a circuit, while preserving gate logic behavior and timing information. While Petri nets have been previously used for simulating combinational and sequential circuits, this is the first work that uses Petri nets for simulating asynchronous circuits. While different asynchronous design styles make various assumptions on the gate and wire delays present with the circuit, the physical implementations of these circuits always have gate and interconnect delays. Unlike previous methods, the proposed methodology is independent of the asynchronous design style used and it can be adapted for all types of asynchronous circuits that use handshaking communication.

Pour le développement des convertisseurs d’électronique de puissance, la simulation en temps réel joue un rôle essentiel dans la validation des performances des convertisseurs et de leur contrôle avant leur réalisation. Cela permet de simuler et reproduire avec précision les formes d’ondes des courants et tensions des convertisseurs de puissance modélisés avec un pas de temps de simulation correspondant exactement au temps physique. Les circuits d’électronique de puissance sont caractérisés par le comportement non linéaire des interrupteurs. Par conséquent, les représentations des dispositifs de commutation sont cruciales dans la simulation en temps réel. Le modèle au niveau système est largement utilisé dans les simulateurs temps réel du commerce et les plates-formes expérimentales, qui modélisent les comportements des interrupteurspar deux états stationnaires distincts - passant et bloqué - et négligent tous les phénomènes transitoires. Ces dernières années, la simulation temps réel au niveau du composant est devenue populaire car elle permet de simuler les formes d'onde de commutation transitoires et de fournir des informations utiles concernant les contraintes sur les interrupteurs , les pertes, les effets parasites et les comportements électrothermiques. Néanmoins, la simulation temps réel au niveau du composant est contrainte par le pas de temps transitoire réalisable en raison des quantités de calcul accrues introduites par la non-linéarité du modèle de commutation.Afin d'intégrer le modèle au niveau du composant dans la simulation en temps réel, cette thèse porte sur l'exploration approfondie des techniques de modélisation et de simulation en temps réel au niveau composantdes convertisseurs d’électronique de puissance. Les techniques de simulation en temps réel les plus récentes sont d’abord examinées de manière exhaustive, tant au niveau du système que du composant. En outre, deux approches de modélisation au niveau du composant sont proposées, à savoir le modèle haute résolution quasi-transitoire (HRQT) et le modèle transitoire linéaire par morceaux (PLT). Dans le modèle HRQT, le modèle de réseau est implémenté par une simulation au niveau système tout en générant les formes d'onde de commutation transitoires avec une résolution de 5 ns, ce qui permet de simuler le convertisseur de puissance avec des transitoires rapides jusqu'à des dizaines de nanosecondes. Compte tenu des effets des transitoires sur l’ensemble du réseau, les modèles non linéaires des IGBT et diodes sont linéarisés par morceaux dans le modèle PLT. À l'aide de techniques efficaces de découplage de circuits, le modèle du convertisseur de puissance au niveau composant peut être simulé de manière stable avec un pas de temps de simulation global de 50 ns. Les deux modèles proposés sont testés et validés via différents cas sur une plate-forme temps réel de National Instruments basée sur un FPGA, comprenant un convertisseur boost boosté entrelacé (FIBC) pour le modèle HRQT, un convertisseur DC-DC-AC pour le modèle PLT et un convertisseur modulaire à plusieurs niveaux (MMC) pour les deux. Des résultats précis sont produits par rapport aux outils de simulation hors ligne. L'efficacité et les valeurs d'application sont également vérifiées par les résultats d’essais en temps réel
In the development cycles of the power electronics converters, the real-time simulation plays an essential role in validating the converters’ and the controllers’ performances before their implementations on real systems. It can simulate and reproduce the current and voltage waveforms of the modeled power electronics converters accurately with a simulation time-step exactly corresponding to the physical time. The power electronics circuits are characterized by nonlinear switching behaviors. Therefore, the representations of switching devices are crucial in real-time simulation. The system-level model is widely used in both commercial real-time simulators and the experimentally built real-time platforms, which models the switching behaviors by two separate steady states – turn-on and turn-off, and neglects all the switching transients. In recent years, the device-level real-time simulation has become popular since it can simulate the transient switching waveforms and provide useful information with regard to the device stresses, the power losses, the parasitic effects, and electro-thermal behaviors. Nevertheless, the device-level real-time simulation is constrained by the achievable transient time-step due to the increased computational amounts introduced by the nonlinearity of the switch model.In order to integrate the device-level model in the real-time simulation, in this thesis, the device-level real-time modeling and simulation techniques of the power electronics converters are deeply explored. The state-of-art real-time simulation techniques are firstly reviewed comprehensively with regard to both system-level and device-level. Moreover, two device-level modeling approaches are proposed, including high- resolution quasi-transient model (HRQT) and the piecewise linear transient (PLT) model. In HRQT model, the network model can be implemented by system-level simulation while generating the transient switching waveforms with a 5 ns resolution, which is good at simulating the power converter with fast switching transients down to tens of nanoseconds. Considering the effects of the transient behaviors on the entire network, the PLT model is proposed by piecewise linearizing the nonlinear IGBT and diode equivalent models. With the help of effective circuit decoupling techniques, the device-level power converter model can be simulated stably with a 50 ns global simulation time-step. The proposed two models are tested and validated via different case studies on National Instruments (NI) FPGA-based real-time platform, including floating interleaved boost converter (FIBC) for HRQT model, DC-DC-AC converter for PLT model, and modular multi-level converter (MMC) for the both. Accurate results are produced compared to offline simulation tools. The effectiveness and the application values are further verified by the results of the real-time experiments

Thesis (M.S.) -- University of Maryland, College Park, 2005.
Thesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.

A key part in the development and verification of digital systems is simulation. But hardware simulators are expensive, and software simulation is not fast enough for designs with a large number of gates. As today’s digital zesigns constantly grow in size (number of gates), and that trend shows no signs to end, faster simulators handling millions of gates are needed.

We investigate how to create a software gate-level simulator able to simulate a high number of gates fast. This involves a trade-off between memory requirement and speed. A compact netlist representation can utilize cache memories more efficient but requires more work to interpret, while high memory requirements can limit the performance to the speed of main memory.

We have selected the Counting Algorithm to implement the experimental simulator MICA. The main reasons for this choice is the compact way in which gates can be stored, but still be evaluated in a simple and standard way.

The report describes the issues and solutions encountered and evaluate the resulting simulator. MICA simulates a SPARC architecture processor called Leon. Larger netlists are achieved by simulating several instances of this processor. Simulation of 128 instances is done at a speed of 9 million gates per second using only 3.5MB memory. In MICA this design correspond to 2.5 million gates.

Thesis (M.C.P.)--Massachusetts Institute of Technology, Dept. of Urban Studies and Planning, 1985.
MICROFICHE COPY AVAILABLE IN ARCHIVES AND ROTCH.
Bibliography: leaves 74-75.
by Wendy L. Rundle.
M.C.P.

This thesis presents an approach to predict the difficulty of levels in a game by simulating game play following a policy learned from human game play. Using state-action pairs tracked from players of the game Candy Crush Saga, we train a Convolutional Neural Network to predict an action given a game state. The trained model then acts as a policy.Our goal is to predict the success rate (SR) of players, from the SR obtained by simulating game play. Previous state-ofthe-art was using Monte Carlo tree search (MCTS) or handcrafted heuristics for game play simulation. We benchmark our suggested approach against one using MCTS. The hypothesis is that, using our suggested approach, predicting the players’ SR from the SR obtained through the simulation, leads to better estimations of the players’ SR.Our results show that we could not only significantly improve the predictions of the players’ SR, but also decrease the time for game play simulation by at least 50 times.
Den här avhandlingen presenterar ett tillvägagångssätt för att förutse svårighetsgrad av spelbanor genom spelsimulering enligt en strategi lärd från mänskligt spelande. Med användning av tillstånd-handlings par insamlade från spelare av spelet Candy Crush Saga, tränar vi ett Convolutional Neural Network att förutse en handling från ett givet tillstånd. Den tränade modellen agerar sedan som strategi. Vårt mål är att förutse success rate (SR) av spelare, från SR erhållen från spelsimulering. Tidigare state-of-the-art använde Monte Carlo tree search (MCTS) eller handgjorda heuristiker för spelsimulering. Vi jämför vårt tillvägagångssätt med MCTS. Hypotesen är att vårt föreslagna tillvägagångssätt leder till bättre förutsägelser av mänsklig SR från SR erhållen från spelsimulering. Våra resultat visar att vi inte bara signifikant kunde förbättra förutsägelserna av mänsklig SR utan också kunde minska tidsåtgången för spelsimulering med åtminstone en faktor 50.

Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les " design tools " permettant alors d'étudier et d'élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l'élaboration d'un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s'appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction.

Afin de dépasser la limite d'échelle, il existe une solution innovante qui permet de fabriquer des structures multi-grilles. Ainsi, un NMOSFET composé de trois grilles indépendantes fabriquées dans la technologie CMOS. En dehors de leur forme, géométrique, le transistor multi-grille est similaire à une structure classique. Une multi-grille NMOSFET peut être fabriquée par l'intégration de tranchées de polysilicium. Ces tranchées sont utilisées dans diverses applications telles que les mémoires DRAM, électronique de puissance ou de capteurs d'image. Les capteurs d'image présentent le problème des charges parasites entre les pixels, appelées diaphonie. Les tranchées sont l'une des solutions qui réduisent ce phénomène. Ces tranchées assurent l'isolation électrique sur toute la matrice des pixels. Nous avons étudié ses caractéristiques en utilisant des mesures I-V, méthode du split C-V et de pompage de charge à deux et à trois niveaux. Son multi-seuil caractéristique a été vérifié. Nous n'avons observé aucune dégradation significative de ces caractéristiques grâce à l'intégration des tranchées. La structure a été simulée par la méthode des éléments finis en 3D via le logiciel TCAD. Ses caractéristiques électriques ont été simulées et confrontées avec les résultats obtenus à partir de mesures électriques. La tension de seuil et la longueur de canal effective ont été extraites. Sa mobilité effective et les pièges de l'interface Si/SiO2 ont également été simulés ou calculés. En raison des performances électriques satisfaisantes et d'un bon rendement, nous avons remarqué que ce dispositif est une solution adéquate pour les applications analogiques grâce aux niveaux de tension multi-seuil
One of the recent solutions to overcome the scaling limit issue are multi-gate structures. One cost-effective approach is a three-independent-gate NMOSFET fabricated in a standard bulk CMOS process. Apart from their shape, which takes advantage of the three-dimensional space, multi gate transistors are similar to the conventional one. A multi-gate NMOSFET in bulk CMOS process can be fabricated by integration of polysilicon-filled trenches. This trenches are variety of the applications for instance in DRAM memories, power electronics and in image sensors. The image sensors suffer from the parasitic charges between the pixels, called crosstalk. The polysilicon - filled trenches are one of the solution to reduce this phenomenon. These trenches ensure the electrical insulation on the whole matrix pixels. We have investigated its characteristics using l-V measurements, C-V split method and both two- and three-level charge pumping techniques. Tts tunable-threshold and multi-threshold features were verified. Tts surface- channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. We observed no significant degradation of these characteristics due to integration of polysilicon-filled trenches in the CMOS process. The structure has been simulated by using 3D TCAD tool. Tts electrical characteristics has been evaluated and compared with results obtained from electrical measurements. The threshold voltage and the effective channel length were extracted. Tts surface-channel low-field electron mobility and the Si/SiO2 interface traps were also evaluated. Owing to the good electrical performances and cost-effective production, we noticed that this device is a good aspirant for analog applications thanks to the multi-threshold voltages

L’objectif de ce travail de Thèse est d’évaluer les capacités de composants numérique de type Système-sur-Puce (SoC en anglais) pour l’implantation de Simulateurs Temps Réel Embarqués (ERTS en anglais) de systèmes électromécaniques et d’électronique de puissance. En effet, l’utilisation de ces simulateurs n’est pas seulement limitée aux validations matériel dans la boucle (en anglais Hardware-in-the-Loop ou HIL) du système mais doivent également être embarqués avec le contrôleur afin d’assurer plusieurs fonctionnalités additionnelles comme l'observation, l'estimation, commande sans capteur (ou sensorless), le diagnostic ou la surveillance de la santé, commande tolérante aux défauts, etc.La réalisation de ces simulateurs doit néanmoins considérer plusieurs contraintes à plusieurs niveaux de développement : durant la modélisation de la partie du système à simuler en temps-réel, durant la réalisation numérique et enfin durant l’implantation sur le composant numérique utilisé. Ainsi, le travail réalisé durant cette Thèse s’est focalisé sur ce dernier niveau et l’objectif était d’évaluer les capacités temps/ressources des composants de type SoC pour l’implantation de modules ERTS. Ce type de plateformes intègrent dans un même composant de puissants processeurs, un circuit logique programmable (de type Field-Programmable Gate Array ou FPGA), et d’autres périphériques, ce qui offre plusieurs opportunités d’implantation.Afin de pallier les limitations liées au codage VHDL de la partie FPGA, il existe des outils High-Level Synthesis (HLS) qui permettent de programmer ces dispositifs en utilisant des langages à haut niveau d'abstraction comme C, C++ ou SystemC. De plus, en incluant des directives et contraintes au code source, ces outils peuvent produire des implémentations matérielles différentes (architecture totalement combinatoire, « pipeline », architecture parallélisées ou factorisées, arranger les données et leurs formats pour une meilleure utilisation des ressources de mémoire, etc.).Dans le but d’évaluer ces différentes implantations, deux cas d’études ont été choisis : le premier se compose d’un Générateur Asynchrone à Double Alimentation (GADA) et le second d’un Convertisseur Modulaire Multiniveau (ou Modular Multi-level Converter - MMC). Vu que la GADA a une dynamique basse/moyenne (dynamiques électriques et mécaniques), deux versions d’implantations ont été évaluées : (i) une implantation full-software en utilisant seulement les processeurs ARM; et (ii) une implantation full-hardware en utilisant l’outil HLS pour programmer la partie FPGA. Ces deux versions ont été évaluées avec différentes optimisations du compilateur et trois formats de données: 64/32-bit en virgule flottante, et 32-bit en virgule flottante. L’approche mixe software/hardware a également été évaluée à travers la caractérisation des transferts de données entre le processeur et l’IP ERTS implantée dans la partie FPGA. Quant au convertisseur MMC, sa complexité et sa forte dynamique (dynamique de commutation) impose une implantation exclusivement full-hardware. Celle-ci a également été réalisée à base d’outils HLS.Enfin pour la validation expérimentale de ce travail de Thèse, une maquette à base de convertisseur MMC a été construite dans le but de comparer des mesures du système réel avec les résultats fournis par l’IP ERTS
This Doctoral Thesis is a detailed study of how suitable System-on-Chip (SoC) devices are for implementing Embedded Real-Time Simulators (ERTS) of electromechanical and power electronic systems. This emerging class of Real-Time Simulators (RTS) are not only expected for Hardware-in-the-Loop (HIL) validations of systems; but they also have to be embedded within the controller to play several roles like observers, parameter estimation, diagnostic, health monitoring, fault-tolerant and sensorless control, etc.The design of these Intellectual Properties (IP) must rigorously consider a set of constraints at different development stages: (i) during the modeling of the system to be real-time simulated; (ii) during the digital realization of the IP; and also (iii) during its final implementation in the digital platform. Thus, the conducted work of this Thesis focuses specially on this last stage and its aim is to evaluate the time/resource performances of recent SoC devices and study how suitable they are for implementing ERTSs. These kind of digital platforms combine powerful general purpose processors, a Field-Programmable Gate Array (FPGA) and other peripherals which make them very convenient for controlling and monitoring a complete system.One of the limitations of these devices is that control engineers are not particularly familiarized with FPGA programming, which needs extensive expertise in order to code these highly sophisticated algorithms using Hardware Description Languages (HDL). Notwithstanding, there exist High-Level Synthesis (HLS) tools which allow to program these devices using more generic programming languages such as C, C++ or SystemC. Moreover, by inserting directives and constraints to the source code, these tools can produce different hardware implementations (e.g. full-combinatorial design, pipelined design, parallel or factorized design, partition or arrange data for a better utilisation of memory resources, etc.).This dissertation is based on the implementation of two representative applications that are well known in our laboratory: a Doubly-fed Induction Generator (DFIG) commonly used as wind turbines; and a Modular Multi-level Converter (MMC) that can be arranged in different configurations and utilized for many different energy conversion purposes. Since the DFIG has low/medium system dynamics (electrical and mechanical ones), both a full-software implementation using solely the ARM processor and a full-hardware implementation using HLS to program the FPGA will be evaluated with different design optimizations and data formats (64/32-bit floating-point and 32-bit fixed-point). Moreover, it will also be investigated whether a system of these characteristics is interesting to be run as a hardware accelerator. Different data transfer options between the Processor System (PS) and the Programmable Logic (PL) have been studied as well for this matter. Conversely, because of its harsh dynamics (switching dynamics), the MMC will be implemented only with a full-hardware approach using HLS tools, as well.For the experimental validation of this Thesis work, a complete MMC test bench has been built from scratch in order to compare the real-world results with its SoC ERTS implementation

The Hybrid Warfare phenomena, which is the subject of the current research, has been framed by the work of Professor Agostino Bruzzone (University of Genoa) and Professor Erdal Cayirci (University of Stavanger), that in June 2016 created in order to inquiry the subject a dedicated Exploratory Team, which was endorsed by NATO Modelling & Simulation Group (a panel of the NATO Science & Technology organization) and established with the participation as well of the author. The author brought his personal contribution within the ET43 by introducing meaningful insights coming from the lecture of “Fight by the minutes: Time and the Art of War (1994)”, written by Lieutenant Colonel US Army (Rtd.) Robert Leonhard; in such work, Leonhard extensively developed the concept that “Time”, rather than geometry of the battlefield and/or firepower, is the critical factor to tackle in military operations and by extension in Hybrid Warfare. The critical reflection about the time - both in its quantitative and qualitative dimension - in a hybrid confrontation it is addressed and studied inside SIMCJOH, a software built around challenges that imposes literally to “Fight by the minutes”, echoing the core concept expressed in the eponymous work. Hybrid Warfare – which, by definition and purpose, aims to keep the military commitment of both aggressor and defender at the lowest - can gain enormous profit by employing a wide variety of non-military tools, turning them into a weapon, as in the case of the phenomena of “weaponization of mass migrations”, as it is examined in the “Dies Irae” simulation architecture. Currently, since migration it is a very sensitive and divisive issue among the public opinions of many European countries, cynically leveraging on a humanitarian emergency caused by an exogenous, inducted migration, could result in a high level of political and social destabilization, which indeed favours the concurrent actions carried on by other hybrid tools. Other kind of disruption however, are already available in the arsenal of Hybrid Warfare, such cyber threats, information campaigns lead by troll factories for the diffusion of fake/altered news, etc. From this perspective the author examines how the TREX (Threat network simulation for REactive eXperience) simulator is able to offer insights about a hybrid scenario characterized by an intense level of social disruption, brought by cyber-attacks and systemic faking of news. Furthermore, the rising discipline of “Strategic Engineering”, as envisaged by Professor Agostino Bruzzone, when matched with the operational requirements to fulfil in order to counter Hybrid Threats, it brings another innovative, as much as powerful tool, into the professional luggage of the military and the civilian employed in Defence and Homeland security sectors. Hybrid is not the New War. What is new is brought by globalization paired with the transition to the information age and rising geopolitical tensions, which have put new emphasis on hybrid hostilities that manifest themselves in a contemporary way. Hybrid Warfare is a deliberate choice of an aggressor. While militarily weak nations can resort to it in order to re-balance the odds, instead military strong nations appreciate its inherent effectiveness coupled with the denial of direct responsibility, thus circumventing the rules of the International Community (IC). In order to be successful, Hybrid Warfare should consist of a highly coordinated, sapient mix of diverse and dynamic combination of regular forces, irregular forces (even criminal elements), cyber disruption etc. all in order to achieve effects across the entire DIMEFIL/PMESII_PT spectrum. However, the owner of the strategy, i.e. the aggressor, by keeping the threshold of impunity as high as possible and decreasing the willingness of the defender, can maintain his Hybrid Warfare at a diplomatically feasible level; so the model of the capacity, willingness and threshold, as proposed by Cayirci, Bruzzone and Gunneriusson (2016), remains critical to comprehend Hybrid Warfare. Its dynamicity is able to capture the evanescent, blurring line between Hybrid Warfare and Conventional Warfare. In such contest time is the critical factor: this because it is hard to foreseen for the aggressor how long he can keep up with such strategy without risking either the retaliation from the International Community or the depletion of resources across its own DIMEFIL/PMESII_PT spectrum. Similar discourse affects the defender: if he isn’t able to cope with Hybrid Threats (i.e. taking no action), time works against him; if he is, he can start to develop counter narrative and address physical countermeasures. However, this can lead, in the medium long period, to an unforeseen (both for the attacker and the defender) escalation into a large, conventional, armed conflict. The performance of operations that required more than kinetic effects drove the development of DIMEFIL/PMESII_PT models and in turn this drive the development of Human Social Culture Behavior Modelling (HCSB), which should stand at the core of the Hybrid Warfare modelling and simulation efforts. Multi Layers models are fundamental to evaluate Strategies and Support Decisions: currently there are favourable conditions to implement models of Hybrid Warfare, such as Dies Irae, SIMCJOH and TREX, in order to further develop tools and war-games for studying new tactics, execute collective training and to support decisions making and analysis planning. The proposed approach is based on the idea to create a mosaic made by HLA interoperable simulators able to be combined as tiles to cover an extensive part of the Hybrid Warfare, giving the users an interactive and intuitive environment based on the “Modelling interoperable Simulation and Serious Game” (MS2G) approach. From this point of view, the impressive capabilities achieved by IA-CGF in human behavior modeling to support population simulation as well as their native HLA structure, suggests to adopt them as core engine in this application field. However, it necessary to highlight that, when modelling DIMEFIL/PMESII_PT domains, the researcher has to be aware of the bias introduced by the fact that especially Political and Social “science” are accompanied and built around value judgement. From this perspective, the models proposed by Cayirci, Bruzzone, Guinnarson (2016) and by Balaban & Mileniczek (2018) are indeed a courageous tentative to import, into the domain of particularly poorly understood phenomena (social, politics, and to a lesser degree economics - Hartley, 2016), the mathematical and statistical instruments and the methodologies employed by the pure, hard sciences. Nevertheless, just using the instruments and the methodology of the hard sciences it is not enough to obtain the objectivity, and is such aspect the representations of Hybrid Warfare mechanics could meet their limit: this is posed by the fact that they use, as input for the equations that represents Hybrid Warfare, not physical data observed during a scientific experiment, but rather observation of the reality that assumes implicitly and explicitly a value judgment, which could lead to a biased output. Such value judgement it is subjective, and not objective like the mathematical and physical sciences; when this is not well understood and managed by the academic and the researcher, it can introduce distortions - which are unacceptable for the purpose of the Science - which could be used as well to enforce a narrative mainstream that contains a so called “truth”, which lies inside the boundary of politics rather than Science. Those observations around subjectivity of social sciences vs objectivity of pure sciences, being nothing new, suggest however the need to examine the problem under a new perspective, less philosophical and more leaned toward the practical application. The suggestion that the author want make here is that the Verification and Validation process, in particular the methodology used by Professor Bruzzone in doing V&V for SIMCJOH (2016) and the one described in the Modelling & Simulation User Risk Methodology (MURM) developed by Pandolfini, Youngblood et all (2018), could be applied to evaluate if there is a bias and the extent of the it, or at least making clear the value judgment adopted in developing the DIMEFIL/PMESII_PT models. Such V&V research is however outside the scope of the present work, even though it is an offspring of it, and for such reason the author would like to make further inquiries on this particular subject in the future. Then, the theoretical discourse around Hybrid Warfare has been completed addressing the need to establish a new discipline, Strategic Engineering, very much necessary because of the current a political and economic environment which allocates diminishing resources to Defense and Homeland Security (at least in Europe). However, Strategic Engineering can successfully address its challenges when coupled with the understanding and the management of the fourth dimension of military and hybrid operations, Time. For the reasons above, and as elaborated by Leonhard and extensively discussed in the present work, addressing the concern posed by Time dimension is necessary for the success of any military or Hybrid confrontation. The SIMCJOH project, examined under the above perspective, proved that the simulator has the ability to address the fourth dimension of military and non-military confrontation. In operations, Time is the most critical factor during execution, and this was successfully transferred inside the simulator; as such, SIMCJOH can be viewed as a training tool and as well a dynamic generator of events for the MEL/MIL execution during any exercise. In conclusion, SIMCJOH Project successfully faces new challenging aspects, allowed to study and develop new simulation models in order to support decision makers, Commanders and their Staff. Finally, the question posed by Leonhard in terms of recognition of the importance of time management of military operations - nowadays Hybrid Conflict - has not been answered yet; however, the author believes that Modelling and Simulation tools and techniques can represent the safe “tank” where innovative and advanced scientific solutions can be tested, exploiting the advantage of doing it in a synthetic environment.

Thesis describes programming of 3D applications, mainly games, on Windows Phone 7 platform and lightly compares this approach with Silverlight platform. It also describes XNA framework in detail and programming plane simulators problems. In the second part of this thesis, reader can find complete description of implementation of a simple airplane simulation for Windows Phone 7 platform, which is based on the XNA framework. The game consists of implementation of terrain, sky, plane, scene and also of physics and the principle of the game.

碩士
國立臺灣大學
電子工程學研究所
105
Unknown values(Xs) may exist in a design due to uninitialized registers or blocks that are powered down. Due to X-pessimism in gate-level logic simulation, such Xs cannot be handled correctly. To eliminate false X, current algorithm repeatedly calls the SAT solver to check if the X is false or not. SAT solvers try to find a single solution and even if the input Boolean function is the same, the SAT solver will be completely re-executed. In this paper, a method to find the dominating real X patterns is presented. Taking use of Binary Decision Diagrams (BDDs), we can find good patterns efficiently. After finding the patterns, we can check the patterns before calling the SAT solver. If a pattern match successfully, we can confirm X is real without calling the SAT solver. Experimental results show that the proposed method can find enough good patterns in a short time.

Timing holds a very important part in any VLSI design and incorporates the sense of realism into the design. Static Timing Analysis (also referred as STA) is one of the many techniques available to verify the timing of a digital design. Static timing analysis is a complete and exhaustive verification of all timing checks of a design, without requiring simulation. The more important aspect of static timing analysis is that the entire design is analyzed once and the required timing checks are performed for all possible paths and scenarios of the design. Further , the design can be analyzed in various corners to ensure the proper functioning of the design in all the scenarios. Thus, STA is a complete and exhaustive method for verifying the timing of a design. The project is aimed at understanding as well as performing clocking and timing closure of the whole SoC chip. This elaborates on the basic flow adopted to check the timing of a chip, procedures to meet them and debug the errors. The tool used here is ETS which helps in forming detailed reports for finding the violations and simulating the timing behaviour of the circuit.

碩士
國立交通大學
生醫工程研究所
104
In Information and Communication Technology (ICT), the panel display had been widely used in many applications, such as TVs, cell phones, flats, multi-parameter monitors, and ultrasound medical equipments. The structure of TFT-LCD has a backlight unit and a panel display is composed of the active matrix which has gate lines controlled by ASG driver circuits, liquid crystal (LC), the transparent electrode and the color filter (CF) film between two polarizer films. Nowadays, panel displays with various sizes are widely used. To fabricate panel displays with high performance and competitiveness, ASG driver circuits play one of key techniques. In general, ASG driver circuit designs strongly rely on adjusting and testing by experienced engineers. However, with the diverse needs for panel displays of information, communication, and biomedical science, designs of ASG driver circuits are getting more and more complex. Thus, we should consider more engineering parameters which need to be optimized at the same time. The genetic algorithm (GA) is usually used for circuit designs, which we can only write one cost function with many design specifications. However, due to many characteristics of ASG driver circuits, the adjusting of the cost function is very difficult. Recently, the multi-objective evolutionary algorithm (MOEA) which can optimize many cost functions at the same time has become more popular in circuit designs. In this study, we optimize the ASG driver circuits by using the MOEA. To improve the power consumption of panel display, we propose the multi-level clock driving method. Cooperating with display manufacturer in Taiwan, we successfully fabricate the sample of the optimized ASG driver circuit which has excellent characteristics. First, the problem of the ASG driver circuit on unified optimization framework can be seperated into two parts, the circuit problem and the solver. The configuration file of the circuit problem calls the mask file which provides the positions of masked parameters as well as the parameter file which sets the ranges of parameters. The configuration file also provides parameters to intermediate _file (written by C++ program) for optimization. The solver generates and chooses the solutions. Furthermore, it also calls the external circuit simulator to calculate the characteristics of ASG driver circuits. The terminal condition is according to generations setting by the configuration file. We design a six-stage ASG driver circuit by using optimized method based on the MOEA. Each stage of this ASG driver circuit has 17 a-Si:H TFTs and 4 capacitors. The objective specifications are the fall time < 3 s and the peak voltage of the ripple < -9 V. The fall time and the peak voltage of the ripple derived from the original design are 4.78 s and -8.81 V, respectively. After optimization, the fall time successfully decrease to 2.65 s, and the peak voltage of the ripple decrease to -9.07 V. Then, in order to reduce the power consumption, we add a novel 3-level clock driving to the optimized ASG driver circuit. The fall time further reduce to 2.35 _s and the peak voltage of the ripple reduce to -9.96 V. Overall, the fall time has about 50 % reduction. Moreover, the fall time of measured data is 2.48 s; the peak voltage of the ripple is -11.3 V. The measured data has a good agreement with the values of simulations, and the ripple of ASG driver circuit also become more smoother. In addition, stress effect would affect the stability and the lifetime of products. The factors of stress effect are temperature, the magnitude of bias voltages and the conducting time. Because of high level voltages, each TFT will suffer from the offset of the threshold voltage. Therefore, we hope the conducting time of TFT become shorter. In Chapter 4, we drive the ASG driver circuit by using three clock signals, and its duty ratio is 33%; in Chapter 5, we design a twelve-stage ASG driver circuit with four clock signals by using optimized method based on the MOEA, and successfully reduce the duty ratio to 25% which decreasing the stress effect. Each stage of the ASG driver circuit has 13 a-Si:H TFTs and 2 capacitors. The objective speci_cations are the rise time < 3.5 s, the fall time < 5.5 s, the amplitude of the ripple < 1.2 V, the total width of TFTs < 12000 m and the clock Ctotal < 25 pf. After optimization, the rise time successfully decrease from 3.63 s to 3.29 s (9% reduction), the fall time decrease from 5.96 s to 5.37 s (10% reduction), the amplitude of the ripple decrease from 1.23 V to 1.15 V (7% reduction), the total width of TFTs decrease from 13550 m to 11635 m (14% reduction), and the clock Ctotal decrease from 25.8 pf to 21.87 pf (15% reduction). In this thesis, Chapter 1 introduces the background, the applications of panel displays, and literature reviews. The process of a-Si:H TFT, the parameter extractor, and operations of the basic ASG driver circuit are shown in Chapter 2. Chapter 3 illustrates the multi-objective evolutionary algorithm as well as the unified optimization framework and give an example to explain the programs and file formation. In Chapter 4, we use the optimized method based on the MOEA to design a six-stage ASG driver circuit. Each stage of the ASG driver circuit has 17 a-Si:H TFTs and 4 capacitors. After that, we apply a novel multi-level clock driving to the optimized ASG driver circuit and fabricate the sample to be measured. In Chapter 5, we further design a twelve-stage ASG driver circuit by using the optimized method based on the MOEA. Each stage of the ASG driver circuit has 13 a-Si:H TFTs and 2 capacitors, and the sample of this ASG driver circuit is fabricating. Chapter 6 will conclude this study and give the future works. Overall, in this thesis, we have successfully designed a six-stage ASG driver circuit by using optimized method based on the MOEA. To improve the power consumption of panel display and characteristics of the ASG driver circuit, we have proposed the 3-level clock driving method. The fall time has about 50% reduction, and it can increase the contrast ratio of panel displays. Ripple become more smoother, and it can increase the stability of panel displays. The most important is we have fabricated the sample of optimized ASG driver circuit with the display manufacturer in Taiwan and the measured data also has a good agreement and feasibility with our researches. Moreover, we added more objectives, and designed a twelve-stage ASG driver circuit by using optimized method based on the MOEA. We have successfully improved all characteristics of the ASG driver circuit at the same time, such as amplitude of the fall time, the total width of TFTs and the clock Ctotal have over 10% reduction, the ripple has 7% reduction and the rise time also has 9% reduction. This study can apply to medium or large panel products with high performance and competitiveness. With the increasing of specification requirements, ASG driver circuit designs are getting more and more complex. Innovation of the optimized method based on the MOEA in this study can be continuously discussed in the future. The designed of the novel clock drivings is also one of key techniques to improve characteristics of ASG driver circuits.

碩士
國立中央大學
網路學習科技研究所
98
Learning to program is difficult to most beginners; this is because learners have to face challenges of learning to form structured solutions to problems and understanding how programs are executed. When learning to program, beginners come across problems like learning rigid syntax and commands that may have seemingly arbitrary or perhaps confusing names. Beginners usually do not know how to begin can cause anxiety and fear towards learning, lowering the learning motivation; therefore, improving the beginners environment of learning to program is indeed important. Hence, this study set up a virtual reality learning environment, called Train B&P. Train B&P is a train simulation game designed in simple visualized way, it allows learners to learn programming through the game-like learning environment. The participants of the study are 117 freshmen from the Department of Information Engineering, attending the "Object-Oriented Programming" course. The purpose of the study is to find out the effects of program learning in a simulation game between students of different ability level. These Students are classified into three different groups –high, medium and low ability level. The study investigates the student’s flow status of different ability level, the changes in learning motivation and differences in learning behavior with the use of the learning system.

碩士
國立臺灣師範大學
資訊教育學系
96
Abstract Based on the principle of simulation game software, this research is to design simulation game for scientific education and compare the effects of simulation game with traditional simulation learning system for the sixth grade in lever principles of scientific education in the elementary school. The participants in this study were 136 sixth graders from four classes of an elementary school in Taipei, Taiwan. The quasi-experimental design with factorial design was employed in the study. The independent variables were two simulation systems, including simulation game system and traditional simulation system.Traditional simulation system was done in 2 classes as control group and the simulation game was done in 2 classes as experimental group. The dependent variables included learning achievements in scientific education, flow experience and scientific attitudes. The purpose of this study was to investigate the effect of different simulation on the sixth graders’ learning achievements, flow experience and scientific attitude. The results showed that (a) the application of simulation game system promoted the learning achievements in scientific education; (b) the application of simulation game system promoted the flow experience; (c) the application of simulation game system had the better scientific attitudes; (d) the application of simulation game had the better system satisfaction.