Academic literature on the topic 'Fully Integrated Voltage Regulators'

Traditional power delivery solutions f or system-on-chip (SoC) applications rely on off-chip voltage regulators. The off-chip power delivery solution is becoming a bottleneck for SoCs, due to 1) coarse voltage domain management, 2) increased cost as well as complexity of the power delivery network, and 3) high I2R loss as supply voltages scale down with the fabrication technology. One promising solution is to integrate the voltage regulators in the SoC. While fully integrated voltage regulators (FIVRs) could resolve these problems, their performance is limited by low efficiency and high chip area overhead, especially if the conversion ratio of the converter is high (≥ 4 to-1). This thesis presents the design and implementation of two fully integrated switched-capacitor (SC) DC-DC voltage regulators. Both regulators are implemented in the SoC along with the microprocessors they deliver power to. I first present a two-stage 4-to-1 SC regulator in a flapping wing micro-robotic bee application. The regulator converts a 3.7V battery voltage down to two lower voltages (~1.8V and ~0.9V) for the rest of the circuits in the SoC. The two-stage topology and the proposed charge recycling technique improve conversion efficiency and provide very fast load regulation to handle the dynamic current fluctuation of the load circuitry. Next, I explore the power delivery architecture at the system level and propose a joint power delivery network that combines SC FIVRs with voltage stacking. Voltage stacking reduces the maximal power that the FIVRs have to provide and “hides” the FIVR conversion loss so that the latter only applies to a portion of the total power consumed by the load. The FIVRs reduce the voltage noise of the stacked voltage domains when the load in the stacked voltage domains consumes a different amount of power. To verify the benefits of this new power delivery system, a fully integrated reconfigurable SC regulator is implemented with 16 Intel microcontroller cores that are stacked in four voltage domains. The SC regulator simultaneously provides power to the four stacked voltage domains (~0.9V) from a single input voltage (~3.6V). The regulator can dynamically change its configuration to optimize its performance according to the current profiles of the stacked load. A hybrid feedback control scheme is implemented to simultaneously regulate the four stacked domains. The proposed power delivery system achieves an average efficiency of 87% and a peak efficiency of 99%. At the end of this thesis, I present my conclusion and discuss the technologies that could further improve FIVR-based power delivery systems in the future.<br>Engineering and Applied Sciences - Engineering Sciences

<p>A novel hybrid regulator topology is proposed to alleviate the weaknesses of existing hybrid topologies. Contrary to the dominant existing practice, a switched-capacitor converter and a resistorless LDO operate in a parallel fashion to supply current and regulate the output voltage. The proposed topology targets a fully integrated regulator without using any inductors and resistors. The primary emphasis is on maximizing power efficiency while maintaining sufficient regulation capability (with ripple voltage less than 10% of the output voltage) and power density. The first implementation of the proposed topology operates in a single frequency mode. Simulation results in 45 nm technology demonstrate a power efficiency of approximately 85% at 100 mA load current with an input and output voltage of, respectively, 1.15 V and 0.5 V. The worst case transient response time is under 20ns when the load current varies from 65 mA to 130 mA. The worst case ripple is 22 mV while achieving a power density of 0.5 W/mm². This single-frequency hybrid voltage regulator is useful (due to its fast and continuous response and high power efficiency) when the output load current is relatively constant at a certain nominal value. However, the performance is degraded when the load current varies significantly beyond the nominal current since the current provided by switched-capacitor converter is constant. The second implementation of the proposed hybrid regulator topology partially alleviates this issue by employing two different frequencies depending on the load current. This design is also implemented in 45 nm technology. It is demonstrated that the power efficiency is maintained within 60% to 80% even though the load current varies by more than 100 mA. The power density remains the same (0.5 W/mm²). The simulation results of the proposed topology are highly competitive with recent work on integrated voltage regulators. </p>

High-performance multi-core processors are fully powered by Fully Integrated Voltage Regulators, which are fully integrated with the microprocessor die and provide power to various domains. The FIVR increases the efficiency of the device while also providing a boost to the available peak power. The FIVR is integrated on the die, and therefore it is also susceptible to faults and aging phenomena. These problems are not tolerable for high reliability applications, such as autonomous self-driving vehicles and in smart factories. The previously developed checker is susceptible to some faults which were not detected. These are called the critical faults and are intolerable. Therefore, two alternate schemes have been developed to detect these faults. In case of failure, the Checker is now able to give an error indication, which can be used to activate recovery procedures. Two solutions have been proposed. The first is a Built-In Self-Test Like scheme that is operated in two modes. The first mode is normal mode where the FIVR Checker operates as normal and detects most faults affecting the FIVR. The second mode is an offline testing mode that detects previously critical faults that are not detected in normal modes. The BIST Scheme was verified with respect to stuck-on transistor, stuck-open transistor and resistive bridging faults and was found to have a high fault coverage. The second scheme is a self-checking checker for the FIVR. This scheme is based on modification of the internal structure of a previously proposed monitor, thus making it completely self-checking. A new Error Indicator is also considered which is totally self-checking. Moreover, the self-checking ability of the scheme was verified with respect to stuck-on transistor, stuck-open transistor and resistive bridging faults, and this scheme was verified to be self-checking for the list of faults considered.

This Thesis Research involves the analysis, simulation and design alternatives for an industrially-relevant voltage regulator. An initial prototype circuit, designed by Texas Instruments Inc., is simulated and analysed in detail. Then an alternative circuit is derived which improves the circuit performance by implementing different compensation techniques and some transistors modifications. The final circuit has excellent phase margin, transient response and load regulation.

Modern microprocessors require low supply voltage (about 1V), but very high current (maximum current is 300A in servers, 100A in desktop PCs and 70A in notebook PCs), and tighter voltage regulation. However, the size of a CPU Voltage Regulator (VR) needs to be reduced. To achieve much higher power density with decent efficiency in VR design is a major challenge. Moreover, the CPU current rating can vary from 40A to 300A for different kinds of computers, and CPU power supply specifications change quickly even for the same type of computers. Since the maximum power rating of one channel converter is limited, the VR channel number may vary over a large range to meet VR specifications. Traditionally, VR design with different channel numbers needs different types of VR controllers. To reduce the developing cost of different control ICs, and to maximize the market share of one design, scalable phase design based on the same type of IC is a new trend in VR design. To achieve higher power density and at the same time to achieve scalable phase design, the concept of Monolithic Voltage Regulator Channel (MVRC) is introduced in this dissertation. MVRC is a power IC with one channel converter's power MOSFETs, drivers and control circuitries monolithically integrated based on lateral device technology and working at high frequency. It can be used alone to supply a POL (Point of Load). And without the need for a separate master controller, multiple MVRC chips can be paralleled together to supply a higher current load such as a CPU. To make MVRC a reality, the key is to develop a fully distributed control scheme and its associated analog IC circuitry, so that it can provide control functions required by microprocessors and the performance must be equal or better than a traditional a centralized VRM controller. These functions includes: multiphase interleaving, Adaptive Voltage Position (AVP) and current sharing. To achieve interleaving, this dissertation introduces a novel distributed interleaving scheme that can easily achieve scalable phase interleaving without channel number limitation. Each channel's interleaving circuitry can be monolithically integrated without any external components. The proposed scheme is verified by a hardware prototype. The key building block is a self-adjusting saw-tooth generator, which can produce accurate saw-tooth waveforms without trimming. The interleaving circuit for each channel has two self-adjusting saw-tooth generators. One behaves as a Phase Lock Loop to produce accurate phase delay, and the other produces carrier signals. To achieve Adaptive Voltage Position and current sharing, a novel distributed control scheme adopting the active droop control for each channel is introduced. Verified by hardware testing and transient simulations, the proposed distributed AVP and current sharing control scheme meets the requirements of Intel's guidelines for today and future's VR design. Monte Carlo simulation and statistics analysis show that the proposed scheme has a better AVP tolerance band than the traditional centralized control if the same current sensing scheme is used, and its current sharing performance is as good as the traditional control. It is critical for the current sensing to achieve a tight AVP regulation window and good current sharing in both the traditional centralized control scheme and the proposed distributed control scheme. Inductor current sensing is widely adopted because of the acceptable accuracy and no extra power loss. However, the Signal-to-Noise Ratio (SNR) of the traditional inductor current sensing scheme may become too small to be acceptable in high frequency VR design where small inductor with small DCR is often adopted. To improve the SNR, a novel current sensing scheme with an accurate V/I converter is proposed. To reduce the complexity of building an accurate V/I converter with traditional Opamps, an accurate monolithic transconductance (Gm) amplifier with a large dynamic range is developed. The proposed Gm amplifier can achieve accurate V/I conversion without trimming. To obtain further verification, above proposed control schemes are monolithically integrated in a dual channel synchronous BUCK controller using TSMC BiCMOS 0.5um process. Testing results show that all the proposed novel analog circuits work as expected. System testing results show good interleaving, current sharing and AVP performance. The silicon size of each channel is 1800×1000um². With proposed current sensing, interleaving, AVP and current sharing, as well as their associated analog IC implementations, the technical barriers to develop a MVRC are overcome. MVRC has the potential to become a generic power IC solution for today and future POL and CPU power management. The proposed distributed interleaving, AVP and current sharing schemes can also be used in any cellular converter system. The proposed analog building blocks like the self-adjusting saw-tooth generator and the accurate transconductance amplifier can be used as basic building blocks in any DC-DC controller.<br>Ph. D.

In this present world, there is a huge requirement of portable devices for that the analysis of low-dropout or LDO regulators have been on high priority. So, for every respective device, there is a power budget that acts as the main constraint to design an LDO. The LDO design aims to suppress the noise and supply noise-free or low noise output. This thesis paper illustrates several designs of output capacitor-less LDO architecture to enhance Power Supply Rejection (PSR) and optimization of the ideas from different literature to achieve the low quiescent current, stability with fast transient response while the input voltage is low over a wide range of load current. Differ-ent types of transistor schematic designs under definite specifications of the LDOs, which are mostly integrated by major components like Error Amplifier (EA) and pass transistor, feedback resistors, and relatively small output capacitor have mostly considered for the designs. However, some buffer attenuation techniques which can improve the PSR have also been shown with a proper diagram. The design of LDOwith the components and how to design the pass device and their trade off’s have been has been discussed. Different techniques of PSR enhancement among which some of the techniques have been implemented have been illustrated with respective diagrams. A study of executed techniques under the specifications with comparative results has been shown with their trade-off with the other architecture. The contribution is an LDO that has been simulated in Cadence specter and designed in CMOS FinFET process node atVdd= 0.95 V with a load current of 50 mA -75 mA and an output voltage of 0.75 V with a small output capacitor of 200 pF, a PSR of−25 dB at 100 MHz has been achieved whereas the current consumption at the load is 245μA, while meeting the targeted stability analysis of gain margin and phase margin of 47 dB and 63◦respectively. A small voltage droop of 36. 6mV for rising edge and−15.99 mV for falling edge over a 100μA to 75 mA step-change in10 ns has been observed.<br>I dagens värld finns det stora behov av bärbara enheter och krav på analys avregulatorer (LDO). För varje typ av enhet finns det en energibudget som fungerarsom huvudsaklig begränsning för att utforma en LDO. LDO-konstruktion syftar tillatt leverera brusfri eller lågbrusig utspänning. Detta examensarbete visar på flerakonstruktioner av utgångskondensatorfria LDO-arkitekturer för att förbättra PowerSupply Rejection (PSR). Optimering av idéer från olika litteraturkällor görs för attuppnå låg viloström och stabilitet med snabb respons med låg ingångsspänning överett brett intervall av lastström. Olika typer av konstruktioner schemanivå för precisa LDO-specifikationer, mestadelsintegrerade med de viktigaste komponenter såsom felförstärkare (Error Amplifier,EA) och passtransistor, återkopplingsmotstånd och relativt små utgångskonden-satorer, har studerats. Buffertdämpningstekniker som kan förbättra PSR har ocksåinkluderats. Konstruktion av LDO:er på komponentnivå och man utformar pass-enheten och dess kompromisser diskuteras också. Implementering av några olikatekniker för PSR-förbättring illustreras med schema. En studie av utförda teknikerenligt specifikationerna med jämförande resultat ingår också. Resultat är en LDO som har simulerats i Cadence Spectre i en CMOS FinFETprocess med en matningsspänning på 0,95 V, en belastningsström på 50 mA - 75mA, en utspänning på 0,75 V och med en liten utgångskondensator på 200 pF. PSRpå−25 dB vid 100 MHz har uppnåtts medan strömförbrukningen vid belastningenär 245μA, samtidigt som kraven på marginal för förstärkning på 47 dB och fas 63°har uppnåtts.  Ett litet spänningsfall på 36,6 mV för stigande signal och−15,99 mV för fallande signal under en förändring från 100 μA till 75 mA på 10 ns harobserverats.<br><p>ISY </p>

Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2016.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 93-96).<br>Wireless sensor networks used in various monitoring and sensing applications rely on energy harvesting for battery-less operation, as it minimizes the need for human intervention, and offers long term monitoring solutions. Typical energy harvesters use high efficiency boost converters, which are able to step-up voltages from as low as 10 mV. However, they often need > 200 mV in order to start up initially. Current solutions for achieving a low voltage start up require the use of bulky off-chip transformers, leading to undesired area overhead. This research work presents proof-of-concept for a fully integrated start-up system, which can cold-start from < 50 mV using on-chip magnetics, and also be used as an energy harvesting charger for ultra low power applications. The use of lossy on-chip transformers in a Meissner Oscillator compared to high-quality off-chip transformers pose new design and optimization challenges. Hence, we have derived intuitive analytical expressions that are well-suited for use with the on-chip magnetics, and used them to co-optimize the oscillator components. An optimized depletion mode MOS transistor was fabricated and tested with an off-chip transformer, to exhibit oscillations from <3 mV DC input voltage. An optimized on-chip transformer, 36x smaller in area than the off-chip transformers, is currently awaiting layout and fabrication. A switched capacitor DC-DC circuit has also been designed, which can rectify and boost up the oscillator's output voltage to 1.2 V, to have a complete start-up system for energy harvesting.<br>by Preetinder Garcha.<br>S.M.

This thesis presents the first fully integrated array of high-voltage (HV) digital-to-analog converters (DACs). It was designed in DALSA Semiconductor's 0.8mum CMOS/DMOS HV process technology. The 6-bit 300V DACs are based on a current-steering, thermometer coded architecture. Two designs adapted to the HV technology are proposed for the current-to-high-voltage conversion as traditional output resistor or op-amp solutions are not optimum for the HV process: one uses a high-compliance current mirror, while the other uses a simple current mirror. The DACs show a DNL of 0.16LSB and 1LSB, respectively, while the INL profile is 0.16LSB and 13LSBs for the first and second designs. The array is suited for applications requiring a set of digitally-controlled high-voltage signals.