Dissertations / Theses on the topic 'Front-end IC'
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1
Tsui, Hau Yiu. "A 5 GHz integrated low-power CMOS RF front-end IC design /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20TSUI.
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Durand, Cédric. "Développement de résonateurs électromécaniques en technologie Silicon On Nothing, à détection capacitive et amplifiée par transistor MOS, en vue d'une co-intégration permettant d'adresser une application de référence de temps." Phd thesis, Université des Sciences et Technologie de Lille - Lille I, 2009. http://tel.archives-ouvertes.fr/tel-00375804.
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Les résonateurs électromécaniques (MEMS), de part leurs bonnes performances, leur petite taille, ou encore leurs possibilités d'intégration au plus proche des transistors, présentent un fort potentiel pour le remplacement des quartz dans les applications de référence de temps.Dans ce contexte, nous proposons de développer des résonateurs électromécaniques en vue d'une intégration « front-end », pour la réalisation d'oscillateurs intégrés. Ainsi, nous avons fabriqué des démonstrateurs à partir des briques de base de la technologie CMOS Silicon On Nothing, en phase de R&D à STMicroelectronics. Du fait de la petite taille des composants, nous avons utilisé un transistor à grille résonante pour amplifier la détection de la résonance. Ainsi, des développements technologiques spécifiques ont permis de fabriquer les résonateurs et leur transistor de détection. La conception des dispositifs a été réalisée à partir du développement d'un modèle électromécanique des résonateurs. Ce modèle est compatible avec les outils de design et peut alors aider à la conception de l'oscillateur MEMS. Nous avons ensuite montré le bon fonctionnement des résonateurs fabriqués, ainsi que celui de l'amplification induite par la
détection MOS. Cette démonstration constitue une première, prouvant la fonctionnalité de la détection MOS pour un composant de petite taille, vibrant dans le plan du substrat. Enfin, nous avons validé le modèle électromécanique à partir d'autres modèles ainsi qu'avec les mesures des composants fabriqués.
En termes de perspectives, le recours à diverses améliorations permettrait d'obtenir des dispositifs
compatibles avec la réalisation d'un oscillateur performant et co-intégré.
3
Huang, Yu-Ting, and 黃瑜婷. "A multi-function biomedical analog front end IC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/93407066082979072037.
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碩士國立臺灣大學
電機工程學研究所
97
With the advancement and maturation of semiconductor technology, the digital and analog circuit has been integrated on the same chip. In recent years, because of the demand on biomedicine, CMOS bio-sensors have already realized successfully with CMOS technique, achieving miniature, low noise, low power and low cost biomedical systems. In addition, analog front-end circuit with the function of signal arrangement is a critical component in the biomedical system. In this thesis, the main three pieces of circuit are instrumentation amplifier (IA), second-order LPF and a programmable gain amplifier (PGA). They are fabricated in TSMC 0.35μm CMOS 2P4M process. The first stage of the system is based on IA which had accomplished by our laboratory and through the digital control switch and feedback loop to carry out the circuit system with the function of adjusting different intensity signal. Then, using a two-order LPF ( Sallen-key circuit ) to suppress the spikes from the clock feedthrough and charge injection caused by nonideality of the chopper switches. Finally, the signal is further amplified by programmable gain amplifier in the last stage. In order to let the whole system to deal with a wide range of biomedical signals and attain appropriate adjustment according to different kind of small signal sources, the design relies on a switch on/off devise to achieve these multi-functions. The die area is 1.8mm x 1.35mm and the power consumption is 944.2uW from a 3V voltage supply.
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Lin, Chin-Chun, and 林慶鈞. "A CMOS FM Broadcast Receiver Front-End IC." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/48519119206244712909.
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碩士國立成功大學
電機工程學系碩博士班
92
This thesis describes a single-chip CMOS receiver for FM Stereo Radio system working in the 88~108-MHz range. Low-power single-cell fully-featured radio receivers, with a minimum of external components are hard to find. For a monolithic implementation, the use of the Low-IF architecture alleviates the necessity of off-chip components, used for image-reject passive filtering. At the same time, DC-offset and self-mixing problems arising from direction-conversion architecture are avoided. This CMOS FM receiver frond-end is a quadrature low-IF receiver consisting of a differential-ended low noise amplifier (LNA) connected to Hartley image-rejection mixer, which comprises Inphase/Quadrature interference mixers, second-order filters, and phase shifter, followed by tenth-order switched-capacitor bandpass filter. The frond-end converts the RF signal to differential I and Q signals, centered at 225-kHz. Degrading of image interference characteristic can be avoided by I/Q IF mixers and phase shift network. The receiver fabricated in a 0.18μm 1P6M mixed-signal CMOS mixed-mode process, achieve peak SNDR of 44.3 dB, peak SNR of 45.3 dB and dynamic range of 70dB with signal frequency of 88~108 MHz and signal bandwidth of 200 kHz. The combination draws 63 mW from a 1.8-V supply. The total chip area including bonding pads is 0.93mm�e1mm where the active area is 0.57mm�e0.62mm.
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"A CMOS Analog Front-End IC for Gas Sensors." Doctoral diss., 2011. http://hdl.handle.net/2286/R.I.8911.
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abstract: This thesis presents a gas sensor readout IC for amperometric and conductometric electrochemical sensors. The Analog Front-End (AFE) readout circuit enables tracking long term exposure to hazardous gas fumes in diesel and gasoline equipments, which may be correlated to diseases. Thus, the detection and discrimination of gases using microelectronic gas sensor system is required. This thesis describes the research, development, implementation and test of a small and portable based prototype platform for chemical gas sensors to enable a low-power and low noise gas detection system. The AFE reads out the outputs of eight conductometric sensor array and eight amperometric sensor arrays. The IC consists of a low noise potentiostat, and associated 9bit current-steering DAC for sensor stimulus, followed by the first order nested chopped £U£G ADC. The conductometric sensor uses a current driven approach for extracting conductance of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage to the sensors and an I/V converter to measure current out of the sensor. The core area for the AFE is 2.65x0.95 mm2. The proposed system achieves 91 dB SNR at 1.32 mW quiescent power consumption per channel. With digital offset storage and nested chopping, the readout chain achieves 500 fÝV input referred offset.Dissertation/Thesis
Ph.D. Electrical Engineering 2011
6
余介恩. "A CMOS Mixed-Signal Front-End IC for Portable." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/84569107517998067224.
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碩士國立交通大學
電機與控制工程系所
97
Due to properties of low-amplitude and non-stationary, most of biomedical signals are easily influenced by examined persons, measured environment, and electronic devices. A novel analog circuit design is proposed in this thesis, which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the multi-channel mixed-signal front-end integrated circuit (MSFEIC) is designed. This circuit is realized into a single chip without any external component. It can not only reduce the number of outer components, but also enhance a better signal-to-noise ratio enormously. In addition, to select system gain and bandwidth corresponding to different amplitude and frequency of biomedical signals, the controllable digital interface is also designed and integrated into MSFEIC. In this thesis, MSFEIC design is composed of four chopper-stabilized instrumentation amplifiers (CHS-IA), a switched-capacitor variable gain amplifier (SC-VGA), a switched-capacitor low-pass filter (SC-LPF), a non-overlapping clock generator, and a cascaded 2-1-1 tri-level sigma-delta analog-to-digital converter (MASH 2-1-1 tri-level ΣΔ ADC). These circuits have been integrated into a single chip of the total area of 1.9198×1.9198mm2 by using TSMC 0.18μm CMOS Mixed-Signal RF General purpose MiM Al 1P6M 1.8&3.3V process. For the simulation results, the proposed chip can achieve 90 dB of SNR, 16-bit resolution at 1024Hz. The total power consumption is about 998�巰 under 1.8V supply.
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Kao, Min-Sheng, and 高旻聖. "CMOS Analog Front-end Transceiver IC for Wireline Communications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68305604504950596777.
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博士國立清華大學
通訊工程研究所
99
This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The proposed 20-Gb/s laser/modulator driver is fabricated in 0.13-µm mixed-signal 1.2/2.5V 1P8M CMOS process. This work consists of a shunt-series inductor peaking pre-driver stage and a pre-emphasis output driver stage with source de-generation configuration including inductive local feedback network to enhance the operation bandwidth. The data rate is measured up to 20-Gb/s with 3.5VPP S.E. output amplitude in driving 50-Ω output load when the input amplitude is less than 0.15VPP and the rise/fall time of output waveform is less than 22-ps. The total power consumption is 900-mW with 1.2/4.0V dual supply and the chip die size is 900×800-µm2. The proposed 10-Gb/s current mode logic (CML) limiting amplifier is fabricated in 0.18-µm 1P6M CMOS process. This work consists of input equalizer, CML output buffer and gain stages with active-load inductive peaking, duty cycle correction (DCC) and gain control features. The circuit techniques include active load inductive peaking, source de-generation peaking and active feedback with current buffer in Cherry-Hooper topology to enhance operation bandwidth. The proposed design provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain and 8-mVpp input sensitivity. The total power consumption is 85-mW with 1.8V supply and the chip die size is 700×400-µm2.
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Huang, Yi shan, and 黃意善. "Design of IEEE802.11a CMOS 5.8 GHz Receiver Front-End IC." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/vsf3r3.
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碩士國立臺北科技大學
電機工程系研究所
98
The thesis is divided into two major parts. One is to designed a high linearity direct conversion RF front-end for 5.8 GHz IEEE802.11/a WIMAX fabricated TSMC 0.18μm 1P6M standard CMOS process.The proposed RF front-end consists a the folded mixer, a differential current reused low-noise amplifier (LNA) and a matching network. The folded mixer is implemented with the PMOS device in the switching stage of mixer and a resonating inductor for to that a low flicker noise. The simulation results show that the power consumption, conversion gain, third-order intercept point (IIP3),and 1-dB compression point (P1dB) are 15.2mW, 21.8 dB, -5.2dBm, -18 dBm, respectively. This indicates that the proposed front-end works with good linearity.By using PMOS device and the folded technique, low flicker noise of 6.4dB is achieved, which is suitable for using as a direct conversion receiver for narrow bandwidth. The chip size is about 1.22×1.25mm2.The other one is to develop a 5.9 GHz image rejection CMOS low noise amplifier using current-reused for superheterodyne architecture. The image-rejection (IR) fliter usually is an external circuit with expensive and large-size components, which is not suit for integration.The destination of this study is to design a image rejection CMOS low noise amplifier with an LC tank to achieve an image rejection function and to have a low power dissipation. The simulation results show that the power consumption, gain, S11, NF, IIP3, P1dB are 5.07 mW, 18 dB at frequency of 5.9 GHz, whereas the gain of -11.9 dB at 7.3GHz, -15dB, 2.6 dB, -17 dBm, and -25 dBm, respectivey.
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Lee, Chih-Wei, and 李誌偉. "Front-End Readout IC for Portable Blood Pressure Sensing System." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/63034757293414152678.
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碩士國立交通大學
電控工程研究所
102
Individualized medical health care is the trend of medical development, specially in the wearable and non-invasive physiological sensing applications. A novel readout circuit for blood pressure sensing system is proposed in this thesis. It is divided into two parts. The first part is conventional structure, including a sensing circuit, an amplification circuit and an analog-to-digital converter (ADC) .The other part is innovative structure which consists of a sensing circuit, an amplification, a peak-sensing circuit and a counter. The designed circuit is accomplished by Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm 1P6M 1.8V mixed‐signal CMOS process. The proposed chips with the die area of 1.35×1.13mm2 and 1.37×1.37mm2 are fabricated by National Applied Study Laboratories National Chip Implementation Center (NARL NCIC). The front-end readout IC is simulated and experimented. The result shows that a sensing system is feasible for portable medical devices.
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Chen, Yi-Chia, and 陳誼家. "Microwatt Dual-Mode Front-End IC for Electrochemical Sensing Applications." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/x4y8zu.
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碩士國立交通大學
電機工程學系
107
With the advanced CMOS process, single-chip integration technology has made electrochemical sensing systems more miniaturized, making them suitable for fast and cost-effective medical screening and environmental monitoring systems. However, low power consumption and low noise are still the biggest challenges of current electrochemical sensing systems. In order to cope with future clinical analysis, the integrated IC must achieve low-power, small-volume, fast and multi-information sensing mechanisms for accurate and convenient electrochemical sensing. In this thesis, a microwatt electrochemical sensing chip with an integrated current-reducer pattern generator and a current-mirror based low-noise chopper-stabilization potentiostat circuit is presented. The pattern generator, utilizing the current reducer technique, creates a sub-Hz ramp signal for the cyclic voltammetry (CV) measurement without large-size passive components. The proposed design adopts the chopper-stabilization and low-noise biasing technique for the potentiostat and a counter-based time-to-digital converter to reduce the amplitude noise effects and to convert the sensing current signal to digital codes for further data processing. The design is fabricated using a 0.18-μm CMOS process and achieves a 41pA current resolution in the current range of ± 5μA while maintaining the R2 linearity of 0.998. The system consumes 16μW from a 1.2V supply when a maximum 5μA sensing current is detected. The power efficiency of the readout interface is 0.31, and the sensing current dynamic range is 108dB. The design is fully integrated into a single chip and is successfully tested in the dual-mode (CA/CV) measurements with commercial gold electrodes in a potassium ferricyanide solution and nanowire sensor in the dopamine solution in sub-millimolar and femto-molar concentrations, respectively.
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Chien, Ping-Chieh, and 錢平傑. "A Front-end Analog Circuit Design for Magnetic Interpolation Encoder IC." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/66vbd7.
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碩士國立交通大學
電控工程研究所
104
The main measurement and positioning apparatus, according to the sensor type of encoder, besides the lacer interferometer that is more high precision displacement measurement system, can be classified into two types, the optical and magnetic encoder. The encoder always employs sensor passing through periodic and equal distance grating and then generates periodic quadrature scaling signals for displacement measurement. The phase is relative to the movement. However, its accuracy is still restricted by properties and mechanical assembly. To improve encoder accuracy or resolution, electronic interpolation technique had been developed. It improves encoder accuracy by subdivision the phase of quadrature scaling signals. According to the trends, this chip with conditioning circuit for magnetic sensor and a 1000-fold interpolation circuit. In addition, the programmable gain amplifier to adjust the sensor voltage for amplitude fixed by decoder. Use the analog-to-digital converter to digitize input quadrature scaling signals and then achieve interpolation via different algorithm. This type can achieve high-fold interpolation even ~thousands. This interpolation method satisfy the requirement of modern semiconductor and precision industry. The designed circuit has been successfully fabricated by using TSMC 0.35-μm CMOS process, where the active area is 6.61 mm2. The power voltage is about 3V. The clock is about 2.4 MHZ. The measured current consumption of chip is about 45.36mA
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Chiang, Shih-Yuan, and 江旭原. "Multi-leads ECG analog front-end IC design and system integration." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/21526276261512252566.
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碩士中華大學
電機工程學系(所)
97
This thesis includes two major parts. One is multi-leads ECG measurement system constructed by OPAs, MCU, and other discrete circuit devices. Another is multi-leads ECG analog front-end IC design. A multi-leads ECG measurement system consists of ECG analog front-end circuits, microcontroller and other related circuits. The proposed multi-leads ECG measurement system can measure three leads ECG signal simultaneously. The ECG data are delivered to a personal computer by RS-232 directly or by USB with a bridge IC. These data will be stored, analyzed and transmitted by a personal computer. The proposition can provide accurate ECG information for personal health care. Also, it is suitable for the applications of distance medical treatment. The proposed multi-leads ECG analog front-end IC design is based on TSMC 0.35um CMOS process. At present, the circuit design, pre-simulation, layout and post-simulation of the proposed three-lead ECG analog front-end IC are conquest. The chip area is about 1100um 2500um. In addition, the proposed design can be extended to more leads easily. A layout of the six-lead ECG analog front-end IC is complete for area-cost evaluation in advance. The chip area is about 2500um 2500um.
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Chang, Kuen-Shan, and 張坤山. "The Study of CMOS RF Front-end IC for Wireless Applications." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/11724308452384753410.
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碩士國立清華大學
電子工程研究所
88
The recent development of wireless communication systems such as cellular phones have increased the emphasis on low cost, high performance, low consumption, and simplicity. But the traditional wireless systems are built from mixture of IC technologies: GaAs or Silicon bipolar for RF front-end, CMOS for the baseband. This approach increases system complexity, cost, and power consumption. The recent advent of CMOS technology and the continued improvement in CMOS device speed have prompted much to the possibility of building analogy sections with radio frequency circuits and baseband digital circuits in the same IC. The techniques offer a feasible and attractive solution to the approaches. This thesis presents the study of CMOS RF front-end circuits composing of low noise amplifier, downconversion mixer and RF oscillator for wireless applications. In the design of low-noise amplifier, this circuit consists of all-nMOSFET gain stage with cascode connection. The gain is about 29dB, the input 1dB compression point is -20dBm, and the noise figure is about 2.1dB. Furthermore, the downconversion mixer is implemented by using the Gilbert Cell. The designed mixer has conversion gain of 6dB, the input 1dB compression point is 0dBm, and the input-referred third-order intercept point (IIP3) is about 9dBm. Finally, the RF oscillator belongs to a LC-oscillator topology. When the frequency of oscillation is at 2.6GHz, the phase noise is about -106dBc/Hz at 100kHz from the carrier. These RF building blocks are fabricated with the standard TSMC 0.35um CMOS technology. The test chip then is measured, and it demonstrates that these RF building blocks illustrate an attractive all-CMOS approach. All of the design, simulation, and experiment are presented in this thesis.
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Chen, Hong-Yang, and 陳紘揚. "A Front-end Analog Circuit Design for Optical Interpolation Encoder IC." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/25249352101237823051.
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楊澤勝. "0.5-V Low Voltage Analog Front-End IC for Biomedical Signal Recording." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/40853827871081346457.
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碩士國立交通大學
電控工程研究所
100
In this thesis, a 0.5-V low voltage programmable CMOS analog front-end IC for biomedical signal acquisition is presented. The design deals with Electrocardiogram (ECG), Electromyogram (EMG), and Electroencephalogram (EEG) signals, while reject DEO (Differential Electrode Offset), common-mode disturbance and solve flicker noise by differential circuits and chopper-stabilized technique with an AC feedback circuit. The analog front-end circuits achieve 36 input-referred noise floor and the noise-efficient factor (NEF) of 3.26. The programmable gain amplifier (PGA) sets voltage gain with digital interface, which could be integrated with DSP easily. The total power consumption is 4.21μW (biasing circuits are excluded). The chip is realized in UMC 1P9M 90nm CMOS process. The active die area is 0.75mm X 0.66mm.
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Pin, Hsu Yu. "A CMOS Low-noise Analog Front-End IC Design for Biomedical Applications." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2707200714460000.
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Pin, Hsu Yu, and 許彧斌. "A CMOS Low-noise Analog Front-End IC Design for Biomedical Applications." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/23772290213259438168.
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碩士臺灣大學
電子工程學研究所
95
With the dramatic development of semiconductor technology in recent years, CMOS bio-sensors have been integrated with CMOS circuits, which make realization of CMOS biomedical SoC possible, leading to miniature and low cost biomedical systems. In addition, analog front-end with the function of signal arrangement is a critical component in the biomedical system. In this thesis, an instrumentation amplifier (IA), a new analog front-end (AFE) IC, and an automatic–gain control amplifier (AGC) based on the TSMC 0.35μm technology are proposed to realize high performance biomedical ICs. At first, through the use of chopper technique in the differential difference amplifier, the proposed IA attains a low offset of 2.5μV, a low input referred noise of 1nV/√HZ, a high gain of 59dB with 40KHZ bandwidth under the 1.55MHZ chopping while drawing 641μW from 3-V voltage supply. The die area is 0.96x0.94mm2. Furthermore, a brand new biomedical analog front-end is presented, and meets high performance using only an IA and a LPF. This AFE circuit not only attains high programmable gains of 58dB-80dB, a low offset of 31μV, a low input referred noise of 70 nV/√HZ, and high CMRR as well as PSRR but also provides rail-to-rail input common-mode range, high driving ability, and rail-to-rail output signal swing. The die area is 2.44 mm2 and the power consumption is 675μW from 3-V voltage supply. Finally, a novel CMOS feed-forward automatic-gain control (FFAGC) amplifier is presented. The proposed amplifier is intended to amplify various kinds of biomedical signals with a wide dynamic range characteristic. The feed-forward automatic-gain control (FFAGC) technique is adopted to provide appropriate gain settings. Furthermore, a class-AB output stage realizes large driving ability for an external ADC. The experimental results showed that variable gains of 0 dB, 6 dB, 14 dB, and 20 dB with a bandwidth of 55 kHz, input referred noise of 200nV/√HZ at 500 Hz, rail-to-rail input common-mode range, and rail-to-rail output dynamic range can be achieved while the output loading capacitor is 330 nF. The power consumption is 819 μW with 3 V of supply voltage.
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Kao, Shuo-Ting, and 高碩廷. "A 0.8-V Low Power Analog Front-End IC for Biomedical Signal Recording." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/62960893918059996314.
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碩士國立交通大學
電機與控制工程系所
97
For medical purposes, there is a growing demand for portable bio-potentials signals systems. We hope that patients can wear the small-size and light-weight devices for long-term monitoring. A 0.8-V low power programmable CMOS analog front-end IC for biomedical signal acquisition is presented. Our design deal with Electrocardiogram (ECG), Electromyogram (EMG), and Electroencephalogram (EEG) signals, while reject DEO (Differential Electrode Offset), common-mode disturbance, and solve flicker noise by chopper-stabilized technique with an AC feedback circuit. The instrumentation amplifier achieves 57 nV/sqHz input-referred noise floor and the noise-efficient factor (NEF) of 4.7. The programmable gain amplifier (PGA) sets voltage gain and bandwidth via digital interface, which could be integrated with DSP easily. Considering that the amplifier provides 70dB dynamic range (DR), a 11-b low-voltage low-power successive approximation register analog-to-digital converter (SAR ADC) is integrated. The SAR ADC circuit achieves Figure of Merit (FOM) of 0.09 pJ/Conv.step, a signal-to-noise-and-distortion ratio (SNDR) of 63dB at sampling rate of 2.67KS/s and power consumptions of 0.31μW. The supply voltage range is from 0.4V to 0.8V. The power consumption of the front-end amplifiers is 1.84μW. The total power consumption is 3.9μW (output buffer and biasing circuits are excluded). The chip is realized in TSMC 1P6M 0.18μm CMOS process. The active die area is 1.12mmX0.36mm.
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Chen, Yung-Chih, and 陳勇志. "Low Voltage High Output Swing Analog Front-End IC for EEG ECG Recording." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/2ue8e3.
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碩士國立交通大學
電機工程學系
102
This thesis presents a 1V low voltage analog front-end IC for biomedical signal acquisition. The front-end amplifier deals with Electrocardiogram (ECG) and Electroencephalogram (EEG) and rejects noise by differential and chopper-stabilized techniques with an AC feedback to reject low frequency noise. This thesis presents a novel amplitude extender which is an interface between the front-end amplifier and the successive approximation Analog-to Digital Converter (SAR ADC). Finally, A SAR ADC converts biomedical signal into digital signal. The power consumption of front-end amplifier is 1.83μW. The total power consumption is 6.92μW, biasing circuit excluded. The chip is realized in TSMC 1P6M 0.18μm CMOS process. The active die area is 1.51mm X 1.51mm.
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Ou, Zong-Cheng, and 歐宗政. "Portable Multi-Lead ECG Recorder and Low-Power Analog Front-End IC Design." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/66146355288561617022.
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碩士中華大學
電機工程學系(所)
98
Abstract This thesis contains two major parts. One is the portable multi-lead ECG recorder. It can be applied to telemedicine, healthcare at home, and course record of disease. Satisfy the demand for modern personal health management. Another is multi-lead ECG analog front-end IC design and pre-simulation. In the future, we may assemble a multi-lead ECG measurement system on a chip with the multi-lead ECG analog front-end circuit, analog to digital converter, and an embedded processor core. The proposed portable multi-lead ECG recorder can process three leads ECG signal simultaneously. It is a low-cost and low-power solution. For the ECG analog front-end circuit, we base on operation amplifiers to construct instrument amplifiers, band-pass filters, post-amplifiers, and offset circuits. For the microcontroller, we use Microchip PIC24FJ128GB106 that embed multi-channel analog to digital converter, serial peripheral interfaces, and a USB interface. When the device is acting alone, ECG data store to a memory card. When the device connects to the personal computer by USB, real-time ECG waveforms can be shown on the screen. Besides, the ECG data that have been stored in memory card can be transmitted and displayed by the personal computer. The planned multi-lead ECG analog front-end IC is based on TSMC 2P4M 0.35um CMOS process. At present, the circuit design and pre-simulation is completed. Next, we may construct a multi-lead ECG measurement system on a chip with this multi-lead ECG analog front-end circuit, a multi-channel analog to digital converter and an embedded processor core. In the future, the proposed portable multi-lead ECG recorder will involve abnormal detecting capability, and contain wireless communications. It can be applied to the prevention and treatment of the heart related disease, for personal health management and healthcare at home. Keyword: Electrocardiogram (ECG), Portable Multi-Lead ECG Recorder, Memory Card, Personal Health Care, Distance Medical Treatment.
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Liou, Zhou-Lun, and 劉周倫. "0.5-V Low Voltage Adjustable bandwidth Analog Front-End IC for Biomedical Signal Recording." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/64860473072063696859.
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碩士國立交通大學
電機工程學系
105
This thesis presents a 0.5V low voltage analog front-end circuit, mainly used in EEG, ECG and EMG measurements. The front-end amplifier rejects noise by chopper stabilization amplifier and AC feedback technology. Simultaneously, the front-end amplifier has an adjustable bandwidth function, which is able to avoid unnecessary power waste by adjusting the system bandwidth when measuring the different frequency signals. Finally, a SAR ADC converts biomedical signal into digital signal. The total power dissipation of the system at high bandwidth mode is 44.84μW, as well as low bandwidth mode is 3.84μW. The chip is realized in UMC 1P6M 0.18µm CMOS process. The active die area is 1.165*1.565mm^2.
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Jyh-Ting, Lai. "New Front-end DSP Algorithms and VLSI Architectures for Cost-efficient Communication Receiver IC Designs." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-0803200701513600.
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Lai, Jyh-Ting, and 賴致廷. "New Front-end DSP Algorithms and VLSI Architectures for Cost-efficient Communication Receiver IC Designs." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/32825166060157395155.
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博士國立臺灣大學
電子工程學研究所
95
The mixed-signal design is a widely employed approach in communication IC design because it can benefit low hardware complexity and less chip-to-chip interfaces. The difficulties of mixed-signal design are often the interface components or signals between analog and digital circuits. These are many digital processing technologies to handle the interface signaling or controlling the analog components. We summarize these kinds of design/technology as the “Front-end Digital Signal Process” (Front-end DSP). In the thesis, we will define and discuss the designs of the Front-end DSP in both wireline and wireless communication systems. We firstly analyze the difficulties and issues of Front-end DSP for wireline and wireless applications. For wireline communication, we study the automatic gain control (AGC) and the equalizer in the Front-end DSP. Traditional approaches of AGC involve estimating the average power or the peak amplitude over an extended period, which results in high hardware complexity and a time-consuming evaluation. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference (ISI). In this thesis, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the digital control unit (DCU) circuitry comprises only one-tenth of the area of a traditional AGC and the output power of the variable-gain amplifier can reach the optimal peak-to-average power ratio under different ISI environments. In addition, we provide a closed-form analysis of the convergence of the scheme, which shows that the total convergence time of Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon-proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-μm cell libraries. Experiments have revealed that the bit error rate is much better than the 802.3u specification, and that the scheme passes the stringent Killer Pattern testing of the University of New Hampshire InterOperability Laboratory. For wireless communication system, we study the automatic gain control (AGC) and the paceket detector (PD) of the Front-end DSP in Multiband orthogonal frequency-division multiplexing (MB-OFDM) system. The MB-OFDM systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate the PD and time-frequency code synchronization, in terms of the requirement for fast synchronization for the frequency hopping, the extremely low receiver sensitivity, and the high hardware complexity. In this part, we systematically analyze the differences between MB-OFDM and conventional OFDM systems, and then propose a band tracking PD (BT-PD) that can cope with a worse-case multipath channel SNR of –8.4 dB with a packet detection error rate of less than 10–5. We also propose several low-cost design schemes for the BT-PD, such as Walsh-Hadamard decomposition, buffered summation, and sign-bit-remaining methods. The estimated gate count of the resulting implemented BT-PD is less than half that of existing solutions. In summary, we study the key components in Front-end DSP of both wireline and wireless communication systems. These components are very crucial but seldom discussed in previous researches. Our systematic approaches of the Front-end DSP can achieve the goals of PAPR optimization, low hardware complexity and better performance in mixed-signal baseband IC design.
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Huang, Chun-Chieh, and 黃俊傑. "BW/Gain Tunable Low Noise Front-End IC Design for Portable Bio-Signal Acquisition System." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/23704798787008028502.
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碩士國立交通大學
電機與控制工程系所
95
Due to low-amplitude and non-stationary properties, most of biomedical signals are easy to be influenced by examined persons, measured environment, and electronic devices. The objective of this thesis is to propose a novel analog circuit design, which is suitable for various biomedical signal acquisitions. In addition to the consideration of low power and low noise, the analog front-end integrated circuit (AFEIC) is presented with design of high common-mode rejection ratio (CMRR) and high power supply ripple rejection ratio (PSRR). This circuit was realized into a single chip without any external component. It can not only reduce the number of outer components, but also greatly enhance a better signal-to-noise ratio. In addition, to select system gain and bandwidth corresponding to different amplitude and frequency of biomedical signals, the digital controllable interface was also designed and integrated into AFEIC. In this thesis, AFEIC design includes one current-balancing instrumentation amplifier (CBIA), one switching capacitance filter (SCF), one non-overlapping clock generator, and one programmable gain amplifier (PGA). These circuits have been integrated into a single chip of the total area of 0.907�e1.129mm2 by using TSMC 0.35�慆 CMOS 2P4M standard process. For the simulation results, the proposed chip can achieve 155 dB of CMRR, 131 dB of PSRR+, and 127 dB of PSRR- at 50 Hz. The power consumption is about 142.4 �巰 under �b1.5V supply.
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Lin, Chih-Yang, and 林志陽. "A Study of GPS RF Front End IC COTS Component Application in Space Radiation Environment." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/32941974642240054973.
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碩士國立臺灣科技大學
機械工程系
100
Today, the growing popularity of global positioning system (GPS) application has become more and more attractive topic for both scientific and navigation experiment onboard a small satellite project. Due to space qualified GPS receiver is always beyond economic budget constrain. Therefore, how to utilize the current stock of commercial grade components (Commercial-Off-The-Shelf, COTS) to going through a series of space level of the environmental testing and screening procedure(s), is considered a practical approach under a reasonable cost. Especially space ionizing radiation environment is the most different between normal ambient application case. Therefore, the Total Ionizing Dose(TID) will be conducted and analyzed to evaluate the space application potential or capability of general commercial GPS component. For the above reasons, this study will understand the space environment conditions and associated effect on semi-conduct electronic component first, then reference the MIL-STD-883G, Method 1019.4, to conduct a different GPS Radio Frequency Front End component under different level of Total Ionizing Dose(TID) exposure with different shield effect tests, in order to verify its performance、reliability and survival in a radiation environment condition.
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Reja, Md Mahbub. "Design of Active CMOS Multiband Ultra-Wideband Receiver Front-End." Phd thesis, 2011. http://hdl.handle.net/10048/1922.
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Inductors are extensively used in the design of radio-frequency circuits. In the last decade, the integration of passive components, especially inductors on silicon chips, has led to the widespread development and implementation of Radio Frequency Integrated Circuits (RFICs) in CMOS technologies. However, on-chip passive inductors occupy a large silicon chip area and hardly scale down with technology scaling. Therefore, on-chip passive inductors become formidable obstacles to the realization of highly dense RFICs to be integrated with other highly dense digital circuits on a single chip using a common fabrication process. In recent years, researchers have focused on replacing passive inductors with transistor-only active circuits, namely active inductors. Active inductors can be realized with only a few transistors, which scale down with technology scaling. Therefore, they occupy a fraction of the chip area of their passive counterparts, and can be implemented densely in CMOS processes. Unlike passive inductors, bias dependent operations of active inductors allow for the tuning of their inductance and quality factor Q, and in turn, tuning the performance parameters of RFICs.
This thesis focuses on the design and development of passive inductorless CMOS RFICs for ultra-wideband (UWB) receiver front-ends using active inductors. A new Q-enhanced and a new bandwidth-extended tunable active inductors are designed. Using the Q-enhanced active inductor, two tunable UWB low-noise amplifiers (LNAs) (two-stage and three-stage UWB LNAs), a UWB mixer and a wideband local-oscillator (LO) driver are designed. Active inductors are utilized to develop a novel wideband active shunt-peaking technique that decreases high-frequency losses to yield a flat gain over a wide bandwidth. A tunable multiband-UWB front-end integrating a two-stage UWB LNA, and a pair of UWB mixers driven by a pair of wideband LO drivers, is fabricated in a 90nm digital CMOS process. The passive inductorless two-stage UWB LNA, three-stage UWB LNA and UWB front-end occupy chip areas of only 0.0114mm2, 0.0227mm2, and 0.1485mm2, respectively. The active CMOS UWB front-end exhibits a measured flat gain of 22.5dB over 2.5-8.8 GHz bandwidth, and its tunability allows for varying the gain and bandwidth.Integrated Circuits and Systems
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Tsai, Chung-Han, and 蔡宗翰. "A Power-Efficient and High-Integrated 8-Channel Front-End IC for Portable Brain-Heart Monitoring." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/37023767275585457959.
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碩士國立交通大學
電子研究所
100
Proportion aging is increasing rapidly in recent years. The worldwide population of people over the age of 65 has been predicted to become 761 million in this year 2025. Hence, the aging society will have a great demand of health-care system for elders, especially an integrated portable one. In this thesis, a preliminary design of high-integrated and low power consumption for processing multi signals such as electroencephalogram （EEG）signal, electrocardiogram （ECG）signal and diffuse optical tomography （DOT）is presented. The significance of this system is to enable the practical development of integrated portable health-care system for brain-heart monitoring. As the biomedical signals are weak, it is necessary to amply them for accurate monitoring. The weak biomedical signals are easily affected by external noise, so the circuit has to reduce the inference of noises. The different biomedical signals have different amplitudes and different bandwidths. Therefore, the circuit also has to deal with these problems. Finally, the biomedical signals are analog signals, but the signals are not only for monitoring but also for signals processing for the most urgent treatment conveniently. So, the analog-to-digital converter cannot be avoided. In other words, it is difficult to integrate these designs on a chip for portable health-care system. To solve this problem, Chopper Differential Difference Amplifier, Adjustable Gain Amplifier, Adjustable Bandwidth Low Pass Filter and Successive Approximation Registers Analog-to-Digital Converter are presented in this thesis. Finally, the results from this front-end circuit will convey to back-end for digital signal processing to achieve the multi-capability biomedical system monitoring chip. This multi-channel, high integrated and low power consumption has been implemented using TSMC 180 nm CMOS Mixed Signal RF General Purpose Standard Process.
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Chen, Xin-Zhuang, and 陳欣壯. "Using Leakage Feedback Element in Low Noise Front-end Amplifier by Pseudo Resistor for Neural Recording Applications IC." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/2rse9z.
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碩士國立交通大學
電控工程研究所
101
This thesis aims to design and implement a low noise, low power consumption front-end amplifier (FEA) that can be applied to various types of weak neural signal acquisition. It’s based on an integrated circuit technology to scale down system size and reduce cost and power consumption. As a case study, the proposed amplifier is designed and simulated using TSMC 0.35μm 2P4M CMOS standard process. The chip is fabricated through the National Chip Implementation Center. Using pseudo-resistor elements and capacitors to build a high-pass filter can achieve a low frequency pole at 0.15Hz. It can remove skin-electrode interface DC offset and avoid FEA saturation or distortion. Meanwhile, this thesis adopt leakage gate-controlled pseudo resistor and the FEA spurious free dynamic range about 58.1dB at 1 kHz. The proposed chip compared with commercially available instrumentation amplifier AD620 and then it’s correlation coefficient value is greater than 0.93. Finally, rat’s experiment results demonstrate the recording capability of the proposed FEA and it is suitable for neural signal recording applications.