Journal articles on the topic 'FPGA'
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1
Girau, Bernard. "FPNA: INTERACTION BETWEEN FPGA AND NEURAL COMPUTATION." International Journal of Neural Systems 10, no. 03 (June 2000): 243–59. http://dx.doi.org/10.1142/s0129065700000211.
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Neural networks are usually considered as naturally parallel computing models. But the number of operators and the complex connection graph of standard neural models can not be directly handled by digital hardware devices. More particularly, several works show that programmable digital hardware is a real opportunity for flexible hardware implementations of neural networks. And yet many area and topology problems arise when standard neural models are implemented onto programmable circuits such as FPGAs, so that the fast FPGA technology improvements can not be fully exploited. Therefore neural network hardware implementations need to reconcile simple hardware topologies with complex neural architectures. The theoretical and practical framework developed in ref. 1 allows this combination thanks to some principles of configurable hardware that are applied to neural computation: Field Programmable Neural Arrays (FPNA) lead to powerful neural architectures that are easy to map onto FPGAs, thanks to a simplified topology and an original data exchange scheme. This paper shows how FPGAs have led to the definition of the FPNA computation paradigm. Then it shows how FPNAs contribute to current and future FPGA-based neural implementations by solving the general problems that are raised by the implementation of complex neural networks onto FPGAs.
2
LEE, HANHO, and GERALD E. SOBELMAN. "VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 17–52. http://dx.doi.org/10.1142/s021812660400126x.
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This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layout and implementation of the new digit-serial FPGA architecture. Digit-serial DSP designs using the digit-serial FPGA (DS-FPGA) are compared to those implemented on Xilinx FPGAs. We have estimated that the DS-FPGA are about 2.5~3 times more efficient in area and faster than the equivalent digit-serial DSP architectures implemented using Xilinx FPGAs.
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Bhandari, Jugal Kishore, Yogesh Kumar Verma, and S. K. Hima Bindhu. "Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers." International Journal of Electrical and Electronics Research 12, no. 1 (February 26, 2024): 139–45. http://dx.doi.org/10.37391/ijeer.120120.
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The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.
4
Mbongue, Joel Mandebi, Danielle Tchuinkou Kwadjo, Alex Shuping, and Christophe Bobda. "Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–31. http://dx.doi.org/10.1145/3474058.
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Cloud deployments now increasingly exploit Field-Programmable Gate Array (FPGA) accelerators as part of virtual instances. While cloud FPGAs are still essentially single-tenant, the growing demand for efficient hardware acceleration paves the way to FPGA multi-tenancy. It then becomes necessary to explore architectures, design flows, and resource management features that aim at exposing multi-tenant FPGAs to the cloud users. In this article, we discuss a hardware/software architecture that supports provisioning space-shared FPGAs in Kernel-based Virtual Machine (KVM) clouds. The proposed hardware/software architecture introduces an FPGA organization that improves hardware consolidation and support hardware elasticity with minimal data movement overhead. It also relies on VirtIO to decrease communication latency between hardware and software domains. Prototyping the proposed architecture with a Virtex UltraScale+ FPGA demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization, which is one of the goals of virtualization. Overall, our FPGA design achieved about 2× higher maximum frequency than the state of the art and a bandwidth reaching up to 28 Gbps on 32-bit data width.
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Yu, Hoyoung, Hansol Lee, Sangil Lee, Youngmin Kim, and Hyung-Min Lee. "Recent Advances in FPGA Reverse Engineering." Electronics 7, no. 10 (October 12, 2018): 246. http://dx.doi.org/10.3390/electronics7100246.
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In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products.
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krishna, Mr P. V. Murali, and Kantumajji Navyasri. "ACCELERATING HIGH-PERFORMANCE VOLTAGE SOURCE INVERTER PROTOTYPING WITH FPGA IMPLEMENTATION." INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENT 07, no. 12 (December 30, 2023): 1–10. http://dx.doi.org/10.55041/ijsrem27818.
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This paper highlights the advantages of FPGA-based rapid prototyping as a powerful tool for accelerating the development cycle of high-performance Voltage Source Inverters. By providing a flexible and efficient platform for algorithm testing, hardware evaluation, and performance optimization, it contributes to advancements in power electronics and facilitates the deployment of robust VSIs in diverse application domains. Through extensive experimentation, we demonstrate the effectiveness of the FPGA-based rapid prototyping platform in achieving high- performance VSI control. The FPGA's real-time capabilities facilitate swift algorithm development and testing, ensuring robustness and reliability. Moreover, the platform supports real-time hardware-level fault analysis and mitigation strategies, enhancing the overall resilience of the VSI. This paper presents an innovative approach utilizing Field- Programmable Gate Arrays (FPGAs) for rapid prototyping of high-performance VSIs. This abstract outlines the core objectives, methods, and potential contributions of a project aimed at expediting the development of high-performance Voltage Source Invertersthrough FPGA-based prototyping. KEYWORDS FPGA (Field-Programmable Gate Array), Voltage Source Inverter, High-Performance Prototyping, Power Electronics, Hardware-in-the-Loop (HIL), Rapid Prototyping, Real-Time Simulation, Control Algorithms, Digital Signal Processing (DSP),Power Conversion, Description Language (HDL),System-on-Chip (SoC),Field-Programmable Analog Array (FPAA),Power Quality, Grid Integration
7
Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.
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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>
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Sauvage, Laurent, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, and Yves Mathieu. "Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/375245.
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FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.
9
Zhao, Tianrun. "FPGA-Based Machine Learning: Platforms, Applications, Design Considerations, Challenges, and Future Directions." Highlights in Science, Engineering and Technology 62 (July 27, 2023): 96–101. http://dx.doi.org/10.54097/hset.v62i.10430.
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Field-Programmable Gate Arrays (FPGAs) have emerged as a promising platform for accelerating machine learning tasks due to their high parallelism, low latency, and hardware customization ability. In this paper, the authors provide an overview of popular FPGA platforms for machine learning and compare the tradeoffs among FPGAs, GPUs, and CPUs for machine learning. The authors also present specific applications of machine learning based on FPGAs, including those in autonomous driving and healthcare. Additionally, the paper explores FPGA design considerations, such as architecture, resource utilization, and power consumption. Nonetheless, obstacles persist in the realm of FPGA-based machine learning that require attention. Identifying the ideal balance between adaptability and performance, considering factors such as space, energy usage, and latency, is still challenging. As the capabilities of FPGAs expand, there is a significant need for devices that have a smaller footprint, reduced power consumption, and minimized delays. The paper emphasizes the necessity of ongoing research in the field of FPGA-based machine learning to address these issues and continue enhancing the performance and effectiveness of machine learning systems.
10
Zhang, Qian Li, Fang Yu, Yan Li, Ming Li, Yan Zhao, and Liang Chen. "Architecture-Specific Mapping Tool for SOI-Based FPGA." Advanced Materials Research 159 (December 2010): 438–43. http://dx.doi.org/10.4028/www.scientific.net/amr.159.438.
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This paper addresses several key issues in the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process, with particular emphasis on FPGA architecture interrelated mapping step and packing method for CAD tool. Considering the routability and testability of the FPGA and the CAD tool, the algorithm combines the FPGA structure with the object netlist, mapping the basic elements into basic building blocks in order to reduce the resource usage. The result is proven in extensive test circuits used in our FPGA design.
11
Xie, Weikun, Wenjing Qi, Xiaohui Lin, and Houjun Wang. "Research on an Intelligent Test Method for Interconnect Resources in an FPGA." Applied Sciences 13, no. 13 (July 7, 2023): 7951. http://dx.doi.org/10.3390/app13137951.
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With the rapid development of integrated circuit production technology, the scale of FPGA circuits has expanded to billions of gates. The complexity of the internal resource structures in the FPGAs (field programmable gate arrays) is continually increasing, and there is an increasing possibility of various faults in these circuits, especially in interconnect resources. These occupy more than 80% of a chip’s area and have the highest fault rate. To ensure the reliability of the FPGAs, it is very important to perform high-coverage testing on the interconnect resources within them. This article uses AMD Xilinx’s Kintex-7 series FPGA as the research object and proposes a deep-priority algorithm based on graph-based models and improved priority algorithms to intelligently wire the FPGA interconnected resources. The routing results were produced using a configuration script written in the XDL language, and the FPGA configuration and testing were conducted accordingly. This approach achieved a high coverage and intelligent testing for the interconnect resources in the FPGAs.
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Wu, Chi-Feng, and Cheng-Wen Wu. "Testing and Diagnosing Dynamic Reconfigurable FPGA." VLSI Design 10, no. 3 (January 1, 2000): 321–33. http://dx.doi.org/10.1155/2000/79281.
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Dynamic reconfigurable field-programmable logic arrays (FPGAs) are receiving notable attention because of their much shorter reconfiguration time as compared with traditional FPGAs. The short reconfiguration time is vital to applications such as reconfigurable computing and emulation. We show in this paper that testing and diagnosis of the FPGA also can take advantage of its dynamic reconfigurability. We first propose an efficient methodology for testing the interconnects of the FPGA, then present several universal test and diagnosis approaches which cover all functional units of the FPGA. Experimental results show that our approach significantly reduces the testing time, without additional cost for diagnosis.
13
Xu, Heyang. "FPGA: The super chip in the age of artificial intelligence." Journal of Physics: Conference Series 2649, no. 1 (November 1, 2023): 012018. http://dx.doi.org/10.1088/1742-6596/2649/1/012018.
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Abstract In modern society, artificial intelligence (AI) is developing more rapidly. And the Field Programmable Gate Array (FPGA) has always been the focus of research as a driving platform. This paper studies in detail the theoretical basis, applications, defects, and future development directions of FPGAs. It is concluded that FPGA has three characteristics: gate array, programmable, and scene, and the detailed positioning of FPGA, the structure, principle, tools, process, and description language of FPGA design. And the unique advantages of FPGA in the field of artificial intelligence: flexible and configurable, special optimizations for convolutional neural networks, and deterministic low latency. Several typical applications of FPGA in the field of artificial intelligence, deficiencies and solutions, and two future development directions. This article will make a great contribution to the development of FPGA in the field of artificial intelligence in the future.
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Malakonakis, Pavlos, Giovanni Isotton, Panagiotis Miliadis, Chloe Alverti, Dimitris Theodoropoulos, Dionisios Pnevmatikatos, Aggelos Ioannou, et al. "Preconditioned Conjugate Gradient Acceleration on FPGA-Based Platforms." Electronics 11, no. 19 (September 24, 2022): 3039. http://dx.doi.org/10.3390/electronics11193039.
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Reconfigurable computing can significantly improve the performance and energy efficiency of many applications. However, FPGA-based chips are evolving rapidly, increasing the difficulty of evaluating the impact of new capabilities such as HBM and high-speed links. In this paper, a real-world application was implemented on different FPGAs in order to better understand the new capabilities of modern FPGAs and how new FPGA technology improves performance and scalability. The aforementioned application was the preconditioned conjugate gradient (PCG) method that is utilized in underground analysis. The implementation was done on four different FPGAs, including an MPSoC, taking into account each platform’s characteristics. The results show that today’s FPGA-based chips offer eight times better performance on a memory-bound problem than 5-year-old FPGAs, as they incorporate HBM and can operate at higher clock frequencies.
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Oliveira, Duarte L., Marius Strum, and Sandro S. Sato. "Burst-Mode Asynchronous Controllers on FPGA." International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/926851.
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FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.
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Alonso, Tobias, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, and Kees Vissers. "Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–34. http://dx.doi.org/10.1145/3470567.
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Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN layers and layers to individual FPGA dies to maximize the total performance of the multi-FPGA system. In the resulting Elastic-DF mapping, the accelerator may be instantiated multiple times, and each instance may be segmented across multiple FPGAs transparently, whereby the segments communicate peer-to-peer through 100 Gbps Ethernet FPGA infrastructure, without host involvement. When applied to ResNet-50, Elastic-DF provides a 44% latency decrease on Alveo U280. For MobileNetV1 on Alveo U200 and U280, Elastic-DF enables a 78% throughput increase, eliminating the performance difference between these cards and the larger Alveo U250. Elastic-DF also increases operating frequency in all our experiments, on average by over 20%. Elastic-DF therefore increases performance portability between different sizes of FPGA and increases the critical throughput per cost metric of datacenter inference.
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Ye, Haobo. "Accelerating convolutional neural networks: Exploring FPGA-based architectures and challenges." Journal of Physics: Conference Series 2786, no. 1 (June 1, 2024): 012004. http://dx.doi.org/10.1088/1742-6596/2786/1/012004.
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Abstract This article provides an in-depth exploration of the principles of Convolutional Neural Network (CNN) and Field Programmable Gate Array (FPGA), focusing on the reasons that make FPGAs well-suited for accelerating CNN algorithms. The discussion begins with an overview of CNN and FPGA fundamentals, highlighting the potential advantages of utilizing FPGAs in accelerating CNN computations. Next, the article introduces four distinct FPGA-based CNN accelerator designs, each presenting its unique creative architecture. These designs showcase a range of characteristics, including reconfigurability, parameterizable, and energy efficiency. The article delves into a detailed analysis of each design, elucidating their innovative aspects and potential benefits in CNN acceleration. By thoroughly understanding the proposed design approaches, the author emphasizes the challenges that arise when implementing FPGA-based CNN accelerators. These challenges encompass aspects such as algorithm mapping, hardware resource utilization, and achieving a balance between flexibility and efficiency. Additionally, the article sheds light on the future prospects of FPGA-based CNN accelerators, exploring potential advancements and research directions in this domain.
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Isaka, Yuya, Michihiro Shintani, and Michiko Inoue. "Unsupervised recycled FPGA detection using exhaustive nearest neighbor residual analysis." Japanese Journal of Applied Physics 61, SC (March 24, 2022): SC1076. http://dx.doi.org/10.35848/1347-4065/ac5107.
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Abstract Measuring and analyzing aging-induced delay degradation of ring oscillators (ROs) is an effective method to detect recycled field-programmable gate arrays (FPGAs). However, detection methods of conventional recycled FPGAs detection methods assume the existence of known fresh FPGAs (KFFs) as training data for machine-learning-based classification, which is an unrealistic assumption. In this paper, we propose an unsupervised recycled FPGA detection method, where little information on KFF is available. In the proposed method, estimated frequency is calculated from neighboring ROs, and then the residual frequency between the measured and estimated frequencies is used for the detection. Because of the systematic component of process variation, the frequencies of neighboring ROs should be similar when the target FPGA is fresh. Therefore, if the residual is high, the target FPGA is determined as recycled. Experiments using 25 commercial FPGAs under various aging scenarios demonstrate that the proposed method successfully distinguishes between recycled and fresh FPGAs.
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Tetenkin, Iaroslav G., and Viacheslav A. Sergeev. "THE MEASUREMENT OF THERMAL PARAMETERS BY CHANGING FREQUENCY OF EMBEDDED RING OSCILLATOR." АВТОМАТИЗАЦИЯ ПРОЦЕССОВ УПРАВЛЕНИЯ 63, no. 1 (2021): 82–90. http://dx.doi.org/10.35752/1991-2927-2021-1-63-82-90.
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The article describes a brief analysis of linear thermal models of digital integrated circuits (DIC) and algorithms for determining the parameters of thermal equivalent circuits of DIC-based on transient thermal characteristics (TTC). It distinguishes the difficulties in implementing the algorithm for determining the thermal parameters of the DIC-based on the method of structure functions according to the JESD51-14 document and describes a new method for measuring the FPGA TTC by changing the frequency of a ring oscillator embedded in the FPGA logic elements. It also considers the hardware-software complex used for measuring the thermal parameters of FPGAs and proposes a simple algorithm for calculating the thermal parameters of FPGAs based on the analysis of the FPGA TTC using methods of numerical differentiation. The specified algorithm for calculating thermal parameters has been tested on the example of FPGA TTC EPM240T100C5 and Lattice M4A5-64/32.
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Skhiri, Rym, Virginie Fresse, Jean Paul Jamont, Benoit Suffran, and Jihene Malek. "From FPGA to Support Cloud to Cloud of FPGA: State of the Art." International Journal of Reconfigurable Computing 2019 (December 5, 2019): 1–17. http://dx.doi.org/10.1155/2019/8085461.
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Field Programmable Gate Array (FPGA) draws a significant attention from both industry and academia by accelerating computationally expensive applications and achieving low power consumption. FPGAs are interesting due to the flexibility and reconfigurabiltiy of their device. Cloud computing becomes a major trend towards infrastructure and computing resources dematerialization. It provides “unlimited” storage capacities and a large number of data and applications that make collaboration easier between multiple (not domain specific) designers. Many papers in the literature have surveyed Cloud and FPGA separately and, more precisely, their services and challenges. The acceleration of applications by FPGA and the unlimited capacities of the cloud are expected to be more and more pervasive. As more and more FPGA are being deployed in traditional cloud, it is appropriate to clarify what is the cloud FPGA and which drawbacks of using FPGA in local are resolved. We present a survey of the cloud FPGA works that have been proposed to exploit the advantages of using FPGA in the cloud. We classify these studies in three services to highlight their benefits and limitations. This survey aims at motivating further researches in cloud FPGA.
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Guo, Shuaizhi, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, and Xi Jin. "RP-Ring: A Heterogeneous Multi-FPGA Accelerator." International Journal of Reconfigurable Computing 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6784319.
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To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.
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Haijoub, Abdelilah, Anas Hatim, Mounir Arioua, Slama Hammia, Ahmed Eloualkadi, and Antonio Guerrero-González. "Implementing Convolutional Neural Networks on FPGA: A Survey and Research." ITM Web of Conferences 52 (2023): 02004. http://dx.doi.org/10.1051/itmconf/20235202004.
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The implementation of CNN FPGA is of increasing importance due to the growing demand for low-power and high-performance edge AI applications. This paper presents a comprehensive survey and research on the topic, with a focus on comparing and evaluating the performance of two main FPGA architectures, streaming and single unit computing. The study includes a detailed evaluation of the state-of-the-art CNNs, LeNet-5 and YOLOv2, on both FPGA architectures. The results provide useful insights into the trade-offs involved, limitations, challenges, and the complexity of implementing CNNs on FPGAs. The paper highlights the difficulties and intricacies involved in implementing CNNs on FPGAs and provides potential solutions for improving performance and efficiency.
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Keller, Andrew M., and Michael J. Wirthlin. "The Impact of Terrestrial Radiation on FPGAs in Data Centers." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–21. http://dx.doi.org/10.1145/3457198.
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Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.
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Hosseinghorban, Ali, and Akash Kumar. "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications." Electronics 11, no. 7 (March 22, 2022): 978. http://dx.doi.org/10.3390/electronics11070978.
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Rapid and continuous evolution in telecommunication standards and applications has increased the demand for a platform with high parallelization capability, high flexibility, and low power consumption. FPGAs are known platforms that can provide all these requirements. However, the evaluation of approaches, architectures, and scheduling policies in this era requires a suitable and open-source benchmark suite that runs on FPGA. This paper harnesses high-level synthesis tools to implement high-performance, resource-efficient, and easy-maintenance kernels for FPGAs. We provide various implementations of each kernel of PHY-Bench and WiBench, which are the most well-known benchmark suites for telecommunication applications on FPGAs. We analyze the execution time and power consumption of different kernels on ARM processors and FPGA. We have made all sources and documentation public for the benefit of the research community. The codes are flexible, and all kernels can easily be regenerated for different sizes. The results show that the FPGA can increase the speed by up to 19.4 times. Furthermore, we show that the power consumption of the FPGA can be reduced by up to 45% by partially reconfiguring a kernel that fits the size of the input data instead of using a large kernel that supports all inputs. We also show that partial reconfiguration can improve the execution time for processing a sub-frame in the uplink application by 33% compared to an FPGA-based approach without partial reconfiguration.
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Jang, Seojin, and Yongbeom Cho. "Reinforcement Learning-Driven Bit-Width Optimization for the High-Level Synthesis of Transformer Designs on Field-Programmable Gate Arrays." Electronics 13, no. 3 (January 30, 2024): 552. http://dx.doi.org/10.3390/electronics13030552.
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With the rapid development of deep-learning models, especially the widespread adoption of transformer architectures, the demand for efficient hardware accelerators with field-programmable gate arrays (FPGAs) has increased owing to their flexibility and performance advantages. Although high-level synthesis can shorten the hardware design cycle, determining the optimal bit-width for various transformer designs remains challenging. Therefore, this paper proposes a novel technique based on a predesigned transformer hardware architecture tailored for various types of FPGAs. The proposed method leverages a reinforcement learning-driven mechanism to automatically adapt and optimize bit-width settings based on user-provided transformer variants during inference on an FPGA, significantly alleviating the challenges related to bit-width optimization. The effect of bit-width settings on resource utilization and performance across different FPGA types was analyzed. The efficacy of the proposed method was demonstrated by optimizing the bit-width settings for users’ transformer-based model inferences on an FPGA. The use of the predesigned hardware architecture significantly enhanced the performance. Overall, the proposed method enables effective and optimized implementations of user-provided transformer-based models on an FPGA, paving the way for edge FPGA-based deep-learning accelerators while reducing the time and effort typically required in fine-tuning bit-width settings.
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Landmann, Christoph, and Rolf Kall. "Graphical Hardware Description as a High-Level Design Entry Method for FPGA-Based Data Acquisition Systems." Key Engineering Materials 613 (May 2014): 296–306. http://dx.doi.org/10.4028/www.scientific.net/kem.613.296.
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Probably one of the most significant developments in the field of software-defined multifunction data acquisition systems and devices is the employment of FPGA (Field-Programmable GateArray) technology, resulting in a tremendous digital processing potential close to the I/O pin. FPGA technology is based on reconfigurable semiconductor devices which can be employed as processing targets in heterogeneous computing architectures for a variety of data acquisition applications. They can primarily be characterized by generic properties, such as deterministic execution, inherent parallelism, fast processing speed and high availability, stability and reliability. Therefore FPGAs areparticularly suitable for use in “intelligent” data acquisition applications that require either in-line digital signal co-processing or real-time system emulation in the field of advanced control, protocol aware communication, hardware-in-the-loop (HIL) as well as RF and wireless test. From the perspective of a domain expert however, primarily being focused on developing applications and algorithms, simple and intuitive design entry methods and tools are required that facilitate the FPGA configuration and design entry process. Traditional FPGA design entry methods and commercially available tools assume a comprehensive knowledge of hardware description languages (HDL),such as VHDL or Verilog®, and implement a process or function at register-level. In contrast, graphical hardware description languages for FPGAs, such as the integrated development environment NI LabVIEW® with FPGA module extension, abstract the design process by means of graphical objects, I/O nodes and interconnecting wires that represent the FPGA’s IP and implement processes, timing, I/O integration and data flow. This paper discusses the advantages of graphical system design for FPGAs over text-based alternatives, introduces interfaces for the integration of 3rd party IP, all backed up by a detailed illustration of a COTS FPGA-based multifunction DAQ target compared to a traditional DAQ architecture.
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Biookaghazadeh, Saman, Pravin Kumar Ravi, and Ming Zhao. "Toward Multi-FPGA Acceleration of the Neural Networks." ACM Journal on Emerging Technologies in Computing Systems 17, no. 2 (April 2021): 1–23. http://dx.doi.org/10.1145/3432816.
Full textAbstract:
High-throughput and low-latency Convolutional Neural Network (CNN) inference is increasingly important for many cloud- and edge-computing applications. FPGA-based acceleration of CNN inference has demonstrated various benefits compared to other high-performance devices such as GPGPUs. Current FPGA CNN-acceleration solutions are based on a single FPGA design, which are limited by the available resources on an FPGA. In addition, they can only accelerate conventional 2D neural networks. To address these limitations, we present a generic multi-FPGA solution, written in OpenCL, which can accelerate more complex CNNs (e.g., C3D CNN) and achieve a near linear speedup with respect to the available single-FPGA solutions. The design is built upon the Intel Deep Learning Accelerator architecture, with three extensions. First, it includes updates for better area efficiency (up to 25%) and higher performance (up to 24%). Second, it supports 3D convolutions for more challenging applications such as video learning. Third, it supports multi-FPGA communication for higher inference throughput. The results show that utilizing multiple FPGAs can linearly increase the overall bandwidth while maintaining the same end-to-end latency. In addition, the design can outperform other FPGA 2D accelerators by up to 8.4 times and 3D accelerators by up to 1.7 times.
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Ahmed, Shoaib. "FPGA-Based Implementation of SCADA System for Fuel Management." Quaid-e-Awam University Research Journal of Engineering, Science & Technology 21, no. 2 (December 29, 2023): 21–28. http://dx.doi.org/10.52584/qrj.2102.03.
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With the emergence of Digital Processors and Logic Design technologies, like FPGAs, the trend of using IC-based plug-and-play modules has been minimized. The focus is commercial off-shelf designing and developing modules and sub-modules on new FPGA technology. Some of the critical factors that make FPGA more suitable include enormous computational power, capabilities to perform logic operations, high-speed clocks, fast memory, and various built-in primitives for computation-intensive arithmetic operations. FPGA becomes suitable for implementing data capturing and processing systems with these characteristics. This paper is about designing and developing an FPGA-based Supervisory Control and Data Acquisition (SCADA) System to monitor and control the fuel level transition between two tanks that generally are designed using PLC. PLC-based SCADA systems are easy to implement, but when discussing performance, PLC cannot replace FPGA. The FPGA chosen is Spartan-3 due to its low cost and meeting the industrial temperature needs. At the same time, it may be translated into any advanced FPGA, producing fewer sources and power consumption benefits. The simulator is Xilinx 14.7 ISE, along with SDK. The implemented system provides the inherent amenities of SCADA along with the benefits of high speed, more accuracy, reduced and predictable delay, and a purely digitized system facilitated by the FPGA.
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LYSENKO, SERGII, OLGA ATAMANIUK, and OLEXANDER BOKHONKO. "METHOD OF CONSTRUCTING HARDWARE ARCHITECTURE FOR COMPUTER VISION SYSTEM BASED ON FPGA." Herald of Khmelnytskyi National University. Technical sciences 319, no. 2 (April 27, 2023): 360–68. http://dx.doi.org/10.31891/2307-5732-2023-319-1-360-368.
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In this work, the methodology of hardware architecture development for computer vision systems based on programmable logic, in particular FPGA, is considered. In the work, the methods of developing architectures for computer vision are studied and the advantages of using FPGA compared to traditional general-purpose processors are established. The paper also considers the main aspects of hardware design on FPGA, in particular, the selection of a suitable development tool, logic design, synthesis, and validation of the developed hardware. The capabilities of FPGAs in providing high performance and efficiency of computer vision systems have been investigated, which makes them attractive and popular for use in visual systems. We discover that FPGA technology offers a high degree of flexibility and configurability, allowing for the creation of custom hardware architectures that can be tailored to specific computer vision applications. In addition, to studying the benefits of using FPGA technology for computer vision, we also consider the main aspects of hardware design on FPGA, including the selection of a suitable development tool, logic design, synthesis, and validation of the developed hardware. By carefully considering these aspects, we can ensure that the hardware architecture we develop is both efficient and effective. Our research shows that the capabilities of FPGAs in providing high performance and efficiency of computer vision systems are truly remarkable. This makes them an attractive choice for use in visual systems, particularly in scenarios where high speed and accuracy are critical. Overall, our work serves to shed light on the many benefits of FPGA technology for computer vision and lays the foundation for further research and development in this exciting field.
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Liu, Dingwei. "The efficient application analysis of FPGA in automotive intelligent control." Applied and Computational Engineering 54, no. 1 (March 29, 2024): 57–63. http://dx.doi.org/10.54254/2755-2721/54/20241261.
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In recent times, the automotive industry has witnessed a remarkable transformation with the rapid development of automotive intelligent control systems. This evolution has shifted consumer expectations from cars being mere modes of transportation to multifunctional lifestyle assistants. A pivotal player in this transformative journey is Field-Programmable Gate Arrays (FPGAs), which have made significant contributions by delivering high-performance and efficiency enhancements across various facets of automotive intelligent control. This article delves into the diverse applications of FPGA technology within the realm of automotive intelligent control, classifying them into three distinct categories. Firstly, it explores FPGA applications in autonomous driving image processing, highlighting their role in enabling real-time image analysis and recognition, a critical component of self-driving vehicles. Secondly, the paper examines FPGA applications in automotive control function implementation, showcasing how FPGAs facilitate the efficient execution of complex control algorithms and decision-making processes in modern automobiles. Lastly, it investigates FPGA applications in automotive electronic design, emphasizing their role in enhancing the overall reliability and performance of electronic systems in vehicles.
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M., Darshan, Vikram Babu D., Charan M. V., Sachin C., and Suchitra M. "Review on FPGA Implementation of CORDIC Algorithm." Recent Trends in Semiconductor and Sensor Technology 1, no. 2 (2024): 1–8. http://dx.doi.org/10.46610/rtsst.2024.v01i02.001.
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The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.
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., Akriti. "The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (March 31, 2024): 17–20. http://dx.doi.org/10.22214/ijraset.2024.58572.
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Abstract: This research investigates challenges in employing the Distributed Arithmetic (DA) algorithm for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). Focusing on coefficient representation, it explores precision trade-offs via fixed-point arithmetic and quantization. Memory optimization strategies, such as efficient storage within FPGA resources, are analysed to reduce memory requirements. Enhancing computational speed involves optimizing lookup table access and architectural modifications. Efficient management of FPGA resources and trade-offs between latency, throughput, and resource usage are also explored. Algorithmic refinements specific to DA-based FIR filters are studied to enhance resource utilization and computational efficiency. Overall, this work offers insights and solutions spanning algorithm design, memory utilization, lookup table speed, and FPGA architecture for more efficient DA-based FIR filter implementations on FPGAs.
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Jamieson, Peter, Donald Blank, Janelle Ghanem, Tyler McGrew, and Giancarlo Corti. "A Methodology for an FPGA Implementation of a Programmable Logic Controller to Control an Atomic Layer Deposition System." International Journal of Reconfigurable Computing 2022 (May 6, 2022): 1–10. http://dx.doi.org/10.1155/2022/8827417.
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In this work, we present an industrial cold walled Atomic Layer Deposition (ALD) system, which can be controlled by either a traditional programmable logic controller (PLC) system or a field-programmable gate array (FPGA) prototyping board. This work presents an FPGA controlled system that takes ladder diagram (LD) control for a PLC and converts this control to Verilog HDL and programs an FPGA such that the FPGA prototyping board is used to control a real industrial application. We explore this approach since FPGA implementation of LD control could significantly reduce the cost of implementing these controllers with other potential advantages such as the improved granularity of timing control from milliseconds to nanoseconds, additional available pins for inputs and outputs far exceeding that of microprocessors, and lower power consumption for control. In this work, we provide details and descriptions of our industrial system (ALD), the LD control of this system and its implementation, our software flow to convert LDs to Verilog HDL, and our FPGA prototype board design to replace the existing electronic controller. We show how our LD-Verilog HDL converter in conjunction with FPGAs matches a PLC and demonstrate some of the benefits of using an FPGA.
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Ullah, Anees, Ali Zahir, Noaman A. Khan, Waleed Ahmad, Alexis Ramos, and Pedro Reviriego. "BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs." Electronics 9, no. 2 (February 19, 2020): 353. http://dx.doi.org/10.3390/electronics9020353.
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Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.
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Gnad, Dennis R. E., Cong Dang Khoa Nguyen, Syed Hashim Gillani, and Mehdi B. Tahoori. "Voltage-Based Covert Channels Using FPGAs." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (June 28, 2021): 1–25. http://dx.doi.org/10.1145/3460229.
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Field Programmable Gate Arrays ( FPGAs ) are increasingly used in cloud applications and being integrated into Systems-on-Chip. For these systems, various side-channel attacks on cryptographic implementations have been reported, motivating one to apply proper countermeasures. Beyond cryptographic implementations, maliciously introduced covert channel receivers and transmitters can allow one to exfiltrate other secret information from the FPGA. In this article, we present a fast covert channel on FPGAs, which exploits the on-chip power distribution network. This can be achieved without any logical connection between the transmitter and receiver blocks. Compared to a recently published covert channel with an estimated 4.8 Mbit/s transmission speed, we show 8 Mbit/s transmission and reduced errors from around 3% to less than 0.003%. Furthermore, we demonstrate proper transmissions of word-size messages and test the channel in the presence of noise generated from other residing tenants’ modules in the FPGA. When we place and operate other co-tenant modules that require 85% of the total FPGA area, the error rate increases to 0.02%, depending on the platform and setup. This error rate is still reasonably low for a covert channel. Overall, the transmitter and receiver work with less than 3–5% FPGA LUT resources together. We also show the feasibility of other types of covert channel transmitters, in the form of synchronous circuits within the FPGA.
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Reddy, Naresh Kumar, and N. Suresh. "An Efficient approach for Design and Testing of FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 192. http://dx.doi.org/10.11591/ijres.v4.i3.pp192-200.
Full textAbstract:
Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise.FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.
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Jumaa, Noor. "Survey: Internet of Thing Using FPGA." Iraqi Journal for Electrical and Electronic Engineering 13, no. 1 (June 1, 2017): 38–45. http://dx.doi.org/10.37917/ijeee.13.1.5.
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Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.
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Jumaa, Noor. "Survey: Internet of Thing Using FPGA." Iraqi Journal for Electrical and Electronic Engineering 13, no. 1 (June 1, 2017): 38–45. http://dx.doi.org/10.37917/ijeee.13.5.
Full textAbstract:
Everything in its way to be computerized and most of the objects are coming to be smart in present days. Modern Internet of Thing (IoT) allows these objects to be on the network by using IoT platforms. IoT is a smart information society that consists of smart devices; these devices can communicate with each other without human's intervention. IoT systems require flexible platforms. Through the use of Field Programmable Gate Array (FPGA), IoT devices can interface with the outside world easily with low power consumption, low latency, and best determinism. FPGAs provide System on Chip (SoC) technique due to FPGAs scalability which enables the designer to implement and integrate large number of hardware clocks at single chip. FPGA can be deemed as a special purpose reprogrammable processor since it can process signals at its input pins, manipulate them, and give off signals on the output pins. In this paper, using FPGA for IoT is the limelight.
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Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (January 1, 2000): 219–35. http://dx.doi.org/10.1155/2000/12198.
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In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g., Actel's ES6500 FPGA family).
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Puranik, Sunil, Mahesh Barve, Swapnil Rodi, and Rajendra Patrikar. "Acceleration of Trading System Back End with FPGAs Using High-Level Synthesis Flow." Electronics 12, no. 3 (January 19, 2023): 520. http://dx.doi.org/10.3390/electronics12030520.
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FPGA technology is widely used in the finance domain. We describe the design of a financial trading system order processing component using FPGAs, implemented with high-level synthesis (HLS) flow. The order processing component is the major contributor to increased delays and low throughput in the current software implementation of trading systems. The objective of FPGA implementation is to reduce the latency of order processing and increase the throughput of trading systems as compared to software implementation. Our design is one of the first attempts to speed up order processing in a trading system using FPGA technology and HLS flow. HLS was used in implementing the design for higher productivity and faster turnaround time. The design shows orders of magnitude of improvement in performance indicating that more complex FPGA systems could be designed using HLS. We obtained more than 2X of an advantage in order processing speed and a reduction in latency with FPGA technology. Moreover, we gained a 4X advantage in terms of productivity using HLS.
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Rawski, Mariusz. "Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAs." International Journal of Electronics and Telecommunications 56, no. 4 (November 1, 2010): 345–50. http://dx.doi.org/10.2478/v10177-010-0045-9.
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Modified Distributed Arithmetic Concept for Implementations Targeted at Heterogeneous FPGAsDistributed Arithmetic (DA) plays an important role in designing digital signal processing modules for FPGA architectures. It allows replacing multiply-and-accumulate (MAC) operations with combinational blocks. The quality of implementations based on DA strongly depends on efficiency of methods that map combinational DA block into FPGA resources. Since modern FPGAs have heterogeneous structure, there is a need for quality algorithms to target these structures and the need for flexible architecture exploration aiding in appropriate mapping. The paper presents a modification of DA concept that allows for very efficient implementation in heterogeneous FPGA architectures.
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Lai, Chiu-Keng, Yaw-Ting Tsao, Shou-Liang Tsai, and Wei-Nan Chien. "Development of an FPGA-Based Motion Control IC for Caving Machine." Advances in Mechanical Engineering 6 (January 1, 2014): 813204. http://dx.doi.org/10.1155/2014/813204.
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Since the Field Programmable Gate Arrays (FPGAs) with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.
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Ramos Colín Robles, José, Ixbalank Torres Zúñiga, Glenda Cea¬-Barcia, Fernando López-Caamal, and Víctor Alcaraz-González. "FPGA-Based Extremum Seeking Control to Maximize the Hydrogen Productivity Rate of a MEC." Memorias del Congreso Nacional de Control Automático 6, no. 1 (October 27, 2023): 538–43. http://dx.doi.org/10.58571/cnca.amca.2023.092.
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In this article it is presented an FPGA-based extremum seeking control that is used to maximize the hydrogen productivity rate in a microbial electrolysis cell (MEC) using the dilution rate as a control action. This extremum seeking control is based in the hydrogen productivity gradient and does not need a mathematical model. To achieve a positive energy balance, such optimization algorithm is implemented in an FPGA using a fixed point representation. By a closed loop simulation test and performance analysis of the FPGA-based extremum seeking control, it is demonstrated that FPGAs are the best implementation choice.
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Heinz, Carsten, Jaco Hofmann, Jens Korinth, Lukas Sommer, Lukas Weber, and Andreas Koch. "The TaPaSCo Open-Source Toolflow." Journal of Signal Processing Systems 93, no. 5 (May 2021): 545–63. http://dx.doi.org/10.1007/s11265-021-01640-8.
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AbstractThe integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.
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Lai, Yi-Hsiang, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, and Zhiru Zhang. "Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects." ACM Transactions on Reconfigurable Technology and Systems 14, no. 4 (December 31, 2021): 1–39. http://dx.doi.org/10.1145/3469660.
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FPGA-based accelerators are increasingly popular across a broad range of applications, because they offer massive parallelism, high energy efficiency, and great flexibility for customizations. However, difficulties in programming and integrating FPGAs have hindered their widespread adoption. Since the mid 2000s, there has been extensive research and development toward making FPGAs accessible to software-inclined developers, besides hardware specialists. Many programming models and automated synthesis tools, such as high-level synthesis, have been proposed to tackle this grand challenge. In this survey, we describe the progression and future prospects of the ongoing journey in significantly improving the software programmability of FPGAs. We first provide a taxonomy of the essential techniques for building a high-performance FPGA accelerator, which requires customizations of the compute engines, memory hierarchy, and data representations. We then summarize a rich spectrum of work on programming abstractions and optimizing compilers that provide different trade-offs between performance and productivity. Finally, we highlight several additional challenges and opportunities that deserve extra attention by the community to bring FPGA-based computing to the masses.
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Wu, Chang Fu. "Analysis and Realization of Critical Points on Hardware Design of FPGA." Advanced Materials Research 950 (June 2014): 133–38. http://dx.doi.org/10.4028/www.scientific.net/amr.950.133.
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FPGA is one kind of important devices that can realize many functions. As the development of communication technology and computer science, more and more technologies are invented and more and more hardware design technologies are sifted out. Therefore, the hardware design based on ASIC can be not fit on the new theories realization. As a new device, FPGA has many advantages including strength function, shorter design circle, less money, more flexible and more intelligent design tools. More and More hardware designs of FPGA are pay more attentions. Therefore, it is significant to make analysis on hardware design of FPGA. The hardware design for FPGA will be related to the FPGA device. In the market Altera and Xilinx FPGAs are used frequently by engineers. Therefore, in this dissertation will be make analysis and realization the critical points in hardware design based on Xilinx FPGA. In this dissertation, the critical point of Hardware Design of FPGA will be described. It will include power source, impedance matching and clock circuit design. There are many hardware design tools used for hardware design including Altium Designer, Protel, Cadence and others. Compared with other design tools, Cadence will have more advantages. Therefore, in this dissertation, Cadence will be used as the design tool for hardware design analysis and realization. With the help of Cadence, one hardware design and signal transmission simulation will be made analysis. With the development of the micro-electronics technology and computer science, the hardware design about FPGA will be taken more and more attentions.
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Kerschbaumer, Ricardo, André Augusto Kaviatkovski, Gabriel Rodrigues Garcia, Carlos Raimundo Erig Lima, and Jean Marcelo Simão. "The Notification Oriented Paradigm Language to Digital Hardware as an Intuitive High-level Synthesis Tool." Revista de Informática Teórica e Aplicada 28, no. 2 (August 29, 2021): 90–106. http://dx.doi.org/10.22456/2175-2745.112006.
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The parallelism allowed by FPGAs has attracted attention for knowing applications that need processing power. However, the need for specific and very technical development language has not stimulate its broad use. As an alternative, there are High-level Synthesis Languages (HSL), which allow less complicated FPGA use. However, they do not tend to take full advantage of the FPGA technology. Therefore, another alternative was developed, based on the Notification Oriented Paradigm (NOP), called NOP for Digital Hardware (NOP-DH). NOP allows development in high level with its rule-oriented language called NOPL. Its entity decoupling, parallelism, and redundancy avoidance are useful for best performance. In turn, the NOP-DH brings NOP for the FPGA context with the benefits observed in software but enhanced by hardware nature. This paper reviews the NOPL for NOP-DH (NOPL-DH) that aims high level programming for FPGA. The paper proposes the NOPL-DH test by independent developers, by developing a monitoring device for a box transporting bidirectional conveyer. As a result, NOPL-DH allowed high-level development under the NOP-DH structure in an FPGA, without the need for technical knowledge and, still, maintaining and exploring the NOP properties in FPGA
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Dwivedi, Akshya. ""Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"." International Journal for Research in Applied Science and Engineering Technology 12, no. 5 (May 31, 2024): 4483–88. http://dx.doi.org/10.22214/ijraset.2024.62485.
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Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resources effectively, balancing latency, throughput, and resource use. It looks at specific improvements to the DA method for FIR filters to make better use of resources and enhance performance. Overall, this work provides insights and solutions for algorithm design, memory use, lookup table speed, and FPGA architecture to make DA-based FIR filter implementations on FPGAs more efficient.
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Roorda, Esther, Seyedramin Rasoulinezhad, Philip H. W. Leong, and Steven J. E. Wilton. "FPGA Architecture Exploration for DNN Acceleration." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (September 30, 2022): 1–37. http://dx.doi.org/10.1145/3503465.
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Recent years have seen an explosion of machine learning applications implemented on Field-Programmable Gate Arrays (FPGAs) . FPGA vendors and researchers have responded by updating their fabrics to more efficiently implement machine learning accelerators, including innovations such as enhanced Digital Signal Processing (DSP) blocks and hardened systolic arrays. Evaluating architectural proposals is difficult, however, due to the lack of publicly available benchmark circuits. This paper addresses this problem by presenting an open-source benchmark circuit generator that creates realistic DNN-oriented circuits for use in FPGA architecture studies. Unlike previous generators, which create circuits that are agnostic of the underlying FPGA, our circuits explicitly instantiate embedded blocks, allowing for meaningful comparison of recent architectural proposals without the need for a complete inference computer-aided design (CAD) flow. Our circuits are compatible with the VTR CAD suite, allowing for architecture studies that investigate routing congestion and other low-level architectural implications. In addition to addressing the lack of machine learning benchmark circuits, the architecture exploration flow that we propose allows for a more comprehensive evaluation of FPGA architectures than traditional static benchmark suites. We demonstrate this through three case studies which illustrate how realistic benchmark circuits can be generated to target different heterogeneous FPGAs.
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Kumar Reddy, B. Naresh, N. Suresh, and J. V. N. Ramesh. "A Gracefully Degrading and Energy-Efficient FPGA Programming using LabVIEW." International Journal of Reconfigurable and Embedded Systems (IJRES) 5, no. 3 (November 1, 2016): 165. http://dx.doi.org/10.11591/ijres.v5.i3.pp165-175.
Full textAbstract:
<p>Programming of Field Programmable Gate Arrays (FPGAs) have long been the domain of engineers with VHDL or Verilog expertise. FPGA’s have caught the attention of algorithm developers and communication researchers, who want to use FPGAs to instantiate systems or implement DSP algorithms. These efforts however, are often stifled by the complexities of programming FPGAs. RTL programming in either VHDL or Verilog is generally not a high level of abstraction needed to represent the world of signal flow graphs and complex signal processing algorithms. This paper describes the FPGA Programs using Graphical Language rather than Verilog, VHDL with the help of LabVIEW and features of the LabVIEW FPGA environment.</p>