Dissertations / Theses: 'FPGA'

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Carrick, Matthew. "Logical Representation of FPGAs and FPGA Circuits within the SCA." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/33858.

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A very basic engineering tradeoff is performance versus flexibility and this design choice must be made when developing a software radio. Hardware devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) all provide a designer with choices along the performance versus flexibility spectrum. The designer must choose a combination of GPP, DSP, FPGA and ASIC devices to balance the needs of performance versus flexibility. The Software Communications Architecture (SCA) is a specification for a software radio architecture produced by the Joint Program Executive Office (JPEO) Joint Tactical Radio System (JTRS). The 2.2 revision of the SCA only implies support for GPPs, with no specified support for additional devices such as FPGAs. However, FPGA integration within the scope of the SCA is still possible. The integration of an additional processing hardware device other than a GPP requires the ability to logically represent the device within the Core Framework. This representation is implemented within the OSSIE Core Framework, an open source implementation of the SCA. The representation requires the support of multiple implementations of signal processing components within the framework, a simple component deployment model, and the abstraction of the FPGA interactions into a software component.
Master of Science

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Lavin, Christopher Michael. "Using Hard Macros to Accelerate FPGA Compilation for Xilinx FPGAs." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2933.

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Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.

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Krčma, Martin. "Akcelerace neuronových sítí v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2014. http://www.nusl.cz/ntk/nusl-235409.

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This thesis deals with a training of the FPNN structures. It focuses on the ways of direct conversion of the pretrained arti cial neural networks to FPNNs. This is useful when original training data set is not reachable.

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Tianxu, Yue. "Convolutional Neural Network FPGA-accelerator on Intel DE10-Standard FPGA." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-178174.

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Convolutional neural networks (CNNs) have been extensively used in many aspects, such as face and speech recognition, image searching and classification, and automatic drive. Hence, CNN accelerators have become a trending research. Generally, Graphics processing units (GPUs) are widely applied in CNNaccelerators. However, Field-programmable gate arrays (FPGAs) have higher energy and resource efficiency compared with GPUs, moreover, high-level synthesis tools based on Open Computing Language (OpenCL) can reduce the verification and implementation period for FPGAs. In this project, PipeCNN[1] is implemented on Intel DE10-Standard FPGA. This OpenCL design acceleratesAlexnet through the interaction between Advanced RISC Machine (ARM) and FPGA. Then, PipeCNN optimization based on memory read and convolution is analyzed and discussed.

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Simmler, Harald C. "Preemptive multitasking auf FPGA-Prozessoren : ein Betriebssystem für FPGA-Prozessoren /." [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9460961.

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Mou, Pedro Antonio. "General purpose bioelectric signals acquisition platform combining FPGA and FPAA = 結合FPGA及FPAA的通用生物電信號採集平台." Thesis, University of Macau, 2010. http://umaclib3.umac.mo/record=b2182896.

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Ivebrink, Pontus, and Peter Ytterström. "Frekvensuppdelning med FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56238.

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Examensarbetets syfte var att skapa ett frekvensspektrum för ljud. För att representera detta frekvensspektrum används staplar av lysdioder. Systemet implementeras på ett Altera DE2 utvecklingskort. Olika sätt för att skapa dessa frekvensuppdelningar har testats och olika metoder för att lösa dessa har också testats.

Den slutliga implementeringen består av en filterbank som utnyttjar nersampling för att återanvända filter och sänka ordningen på dessa. Det största problemet var att få plats med allt på den FPGA som användes. Genom att byta till en lite mer komplicerad men effektivare filterstruktur så löstes detta problem och vi fick även gott om utrymme över.

Manualer och datablad har inte alltid varit lätta att tolka och ibland har andra metoder använts än de som beskrivs i dessa manualer med tips från support forum och handledare. Det finns vissa förbättringar att göra och vissa saker skulle kunnat göras annorlunda för att spara resurser med ett lite sämre resultat. När projektet var klart hade alla krav som ställts uppfyllts.

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Gravdal, Fredrik. "Selvrekonfigurering av FPGA." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10356.

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Den tradisjonelle designflyten i utviklingen av mikroelektronikk forutsetter at alle utviklingsaktivitetene er unnagjort pre-kjøretid, og at ferdiggenererte, udelelige konfigurasjonsfiler brukes for å konfigurere brikkene. De fleste systemer som benytter FPGA-teknologi i dag har derfor et begrenset utvalg forhåndsgenererte konfigurasjoner å velge mellom for å løse en oppgave. Ideen bak denne oppgaven er ønsket om å lage et rekonfigurerbart system der det er FPGA-en selv som står for rekonfigureringen uten noe behov for ekstern tilkobling eller manipulasjon. Dette for å drive den innovative utviklingen av dynamiske hardwaresystemer. Systemet er laget på en Suzakuplattform med en Spartan-3 XC3S1000 FPGA fra Xilinx. Det er utviklet to program, CLBRead og CLBWrite som kjøres på en microblazeprosessor. CLBRead kan lese en CLB-struktur med forskjellig størrelse, der en enkelt CLB er den minste oppdelingen, til fil. En CLB-struktur kan leses ut fra flash på FPGA-kortet, eller fra en bitstrømsfil på en PC. CLBWrite skriver en filstruktur generert av CLBRead til flashområdet der FPGA-konfigurasjonene ligger. Ved oppstart av FPGA-en vil det nye oppsettet konfigureres opp. Systemet som er utviklet gjør at FPGA-en kan rekonfigureres helt uten behov for ekstern tilkobling eller manipulasjon. Det er FPGA-en selv som gjør hele jobben. Forskjellige moduler kan lagres og lastes inn ved behov. Systemer er testet med to moduler, en OG-port og en ELLER-port, der disse kan byttes med hverandre og endringene kan måles med et digitalt multimeter.

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Paananen, V. (Ville). "Neuroverkkojen FPGA-toteutus." Bachelor's thesis, University of Oulu, 2018. http://urn.fi/URN:NBN:fi:oulu-201805312377.

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Tässä työssä esitellään kaksi erilaista neuroverkkoa, monikerrosperceptron ja konvolutionaalinen neuroverkko, ja tutkitaan niiden toteutettavuutta käyttämällä FPGA-piirirakennetta. Työssä kuvataan neuroverkkojen taustaa ja esitellään niiden toimintaa ja suunnittelua ohjaavia parametreja. Lisäksi tutkitaan FPGA-piirien eduja ja haasteita. Työ tehtiin kirjallisuuskatsauksena käyttämällä lähteinä ajankohtaisten neuroverkkotutkimusten tuloksia
This work presents two different neural networks, multi-layer-perceptron and convolutional neural network and their FPGA-implementation is researched. The work describes the background for neural networks and presents their operation and the parameters that guide their design. The benefits and challenges of FPGA-circuits are also researched. The work was done as a literature review using the the contemporary neural network research

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Малахова, О. Ю., І. О. Шевцов, and В. С. Чумак. "Електроміограф на FPGA." Thesis, ХНУВС, 2022. https://openarchive.nure.ua/handle/document/20336.

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Електроміографія є методом дослідження біопотенціалів, що утворюються в скелетних м’язах людини і тварин під час збудження м’язових волокон. Електроміографічні дослідження широко використовуються в дослідженнях рухових розладів в ортопедії та протезуванні, фізіології роботи та руху, аналізу втоми і рухових навичок, що також носить загальну назву інженерної психології, а також у передових дослідження нервової активності, психофізіологічних дослідженнях вікових особливостей, тому, грамотне призначення ЕМГобстеження дозволяє отримати максимум інформації за мінімальних витрат часу, що сприяє великому різноманіттю приладів ЕМГ – електроміографів, які відрізняються функціями, розмірами і технічними характеристиками

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Santos, Tiago Vallejo dos. "Sudoku em FPGA." Master's thesis, Universidade de Aveiro, 2011. http://hdl.handle.net/10773/8946.

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Mestrado em Engenharia Electrónica e Telecomunicações
Este trabalho, desenvolvido no âmbito dos sistemas reconfiguráveis, tem como objetivo a implementação de um solucionador de puzzles Sudoku, quer em software quer em hardware, tentando minimizar o seu tempo de solução. Deste modo, foram desenvolvidos três solucionadores: Simples, apenas capaz de resolver puzzles simples, Tentativa e Erro, que implementa um algoritmo de Breadth-First Search para solucionar puzzles mais complexos, e, por fim, o solucionador Tentativa e Erro com capacidade para processamento paralelo, também este capaz de solucionar puzzles mais complexos. Todos estes solucionadores foram implementados e testados numa FPGA da família Spartan-3E da Xilinx, usando, para isso, uma placa de prototipagem da Digilent. Os resultados obtidos foram comparados entre as várias implementações abordadas, assim como com outros solucionadores existentes.
This work, developed in the context of reconfigurable systems, has as an objective the implementation of a Sudoku solver, both in software and hardware, and attempting to minimize its solution time. Thus, three solvers were developed: Simple, only able to solve simple puzzles, Trial and Error, which implements a Breadth-First Search algorithm, being able to solve more complex puzzles, and, finally, the Trial and Error solver with the possibility of parallel processing, being also able to solve complex puzzles. All these solvers were implemented and tested on an FPGA of Xilinx Spartan- -3E family, using for this purpose a prototyping board from Digilent. The results were compared between the various implementations, as well as with other state-of-the-art solvers.

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Hauck, Scott. "Multi-FPGA systems /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.

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Schüler, Erik. "Uma interface para o aumento da faixa de freqüências de operação de FPAAS." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2004. http://hdl.handle.net/10183/6466.

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O crescente avanço nas mais diversas áreas da eletrônica, desde instrumentação em baixa freqüência até telecomunicações operando em freqüências muito elevadas, e a necessidade de soluções baratas em curto espaço de tempo que acompanhem a demanda de mercado, torna a procura por circuitos programáveis, tanto digitais como analógicos, um ponto comum em diversas pesquisas. Os dispositivos digitais programáveis, que têm como grande representante os Field Programmable Gate Arrays (FPGAs), vêm apresentando um elevado e contínuo crescimento em termos de complexidade, desempenho e número de transistores integrados, já há várias décadas. O desenvolvimento de dispositivos analógicos programáveis (Field Programmable Analog Arrays – FPAAs), entretanto, esbarra em dois pontos fundamentais que tornam sua evolução um tanto latente: a estreita largura de banda alcançada, conseqüência da necessidade de um grande número de chaves de programação e reconfiguração, e a elevada área consumida por componentes analógicos como resistores e capacitores, quando integrados em processos VLSI Este trabalho apresenta uma proposta para aumentar a faixa de freqüências das aplicações passíveis de serem utilizadas tanto em FPAAs comerciais quanto em outros FPAAs, através da utilização de uma interface de translação e seleção de sinais, mantendo características de programabilidade do FPAA em questão, sem aumentar em muito sua potência consumida. A proposta, a simulação e a implementação da interface são apresentadas ao longo desta dissertação. Resultados de simulação e resultados práticos obtidos comprovam a eficácia da proposta.
The increasing advance in several areas of electronics, from low frequency instrumentation to telecommunications operating in very high frequencies, and the necessity of low cost solutions in a short space of time, following the demand of the market, makes the search for digital and analog programmable circuits a common point in many researches. Digital programmable devices, which have as a great representant Field Programmable Gate Arrays (FPGAs) devices, have shown a high and continuous increase in terms of complexity, performance and number of integrated transistors for many decades. The development of analog programmable devices (Field Programmable Analog Arrays – FPAAs), however, stops in two fundamental points that make their evolution slow: the narrow bandwidth reached, consequence of the necessity of a great number of programming and configuration switches, and the huge area occupied for analog components as resistors and capacitors, when integrated in a VLSI process. This work presents a proposal to increase the frequency range of the applications that can be used also with commercials FPAAs and others FPAAs, through the use of an interface to translate and select signals, keeping the programmability characteristics of the FPAA, without increasing so much the dissipated power. The proposal, simulation and implementation of the interface are presented in this dissertation. The simulations and practical results obtained show the proposal efficiency.

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Kornmesser, Klaus. "Das FPGA-Entwicklungssystem CHDL eine vollständige, C++-basierte Entwicklungsumgebung für FPGA-Koprozessoren /." [S.l. : s.n.], 2004. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB11612006.

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Arntsen, Stian Reiersen. "FPGA-plattform for AHEAD." Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10261.

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Denne rapporten bygger på arbeidet som er gjort i forbindelse med en FPGA plattform for AHEAD prosjektet. Teori og arbeid i rapporten er bygd rundt den valgte FPGA utviklingsplattformen Suzaku-S. Rapporten begynner med litt beskrivelse av AHEAD og systemet, samt en motivasjon med forklaring av hva dette kan brukes til. Videre går en inn på litt teori om hvilke krav som stilles til slike systemer og hvilke av kravene som er tilfredsstilt ved valget av den nevnte utviklingsplattform. Rapporten inneholder videre en dokumentasjon på arbeidet som er utført og en forklaring på hvordan den ferdige versjon 1 av AHEAD plattformen virker. Resultatet er altså en ferdig FPGA-plattform uten ekstern mikroprosessor, der en heller valgte å bruke FPGAens interne prosessor. Plattformen inngår i en verktøykjede som inneholder utviklings-PC, FPGA-plattform og http-server. Mikroprosessoren i FPGAen kjører en tilpasset uClinux som operativsystem. uClinux er tilpasset spesielt denne prosessoren og dette systemet, og er kompilert på utviklings-PCen. FPGA-plattformen som er implementert er en html/script-basert AHEAD-server. Det vil si at plattformen bruker html kode og en webserver som grensesnitt, samt linker til script for å lage funksjonalitet på plattformen som kan styres eksternt. Den endelige FPGA-plattformen implementerer en dynamisk rekonfigurering styrt eksternt, med to forskjellige maskinvare konfigurasjoner. Resultatet av en aritmetisk operasjon er vist i et webservet grensesnitt, der en kan velge å laste ned en adderende maskinvarekonfigurasjon, og en subtraherende maskinvarekonfigurasjon. Resultatet av operasjonen er da selvfølgelig avhengig av hvilken maskinvarekonstruksjon som er lastet ned til FPGAen. En del av dokumentasjonen i rapporten er direkte skrevet for eventuelt videre arbeid med akkurat denne utviklingsplattform og de designverktøy som er brukt. Det er gitt forslag til hva det kan være lurt å jobbe videre med, og hvilke oppgaver som må prioriteres for å komme nærmere et ferdig AHEAD system. Til slutt er det gitt en konklusjon av arbeidet og hvordan fremdriften har vært.

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Østby, Kenneth. "FPGA Framework for CMP." Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8782.

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The single core processor stagnated due to four major factors. (1) The lack of instruction level parallelism to exploit, (2) increased power consumption, (3) complexity involved in designing a modern processor, and (4) the gap in performance between memory and the processor. As the gate size has decreased, a natural solution has been to introduce several cores on the same die, creating a chip multicore processor. However, the introduction of chip multicore processors has brought a new set of new challenges such as power consumptions and cache strategies. Although throughly researched in context of super computers, the chip multiprocessor has decreased in physical size, and thus some of the old paradigms should be reevaluated, and new ones found. To be able to research, simulate and experiment on new multicore architectures, simulators and methods of prototyping are needed by the community, and has traditionally been done by software simulators. To help decrease the time between results, and increase the productivity a hardware based method of prototyping is needed. This thesis contributes by presenting a novel multicore architecture with interchangeable and easily customizable units allowing the developers to extend the architecture, rewriting only the subsystem in question. The architecture is implemented in VHDL and has been tested on a Virtex FPGA, utilizing the MicroBlaze microcontroller. Based upon FPGA technologies, the platform has a more accurate nature than a software based simulator. The thesis also shows that a hardware based environment will significantly decrease the time to results.

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Zhou, Ruoxing. "Dynamic Partial Reconfigurable FPGA." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-74486.

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Partial Reconfigurable FPGA provides ability of reconfigure the FPGA duringrun-time. But the reconfigurable part is disabled while performing reconfiguration. In order to maintain the functionality of system, data stream should be hold for RP during that time. Due to this feature, the reconfiguration time becomes critical to designed system. Therefore this thesis aims to build a functional partial reconfigurable system and figure out how much time the reconfiguration takes. A XILINX ML605 evaluation board is used for implementing the system, which has one static part and two partial reconfigurable modules, ICMP and HTTP. A Web Client sends different packets to the system requesting different services. These packets’ type information are analyzed and the requests are held by a MicroBlaze core, which also triggers the system’s self-reconfiguration. The reconfiguration swaps the system between ICMP and HTTP modules to handle the requests. Therefore, the reconfiguration time is defined between detection of packet type and completion of reconfiguration. A counter is built in SP for measuring the reconfiguration time. Verification shows that this system works correctly. Analyze of test results indicates that reconfiguration takes 231ms and consumes 9274KB of storage, which saves 93% of time and 50% of storage compared with static FPGA configuration.

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Yan, Dandan. "FPGA Platform for Debug." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-92244.

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FPGA-based prototyping is increasingly used in ASIC developments today to allow hardware/software co-design well ahead of chip fabrication and acceleration of functional verification of ASIC designs and the surrounding system. This thesis addresses an FPGA platform that can be applied in the development of next generation target debugger system. This FPGA platform can also be used for prototyping and verification acceleration of Ericsson ASIC IP:s. Micro Ericsson ASIC (μ-EA) system is implemented in Xilinx Virtex-6 FPGA board with the SERDES port that can be tested at 1.25/2.5Gbps. This design costs 62% of FPGA device resources at a frequency of 2.5MHz. The access of Trace Buffer, MEMORY and DSP inside μ-EA proves achievable as well. Moreover, DSP core inside μ-EA is capable of running software and sending out trace messages to debug block, using DebugTool through a Nexus trace probe. This FPGA platform combined with probe and debug tools developed by Ericsson Digital ASIC Unit can be used to verify and validate the next generation debugger systems before ASIC arrives.

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Stymne, Petter. "Säkerhetskritiska standarder och FPGA." Thesis, Umeå universitet, Institutionen för tillämpad fysik och elektronik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:umu:diva-66929.

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IEC 61508, ISO 26262, DO-254 och CENELEC EN 5012x är alla standarder för utveckling av säkerhetskritiska system. Dessa fyra är applicerbara på bilar upp till 3.5 ton (ISO 26262), flyg (DO-254), tåg (Cenelec EN 5012x) samt IEC 61508 vilket är en standard för flertalet industrigrenar. När ett säkerhetskritiskt system skall implementeras i en FPGA så kan problem uppstå. Detta för att en FPGA ibland räknas till hårdvara men utvecklingen följer samma mönster som mjukvaruutveckling. Detta examensarbetes huvuduppgift är att klargöra hur de olika standarderna ser på FPGA utveckling samt verifiering med hjälp av utökad funktionell verifiering. Uppsatsen är uppdelad i två delar. Den första delen behandlar de säkerhetskritiska standarderna. Vi kommer att gå igenom dessa för att få en översikt samt visa vilka skillnader likheter som finns. Hur ställer de sig till FPGA, hårdvara eller mjukvara. Del två går igenom ett projekt i enlighet med IEC 61508, inklusive metoder för funktionell verifiering ingå. Dessa metoder är ABV (Assertion Based Verification) samt täckningsgrad för verifieringen. Har vi verifierat tillräckligt och vilka krav ställs på ett projekt enligt IEC 61508. I den här delen går vi även igenom hur de olika standarderna ser på FPGA:er samt några rekommendationer gällande FPGA utveckling och säkerhetskritiska system.

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Wood, Christopher Landon. "Runtime partial FPGA reconfiguration." Thesis, Georgia Institute of Technology, 2002. http://hdl.handle.net/1853/15051.

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Beeckler, John Sachs. "FPGA particle graphics hardware." Thesis, McGill University, 2006. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=98944.

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Particle graphics simulations are well suited for modeling phenomena such as water, cloth, explosions, fire, smoke, and clouds. They are normally realized in software, as part of an interactive graphics application. Their use in such applications is limited by the computational burden and resource competition they create. This thesis presents the design and implementation of a reconfigurable hardware particle graphics system for accelerating real-time particle graphics effects: The Particle Pipe. We explore the design process, implementation issues, limitations, challenges, and new possibilities of using FPGAs for the acceleration of real-time particle graphics. The Particle Pipe has been synthesized to an operating frequency of 130 MHz and has the potential for an increase in performance of two orders of magnitude over software methods and one order of magnitude over GPU methods.

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Silva, Thiago de Oliveira. "Elastic circuits in FPGA." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2017. http://hdl.handle.net/10183/174540.

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O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers.
The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

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Hrbáček, Radek. "Koevoluční algoritmus v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2013. http://www.nusl.cz/ntk/nusl-236407.

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This thesis deals with the design of a hardware acceleration unit for digital image filter design using coevolutionary algorithms. The first part introduces reconfigurable logic device technology that the acceleration unit is based on. The theoretical part also briefly characterizes evolutionary and coevolutionary algorithms, their principles and applications. Traditional image filter designs are compared with the biologically inspired design methods. The hardware unit presented in this thesis exploits dual MicroBlaze system extended by custom peripherals to accelerate cartesian genetic programming. The coevolutionary image filter design is accelerated up to 58 times. The hardware platform functionality in the task of impulse noise filter design and edge detector design has been empirically analyzed.

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Žižka, Martin. "Stavový firewall v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2012. http://www.nusl.cz/ntk/nusl-236618.

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This thesis describes the requirements analysis, design and implementation of stateful packet filtering to an existing stateless firewall. They also deals with testing of the implemented system. The first two chapters describe the properties NetCOPE development platform for FPGA. They also describes the principle of operation firewall, which also serves as a requirements specification for stateful firewall. Then describes the detailed design of individual modules to modify the existing firewall and the proposal for the creation of new modules. It also discusses the implementation of the proposed modules and testing for proper operation. Finally, it discuss the current state of the thesis and describes possible future expansion.

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Sigmund, Stanislav. "Přehrávač videa využívající FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2010. http://www.nusl.cz/ntk/nusl-412823.

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This thesis deals with possible and realized decompression and playing of video on platforms, using FPGA unit. For implementation of this player is used platform FITKit, which has integrated VGA connector and large enough RAM memory. It uses a hard drive as memory medium with FAT32 file system.

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Subramanian, Rishi Bharadwaj. "FPGA Based Satisfiability Checking." University of Cincinnati / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1583154848438753.

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Qureshi, Kamran. "Pedestrian Detection on FPGA." Thesis, Mittuniversitetet, Avdelningen för elektronikkonstruktion, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-21509.

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Image processing emerges from the curiosity of human vision. To translate, what we see in everyday life and how we differentiate between objects, to robotic vision is a challenging and modern research topic. This thesis focuses on detecting a pedestrian within a standard format of an image. The efficiency of the algorithm is observed after its implementation in FPGA. The algorithm for pedestrian detection was developed using MATLAB as a base. To detect a pedestrian, a histogram of oriented gradient (HOG) of an image was computed. Study indicates that HOG is unique for different objects within an image. The HOG of a series of images was computed to train a binary classifier. A new image was then fed to the classifier in order to test its efficiency. Within the time frame of the thesis, the algorithm was partially translated to a hardware description using VHDL as a base descriptor. The proficiency of the hardware implementation was noted and the result exported to MATLAB for further processing. A hybrid model was created, in which the pre-processing steps were computed in FPGA and a classification performed in MATLAB. The outcome of the thesis shows that HOG is a very efficient and effective way to classify and differentiate different objects within an image. Given its efficiency, this algorithm may even be extended to video.

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Kraus, Václav. "Analyzátor signálu s FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2018. http://www.nusl.cz/ntk/nusl-377127.

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The aim of this thesis is to study the possibilities of spectrum calculations, as well as data transfer via USB 3.0 and data saving to a DDR3 memory via FPGA. The focus is also on design and realization of a spectral analyzer with a record of samples to DDR memory expnaded by a narrowband converter using gate arrays. The work is divided into two sections, the first one dealing with the theoretical background. The second part denotes the realization of the design. The result of this work is a signal analyzer in a FPGA controlled from a computer application via the USB 3.0 interface.

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Němec, Tomáš. "Zpracování zvuku v obvodech FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2011. http://www.nusl.cz/ntk/nusl-374600.

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30

Manoni, Simone. "EPAC Multi-FPGA SerDes: Enabling Partitioning of the European Processor Accelerator on Multiple FPGAs." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2022.

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European Processor Initiative (EPI) è un progetto attualmente implementato nella seconda fase di un accordo con la Commissione europea, il cui scopo è quello di progettare e attuare una tabella di marcia per una nuova famiglia di processori europei a basso consumo per l'extreme scale computing, Big-Data, HPC e altre applicazioni emergenti. La prima fase di EPI è iniziata nel dicembre 2018 ed è stata completata con successo nel novembre 2021, con la consegna dei primi 143 test chip (EPACs) per l'unione europea. Il bring-up dei test chip è avvenuto con successo e ha eseguito il suo primo programma inviando i tradizionali saluti "Hello World!" in diverse lingue. Per eseguire tutte le necessarie procedure di prototipazione e test necessarie prima di inviare un chip in produzione, è necessario che l'EPAC sia emulato da un dispositivo FPGA. Tuttavia, la dimensione di EPAC è troppo grande per implementare e prototipare il progetto completo sulla maggior parte degli FPGA commerciali. Pertanto, fino ad ora, la prototipazione è stata è stata effettuata disabilitando diverse parti del sistema una per una, in modo che il sistema ridotto potesse essere implementato in un singolo FPGA. Il lavoro presentato in questa tesi, che è stato svolto all'interno di Semidynamics Technology Services per EPI, ha avuto come contributo la concezione del partizionamento EPAC su un sistema multi-FPGA, la definizione dell'architettura e la progettazione di un modulo Serializzatore-Deserializzatore che permette il partizionamento EPAC del sistema multi-FPGA, al fine di realizzare un emulatore Full-Chip.

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Negrini, Marco. "Controllo Numerico con Sviluppo FPGA." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2018. http://amslaurea.unibo.it/17283/.

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Le macchine a Controllo Numerico Computerizzato sono molto usate nell' automazione industriale. La funzione più importante è il controllo del movimento. L' implementazione del software che gestisce queste macchine dipende dal tipo di processore che lo esegue, infatti lo sviluppo delle macchine a controllo numerico va di pari passo con quello dei computer. Grazie allo sviluppo di soluzioni Open Surce in questo campo possiamo notare diversi approcci per l' architettura software. Le comunità interessate alla stampa 3D hanno optato per micro-controllori dato il loro basso costo, mentre per le macchine per la fresa storicamente viene usato un computer con un sistema operativo completo. Stampa 3D e frese, anche se compiono operazioni opposte, sono entrambe controllate numericamente, e quindi il software è lo stesso per entrambe. I micro-controllori sono economici e possono essere usati per efficaci soluzioni stand-alone, ma faticano a gestire la complessità di interfaccie di rete o interfaccie video. Dall' altra parte, computer e sistemi operativi hanno kernel multi-thread e driver di rete e video, ma devono comunicare con controllori per la gestione continuata di eventi. In particolare il progetto Machinekit: funziona su un sistema operativo GNU/Linux, ottenendo i vantaggi dei linguaggi di alto livello come python. Attualmente richiede piattaforme specifiche per interfacciarsi con i motori, ma è possibile aggiungere nuove piattaforme. Questa tesi si pone l' obiettivo di sviluppare una possibile piattaforma alternativa. Ed è stato posto il vincolo di utilizzare solo strumenti Open Source.

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Pasquale, Ruggero. "Dispositivi FPGA: architetture a confronto." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2019. http://amslaurea.unibo.it/18594/.

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L’obiettivo di questo studio è quello di analizzare le tecnologie adoperate nello sviluppo di circuiti FPGA per poi porre a confronto le architetture di famiglie di ultima generazione. Una volta analizzate le architetture, verranno effettuate delle simulazioni attraverso il software Quartus II Lite per verificare le prestazioni delle famiglie prese in esame, allo scopo di confrontare le prestazioni rilevate.

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Martinsson, Mike. "Sammanvägning av diversitetssignaler med FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-10323.

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Genom samtal med radioamatörer visade det sig att det fanns ett intresse för att använda rumsdiversitet på deras mottagare då de upplevde fädning (vid körning med bil) som ett problem för hörbarheten. I ett system där mottagaren är stationär och sändaren mobil kommer den mottagna signalen att fäda ibland då radiovågorna tar olika vägar till mottagaren och ibland förstärker och ibland stör varandra. Tanken med detta examensarbete var att kunna ta emot två bandbegränsade audiosignaler från två mottagare med varsin antenn som tar emot samma signal (rumsdiversitet) och vikta ihop dessa med lämplig metod för att få ut en bättre signal. Om man kunde implementera ett diversitetssystem med VHDL i en FPGA så skulle man få ett system som var både billigt och flexibelt. I det här examensarbetet har jag försökt att konstruera ett sådant system.

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Næss, Erik Normann. "Implementing Controller Strategies in FPGA." Thesis, Norwegian University of Science and Technology, Department of Engineering Cybernetics, 2009. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8983.

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In todays industrial applications there is an increasing demand for good control algorithms and implementions. This may be because of increased competition leading to smaller economic margins, safety reasons or even environmental reasons etc. With such demands comes the need for faster and more efficient hardware. Unfortunately, even though CPU-speed has more or less sky-rocketed the last decades, using such solutions for a typical embedded system is not very cost efficient, practical or robust. Thus, many embedded systems now a days use complete microcontrollers, such as the ATMEL AVR-chips. These however, run on far slower clock speeds than pure CPUs, and are not capable of performing the calculations needed for real-time controlling using for example an MPC controller. One way of getting around the performance issue, could be to construct the controller entirely in hardware, designed specifically for the task at hand. This paper will look at how this is possible to accomplish by using an FPGA, and how much performance gain it is possible to achieve on this platform.

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Zorer, Tolga. "Vme Slave Implementation On Fpga." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/2/12610128/index.pdf.

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In today&rsquo
s complex technological systems, there is a need of multi tasking several units running in accordance. Each unit is composed of several intelligent microcontroller cards. Each intelligent card performs a different task that the unit is responsible of. For this reason, there is a need of common communication bus between these cards in order to accomplish the task duties. VME (Versa Module Euro-Card) bus is a well known, the most reliable and the commonly used communication bus, even if it was standardized three decades ago. In this thesis work, the world wide accepted VME parallel bus protocol is implemented on FPGA (Field programmable Gate Array). The implementation covers the VME standard slave protocols. The VME Slave Module has been developed by VHDL (Very high level Hardware Description Language). The simulations have been carried over a computer based environment. After the verification of the VHDL code, an Intellectual Property (IP) core is synthesized and loaded into the FPGA. The FPGA based printed circuit board has been designed and the IP core&rsquo
s function has been tested by bus protocol checkers for all of its functionality. The designed hardware has several standard serial communication ports, such as
USB, UART and I2C. Through the developed card and the add-on units, it is also possible to communicate with these serial ports over the VME bus.

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Ozkan, Ibrahim. "Traffic Sign Detection Using Fpga." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/2/12611788/index.pdf.

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In this thesis, real time detection of traffic signs using FPGA hardware is presented. Traffic signs have distinctive color and shape properties. Therefore, color and shape based algorithms are chosen to implemented on FPGA. FPGA supports sufficient logic to implement complete systems and sub-systems. Color information of images/frames is used to minimize the search domain of detection process. Using FPGA, real time conversion of YUV space to RGB space is performed. Furthermore, color thresholding algorithm is used to localize the sign in the image/video depending on the color. Edges are the most important image/frame attributes that provide valuable information about the shape of the objects. Sobel edge detection algorithm is implemented on FPGA. After color segmentation, FPGA implementation of Sobel algorithm is used to find the edges of candidate traffic signs in real time. Later, radial symmetry based shape detection algorithm is used to determine circular traffic signs. Each FPGA implemented algorithm is tested by using video sequences and static images. In addition, combined implementation of color based and shape based algorithms are tested. Joint application of color and shape based algorithms are used in order to reduce search domain and the processing time of detection process. Designing architecture on FPGA makes traffic sign detection system portable as a final product and relatively more efficient than the computer based detection systems. The resulting hardware is suitable where cost and compactness constraints are important.

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ZENG, HAOMING. "FPGA based smart NIR camera." Thesis, Mittuniversitetet, Institutionen för informationsteknologi och medier, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-17613.

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Road conditions are a critical issue for road users as, if not given sufficient attention, they may threaten users’ lives. The environmental parameters, such as snowy, icy, dry and wet, are important in relation to the condition of roads. This is particularly true in relation to the northern regions and greatest concern should be in relation to snowy and icy situations. In this thesis, a system based on an InGaAs area scan sensor utilizes NIR technology to detect water or ice on the road so as to enable drivers to avoid slippery road conditions. The conditions caused by freezing water on road surface are particularly dangerous and are not easy to observe and it is hope that this project will boost traffic safety. The system is able to assist road maintenance personnel in forecasting and detecting slippery road conditions during winter road maintenance (WRM). The system, which is based on FPGA, has functionalities that display the captured images on an HDMI monitor and send the images to the software on a host PC via the UART protocol. An interface board, which carries the sensor and which connects to the FPGA board, is developed for NIR sensor. VHDL implementation and PC software design are the works included in the project. Besides, this device is exploited utilizing InGaAs image sensor. According to its features, it can be applied in other applications which will also be discussed. Finally, experiments are conducted in order to investigate the system’s operation with the variation of temperature.

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Denning, Daniel. "Encryption systems for FPGA computing." Thesis, University of Glasgow, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.438606.

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Lindström, Gustaf. "Strömsnål FM-demodulering med FPGA." Thesis, Linköpings universitet, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-70263.

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Rutiner skrivna i Verilog har utvecklats för avkodning av en frekvensmodulerad signal givet ett Analog Devices AD9874-chip. Olika metoder för I/Q-demodulation har utvärderats och av dessa har CORDIC valts och implementerats i Verilog. Koden har till viss del testats på en IGLOO nano-FPGA men framförallt simulerats och verifierats i ModelSim.
Routines written in Verilog have been developed to perform I/Q-demodulation of a frequency modulated signal given valuesfrom a Analog Devices AD9874 chip. Different methods for I/Q-demodulation have been evaluated and among theseCORDIC has been chosen and implemented in Verilog. The code has to some extent been tested on a IGLOO nano FPGA but foremost been simulated and verified in ModelSim.

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Davari, Mahdad. "Improving an FPGA Optimized Processor." Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-71190.

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This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA. Instruction and data caches will be designed and implemented. Interrupt support will be added as well, preparing the microprocessor core to host operating systems. Thorough verification of the added modules is also emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps.

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Sasnauskas, Justas. "Neuroninio procesoriaus prototipas FPGA technologijoje." Master's thesis, Lithuanian Academic Libraries Network (LABT), 2005. http://vddb.library.lt/obj/LT-eLABa-0001:E.02~2005~D_20050525_105428-25828.

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In this paper it is described a method of creation of a neuroprocessor prototype, from high abstraction level to FPGA technology. Most common neuroprocessor architectures are overviewed, and canonical model of the neuroprocessor is created accordingly. Based on the canonical model the serial structure neuroprocessor mathematical model is formed and evaluated. The model is than described in SystemC programming language. In the experimental part, the correct functionality of the neuroprocessor is evaluated and the results of synthesis are analyzed.

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Khalid, Ahmed Usman. "FPGA emulation of quantum circuits." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=98979.

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In recent years, new and novel forms of computation employing different natural phenomena such as the spin of atoms or the orientation of protein molecules have been proposed and are in the very initial stages of development. One of the most promising of these new computation techniques is quantum computing that employs various physical effects observed at the quantum level to provide significant improvement in certain computation tasks such as data search and factorization. An assortment of software-based simulators of quantum computers have been developed recently to assist in the development of this new computation process. However, efficiently simulating quantum algorithms at the software level is quite challenging since the algorithms have exponential run-times and memory requirements. Furthermore, the sequential nature of software-based computation makes simulating the parallel nature of quantum computation exceedingly difficult. In this thesis, the first hardware-based quantum algorithm emulation technique is presented. The emulator uses FPGA technology to model quantum circuits. Parallel computation available at the hardware level allows considerable speed-up as compared to the state-of-the-art software simulators as well as provides a greater insight into precision requirements for simulating quantum circuits.

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Leaver, Andrew C. "FPGA design and systems compilation." Thesis, University of Oxford, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.296767.

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Nigania, Nimit. "FPGA prototyping of custom GPGPUs." Thesis, Georgia Institute of Technology, 2014. http://hdl.handle.net/1853/51966.

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Prototyping new systems on hardware is a time-consuming task with limited scope for architectural exploration. The aim of this work was to perform fast prototyping of general-purpose graphics processing units (GPGPUs) on field programmable gate arrays (FPGAs) using a novel tool chain. This hardware flow combined with the higher level simulation flow using the same source code allowed us to create a whole tool chain to study and build future architectures using new technologies. It also gave us enough flexibility at different granularities to make architectural decisions. We will also discuss some example systems that were built using this tool chain along with some results.

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Zhao, Jin. "Video/Image Processing on FPGA." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-theses/503.

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Video/Image processing is a fundamental issue in computer science. It is widely used for a broad range of applications, such as weather prediction, computerized tomography (CT), artificial intelligence (AI), and etc. Video-based advanced driver assistance system (ADAS) attracts great attention in recent years, which aims at helping drivers to become more concentrated when driving and giving proper warnings if any danger is insight. Typical ADAS includes lane departure warning, traffic sign detection, pedestrian detection, and etc. Both basic and advanced video/image processing technologies are deployed in video-based driver assistance system. The key requirements of driver assistance system are rapid processing time and low power consumption. We consider Field Programmable Gate Array (FPGA) as the most appropriate embedded platform for ADAS. Owing to the parallel architecture, an FPGA is able to perform high-speed video processing such that it could issue warnings timely and provide drivers longer time to response. Besides, the cost and power consumption of modern FPGAs, particular small size FPGAs, are considerably efficient. Compared to the CPU implementation, the FPGA video/image processing achieves about tens of times speedup for video-based driver assistance system and other applications.

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46

Similä, L. (Lauri). "SPI-väylän toteutus FPGA-piirille." Bachelor's thesis, University of Oulu, 2018. http://jultika.oulu.fi/Record/nbnfioulu-201905081630.

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Tiivistelmä. Tässä työssä toteutetaan SPI-väyläprotokolla SystemVerilog-kovonkuvauskielellä. Suunnittelun pohjana käytetään Motorolan SPI-väyläprotokollaa. Aluksi perehdytään väyläprotokollan teoriaan, minkä jälkeen luodaan SPI-väylän rekisterisiirtotason malli. Mallin toiminta varmennetaan simulointiohjelmalla, ja sille ajetaan FPGA-synteesi. Lopullista porttitason mallia verrataan rekisterisiirtotason malliin ja todetaan mallien yhtäpitävyys.Implementation of SPI on FPGA board. Abstract. In this project, a Serial Peripheral Interface is implemented with SystemVerilog hardware description language. The design is based on Motorola’s SPI specification. At first, the theory of Serial Peripheral Interface is presented, and after that, a register-transfer level design is created. The logic behaviour of the design is verified by simulation. The design is synthesized for a specific FPGA board. In the end, the final gate level model is compared to the register-transfer level model.

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Samal, Kruttidipta. "FPGA acceleration of CNN training." Thesis, Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/54467.

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This thesis presents the results of an architectural study on the design of FPGA- based architectures for convolutional neural networks (CNNs). We have analyzed the memory access patterns of a Convolutional Neural Network (one of the biggest networks in the family of deep learning algorithms) by creating a trace of a well-known CNN architecture and by developing a trace-driven DRAM simulator. The simulator uses the traces to analyze the effect that different storage patterns and dissonance in speed between memory and processing element, can have on the CNN system. This insight is then used create an initial design for a layer architecture for the CNN using an FPGA platform. The FPGA is designed to have multiple parallel-executing units. We design a data layout for the on-chip memory of an FPGA such that we can increase parallelism in the design. As the number of these parallel units (and hence parallelism) depends on the memory layout of input and output, particularly if parallel read and write accesses can be scheduled or not. The on-chip memory layout minimizes access contention during the operation of parallel units. The result is an SoC (System on Chip) that acts as an accelerator and can have more number of parallel units than previous work. The improvement in design was also observed by comparing post synthesis loop latency tables between our design and one with a single unit design. This initial design can help in designing FPGAs targeted for deep learning algorithms that can compete with GPUs in terms of performance.

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Junttila, J. (Joel). "I2S-väyläliitynnän toteutus FPGA-piirille." Bachelor's thesis, University of Oulu, 2017. http://urn.fi/URN:NBN:fi:oulu-201612303346.

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Tutkimuksen aiheena oli tehdä toimiva I2S-väylä protokolla ja tutkia voiko piiriä luoda FPGA-piirille. Piirille tehtiin RTL-toteutus SystemVerilog kovonkuvauskielellä. Sen jälkeen piirille ajettiin FPGA-synteesi Alteran Cyclone 5 GX FPGA-piirille. Suurin kellotaajuus oli 263,5 MHz ja logiikkalohkoja käytettiin 18 kappaletta. Lopuksi tutkittiin päästiinkö tavotteisiin
The subject of the Bachelor’s Thesis was to create a workable I2S bus protocol and to examine if it is possible to create the I2S circuit to FPGA. RTL-model was made to the circuit with a hardware description language SystemVerilog. After that FPGA synthesis was execute to the Altera’s Cyclone 5 GX. The maximum clock frequency was 263,5 MHz and 18 logic blocks were used. Finally, the end results were examined to see if they met the objectives of this study

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Mocho, Renato Ubiratan Reis. "Circuitos assíncronos na plataforma FPGA." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2006. http://hdl.handle.net/10183/8765.

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Os circuitos digitais cada vez mais são exigidos quanto ao desempenho e modularidade nos processos dos dias atuais. Para resolver estes processos, o comércio utiliza largamente circuitos digitais síncronos, que se baseiam no controle do sincronismo através de um relógio central. Esses circuitos, apesar de serem de fácil implementação e terem uma metodologia já conhecida, apresentam limitações quando se considera a distribuição dos sinais de sincronismo, a interferência do meio e os possíveis atrasos. Os circuitos assíncronos apresentam uma solução natural a essas exigências, uma vez que, possuem independência do sinal do relógio e toda sua construção é modular. Este trabalho apresenta um estudo comparativo de alguns estilos de projetos para construção de circuitos assíncronos utilizando dispositivos programados por lógica, PLDs, utilizando ferramentas de síntese lógica comerciais para circuitos síncronos. Esses circuitos assíncronos são descritos em VHDL para as células Muller, elementos M de N, registrador assíncrono, somadores e circuitos mais complexos em anel assíncrono e implementados em CPLDs e FPGAs. Os circuitos mais complexos são construídos em quatro estilos de projeto para os circuitos dos somadores: Descrição comportamental com indicação forte do sinal, DIMS, NCL e derivação a partir de circuito combinacional síncrono. Através dessa avaliação foi possível verificar as tendências do custo de elementos de programação e atrasos para realização de cálculos, frente aos circuitos síncronos similares.
This work presents a study about the implementation of asynchronous circuits on programmable devices platform. It investigates four different ways of implementing asynchronous circuits, including implementation of several different circuits in platforms provided by three different manufacturers. The implemented asynchronous circuits have a very poor performance when compared to their synchronous counterpart. However, this was expected as the platforms used were developed to be used with synchronous designs. The contributions of this work are in the following areas. First, it was described in detail how to implement VHDL code for self-timed designs. Second, different design were implemented to test the VHDL descriptions in the chosen platforms. Third, by comparing four different asynchronous styles, it is possible to find a style that is the more adequate for use in current FPGAs. Fourth, by analyzing the results obtained, it was possible to derive some conclusions on why asynchronous designs are so costly for these platforms and derive some suggestions to be used in the implementation of asynchronous FPGAs.

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Náplava, Tomáš. "Přehrávač MP3 souborů v FPGA." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2012. http://www.nusl.cz/ntk/nusl-236597.

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This work deals with the design and implementation of a hardware unit that is capable of playing MPEG-1 Layer III files, compliant with ISO/IEC 11172-3. There are given the benefits of using the MP3 format and principles that make it possible to compress the size of the resulting music recordings. The file format and all parts of the header are thoroughly studied as well as the method of encoding information. The process of the data decoding is divided into several consecutive, more or less discrete functional units and these units are designed and described in a hardware description language VHDL. There are also discussed features of FPGA chips - programmable gate arrays. Those are used for physical realization of the MP3 player. A development board is selected, including such an FPGA chip and other resources that allow synthesis of the entire circuit and playback in real time.

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Dissertations / Theses on the topic 'FPGA'

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