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Dissertations / Theses on the topic 'FPGA resources'
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Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191286.
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Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum.
This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface.
A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow.
This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.
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Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-231445.
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The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is requiredDas Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt
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Iordache, Ancuta. "Performance-cost trade-offs in heterogeneous clouds." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S045/document.
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Les infrastructures de cloud fournissent une grande variété de ressources de calcul à la demande avec différents compromis coût-performance. Cela donne aux utilisateurs des nombreuses opportunités pour exécuter leurs applications ayant des besoins complexes en ressources, à partir d’un grand nombre de serveurs avec des interconnexions à faible latence jusqu’à des dispositifs spécialisés comme des GPUs et des FPGAs. Les besoins des utilisateurs concernant l’exécution de leurs applications peuvent varier entre une exécution la plus rapide possible, la plus chère ou un compromis entre les deux. Cependant, le choix du nombre et du type des ressources à utiliser pour obtenir le compromis coût-performance que les utilisateurs exigent constitue un défi majeur. Cette thèse propose trois contributions avec l’objectif de fournir des bons compromis coût-performance pour l’exécution des applications sur des plates-formes hétérogènes. Elles suivent deux directions : un bon usage des ressources et un bon choix des ressources. Nous proposons comme première contribution une méthode de partage pour des accélérateurs de type FPGA dans l’objectif de maximiser leur utilisation. Dans une seconde contribution, nous proposons des méthodes de profilage pour la modélisation de la demande en ressources des applications. Enfin, nous démontrons comment ces technologies peuvent être intégrées dans une plate-forme de cloud hétérogèneCloud infrastructures provide on-demand access to a large variety of computing devices with different performance and cost. This creates many opportunities for cloud users to run applications having complex resource requirements, starting from large numbers of servers with low-latency interconnects, to specialized devices such as GPUs and FPGAs. User expectations regarding the execution of applications may vary between the fastest possible execution, the cheapest execution or any trade-off between the two extremes. However, enabling cloud users to easily make performance-cost trade-offs is not a trivial exercise and choosing the right amount and type of resources to run applications accordingto user expectations is very difficult. This thesis proposes three contributions to enable performance-cost trade-offs for application execution in heterogeneous clouds by following two directions: make good use of resources and make good choice of resources. We propose as a first contribution a method to share FPGA-based accelerators in cloud infrastructures having the objective to improve their utilization. As a second contribution we propose profiling methods to automate the selection of heterogeneous resources for executing applications under user objectives. Finally, we demonstrate how these technologies can be implemented and exploited in heterogeneous cloud platforms
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Hassan, Mohamed Nabil. "Low resource scalable elliptic curve cryptography on FPGA." Thesis, University of Sheffield, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.522417.
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Lam, Andrew H. "An analytical model of logic resource utilization for FPGA architecture development." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/19753.
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Designers constantly strive to improve Field-Programmable Gate Array (FPGA) performance through innovative architecture design. To evaluate performance, an understanding of the effects of modifying logic blocks structures and routing fabrics on performance is needed. Current architectures are evaluated via computer-aided design (CAD) simulations that are labourious and computationally-expensive experiments to perform. A more scientific method, based on understanding the relationships between architectural parameters and performance will enable the rapid evaluation of new architectures, even before the development of a CAD tool.
This thesis presents an analytical model that describes such relationships and is based principally on Rent’s Rule. Specifically, it relates logic architectural parameters to the area efficiency of an FPGA. Comparison to experimental results show that our model is accurate. This accuracy combined with the simple form of the model’s equations make it a powerful tool for FPGA architects to better understand and guide the development of future FPGA architectures.
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Hinnerson, Martin. "A Resource Efficient, HighSpeed FPGA Implementation of Lossless Image Compression for 3D Vision." Thesis, Linköpings universitet, Datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-165300.
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High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless compression algorithms and the implementation operate at 214.3 MHz with a max throughput of 3.43 Gbit/s. The compression ratio is compared to that of competing implementations from Teledyne DALSA Inc. and Pleora Technologies on a set of typical 3D range data images. The proposed algorithm achieve a higher compression ratio while maintaining a small hardware footprint.
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Thangella, Praneeth Kumar, and Aravind Reddy Gundla. "Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16547.
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AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.
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Tolmie, Donald Francois. "Design of a low-resource 2D graphics engine for FPGAs." Master's thesis, Faculty of Engineering and the Built Environment, 2018. http://hdl.handle.net/11427/30042.
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This study focused on the design and implementation of a low-resource graphics engine, MicroGE, which can be implemented on an FPGA. MicroGE uses a minimal amount of FPGA resources when compared to other graphics engines. After researching existing graphics engines, it was discovered that most make use of a memory space to store frame buffer data. Because of the restrictions that were imposed on the design of MicroGE, it could not incorporate a large enough memory space to store a frame buffer. It was specified that MicroGE should be able to fit on low-resource FPGAs, without any external memory components. Also, MicroGE should be able to fit on modern, high-resource, FPGAs without using a significant amount of those FPGAs’ resources. These goals were achieved by designing MicroGE according to an architecture which differs from the ones of existing graphics engines. MicroGE only renders parts of the video frame, which can be stored in a small memory space, before those parts are transmitted to an HDMI or DVI monitor. After the design was completed, MicroGE, along with other components, was implemented in a VHDL design. Hardware was developed, which contained a Spartan-6 LX25 FPGA, to verify this VHDL. Other verification methods, including the use of VHDL test benches, were also used to verify the VHDL design. A software library, MGAPI, was developed on an Arduino Due microcontroller board. This software library allowed the Arduino Due to display graphics on an HDMI monitor via MicroGE. The Arduino Due was able to update the display of 1000 graphics primitives within 111 ms. The internal FPGA RAM resource usage of MicroGE, 792 kb, was found to be significantly lower than the amount of memory required for a frame buffer. Even though these results were satisfactory, there are still many improvements that can be made to MicroGE. These improvements include increasing the number of rendering capabilities, optimisation of power usage, and increasing the control and video output interfaces.
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Yao, Jia Stroud Charles E. "Built-In self-test of global routing resources in Virtex-4 FPGAs." Auburn, Ala., 2009. http://hdl.handle.net/10415/1723.
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Simons, Taylor Scott. "High-Speed Image Classification for Resource-Limited Systems Using Binary Values." BYU ScholarsArchive, 2021. https://scholarsarchive.byu.edu/etd/9097.
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Image classification is a memory- and compute-intensive task. It is difficult to implement high-speed image classification algorithms on resource-limited systems like FPGAs and embedded computers. Most image classification algorithms require many fixed- and/or floating-point operations and values. In this work, we explore the use of binary values to reduce the memory and compute requirements of image classification algorithms. Our objective was to implement these algorithms on resource-limited systems while maintaining comparable accuracy and high speeds. By implementing high-speed image classification algorithms on resource-limited systems like embedded computers, FPGAs, and ASICs, automated visual inspection can be performed on small low-powered systems. Industries like manufacturing, medicine, and agriculture can benefit from compact, high-speed, low-power visual inspection systems. Tasks like defect detection in manufactured products and quality sorting of harvested produce can be performed cheaper and more quickly. In this work, we present ECO Jet Features, an algorithm adapted to use binary values for visual inspection. The ECO Jet Features algorithm ran 3.7x faster than the original ECO Features algorithm on embedded computers. It also allowed the algorithm to be implemented on an FPGA, achieving 78x speedup over full-sized desktop systems, using a fraction of the power and space. We reviewed Binarized Neural Nets (BNNs), neural networks that use binary values for weights and activations. These networks are particularly well suited for FPGA implementation and we compared and contrasted various FPGA implementations found throughout the literature. Finally, we combined the deep learning methods used in BNNs with the efficiency of Jet Features to make Neural Jet Features. Neural Jet Features are binarized convolutional layers that are learned through deep learning and learn classic computer vision kernels like the Gaussian and Sobel kernels. These kernels are efficiently computed as a group and their outputs can be reused when forming output channels. They performed just as well as BNN convolutions on visual inspection tasks and are more stable when trained on small models.
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Fowers, Spencer G. "Limited Resource Feature Detection, Description, and Matching." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/3207.
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The aims of this research work are to develop a feature detection, description, and matching system for low-resource applications. This work was motivated by the need for a vision sensor to assist the flight of a quad-rotor UAV. This application presented a real-world challenge of autonomous drift stabilization using vision sensors. The initial solution implemented a basic feature detector and matching system on an FPGA. The research then pursued ways to improve the vision system. Research began with color feature detection, and the Color Difference of Gaussians feature detector was developed. CDoG provides better results than gray scale DoG and does not require any additional processing than gray scale if implemented in a parallel architecture. The CDoG Scale-Invariant Feature Transform modification was developed which provided color feature detection and description to the gray scale SIFT descriptor. To demonstrate the benefits of color information, the CDSIFT algorithm was applied to a real application: library book inventory. While color provides added benefit to the CDSIFT descriptor, CDSIFT descriptors are still computationally intractable for a low-resource hardware implementation. Because of these shortcomings, this research focused on developing a new feature descriptor. The BAsis Sparse-coding Inspired Similarity (BASIS) descriptor was developed with low-resource systems in mind. BASIS utilizes sparse coding to provide a generic description of feature characterstics. The BASIS descriptor provided improved accuracy over SIFT, and similar accuracy to SURF on the task of aerial UAV frame-to-frame feature matching. However, basis dictionaries are non-orthogonal and can contain redundant information. In addition to a feature descriptor, an FPGA-based feature correlation (or matching) system needed to be developed. TreeBASIS was developed to answer this need and address the redundancy issues of BASIS. TreeBASIS utilizes a vocabulary tree to drastically reduce descriptor computation time and descriptor size. TreeBASIS also obtains a higher level of accuracy than SIFT, SURF, and BASIS on the UAV aerial imagery task. Both BASIS and TreeBASIS were implemented in VHDL and are well suited for low-resource FPGA applications. TreeBASIS provides a complete feature detection, description, and correlation system-on-a-chip for low-resource FPGA vision systems.
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Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем." Thesis, Національний аерокосмічний університет ім. М. Є. Жуковського "Харківський авіаційний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38557.
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Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р.
Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з урахуванням заданої пріоритетної характеристики. У дисертаційній роботі вперше запропоновано модель мультипараметризовних проектів програмованої логіки, яка враховує можливість зміни розрядності і інтерпретації вхід-вихідних даних, функцій та архітектур компонентів і проектів на їх основі, що дозволяє сформувати множину варіантів для реалізації з потрібною продуктивністю і надійністю при обмежених апаратних ресурсах кристала. Вдосконалено метод розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем який відрізняється від відомих можливістю вибору архітектури і паралельної або послідовної реалізації компонентів проекту, що дозволяє підвищити продуктивність або скоротити обсяг апаратних ресурсів. Отримав подальший розвиток метод підвищення надійності вбудованих систем на програмовній логіці який відрізняється від відомих можливістю конфігурації різних варіантів відмовостійких архітектур, що дозволяє підвищити стійкість до збоїв та відмов. Проведено експериментальне дослідження кількості необхідних ресурсів програмовної логіки для мультипараметризовної реалізації арифметичних операцій, в тому числі реалізацію параметризовних суматорів і помножувачів.PhD Thesis for scientific degree candidate of technical sciences in the specialty 05.13.05 – computer systems and components. – National Technical University "Kharkіv Polytechnic Institute", Ministry of Education and Science of Ukraine, Kharkіv 2018. The dissertation solves scientific and technical tasks – developing of methods and tools of multiparametrized PLD-based projects prototyping for embedded systems. The goal of the work is to reduce the number of required resources, to increase the productivity or to increase the reliability of FPGA-based embedded systems depending on the provided priority characteristic. In PhD thesis the model of multiparametrized FPGA-based projects is proposed, which takes into account the possibility of changing the bit depth and interpretation of input-output information, functions and architectures of components and projects based on them, which allows to generate many variants for implementation with the required performance and reliability within limited hardware resources of the chip. The method for developing of multiparametrized FPGA-based projects for embedded systems has been improved and now, unlike known ones, provides the ability to choice of architecture and parallel or sequential way of project components implementation, which allows to increase productivity or reduce the amount of hardware resources. The method of reliability improvement of FPGA-based embedded systems has been further developed and now, unlike known ones, provides possibility of various pre developed redundant architectures configuring, which increases the tolerance to SEU and failures. The suggested model, methods and tools have been implemented during development of FPGA based embedded systems in aviation ice-protection system for plane AN-140, medical systems, for RS-codes, cryptographic hash functions and 5 algorithms of block ciphers, including AES, DES and IDEA.
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Перепелицин, Артем Євгенович. "Методи і засоби розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем." Thesis, Національний технічний університет "Харківський політехнічний інститут", 2018. http://repository.kpi.kharkov.ua/handle/KhPI-Press/38548.
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Дисертація на здобуття наукового ступеня кандидата технічних наук (доктора філософії) за спеціальністю 05.13.05 "Комп'ютерні системи та компоненти". – Національний технічний університет "Харківський політехнічний інститут", Харків, 2018 р.
Дисертаційна робота присвячена розв'язанню важливої науково-технічної задачі, яка полягає в розробленні методів і засобів створення мультипараметризовних проектів програмованої логіки для вбудованих систем. Метою роботи є скорочення кількості необхідних ресурсів, підвищення продуктивності або підвищення надійності вбудованих систем на програмовної логіці з урахуванням заданої пріоритетної характеристики. У дисертаційній роботі вперше запропоновано модель мультипараметризовних проектів програмованої логіки, яка враховує можливість зміни розрядності і інтерпретації вхід-вихідних даних, функцій та архітектур компонентів і проектів на їх основі, що дозволяє сформувати множину варіантів для реалізації з потрібною продуктивністю і надійністю при обмежених апаратних ресурсах кристала. Вдосконалено метод розроблення мультипараметризовних проектів програмованої логіки для вбудованих систем який відрізняється від відомих можливістю вибору архітектури і паралельної або послідовної реалізації компонентів проекту, що дозволяє підвищити продуктивність або скоротити обсяг апаратних ресурсів. Отримав подальший розвиток метод підвищення надійності вбудованих систем на програмовній логіці який відрізняється від відомих можливістю конфігурації різних варіантів відмовостійких архітектур, що дозволяє підвищити стійкість до збоїв та відмов. Проведено експериментальне дослідження кількості необхідних ресурсів програмовної логіки для мультипараметризовної реалізації арифметичних операцій, в тому числі реалізацію параметризовних суматорів і помножувачів.PhD Thesis for scientific degree candidate of technical sciences in the specialty 05.13.05 – computer systems and components. – National Technical University "Kharkіv Polytechnic Institute", Ministry of Education and Science of Ukraine, Kharkіv 2018. The dissertation solves scientific and technical tasks – developing of methods and tools of multiparametrized PLD-based projects prototyping for embedded systems. The goal of the work is to reduce the number of required resources, to increase the productivity or to increase the reliability of FPGA-based embedded systems depending on the provided priority characteristic. In PhD thesis the model of multiparametrized FPGA-based projects is proposed, which takes into account the possibility of changing the bit depth and interpretation of input-output information, functions and architectures of components and projects based on them, which allows to generate many variants for implementation with the required performance and reliability within limited hardware resources of the chip. The method for developing of multiparametrized FPGA-based projects for embedded systems has been improved and now, unlike known ones, provides the ability to choice of architecture and parallel or sequential way of project components implementation, which allows to increase productivity or reduce the amount of hardware resources. The method of reliability improvement of FPGA-based embedded systems has been further developed and now, unlike known ones, provides possibility of various pre developed redundant architectures configuring, which increases the tolerance to SEU and failures. The suggested model, methods and tools have been implemented during development of FPGA based embedded systems in aviation ice-protection system for plane AN-140, medical systems, for RS-codes, cryptographic hash functions and 5 algorithms of block ciphers, including AES, DES and IDEA.
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Mollberg, Alexander. "A Resource-Efficient and High-Performance Implementation of Object Tracking on a Programmable System-on-Chip." Thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124044.
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The computer vision problem of object tracking is introduced and explained. An approach to interest point based feature detection and tracking using FAST and BRIEF is presented and the selection of algorithms suitable for implementation on a Xilinx Zynq7000 with an XC7Z020 field-programmable gate array (FPGA) is detailed. A modification to the smoothing strategy of BRIEF which significantly reduces memory utilization on the FPGA is presented and benchmarked against a reference strategy. Measures of performance and resource efficiency are presented and utilized in an iterative development process. A system for interest point based object tracking that uses FAST for feature detection and BRIEF for feature description with the proposed smoothing modification is implemented on the FPGA. The design is described and important design choices are discussed.
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Hartman, Garrett Sean. "Real-Time Color TreeBASIS Feature Matching on a Limited-Resource Hardware System." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/4002.
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This research has been conducted in order to create a robust, lightweight feature detecting and matching algorithm that builds upon the foundation set by the TreeBASIS algorithm. The goal is to create a color-based version of the TreeBASIS algorithm that uses less hardware resources than the original, is more accurate in its matching capabilities, can successfully be deployed on a resource-limited FPGA platform, and can process in real time. This thesis first presents the newly designed hardware tri-channel FAST Feature Detector that finds features in color. Next the TreeBASIS algorithm is analyzed to discover what improvements can be made in order to reduce its resource usage sufficiently to be able to run on the Xilinx Virtex-4 FX60 while processing color features. At the same time, a software version of the Color TreeBASIS algorithm is compared to the original algorithm and is found to have a 93.3% accuracy on a test set of aerial images, surpassing the accuracy of TreeBASIS by nearly 12%. Then the hardware is meticulously reviewed to discover even more optimizations that allow the Color TreeBASIS algorithm to easily fit onto the Virtex-4 FX60. Next a new application for the matching algorithm, object detection, is introduced as well as the hardware needed to support it. Finally the algorithm is tested on the FPGA system for object detection and is able to successfully identify objects at 60 FPS. Color TreeBASIS proves itself to be more accurate than the TreeBASIS algorithm in the aerial images tests, it ends up using less memory and logic resources than its predecessor, even though it processes three times as much data, it is successfully deployed on a resource-limited FPGA system, and it shows accurate results in real-time object identification, generating an accurate homography 20 to 45% of the time while processing matches at a rate of 60 FPS.
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Al, Rawashdeh Khaled. "Toward a Hardware-assisted Online Intrusion Detection System Based on Deep Learning Algorithms for Resource-Limited Embedded Systems." University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1535464571843315.
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Young, Jeffrey Scott. "Global address spaces for efficient resource provisioning in the data center." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50261.
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The rise of large data sets, or "Big Data'', has coincided with the rise of clusters with large amounts of memory and GPU accelerators that can be used to process rapidly growing data footprints. However, the complexity and performance limitations of sharing memory and accelerators in a cluster limits the options for efficient management and allocation of resources for applications. The global address space model (GAS), and specifically hardware-supported GAS, is proposed as a means to provide a high-performance resource management platform upon which resource sharing between nodes and resource aggregation across nodes
can take place. This thesis builds on the initial concept of GAS with a model that is matched to "Big Data'' computing and its data transfer requirements.
The proposed model, Dynamic Partitioned Global Address Spaces (DPGAS), is implemented using a commodity converged interconnect, HyperTransport over Ethernet (HToE), and a software framework, the Oncilla runtime and API. The DPGAS model and associated hardware and software components are used to investigate two application spaces, resource sharing for time-varying workloads and
resource aggregation for GPU-accelerated data warehousing applications. This work demonstrates that hardware-supported GAS can be used improve the performance and power consumption of memory-intensive applications, and that it can be used to simplify host and accelerator resource management in the data center.
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Mahmood, Adnan, and Zaheer Ahmed Mohammed. "DESIGN AND PROTOTYPE OF RESOURCE NETWORK INTERFACES FOR NETWORK ON CHIP." Thesis, Jönköping University, JTH, Computer and Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:hj:diva-11114.
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Network on Chip (NoC) has emerged as a competitive and efficient communication infrastructure for the core based design of System on Chip. Resource (core), router and interface between router and core are the three main parts of a NoC. Each core communicates with the network through the interface, also called Resource Network Interface (RNI). One approach to speed up the design at NoC based systems is to develop standardized RNI. Design of RNI depends to some extent on the type of routing technique used in NoC. Control of route decision base the categorization of source and distributed routing algorithms. In source routing a complete path to the destination is provided in the packet header at the source, whereas in distributed routing, the path is dynamically computed in routers as the packet moves through the network. Buffering, flitization, deflitization and transfer of data from core to router and vice versa, are common responsibilities of RNI in both types of routing. In source routing, RNI has an extra functionality of storing complete paths to all destinations in tables, extracting path to reach a desired destination and adding it in the header flit. In this thesis, we have made an effort towards designing and prototyping a standardized and efficient RNI for both source and distributed routing. VHDL is used as a design language and prototyping of both types RNI has been carried out on Altera DE2 FPGA board. Testing of RNI was conducted by using Nios II soft core. Simulation results show that the best case flit latency, for both types RNI is 4 clock cycles. RNI design is also resource efficient because it consumes only 2% of the available resources on the target platform.
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Sun, Hua. "Throughput constrained and area optimized dataflow synthesis for FPGAS." Diss., CLICK HERE for online access, 2008. http://contentdm.lib.byu.edu/ETD/image/etd2276.pdf.
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Hireche, Chabha. "Etude et implémentation sur SoC-FPGA d'une méthode probabiliste pour le contrôle de mission de véhicule autonome Embedded context aware diagnosis for a UAV SoC platform, in Microprocessors and Microsystems 51, June 2017 Context/Resource-Aware Mission Planning Based on BNs and Concurrent MDPs for Autonomous UAVs, in MDPI-Sensors Journal, December 2018." Thesis, Brest, 2019. http://www.theses.fr/2019BRES0067.
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Les systèmes autonomes embarquent différents types de capteurs, d’applications et de calculateurs puissants. Ils sont donc utilisés dans différents domaines d’application et réalisent diverses missions simples ou complexes. Ces missions se déroulent souvent dans des environnements non déterministes avec la présence d’évènements aléatoires pouvant perturber le déroulement de la mission. Il est donc nécessaire d’évaluer régulièrement l’état de santé du système et de ses composants matériels et logiciels dans le but de détecter les défaillances à l’aide de réseaux Bayésiens. Par la suite, une décision est prise par le planificateur de mission en générant un nouveau plan de mission assurant la continuité de la mission en réponse à l’événement détecté. Cette décision est prise à l’aide du modèle Markov Decision Process en fonction de contraintes telles que l’objectif de la mission, l’état de santé des capteurs et des applications embarqués, la stratégie de réalisation de la mission ‘stratégie safety’ ou ‘stratégie mission first’, etc. Comme les systèmes autonomes exécutent différentes tâches qui demandent différentes performances, il est nécessaire de penser à l’utilisation d’accélérateurs matériels sur SoC-FPGA dans le but de répondre aux contraintes de calculs hautes performances et décharger le CPU si besoinAutonomous systems embed different types of sensors, applications and powerful calculators. Thus, they are used in different fields of application and perform various simple or complex tasks. Generally, these missions are executed in nondeterministic environments with the presence of random events that can affect the mission's progress. Therefore, it is necessary to regularly assess the health of the system and its hardware and software components in order to detect failures using Bayesian Networks.Subsequently, a decision is made by the mission planner by generating a new mission plan that ensures the mission in response to the detected event. This decision is made using the Markov Decision Process model based on constraints such as the mission objective, the health status of sensors and embedded applications, the mission policy "safety policy" or "mission first policy", etc. As autonomous systems perform different tasks that require different performance, it is necessary to consider the use of hardware accelerators on SoC-FPGA in order to meet high-performance computing constraints and unload the CPU if needed
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Boukhtache, Seyfeddine. "Système de traitement d’images temps réel dédié à la mesure de champs denses de déplacements et de déformations." Thesis, Université Clermont Auvergne (2017-2020), 2020. http://www.theses.fr/2020CLFAC054.
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Cette thèse s’inscrit dans un cadre pluridisciplinaire. Elle traite de la problématique du temps réel et de celle des performances métrologiques en traitement d’images numériques. Elle s'intéresse plus particulièrement à la photomécanique. Il s'agit d'une discipline récente visant à développer et à utiliser au mieux des systèmes de mesure de champs entiers de petits déplacements et de petites déformations en surface de solides soumis à des sollicitations thermomécaniques. La technique utilisée dans cette thèse est la corrélation des images numériques (CIN), qui se trouve être l'une des plus employées dans cette communauté. Elle représente cependant des limitations à savoir un temps de calcul prohibitif et des performances métrologiques améliorables afin d'atteindre celles des capteurs ponctuels classiques comme les jauges de déformation.Ce travail s'appuie sur deux axes d'étude pour relever ce défi. Le premier repose sur l'optimisation de l'interpolation d'images qui est le traitement le plus coûteux dans la CIN. Une accélération est proposée en utilisant une implémentation matérielle parallélisée sur FPGA, tout en tenant compte de la consommation des ressources matérielles et de la précision. La principale conclusion est qu'un seul FPGA (dans les limites technologiques actuelles) ne suffit pas à implémenter l'intégralité de l'algorithme CIN. Un second axe d'étude a donc été proposé. Il vise à développer et à utiliser des réseaux de neurones convolutifs pour tenter d'atteindre à la fois des performances métrologiques meilleures que la CIN et un traitement en temps réel. Cette deuxième étude a montré l'efficacité d'un tel outil pour la mesure des champs de déplacements et de déformations. Elle ouvre de nouvelles perspectives en termes de performances métrologiques et de rapidité des systèmes de mesure de champsThis PhD thesis has been carried out in a multidisciplinary context. It deals with the challenge of real-time and metrological performance in digital image processing. This is particularly interesting in photomechanics. This is a recent field of activity, which consists in developing and using systems for measuring whole fields of small displacements and small deformations of solids subjected to thermomechanical loading. The technique targeted in this PhD thesis is Digital Images Correlation (DIC), which is the most popular measuring technique in this community. However, it has some limitations, the main one being the computing resources and the metrological performance, which should be improved to reach that of classic pointwise measuring sensors such as strain gauges.In order to address this challenge, this work relies on two main studies. The first one consists in optimizing the interpolation process because this is the most expensive treatment in DIC. Acceleration is proposed by using a parallel hardware implementation on FPGA, and by taking into consideration the consumption of hardware resources as well as accuracy. The main conclusion of this study is that a single FPGA (current technology) is not sufficient to implement the entire DIC algorithm. Thus, a second study has been proposed. It is based on the use of convolutional neural networks (CNNs) in an attempt to achieve both better metrological performance than CIN and real-time processing. This second study shows the relevance of using CNNs for measuring displacement and deformation fields. It opens new perspectives in terms of metrological performance and speed of full-field measuring systems
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Isaacson, Spencer W. "Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip." BYU ScholarsArchive, 2007. https://scholarsarchive.byu.edu/etd/971.
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Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. A simple real-time processor has been designed to provide support for a hardware-assisted real-time operating system providing fast context switches. As part of the hardware RTOS, the following have been implemented in hardware: scheduler, register banks, mutex, semaphore, queue, interrupts, event, and others. A novel circuit called the Task-Resource Matrix has been created to allow fast inter/intra processor communication and synchronization.
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Hung, Yu-Shan, and 洪羽珊. "performance driven FPGA partitioning with complex resources." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/96617730412697036494.
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碩士中原大學
資訊工程研究所
89
To shorten time to market , the architecture , FPGA, is used widely. Because the circuit is larger and more complex, it is necessary to partition a large circuit to several sub-circuits. Although a FPGA is programmable, the chief shortcoming of FPGA is poor performance, so that many real time systems can not implemented by FPGAs, especially when we deal with the problem of FPGA partitioning, the performance problem is more serious. We will partition the circuit to several different FPGAs and the delay of the wires cross two FPGAs is larger. We hope to decrease the delay of the critical path to achieve the performance driven goal. As the fabrication technology rapidly evolves, the FPGA with single resource is not enough, so the architecture of FPGA with complex resources is brought up. The Objective of our research is performance driven partitioning that partition the circuit to FPGAs with complex resources successfully with cost minimization. When we partition the circuit, we do not increase the delay of the critical path as far as possible. In the results of the experiments, we can see the algorithm not only partition the circuit with cost minimization but also improve the performance of the partitioning.
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Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, 2015. https://tud.qucosa.de/id/qucosa%3A29126.
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Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum.
This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface.
A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow.
This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.
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Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, 2017. https://tud.qucosa.de/id/qucosa%3A30681.
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The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is required.Das Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt.
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黃峻然. "A Rearrangeable Hierarchical Interconnection Structure for FPGA Routing Resource." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29154315050553224929.
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碩士國立臺灣海洋大學
資訊工程學系
98
Field Programmable Gate Arrays (FPGA’s) are now widely used for the implementation of digital circuits and many commercial products. Since the programmable switches usually have high resistance and capacitance and occupy a large area, the number of programmable switches used in an FPGA affects its speed performance, die size, and routability. In this thesis, we propose a rearrangeable hierarchical switching network (HSN) for the implementation of an FPGA. The main component of this HSN consists of polygonal switch blocks and crossbars. With the same size and the same number of switches as our HSN, a clique-based hierarchical switching network is shown not rearrangeable. The HSN can reduce the number of switches along interconnecting paths, such that the speed performance of an FPGA can be improved.
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Chen, Yen-Yu, and 陳彥宇. "FPGA Realization of a MIMO-OFDM System with Optimized Hardware Resource Utilization." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/04667297508207657216.
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碩士國立交通大學
電信工程系所
94
In recent years, orthogonal frequency division multiplexing (OFDM) becomes a key technology in the development of new wireless communication systems, enabling high data rate transmission, and is suitable for frequency selective channels caused by multipath propagation. On the other hand, multiple-input multiple-output (MIMO) technique has a great potential of delivering either a dramatic increase of throughput or improvement of link quality. Combined with the MIMO technique, OFDM systems become more suited to next generation wireless communications. In this thesis, we propose a total solution for building up a 2×2 MIMO-OFDM system on two FPGA-based platforms: a fast prototyping platform Aptix® MP3CF and a self-designed platform. There are two space-time algorithms adopted in our system, including Space-Time Block Coding (STBC) and Vertical Bell Labs Layered Space-Time (VBLAST). Furthermore, since fixed-point computation is adopted in our system due to the cost and complexity of floating-point hardware, we also propose a quantization algorithm which can not only minimize the hardware resource requirement but also constrain the quantization error within a specified limit when converting floating-point arithmetic to fixed-point arithmetic.
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Masrani, Divyang K. "Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low." 2006. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=442188&T=F.
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Hou, Guan-Hao, and 侯冠豪. "An FPGA-based 200-ps Resolution 16-channel Formatter with Low Resource Usage." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/t9fe25.
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碩士國立臺灣大學
電子工程學研究所
106
Automatic Test Equipment (ATE) is used to test the performance and features of the Inte-grated Circuit, and avoiding the defective ICs from entering to the market. Formatter in the ATE is the vital core module to load the symbol data by user’s defi-nition, and then generate the testing waveform for the circuit which should be measured. In this paper, it proposes a new way to generate the new symbol and time/format set table, and implements the muti-channel formatter on Xilinx Spatan-6 FPGA board. Using the especially designed for the programmable delay line as a sequential circuit, it can ac-curate control the timing of edge placement, and improve the accuracy of edge placement by calibration mechanism. At last, the 16-channel FPGA formatter implemented in this paper has 100 Msps generation frequency, 200 ps edge placement resolution, and high accuracy with the inte-gral nonlinearity error less than 0.5 LSB.
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Wei, Ya-Ti, and 魏雅笛. "Using Decision Trees to Improve Resource Utilization on FPGA-based Network Intrusion Detection System." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/89652649266820124688.
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碩士國立中央大學
資訊管理研究所
97
As network services become more and more important in our society, the demand for network security systems is increasing. Network intrusion detection systems (NIDS) provide an effective and secure solution to the network attacks and are widely used in enterprises. Many NIDSs, such as Snort, are based on software, so their processing speeds are much slower than wire-speed. FPGA technology has properties which are high speed string matching and reprogrammable, but the resources in FPGA are limited while the database of signatures has become very large and keeps growing. In this thesis we use decision tree to improve the utilization of resources when implementing NIDS on FPGA. The system uses decision tree to process the rule header to reduce resource requirements. Rule options are organized to multiple string matching groups according to the matching results of rule header. We implement an IDS circuit that process 1023 Snort rules at FPGA. The experimental results show that the system can reduce the average of resource by 56%. In addition, we develop a tool to automatically generate the Verilog HDL source code of the IDS circuit from a Snort rule set. Using the FPGA and the IDS circuit generator, the proposed system is able to update the matching rule corresponding to new intrusion and attacks.
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Chang, Yi-Fan, and 張奕凡. "Resource-Aware Asynchronous Circuit Synthesis on FPGA and a Case Study of Secure AES Design." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/xfhz93.
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碩士國立臺灣大學
電子工程學研究所
107
Asynchronous circuits have distinct advantages over their synchronous counterparts, e.g., in their security against side-channel attacks, resilience against process variation, robustness against environmental fluctuation, low electromagnetic interference, and ease of design composition, among other benefits. Among various asynchronous delay models, quasi-delay insensitive (QDI) circuits with dual-rail encoding are promising due to its relaxed timing assumption and timing robustness. Furthermore, dual-rail precharge logic (DRPL) has been considered to be a practical countermeasure method to mitigate information leakage in power consumption by dual-rail encoding. On the other hand, FPGA implementation becomes an essential building block in system-on-a-chip (SoC) design due to its reconfigurability. Compared to ASIC implementation, the reconfigurability of FPGAs also provides a convenient procedure for design adjustment against side-channel attacks through physical measurements. However, mapping QDI circuits on FPGA is challenging due to limited resources. In this thesis, we propose the effective implementation of asynchronous basic units on synchronous-based FPGA and show the design automation flow to synthesize more complex asynchronous design quickly. Besides, we propose the interface between synchronous and asynchronous domain for data transmission. Finally, to confirm the feasibility of our synthesis framework, we realize an Advanced Encryption Standard (AES) design and perform differential power analysis (DPA) to justify the security of asynchronous AES compared to its synchronous counterparts.
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Tseng, Su-Fen, and 曾淑芬. "Cost Minimization of Partitioned Circuits with Complex Resource Constraints in FPGAs." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/06409114514119696010.
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碩士中原大學
資訊工程學系
87
In FPGAs with complex resources, each circuit element can be implemented by variant resources and each resource can implement one ore more circuit elements. Usually it is difficult to randomly generate a feasible initial solution. In this thesis, we have solved this by maximum-matching method. A new cost minimization partitioning problem with complex resource constraints in FPGAs is formulated and solved. We first write the complex resources constraints in ILP model and use the ILP solver, LINGO, to find the types and numbers of FPGA chips needed to minimize the total cost. Once the FPGA chips are found, we then use the techniques of vertex ordering and maximum-matching to partition the given circuit according to the FPGA resources we found in ILP solver. The purpose of using maximum-matching and vertex ordering methods is trying to find a feasible partition with a smaller cut-size. Experimental results on the MCNC LGSynth91 benchmark shows that circuit according to the FPGA resources we found in ILP solver having 20% lower cost on average then the circuits using only one type FPGA. The proposed vertex ordering technique reduces the cost by 19% compared with the method without vertex ordering.
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Bridger, Andrew B. "Increasing the spectral efficiency of contunous phase modulation applied to digital microwave radio : a resource efficient FPGA receiver implementation : [a thesis presented in partial fulfilment of the requirements for the degree of Master of Engineering in Electronics and Computer Systems Engineering at Massey University, Palmerston North, New Zealand ] EMBARGED UNTIL 1 JUNE 2012." 2009. http://hdl.handle.net/10179/1366.
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In modern point to point microwave radio systems used to backhaul cellular voice and data traffic, quadrature amplitude modulation (QAM) is the norm. These systems require a highly linear power amplifier which is expensive and has relatively low power efficiency. Recently, continuous phase modulation (CPM) has been deployed in this market. The CPM transmitted waveform has a constant envelope and so a non-linear RF power amplifier can be used. This significantly reduces cost and improves power efficiency. Two important disadvantages of CPM are receiver complexity and inferior spectral efficiency compared to QAM. This thesis demonstrates a 50% spectral efficiency improvement over an existing CPM configuration without loss of detection efficiency. This is achieved by moving to coherent demodulation and extending the duration of the CPM phase pulse to 3 symbol periods. This new CPM configuration of h=1/4, M=4, L=3, is evaluated against ETSI requirements for a 28 MHz channel carrying 24 E1 circuits. Simulation of the receiver floating point model demonstrates all requirements are met. The detection efficiency requirement is exceeded by 4.7 dB. Carrier recovery, phase and timing synchronisation are assumed to be ideal. The 50% increased symbol rate, coherent reception and a longer smoother phase pulse, conspire to increase receiver complexity substantially. The Viterbi algorithm is used to perform maximum-likelihood detection resulting in a 128 state trellis. This application has a stringent cost requirement that limits the implementation target to a Field Programmable Gate Array (FPGA) costing less than US$30. To demonstrate this demanding cost target is met, the two most computationally expensive receiver functions, the branch metric unit and path metric processing unit, are implemented in VHDL and targeted to a Xilinx Spartan 3A-DSP 1800 FPGA. The implementation uses 67% of the available logic resources, thus meeting the cost requirement. The branch metric unit is implemented using a distributed arithmetic technique that performs the equivalent of 27.6 giga-multiplies/s, consuming only 23% of the available FPGA logic cells. This is very efficient compared to a conventional approach using all the FPGA’s embedded multipliers which combined can only achieve 21 giga-multiplies/s. The Viterbi path metric processing unit is implemented using a more conventional state-parallel architecture. To reduce state metric routing complexity, states are grouped into radix-4 units comprising dual add-compare-select (ACS) units. By utilising a spare cycle in the deep ACS pipeline, each ACS unit processes two output state metrics, thus halving the number of ACS units required. This implementation uses 44% of the available FPGA resources and meets timing at 204.5 MHz, exceeding the throughput requirement of 54 Mbit/s.
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Müller, Günter Stefan. "FTIR-ATR spectroscopic and FTIR-FPA microscopic investigations on panel board production processes using Grand fir (Abies grandis (Douglas ex D. Don) Lindl.) and European beech (Fagus sylvatica L.)." Doctoral thesis, 2008. http://hdl.handle.net/11858/00-1735-0000-0006-B10E-4.
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