Relevant bibliographies by topics / FPGA resources

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'FPGA resources'

Author: Grafiati
Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "FPGA resources"

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Caffarena, Gabriel, Juan A. López, Gerardo Leyva, Carlos Carreras, and Octavio Nieto-Taladriz. "Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs." International Journal of Reconfigurable Computing 2009 (2009): 1–14. http://dx.doi.org/10.1155/2009/703267.

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We address the automatic synthesis of DSP algorithms using FPGAs. Optimized fixed-point implementations are obtained by means of considering (i) a multiple wordlength approach; (ii) a complete datapath formed of wordlength-wise resources (i.e., functional units, multiplexers, and registers); (iii) an FPGA-wise resource usage metric that enables an efficient distribution of logic fabric and embedded DSP resources. The paper shows (i) the benefits of applying a multiple wordlength approach to the implementation of fixed-point datapaths and (ii) the benefits of a wise use of embedded FPGA resources. The use of a complete fixed-point datapath leads to improvements up to 35%. And, the wise mapping of operations to FPGA resources (logic fabric and embedded blocks), thanks to the proposed resource usage metric, leads to improvements up to 54%.
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Guo, Shuaizhi, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, and Xi Jin. "RP-Ring: A Heterogeneous Multi-FPGA Accelerator." International Journal of Reconfigurable Computing 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/6784319.

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To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.
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Liu, Huiqun, Kai Zhu, and D. F. Wong. "FPGA Partitioning with Complex Resource Constraints." VLSI Design 11, no. 3 (January 1, 2000): 219–35. http://dx.doi.org/10.1155/2000/12198.

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In this paper, we present an algorithm for circuit partitioning with complex resource constraints in large FPGAs. Traditional partitioning methods estimate the capacity of an FPGA device by counting the number of logic blocks, however this is not accurate with the increasing diverse resource types in the new FPGA architectures. We first propose a network flow based method to optimally check whether a circuit or a subcircuit is feasible for a set of available heterogeneous resources. Then the feasibility checking procedure is integrated in the FM-based algorithm for circuit partitioning. Incremental flow technique is employed for efficient implementation. Experimental results on the MCNC benchmark circuits show that our partitioning algorithm not only yields good results, but also is efficient. Our algorithm for partitioning with complex resource constraints is applicable for both multiple FPGA designs (e.g., logic emulation systems) and partitioning-based placement algorithms for a single large hierarchical FPGA (e.g., Actel's ES6500 FPGA family).
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Ullah, Anees, Ali Zahir, Noaman A. Khan, Waleed Ahmad, Alexis Ramos, and Pedro Reviriego. "BPR-TCAM—Block and Partial Reconfiguration based TCAM on Xilinx FPGAs." Electronics 9, no. 2 (February 19, 2020): 353. http://dx.doi.org/10.3390/electronics9020353.

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Field Programmable Gate Arrays (FPGAs) based Ternary Content Addressable Memories (TCAMs) are widely used in high-speed networking applications.However, TCAMs are not present on state-of-the-art FPGAs and need to be emulated on SRAM-based memories (i.e., LUTRAMs and Block RAMs) which requires a large amount of FPGA resources. In this paper, we present an efficient methodology to implement FPGA-based TCAMs with significant resource savings compared to existing schemes. The proposed methodology exploits the fracturable nature of Look Up Tables (LUTs) and the built-in slice carry-chains for simultaneous mapping of two rules and its matching logic to a single FPGA slice. Multiple slices can be stacked together to build deeper and wider TCAMs in a modular way. The combination of all these techniques results in significant savings in resource utilization compared to existing approaches.
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Cho, Mannhee, and Youngmin Kim. "FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit." Electronics 10, no. 22 (November 19, 2021): 2859. http://dx.doi.org/10.3390/electronics10222859.

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Convolutional neural networks (CNNs) are widely used in modern applications for their versatility and high classification accuracy. Field-programmable gate arrays (FPGAs) are considered to be suitable platforms for CNNs based on their high performance, rapid development, and reconfigurability. Although many studies have proposed methods for implementing high-performance CNN accelerators on FPGAs using optimized data types and algorithm transformations, accelerators can be optimized further by investigating more efficient uses of FPGA resources. In this paper, we propose an FPGA-based CNN accelerator using multiple approximate accumulation units based on a fixed-point data type. We implemented the LeNet-5 CNN architecture, which performs classification of handwritten digits using the MNIST handwritten digit dataset. The proposed accelerator was implemented, using a high-level synthesis tool on a Xilinx FPGA. The proposed accelerator applies an optimized fixed-point data type and loop parallelization to improve performance. Approximate operation units are implemented using FPGA logic resources instead of high-precision digital signal processing (DSP) blocks, which are inefficient for low-precision data. Our accelerator model achieves 66% less memory usage and approximately 50% reduced network latency, compared to a floating point design and its resource utilization is optimized to use 78% fewer DSP blocks, compared to general fixed-point designs.
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Alonso, Tobias, Lucian Petrica, Mario Ruiz, Jakoba Petri-Koenig, Yaman Umuroglu, Ioannis Stamelos, Elias Koromilas, Michaela Blott, and Kees Vissers. "Elastic-DF: Scaling Performance of DNN Inference in FPGA Clouds through Automatic Partitioning." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–34. http://dx.doi.org/10.1145/3470567.

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Customized compute acceleration in the datacenter is key to the wider roll-out of applications based on deep neural network (DNN) inference. In this article, we investigate how to maximize the performance and scalability of field-programmable gate array (FPGA)-based pipeline dataflow DNN inference accelerators (DFAs) automatically on computing infrastructures consisting of multi-die, network-connected FPGAs. We present Elastic-DF, a novel resource partitioning tool and associated FPGA runtime infrastructure that integrates with the DNN compiler FINN. Elastic-DF allocates FPGA resources to DNN layers and layers to individual FPGA dies to maximize the total performance of the multi-FPGA system. In the resulting Elastic-DF mapping, the accelerator may be instantiated multiple times, and each instance may be segmented across multiple FPGAs transparently, whereby the segments communicate peer-to-peer through 100 Gbps Ethernet FPGA infrastructure, without host involvement. When applied to ResNet-50, Elastic-DF provides a 44% latency decrease on Alveo U280. For MobileNetV1 on Alveo U200 and U280, Elastic-DF enables a 78% throughput increase, eliminating the performance difference between these cards and the larger Alveo U250. Elastic-DF also increases operating frequency in all our experiments, on average by over 20%. Elastic-DF therefore increases performance portability between different sizes of FPGA and increases the critical throughput per cost metric of datacenter inference.
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Wang, Gui Tang, Rui Huang Wang, Feng Wang, and Wen Juan Liu. "An Implementation and Improvement of Fast Two-Dimensional Median Filtering." Applied Mechanics and Materials 55-57 (May 2011): 95–100. http://dx.doi.org/10.4028/www.scientific.net/amm.55-57.95.

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This paper discussed a conventional fast median filtering algorithm for FPGA implementation. An improved way -- Quasi-median filtering algorithm -- have been proposed to reduce the occupancy rate of FPGA resources on the premise of ensuring the result of median filtering. Through the detailed analysis and comparison of results of simulation and experiments, conclusions can be drawn that such improvements can achieve better filtering results, and can reduce FPGA resource utilization. It offers some value for the application of design which requires more FPGA resources.
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Pérez, Ignacio, and Miguel Figueroa. "A Heterogeneous Hardware Accelerator for Image Classification in Embedded Systems." Sensors 21, no. 8 (April 9, 2021): 2637. http://dx.doi.org/10.3390/s21082637.

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Convolutional neural networks (CNN) have been extensively employed for image classification due to their high accuracy. However, inference is a computationally-intensive process that often requires hardware acceleration to operate in real time. For mobile devices, the power consumption of graphics processors (GPUs) is frequently prohibitive, and field-programmable gate arrays (FPGA) become a solution to perform inference at high speed. Although previous works have implemented CNN inference on FPGAs, their high utilization of on-chip memory and arithmetic resources complicate their application on resource-constrained edge devices. In this paper, we present a scalable, low power, low resource-utilization accelerator architecture for inference on the MobileNet V2 CNN. The architecture uses a heterogeneous system with an embedded processor as the main controller, external memory to store network data, and dedicated hardware implemented on reconfigurable logic with a scalable number of processing elements (PE). Implemented on a XCZU7EV FPGA running at 200 MHz and using four PEs, the accelerator infers with 87% top-5 accuracy and processes an image of 224×224 pixels in 220 ms. It consumes 7.35 W of power and uses less than 30% of the logic and arithmetic resources used by other MobileNet FPGA accelerators.
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Sauvage, Laurent, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, and Yves Mathieu. "Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/375245.

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FPGA design of side-channel analysis countermeasures using unmasked dual-rail with precharge logic appears to be a great challenge. Indeed, the robustness of such a solution relies on careful differential placement and routing whereas both FPGA layout and FPGA EDA tools are not developed for such purposes. However, assessing the security level which can be achieved with them is an important issue, as it is directly related to the suitability to use commercial FPGA instead of proprietary custom FPGA for this kind of protection. In this article, we experimentally gave evidence that differential placement and routing of an FPGA implementation can be done with a granularity fine enough to improve the security gain. However, so far, this gain turned out to be lower for FPGAs than for ASICs. The solutions demonstrated in this article exploit the dual-output of modern FPGAs to achieve a better balance of dual-rail interconnections. However, we expect that an in-depth analysis of routing resources power consumption could still help reduce the interconnect differential leakage.
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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>
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Dissertations / Theses on the topic "FPGA resources"

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Genßler, Paul Richard. "Virtualisation of FPGA-Resources for Concurrent User Designs Employing Partial Dynamic Reconfiguration." Thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2016. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-191286.

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Reconfigurable hardware in a cloud environment is a power efficient way to increase the processing power of future data centers beyond today\'s maximum. This work enhances an existing framework to support concurrent users on a virtualized reconfigurable FPGA resource. The FPGAs are used to provide a flexible, fast and very efficient platform for the user who has access through a simple cloud based interface. A fast partial reconfiguration is achieved through the ICAP combined with a PCIe connection and a combination of custom and TCL scripts to control the tool flow. This allows for a reconfiguration of a user space on a FPGA in a few milliseconds while providing a simple single-action interface to the user.
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Genßler, Paul R. "Virtualized Reconfigurable Resources and Their Secured Provision in an Untrusted Cloud Environment." Master's thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-231445.

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The cloud computing business grows year after year. To keep up with increasing demand and to offer more services, data center providers are always searching for novel architectures. One of them are FPGAs, reconfigurable hardware with high compute power and energy efficiency. But some clients cannot make use of the remote processing capabilities. Not every involved party is trustworthy and the complex management software has potential security flaws. Hence, clients’ sensitive data or algorithms cannot be sufficiently protected. In this thesis state-of-the-art hardware, cloud and security concepts are analyzed and com- bined. On one side are reconfigurable virtual FPGAs. They are a flexible resource and fulfill the cloud characteristics at the price of security. But on the other side is a strong requirement for said security. To provide it, an immutable controller is embedded enabling a direct, confidential and secure transfer of clients’ configurations. This establishes a trustworthy compute space inside an untrusted cloud environment. Clients can securely transfer their sensitive data and algorithms without involving vulnerable software or a data center provider. This concept is implemented as a prototype. Based on it, necessary changes to current FPGAs are analyzed. To fully enable reconfigurable yet secure hardware in the cloud, a new hybrid architecture is required
Das Geschäft mit dem Cloud Computing wächst Jahr für Jahr. Um mit der steigenden Nachfrage mitzuhalten und neue Angebote zu bieten, sind Betreiber von Rechenzentren immer auf der Suche nach neuen Architekturen. Eine davon sind FPGAs, rekonfigurierbare Hardware mit hoher Rechenleistung und Energieeffizienz. Aber manche Kunden können die ausgelagerten Rechenkapazitäten nicht nutzen. Nicht alle Beteiligten sind vertrauenswürdig und die komplexe Verwaltungssoftware ist anfällig für Sicherheitslücken. Daher können die sensiblen Daten dieser Kunden nicht ausreichend geschützt werden. In dieser Arbeit werden modernste Hardware, Cloud und Sicherheitskonzept analysiert und kombiniert. Auf der einen Seite sind virtuelle FPGAs. Sie sind eine flexible Ressource und haben Cloud Charakteristiken zum Preis der Sicherheit. Aber auf der anderen Seite steht ein hohes Sicherheitsbedürfnis. Um dieses zu bieten ist ein unveränderlicher Controller eingebettet und ermöglicht eine direkte, vertrauliche und sichere Übertragung der Konfigurationen der Kunden. Das etabliert eine vertrauenswürdige Rechenumgebung in einer nicht vertrauenswürdigen Cloud Umgebung. Kunden können sicher ihre sensiblen Daten und Algorithmen übertragen ohne verwundbare Software zu nutzen oder den Betreiber des Rechenzentrums einzubeziehen. Dieses Konzept ist als Prototyp implementiert. Darauf basierend werden nötige Änderungen von modernen FPGAs analysiert. Um in vollem Umfang eine rekonfigurierbare aber dennoch sichere Hardware in der Cloud zu ermöglichen, wird eine neue hybride Architektur benötigt
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Iordache, Ancuta. "Performance-cost trade-offs in heterogeneous clouds." Thesis, Rennes 1, 2016. http://www.theses.fr/2016REN1S045/document.

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Les infrastructures de cloud fournissent une grande variété de ressources de calcul à la demande avec différents compromis coût-performance. Cela donne aux utilisateurs des nombreuses opportunités pour exécuter leurs applications ayant des besoins complexes en ressources, à partir d’un grand nombre de serveurs avec des interconnexions à faible latence jusqu’à des dispositifs spécialisés comme des GPUs et des FPGAs. Les besoins des utilisateurs concernant l’exécution de leurs applications peuvent varier entre une exécution la plus rapide possible, la plus chère ou un compromis entre les deux. Cependant, le choix du nombre et du type des ressources à utiliser pour obtenir le compromis coût-performance que les utilisateurs exigent constitue un défi majeur. Cette thèse propose trois contributions avec l’objectif de fournir des bons compromis coût-performance pour l’exécution des applications sur des plates-formes hétérogènes. Elles suivent deux directions : un bon usage des ressources et un bon choix des ressources. Nous proposons comme première contribution une méthode de partage pour des accélérateurs de type FPGA dans l’objectif de maximiser leur utilisation. Dans une seconde contribution, nous proposons des méthodes de profilage pour la modélisation de la demande en ressources des applications. Enfin, nous démontrons comment ces technologies peuvent être intégrées dans une plate-forme de cloud hétérogène
Cloud infrastructures provide on-demand access to a large variety of computing devices with different performance and cost. This creates many opportunities for cloud users to run applications having complex resource requirements, starting from large numbers of servers with low-latency interconnects, to specialized devices such as GPUs and FPGAs. User expectations regarding the execution of applications may vary between the fastest possible execution, the cheapest execution or any trade-off between the two extremes. However, enabling cloud users to easily make performance-cost trade-offs is not a trivial exercise and choosing the right amount and type of resources to run applications accordingto user expectations is very difficult. This thesis proposes three contributions to enable performance-cost trade-offs for application execution in heterogeneous clouds by following two directions: make good use of resources and make good choice of resources. We propose as a first contribution a method to share FPGA-based accelerators in cloud infrastructures having the objective to improve their utilization. As a second contribution we propose profiling methods to automate the selection of heterogeneous resources for executing applications under user objectives. Finally, we demonstrate how these technologies can be implemented and exploited in heterogeneous cloud platforms
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Hassan, Mohamed Nabil. "Low resource scalable elliptic curve cryptography on FPGA." Thesis, University of Sheffield, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.522417.

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Lam, Andrew H. "An analytical model of logic resource utilization for FPGA architecture development." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/19753.

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Designers constantly strive to improve Field-Programmable Gate Array (FPGA) performance through innovative architecture design. To evaluate performance, an understanding of the effects of modifying logic blocks structures and routing fabrics on performance is needed. Current architectures are evaluated via computer-aided design (CAD) simulations that are labourious and computationally-expensive experiments to perform. A more scientific method, based on understanding the relationships between architectural parameters and performance will enable the rapid evaluation of new architectures, even before the development of a CAD tool. This thesis presents an analytical model that describes such relationships and is based principally on Rent’s Rule. Specifically, it relates logic architectural parameters to the area efficiency of an FPGA. Comparison to experimental results show that our model is accurate. This accuracy combined with the simple form of the model’s equations make it a powerful tool for FPGA architects to better understand and guide the development of future FPGA architectures.
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Hinnerson, Martin. "A Resource Efficient, HighSpeed FPGA Implementation of Lossless Image Compression for 3D Vision." Thesis, Linköpings universitet, Datorteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-165300.

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High speed laser-scanning cameras such as Ranger3 from SICK send 3D images with high resolution and dynamic range. Typically the bandwidth of the transmission link set the limit for the operational frequency of the system. This thesis show how a lossless image compression system in most cases can be used to reduce bandwidth requirements and allow for higher operational frequencies. A hardware encoder is implemented in pl on the ZC-706 development board featuring a ZYNQ Z7045 SoC. In addition, a software decoder is implemented in C++. The encoder is based on the felics and jpeg-ls lossless compression algorithms and the implementation operate at 214.3 MHz with a max throughput of 3.43 Gbit/s. The compression ratio is compared to that of competing implementations from Teledyne DALSA Inc. and Pleora Technologies on a set of typical 3D range data images. The proposed algorithm achieve a higher compression ratio while maintaining a small hardware footprint.
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Thangella, Praneeth Kumar, and Aravind Reddy Gundla. "Complex-Multiplier Implementation for Resource Flexible Pipelined FFTs in FPGAs." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-16547.

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AbstractDifferent approaches for implementing a complex multiplier in pipelined FFT are considered andimplemented to find an efficient one in this project. The implemented design is synthesized on Cyclone IIand Stratix III to know the performance. The design is implemented with a focus of reducing the resourcesused. Some approaches resulted in the reduced number of DSP blocks and others resulted in reducednumber of LUTs. Analysis of Synthesis results is performed for different widths (bit lengths) of complexmultiplier approaches.

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Tolmie, Donald Francois. "Design of a low-resource 2D graphics engine for FPGAs." Master's thesis, Faculty of Engineering and the Built Environment, 2018. http://hdl.handle.net/11427/30042.

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This study focused on the design and implementation of a low-resource graphics engine, MicroGE, which can be implemented on an FPGA. MicroGE uses a minimal amount of FPGA resources when compared to other graphics engines. After researching existing graphics engines, it was discovered that most make use of a memory space to store frame buffer data. Because of the restrictions that were imposed on the design of MicroGE, it could not incorporate a large enough memory space to store a frame buffer. It was specified that MicroGE should be able to fit on low-resource FPGAs, without any external memory components. Also, MicroGE should be able to fit on modern, high-resource, FPGAs without using a significant amount of those FPGAs’ resources. These goals were achieved by designing MicroGE according to an architecture which differs from the ones of existing graphics engines. MicroGE only renders parts of the video frame, which can be stored in a small memory space, before those parts are transmitted to an HDMI or DVI monitor. After the design was completed, MicroGE, along with other components, was implemented in a VHDL design. Hardware was developed, which contained a Spartan-6 LX25 FPGA, to verify this VHDL. Other verification methods, including the use of VHDL test benches, were also used to verify the VHDL design. A software library, MGAPI, was developed on an Arduino Due microcontroller board. This software library allowed the Arduino Due to display graphics on an HDMI monitor via MicroGE. The Arduino Due was able to update the display of 1000 graphics primitives within 111 ms. The internal FPGA RAM resource usage of MicroGE, 792 kb, was found to be significantly lower than the amount of memory required for a frame buffer. Even though these results were satisfactory, there are still many improvements that can be made to MicroGE. These improvements include increasing the number of rendering capabilities, optimisation of power usage, and increasing the control and video output interfaces.
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Yao, Jia Stroud Charles E. "Built-In self-test of global routing resources in Virtex-4 FPGAs." Auburn, Ala., 2009. http://hdl.handle.net/10415/1723.

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Simons, Taylor Scott. "High-Speed Image Classification for Resource-Limited Systems Using Binary Values." BYU ScholarsArchive, 2021. https://scholarsarchive.byu.edu/etd/9097.

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Image classification is a memory- and compute-intensive task. It is difficult to implement high-speed image classification algorithms on resource-limited systems like FPGAs and embedded computers. Most image classification algorithms require many fixed- and/or floating-point operations and values. In this work, we explore the use of binary values to reduce the memory and compute requirements of image classification algorithms. Our objective was to implement these algorithms on resource-limited systems while maintaining comparable accuracy and high speeds. By implementing high-speed image classification algorithms on resource-limited systems like embedded computers, FPGAs, and ASICs, automated visual inspection can be performed on small low-powered systems. Industries like manufacturing, medicine, and agriculture can benefit from compact, high-speed, low-power visual inspection systems. Tasks like defect detection in manufactured products and quality sorting of harvested produce can be performed cheaper and more quickly. In this work, we present ECO Jet Features, an algorithm adapted to use binary values for visual inspection. The ECO Jet Features algorithm ran 3.7x faster than the original ECO Features algorithm on embedded computers. It also allowed the algorithm to be implemented on an FPGA, achieving 78x speedup over full-sized desktop systems, using a fraction of the power and space. We reviewed Binarized Neural Nets (BNNs), neural networks that use binary values for weights and activations. These networks are particularly well suited for FPGA implementation and we compared and contrasted various FPGA implementations found throughout the literature. Finally, we combined the deep learning methods used in BNNs with the efficiency of Jet Features to make Neural Jet Features. Neural Jet Features are binarized convolutional layers that are learned through deep learning and learn classic computer vision kernels like the Gaussian and Sobel kernels. These kernels are efficiently computed as a group and their outputs can be reused when forming output channels. They performed just as well as BNN convolutions on visual inspection tasks and are more stable when trained on small models.
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Books on the topic "FPGA resources"

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(Illustrator), Geraldine Sponce, and Sean MacGarry (Illustrator), eds. Primary School Workbook (FPA Education & Training Resources). Family Planning Association, 1993.

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Massey, Doreen E., and Gill Lenderyou. Sex Education Factpack (FPA Education & Training Resources). 2nd ed. Family Planning Association, 1993.

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Masrani, Divyang K. Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low. 2006.

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Masrani, Divyang K. Expanding stereo-disparity range in an FPGA-system while keeping resource utilisation low. 2006, 2006.

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Book chapters on the topic "FPGA resources"

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León-Javier, Alejandro, Marco A. Moreno-Armendáriz, and Nareli Cruz-Cortés. "Designing a Compact Genetic Algorithm with Minimal FPGA Resources." In Advances in Intelligent and Soft Computing, 349–57. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03156-4_35.

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Siozios, Kostas, Dimitrios Soudris, and Antonios Thanailakis. "Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources." In Lecture Notes in Computer Science, 403–14. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11847083_39.

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Sugier, Jarosław. "Improving FPGA Implementations of BLAKE and BLAKE2 Algorithms with Memory Resources." In Advances in Dependability Engineering of Complex Systems, 394–406. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59415-6_38.

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Simpson, Philip. "Resource Scoping." In FPGA Design, 15–21. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_4.

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Simpson, Philip Andrew. "Resource Scoping." In FPGA Design, 29–38. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_5.

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Wires, Kent E., Michael J. Schulte, and Don McCarley. "FPGA Resource Reduction Through Truncated Multiplication." In Field-Programmable Logic and Applications, 574–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_59.

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Fröning, Holger, Federico Silla, and Hector Montaner. "MEMSCALE: Re-architecting Memory Resources for Clusters." In High-Performance Computing Using FPGAs, 569–604. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-1791-0_19.

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Zhao, Qian, Yoshimasa Ohnishi, Masahiro Iida, and Takaichi Yoshida. "A Resource Reduced Application-Specific FPGA Switch." In Lecture Notes in Computer Science, 58–67. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-17227-5_5.

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Frönin, Holger, Federico Silla, and Hector Montaner. "Erratum: MEMSCALE: Re-architecting Memory Resources for Clusters." In High-Performance Computing Using FPGAs, E1. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-1791-0_26.

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Shirakura, Yudai, Taisei Segawa, Yuichiro Shibata, Kenichi Morimoto, Masaharu Tanaka, Masanori Nobe, Hidenori Maruta, and Fujio Kurokawa. "A Redundant Design Approach with Diversity of FPGA Resource Mapping." In Lecture Notes in Computer Science, 119–31. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-30481-6_10.

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Conference papers on the topic "FPGA resources"

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Bragança, Lucas, Jeronimo Penha, Michael Canesche, Dener Ribeiro, José Augusto M. Nacif, and Ricardo Ferreira. "An Open-Source Cloud-FPGA Gene Regulatory Accelerator." In Simpósio em Sistemas Computacionais de Alto Desempenho. Sociedade Brasileira de Computação, 2021. http://dx.doi.org/10.5753/wscad.2021.18527.

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Abstract:
FPGAs are suitable to speed up gene regulatory network (GRN) algorithms with high throughput and energy efficiency. In addition, virtualizing FPGA using hardware generators and cloud resources increases the computing ability to achieve on-demand accelerations across multiple users. Recently, Amazon AWS provides high-performance Cloud's FPGAs. This work proposes an open source accelerator generator for Boolean gene regulatory networks. The generator automatically creates all hardware and software pieces from a high-level GRN description. We evaluate the accelerator performance and cost for CPU, GPU, and Cloud FPGA implementations by considering six GRN models proposed in the literature. As a result, the FPGA accelerator is at least 12x faster than the best GPU accelerator. Furthermore, the FPGA reaches the best performance per dollar in cloud services, at least 5x better than the best GPU accelerator.
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Gardel, Alfredo, Ignacio Bravo, Jose L. Lazaro, Beatriz Perez, Javier Balinas, and Alvaro Hernandez. "Verification of FPGA internal resources." In 2009 IEEE International Symposium on Intelligent Signal Processing - (WISP 2009). IEEE, 2009. http://dx.doi.org/10.1109/wisp.2009.5286572.

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Veedu, B. M., A. Azam, and M. A. Soderstrand. "FPGA resources for simple heterodyne filter." In Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers. IEEE, 2001. http://dx.doi.org/10.1109/acssc.2001.987710.

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Mayer-Lindenberg, Fritz. "High-Level FPGA Programming through Mapping Process Networks to FPGA Resources." In 2009 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE, 2009. http://dx.doi.org/10.1109/reconfig.2009.73.

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Chih-Chang Lin, D. Chang, Yu-Liang Wu, and M. Marek-Sadowska. "Time-multiplexed routing resources for FPGA design." In Proceedings of Custom Integrated Circuits Conference. IEEE, 1996. http://dx.doi.org/10.1109/cicc.1996.510532.

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Kasik, V., and Z. Chvostkova. "FPGA in technical resources of medical imaging." In 2013 IEEE 11th International Symposium on Applied Machine Intelligence and Informatics (SAMI). IEEE, 2013. http://dx.doi.org/10.1109/sami.2013.6480973.

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Mirsky and DeHon. "MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources." In Proceedings IEEE Symposium on FPGAs for Custom Computing Machines. IEEE, 1996. http://dx.doi.org/10.1109/fpga.1996.564808.

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Perwaiz, Aqib, Shoab A. Khan, and Hamid M. Komboh. "Optimization for Quantization and Embedded Resources on FPGA." In 2009 International Conference on New Trends in Information and Service Science (NISS). IEEE, 2009. http://dx.doi.org/10.1109/niss.2009.199.

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Hale, Robert, and Brad Hutchings. "Preallocating Resources for Distributed Memory Based FPGA Debug." In 2019 29th International Conference on Field Programmable Logic and Applications (FPL). IEEE, 2019. http://dx.doi.org/10.1109/fpl.2019.00067.

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Latino, Carl, Marco A. Moreno-Armendariz, and Martin Hagan. "Realizing general MLP networks with minimal FPGA resources." In 2009 International Joint Conference on Neural Networks (IJCNN 2009 - Atlanta). IEEE, 2009. http://dx.doi.org/10.1109/ijcnn.2009.5178680.

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Reports on the topic "FPGA resources"

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Selvakkumaran, Navaratnasothie, Abhishek Ranjan, Salil Raje, and George Karypis. Scalable Partitioning Algorithms for FPGAs With Heterogeneous Resources. Fort Belvoir, VA: Defense Technical Information Center, September 2004. http://dx.doi.org/10.21236/ada439474.

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