Dissertations / Theses on the topic 'FPGA design'

This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures.

A design methodology to mitigate timing problems due to long wire delays is proposed. The timing problems are taking care of at architecture level instead of layout level in this design method so that no change is needed when the whole design goes to backend design. Hence design iterations are avoided by using this design methodology. The proposed design method is based on STARI architecture, and a novel initialization mechanism is proposed in this paper. Low frequency global clock is used to synchronize the communication and PLLs are used to provide high frequency working clocks. The feasibility of new design methodology is proved on FPGA test board and the implementation details are also described in this paper. Only standard library cells are used in this design method and no change is made to the traditional design flow. The new design methodology is expected to reduce the timing closure effort in high frequency and complex digital design in deep submicron technologies.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 67-71).
The intercornnect delay in the new generations of integrated circuits imposes a significant limitation on the performance of ICs. 3-Dimensional integration of integrated circuits had been proposed to improve the interconnect delay. In this research, the effect of 3-D integration on the delay and power of FPGA chips is analyzed. Different physical partitioning of FPGAs is proposed for 3-D integration and one is analyzed in detail. The size of 3-D FPGAs differs from the size of 2-D FPGAs because of the overhead of 3-1D connections and different connectivity in switch blocks. Layout of 2-D and 3-D FPGAs is prepared to compare their size. To compare 3-D and 2-D FPGAs properly, two basic routability metrics are proposed to compare the routability of 3-D and 2-D circuits. Then, the delay of a 2-D and a 3-D FPGA with the same routability is compared. It is shown that 20%-29% delay improvement can be achieved by using a 3-D FPGA. In addition, the power consumption of 3-D FPGAs is analyzed. It is shown that if the supply voltage and the operating frequency of a 3-D FPGA are held to be the same as a 2-D FPGA, 17%-22% power improvement can be achieved. However, 3-D FPGAs can run faster since their delay is improved as well. If the delay improvement is traded off for more power saving by lowering the supply voltage, 35%-39% power improvement can be expected. Finally, to reduce the magnitude of supply current required for an integrated circuit, the method of stacking logic circuits is analyzed. This method requires level conversion between different supply domains. In this research, the architecture of several level converters are described and their delays are compared.
by Payam Lajevardi.
S.M.

Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.

In this thesis, an FPGA based hash processor is designed and implemented using a hardware description language
VHDL. Hash functions are among the most important cryptographic primitives and used in the several fields of communication integrity and signature authentication. These functions are used to obtain a fixed-size fingerprint or hash value of an arbitrary long message. The hash functions SHA-1 and SHA2-256 are examined in order to find the common instructions to implement them using same hardware blocks on the FPGA. As a result of this study, a hash processor supporting SHA-1 and SHA2-256 hashing and having a standard UART serial interface is proposed. The proposed hash processor has 14 instructions. Among these instructions, 6 of them are special instructions developed for SHA-1 and SHA-256 hash functions. The address length of the instructions is six bits. The data length is 32 bits. The proposed instruction set can be extended for other hash algorithms and they can be implemented over the same architecture. The hardware is described in VHDL and verified on Xilinx FPGAs. The advantages and open issues of implementing hash functions using a processor structure are also discussed.

This dissertation proposes an alternative FPGA design compilation flow to reduce the back-end time required to implement an FPGA design to below the level at which the user's attention is lost. To do so, this flow focuses on enforcing modular design for both productivity and code reuse, while minimizing reliance on standard tools. This can be achieved by using a library of precompiled modules and associated meta-data to enable bitstream-level assembly of desired designs. In so doing, assembly would occur in a fraction of the time of traditional back-end tools. Modules could be bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. This turbo flow (TFlow) aims to enable software-like turn-around time for faster prototyping by leveraging precompiled components. As a result, large device compilations would be assembled in seconds, within the deadline imposed by the human attention span.
Ph. D.

Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.
Ph. D.

In this study, universal motion command generator systems utilizing a Field Programmable Gate Array (FPGA) and an interface board for Robotics and Computer Numerical Control (CNC) applications have been developed. These command generation systems can be classified into two main groups as polynomial approximation and data compression based methods. In the former type of command generation methods, the command trajectory is firstly divided into segments according to the inflection points. Then, the segments are approximated using various polynomial techniques. The sequence originating from modeling error can be further included to the generated series. In the second type, higher-order differences of a given trajectory (i.e. position) are computed and the resulting data are compressed via lossless data compression techniques. Besides conventional approaches, a novel compression algorithm is also introduced in the study. This group of methods is capable of generating trajectory data at variable rates in forward and reverse directions. The generation of the commands is carried out according to the feed-rate (i.e. the speed along the trajectory) set by the external logic dynamically. These command generation techniques are implemented in MATLAB and then the best ones from each group are realized using FPGAs and their performances are assessed according to the resources used in the FPGA chip, the speed of command generation, and the memory size in Static Random Access Memory (SRAM) chip located on the development board.

Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced.

GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload.

Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

The field programmable gate array (FPGA) is a powerful technology, and since its introduction broad prospects have opened up for engineers to creatively design and implement complete systems in various fields. One such area that has a long history in information and network security is cryptography, which is considered in this thesis. The challenge for engineers is to design secure cryptographic systems, which should work efficiently on different platforms with the levels of security required. In addition, cryptographic functionalities have to be implemented with acceptable degrees of complexity while demanding lower power consumption. The present work is devoted to the design of an efficient block cipher that meets contemporary security requirements, and to implement the proposed design in a configurable hardware platform. The cipher has been designed according to Shannon’s principles and modern cryptographic theorems. It is an iterated symmetric-key block cipher based on the substitution permutation network and number theoretic transform with variable key length, block size and word length. These parameters can be undisclosed when determined by the system, making cryptanalysis almost impossible. The aim is to design a more secure, reliable and flexible system that can run as a ratified standard, with reasonable computational complexity for a sufficient service time. Analyses are carried out on the transforms concerned, which belong to the number theoretic transforms family, to evaluate their diffusion power, and the results confirm good performance in this respect mostly of a minimum of 50%. The new Mersenne number transform and Fermat number transform were included in the design because their characteristics meet the basic requirements of modern cryptographic systems. A new 7×7 substitution box (S-box) is designed and its non-linear properties are evaluated, resulting in values of 2-6 for maximum difference propagation probability and 2-2.678 for maximum input-output correlation. In addition, these parameters are calculated for all S-boxes belonging to the previous and current standard algorithms. Moreover, three extra S-boxes are derived from the new S-box and another three from the current standard, preserving the same non-linear properties by reordering the output elements. The robustness of the proposed cipher in terms of differential and linear cryptanalysis is then considered, and it is proven that the algorithm is secure against such well-known attacks from round three onwards regardless of block or key length. A number of test vectors are run to verify the correctness of the algorithm’s implementation in terms of any possible error, and all results were promising. Tests included the known answer test, the multi-block message test, and the Monte Carlo test. Finally, efficient hardware architectures for the proposed cipher have been designed and implemented using the FPGA system generator platform. The implementations are run on the target device, Xilinx Virtex 6 (XC6VLX130T-2FF484). Using parallel loop-unrolling architecture, a high throughput of 44.9 Gbits/sec is achieved with a power consumption of 1.83W and 8030 slices for implementing the encryption module with key and block lengths of 16×7 bits. There are a variety of outcomes when the cipher is implemented on different FPGA devices as well as for different block and key lengths.

FPGA devices are an important component in many modern devices. This means that it is important that VLSI designers have a thorough knowledge of how to optimize designs for FPGAs. While the design flows for ASICs and FPGAs are similar, there are many differences as well due to the limitations inherent in FPGA devices. To be able to use an FPGA efficiently it is important to be aware of both the strengths and oweaknesses of FPGAs. If an FPGA design should be ported to an ASIC at a later stage it is also important to take this into account early in the design cycle so that the ASIC port will be efficient. This thesis investigates how to optimize a design for an FPGA through a number of case studies of important SoC components. One of these case studies discusses high speed processors and the tradeoffs that are necessary when constructing very high speed processors in FPGAs. The processor has a maximum clock frequency of 357~MHz in a Xilinx Virtex-4 devices of the fastest speedgrade, which is significantly higher than Xilinx' own processor in the same FPGA. Another case study investigates floating point datapaths and describes how a floating point adder and multiplier can be efficiently implemented in an FPGA. The final case study investigates Network-on-Chip architectures and how these can be optimized for FPGAs. The main focus is on packet switched architectures, but a circuit switched architecture optimized for FPGAs is also investigated. All of these case studies also contain information about potential pitfalls when porting designs optimized for an FPGA to an ASIC. The focus in this case is on systems where initial low volume production will be using FPGAs while still keeping the option open to port the design to an ASIC if the demand is high. This information will also be useful for designers who want to create IP cores that can be efficiently mapped to both FPGAs and ASICs. Finally, a framework is also presented which allows for the creation of custom backend tools for the Xilinx design flow. The framework is already useful for some tasks, but the main reason for including it is to inspire researchers and developers to use this powerful ability in their own design tools.

Advances in FPGA density and complexity have not been matched by a corresponding improvement in the performance of the implementation tools. Knowledge of incremental changes in a design can lead to fast turnaround times for implementing even large designs. A high-level overview of an incremental productivity flow, focusing on the back-end FPGA design is provided in this thesis. This thesis presents a management paradigm that is used to capture the design specific information in a format that is reusable across the entire design process. A C++ based internal data structure stores all the information, whereas XML is used to provide an external view of the design data. This work provides a vendor independent, universal format for representing the logical and physical information associated with FPGA designs.
Master of Science

Three algorithms for video scaling were developed and tested in software, for implementation on an FPGA. Two of the algorithms were implemented in a video scaler system. These two algorithms scale up with factors 1.25 and 1.875, which is used for scaling SD WIDE to HD resolution and SD WIDE to FullHD resolution, respectively. An algorithm with scaling factor 1.5, scaling HD to FullHD, was also discussed, but not implemented. The video scaler was tested with a verilog testbench provided by ARM. When passing the testbench, the video scaler system was loaded on an FPGA. Results from the FPGA were compared with the software algorithms and the simulation results from the testbench. The video scaler implemented on the FPGA produced predictable results. Even though a fully functional video scaler was made, there were not time left to create the necessary software drivers and application software that would be needed to run the video scaler in real time with live video output. So a comparison of the output from the implemented algorithms is performed with common scaling algorithms used in video scalers, such as bilinear interpolation and bicubic interpolation. This thesis also deal with graphics scaling. Some well-known algorithms for graphic scaling were written in software, including a self-made algorithm to suit hardware. These algorithms were not implemented in hardware, but comparison of the results are performed.

O avanço da microeletrônica nas últimas décadas trouxe maior densidade aos circuitos integrados, possibilitando a implementação de funções de alta complexidade em uma menor área de silício. Como efeito desta integração em larga escala, as latências dos fios passaram a representar uma maior fração do atraso de propagação de dados em um design, tornando a tarefa de “timing closure” mais desafiadora e demandando mais iterações entre etapas do design. Por meio de uma revisão na teoria dos circuitos insensíveis a latência (Latency-Insensitive theory), este trabalho explora a metodologia de designs elásticos (Elastic Design methodology) em circuitos síncronos, com o objetivo de solucionar o impacto que a latência adicional dos fios insere no fluxo de design de circuitos integrados, sem demandar uma grande mudança de paradigma por parte dos designers. A fim de exemplificar o processo de “elasticização”, foi implementada uma versão síncrona da arquitetura do microprocessador Neander que posteriormente foi convertida a um Circuito Elástico utilizando um protocolo insensível a latência nas transferências de dados entre os processos computacionais do design. Ambas as versões do Neander foram validadas em uma plataforma FPGA utilizando ferramentas e fluxo de design síncrono bem estabelecidos. A comparação das características de timing e área entre os designs demonstra que a versão Elástica pode apresentar ganhos de performance para sistemas complexos ao custo de um aumento da área necessária. Estes resultados mostram que a metodologia de designs elásticos é uma boa candidata para projetar circuitos integrados complexos sem demandar custosas iterações entre fases de design e reutilizando as já estabelecidas ferramentas de design síncrono, resultando em uma alternativa economicamente vantajosa para os designers.
The advance of microelectronics brought increased density to integrated circuits, allowing high complexity functions to be implemented in smaller silicon areas. As a side effect of this large-scale integration, the wire latencies became a higher fraction of a design’s data propagation latency, turning timing closure into a challenging task that often demand several iterations among design phases. By reviewing the Latency-Insensitive theory, this work presents the exploration of the Elastic Design methodology in synchronous circuits, with the objective of solving the increased wire latency impact on integrated circuits design flow without requiring a big paradigm change for designers. To exemplify the elasticization process, the educational Neander microprocessor architecture is synchronously implemented and turned into an Elastic Circuit by using a latency-insensitive protocol in the design’s computational processes data transfers. Both designs are validated in an FPGA platform, using well known synchronous design tools and flow. The timing and area comparison between the designs demonstrates that the Elastic version can present performance advantages for more complex systems at the price of increased area. These results show that the Elastic Design methodology is a good candidate for designing complex integrated circuits without costly iterations between design phases. This methodology also leverages the reuse of the mostly adopted synchronous design tools, resulting in a cost-effective alternative for designers.

Since its introduction in the 1980s, field-programmable gate arrays have seen a growing use over the years. Nowadays FPGAs are found in everything from planetary rovers and base transceiver stations to bitcoin miners. With the technological advancements and the growth of the market, there has been a steady flow of new models with increasing capacity. To make it possible to use this capacity in an efficient way, also the software tools have been improved. The applications in research have grown and so has the will to compare both the speed and size between different implementations that try to solve the same or similar problem. However, how to make a good comparison is not well defined. Since few research papers have source code available, such comparisons are hard to make and there is a high risk of comparing apples to pears. In this thesis, we will study the impact of different software settings and design constraints on the FPGA design flows to better understand how to report research results. This will be done by running selected designs through different EDA tools, using various settings and finally analyse the data the tools provide. At the end we will begin to define guidelines for how to report and compare implementation data, to give a good account of their performance compared to other designs.

The process of FPGA reconfiguration is to recompile a design and then update the FPGA configuration correspondingly. Traditionally, FPGA design compilation follows the way how hardware is compiled for achieving high performance, which requires a long computation time. How to efficiently compile a design becomes the bottleneck for FPGA reconfiguration. It is promising to apply some techniques or concepts from software to facilitate FPGA reconfiguration. This dissertation explores such an idea by utilizing three types of low-level manipulation on FPGA logic and routing resources, i.e. relocating, mapping/placing, and routing. It implements an FMA technique for "fast reconfiguration". The FMA makes use of the software compilation technique of reusing pre-compiled libraries for explicitly reducing FPGA compilation time. Based the software concept of Autonomic Computing, this dissertation proposes to build an Autonomous Adaptive System (AAS) to achieve "self-reconfiguration". An AAS absorbs the computing complexity into itself and compiles the desired change on its own. For routing, an FPGA router is developed. This router is able to route the MCNC benchmark circuits on five Xilinx devices within 0.35 ~ 49.05 seconds. Creating a routing-free sandbox with this router is 1.6 times faster than with OpenPR. The FMA uses relocating to load pre-compiled modules and uses routing to stitch the modules. It is an essential component of TFlow, which achieves 8 ~ 39 times speedup as compared to the traditional ISE flow on various test cases. The core part of an AAS is a lightweight embedded version of utilities for managing the system's hardware functionality. Two major utilities are mapping/placing and routing. This dissertation builds a proof-of-concept AAS with a universal UART transmitter. The system autonomously instantiates the circuit for generating the desired BAUD rate to adapt to the requirement of a remote UART receiver.
Ph. D.

Avec le développement de l'industrie électronique, on constate un nombre croissant de projets avec des contraintes matérielles et temporelles de plus en plus élevées, ce qui conduit à l'utilisation de FPGA (Field Programmable Gate Arrays). Pour cela, le concepteur doit avoir une bonne connaissance de la programmation VHDL car cela nécessite beaucoup de formation et de pratique pour maîtriser ces architectures. Mais même pour les spécialistes, le processus de développement prend beaucoup de temps. Par conséquent, le développement d'un outil pour aider les utilisateurs non experts à travailler sur FPGA est nécessaire.Des outils tels que Simulink+HDL coder proposent une interface graphique pour créer un design en posant des blocs sur un tableau et en les connectant. Malheureusement, ce type d’outil souffre de deux défauts. Le premier est qu'il ne prend pas en compte les caractéristiques physiques de l'architecture cible. L'autre est qu'il ne vérifie pas si les flux de données entrant sont traités correctement par le design. Cela oblige le développeur à créer de nombreux tests, ce qui est fastidieux et consommateur en temps. Par conséquent, ce n’est pas une solution adaptée pour produire des applications dans un environnement en temps réel et des contraintes matérielles strictes.Pour gérer la complexité et la taille croissante des designs, l’abstraction est devenue graduellement essentielle. Des modèles ont émergé afin de représenter un design comme un graphe d’acteurs (c.a.d. de blocs), avec une analyse statique de l’exécution du graphe. Néanmoins, ces modèles sont basés sur une description plus ou moins fidèle du comportement d’architecture réelles telles que les FPGAs.Dans cette thèse, nous nous concentrons sur l'étude d’un nouveau modèle et d’un nouvel outil logiciel pour aider les utilisateurs non experts à concevoir automatiquement des implémentations correctes de FPGA. Les principales contributions sont résumées comme suit:1. Les limitations des modèles SDF existants, en particulier ceux du modèle SDF-AP, sont décrites et illustrées par l'analyse d'exemples caractéristiques. Les deux problèmes les plus courants rencontrés dans les implémentations d'assemblages de blocs sont la production de résultats incorrects et la croissance infinie de la taille du tampon.2. Nous proposons un nouveau modèle appelé "Actors with Stretchable Access Patterns" (ASAP) qui décrit le comportement matériel de façon mins limitée que les approches antérieures. Il s'agit d'une manière originale de résoudre le problème d'ordonnancement des acteurs, adaptée aux FPGAs. Il permet de déterminer l'exactitude mathématique d'une exécution sans lancer de simulations complexes. Il peut non seulement modéliser correctement les comportements des acteurs, mais aussi éviter les inconvénients mentionnés ci-dessus. Des algorithmes implémentant ces principes sont également fournis.3. Nous avons étudié des stratégies et des algorithmes connexes pour analyser un graphe représentant un design. L’exactitude du traitement peut être analysée par une série d'algorithmes permettant par exemple la vérification de la vitesse des flux et la vérification de la compatibilité des patterns. Il est ainsi possible de calculer la vitesse de décimation ou la longueur de délais à appliquer sur les entrées lorsqu'une erreur de correction est détectée.4. Un logiciel d’aide à la création de design est également développé. Il est appelé BlAsT (Block Assembly Tool) et vise à compenser les inconvénients des outils similaires tels que Simulink + HDL. Dans BlAsT, les algorithmes du modèle ASAP sont utilisés pour vérifier que pour un flux d'entrée donné, le système peut produire un résultat correct et finalement générer des codes VHDL directement utilisables sur une carte FPGA réelle. De plus, l'outil détermine automatiquement les décimations et les modifications requises. Ainsi, un utilisateur sans aucune compétence de programmation, est capable créer un design pour FPGA
With the development of electronic industry, a growing number of projects require real-time streaming applications on embedded platforms. These comprise increasingly high hardware and timing constraints, which leads to the use of FPGAs (Field Programmable Gate Arrays). Usually, the designer should have a good knowledge of programming with VHDL or Verilog HDL. Unfortunately, only specialists can do it, because this needs a lot of training and practices to master these architectures. Furthermore, even for specialists, the process of development is quite time consuming. Therefore, how to develop a tool to help non-expert users working on FPGA is a promising but challenging work.Tools like Simulink+HDL coder provide a graphical interface to create a design, by putting functional blocks on a layer and to connect them. Nevertheless, such tools are generally suffering from two flaws. One is that they do not take the physical characteristics of the target architecture of the application into account, including that of the selected FPGA. The other one is that they do not check whether a data stream is processed correctly by the design, besides creating many test-benches, which is tedious and time consuming for the developer. Therefore, they are not suitable to produce applications in real-time environment and high hardware constraints.In order to manage the ever-increasing size and complexity of designs, the abstraction is gradually more and more essential. Some models have emerged to represent a design as a graph of actors (i.e. blocks), with a static analysis of the graph execution. Nevertheless, they have an unfaithful description of the behavior real architectures like an FPGA.In this dissertation, we concentrate on the study of a novel model and software tool that can help non-expert users for automatic design of FPGA implementations correctly. The main contributions are summarized as follows:1. The limits of existing SDF models, in particular those of the SDF-AP model, are described and illustrated by the analysis of characteristic examples. The two most common problems encountered in block assembly implementations are the production of incorrect results and the infinite growth of buffer size.2. We propose a new model called Actors Stretchable Access Patterns (ASAP) that describes the hardware behaviors as efficiently and precisely as possible. This is a novel way to address the scheduling problem of actors, adapted to FPGA architectures. It opens the possibility to determine the execution correctness mathematically without launching complex simulations. It can not only model actors' behaviors properly, but also avoid the above mentioned drawbacks. Algorithms that implement these principles also provided.3. We investigate strategies and related algorithms to analyze a graph representing a designed system. Its correctness can be analyzed by a series of algorithms, such as sample rate checking and pattern compatibility checking. The decimation rate or the delay length to be applied on actor's input can be computed when a correctness failure is detected. This increases the number of possible real FPGA implementations covered by the block assembly method.4. A software tool based on the concept of functional block graph is also developed. It is called BlAsT (Block Assembly Tool) and aims to compensate the drawbacks of other tools based on the same concepts, as for example Simulink + HDL coder. In BlAsT, the proposed ASAP model and related algorithms are used to check that for a given input stream, whether the system can produce a correct result and finally generate VHDL code directly usable on a real FPGA-based board. Otherwise, the tool determines the required decimations and modifications on the graph automatically. It makes a user without any programming skills to make designs on FPGAs thanks to the friendly graphic interface

Field Programmable Gate Arrays (FPGAs) are widely used in prototyping digital circuits. However commercial FPGAs are not very suitable for asynchronous design. Both the architecture of the FPGAs and the synthesis tools are mostly tailored to synchronous design. Therefore potential advantages of the asynchronous circuits could not be observed when they are implemented on commercial FPGAs. This is shown by designing an asynchronous arithmetic logic unit (ALU), implemented in the style of micropipelines, on the Xilinx Virtex XCV300 FPGA family. The hazard characteristics of the target FPGA have been analyzed and a methodology for selftimed asynchronous circuits has been proposed. The design methodology proposes first designing a hazard-free cell set, and then using relationally placed macros (RPMs) to keep the hazard-free behavior, and incremental design technique to combine modules in upper levels without disturbing their timing characteristics. The performance of the asynchronous ALU has been evaluated in terms of the logic slices occupied in the FPGA and data latencies, and a comparison is made with a synchronous ALU designed on the same FPGA.

In this work, a new deinterleaving algorithm that can be used as a part of an ESM system and its implementation by using an FPGA is studied. The function of the implemented algorithm is interpreting the complex electromagnetic military field in order to detect and determine different RADARs and their types by using incoming RADAR pulses and their PDWs. It is assumed that RADAR signals in the space are received clearly and PDW of each pulse is generated as an input to the implemented algorithm system. Clustering analysis and a new interpreting process is used to deinterleave the RADAR pulses. In order to implement the algorithm, FPGA is used for achieving a faster and more efficient system. Comparison of the new algorithm and the previous deinterleaving studies is done. The simulation results are shown and discussed in detail.

In order to perform the production testing of the video quality of manufactured set-top-boxes for digital television, an FPGA-based measurement system is designed. Background on sampling and video signals are given, as well as the requirements given by Motorola. From this, a design is proposed and implemented. The demonstrator works as planned and shows good performance in regards to signal to noise ratio and differential gain. The implemented digital communication protocols, such as USB and I2C, also work as expected.

The main conclusion from this thesis is that implementing video test systems using FPGA is a good approach offering many advantages compared to commercial video measurement instruments or plug-in cards for PCs.

This diploma work describes how an FPGA is designed to control a CAN controller. It describes the different tools used when working with Actel’s design tools and the sequence of work applied. It gives a short overview of a multiplexer, the CAN bus, an analog/digital-converter and some more information on the actual FPGA. It also brings up the design process of the FPGA, planning, coding, simulating, testing and finally programming the FPGA. The different parts implemented in the FPGA are a shift-register and two state- machines that are connected with each other. They work together to control the SJA1000 CAN controller made by Philips. They also receive data from the analog/digital-converter that they forward onwards to the CAN controller that forward the data on the CAN bus.

碩士
國立臺灣師範大學
工業教育學系
97
On 2000, the National Institute of Standards and Technology (NIST) announced that the Rijndael encryption algorithm was chosen as the Advanced Encryption Standard (AES), which would be the next generation of encryption standard to replace the Data Encryption Standard (DES), and became the federal information encryption standard the next year. 　　In our research, which is differ from other AES algorithm in data-path width of 128 bit or 32 bit that would probably pipelined to achieve high throughput like tens Giga Bit Per Second (GBPS). In fact, an 8 bit width data-path AES algorithm should be enough in some consuming electronic applications such as Radio Frequency Identification (RFID) which needs only a slower data transfer rate. 　　In this thesis, we implemented an 8 bit AES circuits on Field Programmable Gate Array (FPGA) and expected that it could be used in many different applications by its advantages of small area and more high through. More, the AES circuits were written in VHDL code by the designing tool of Xilinx ISE and verified and simulated by ModelSim. Moreover, by the way of using Block RAMs could reduce area (here is Slices utilization) effectively and provide a good throughput.

碩士
雲林科技大學
電機工程系碩士班
98
With the fast progress of the industrial technology , in order to make products more competitive , we have to develop towards thoroughly automation of industry , while motion control is an enevitable part . Further , in the design of moving control , the produce of moving orders is often more important than or as important as other kinds of design of the control system . In this thesis , we set FPGA to be the foundation , and it is suitable for the moving control system of gauge tool machine . Its main module is composed of two intensified 8051 , used to deal with the terminal program and motion control program separately .There is 4K byte Dual-Port Ram set between two processsors , and queue structure is used to accomplish the communication between the two . Also the gohome procedure , joystick procedure and CNC procedure are designed according to the need of the machine , and there is still protecting software set to avoid damage of the machine if the moving is out of control . In this thesis , we give moving orders to FPGA motion controller by PC , and execute correspondent program through the explanation of moving orders . Then detail interpolation and give out uniform pulse by trajetories planning and DDA so as to motivate the servo motor of gauge tool machine to accomplish the moving control of gauge tool machine. This study develop universal moving control system based on different needs of hardware platform through communication and cooperation with domestic factories . After various examinations , the result shows that this system does meet the goal that is set.

碩士
國立臺灣科技大學
機械工程系
89
Abstract The paper focuses on designing a motion controller using the programmable logic elements as a main circuit ,whichcommunicates with PC(Personal Computer) by printer port. The system includes a PC as control unit and I/O interface to connect motor drives. In order to downsize the printed circuit board, the FPGA is adoped to communicate with ADMC201 chip. The VHDL is used to design FPGA that can replace encoding and peripheral circuit. The circuit design can use module to decrease the cost and to increase the overall operation speed. The reconfigurable hardware module of CPLD or FPGA is the function execution kernal of the whole motion-controller.　It contains three sections: the input output section, the function block section, and the control section. The reconfigurable hardware module of CPLD or FPGA is a stretchable controller with high reliability and elasticity. The control system hardware is implemented through the VHDL description language. VHDL is compatible with many other device. VHDL can mitigate and simplify the translation of the system module to the hardware structure. The usage of the component has the characters of reuse and expansion, the efficiency of the designe and use would be enhanced, and system can also be promoted with usability.

碩士
國立臺灣科技大學
電子工程系
104
In recent years, wireless communication and embedded system develop rapidly. We are going to focus on antenna module integration and application in this paper. The use of wireless LAN band is so crowded and messy nowadays that we set up a platform which can transmit or receive in multiband. We use 2×2 MIMO OFDM to implement wireless LAN based on 802.11 a/g. According to different modulation mode, verify the bit error rate, throughput, distance and channel condition. We can apply on Internet of Things ( IoT ). AD-FMCOMMS3 combine with Virtex 6 FPGA WARP v3 and build embedded system in FPGA by System on Chip (SoC). Then use firmware to control the mode of transmission and reception. When antenna received the 802.11 packet, the signal pass through voltage gain amplifier, SPI control, clock synchronization and transmission interface. The embedded system included hardware / firmware design, hardware based on Microblaze processor and FPGA design. Firmware is developed on Xilinx SDK.

Leong Monk Ping.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (p. 255-278).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Mode of access: World Wide Web.
Abstracts in English and Chinese.

碩士
國立臺北科技大學
電腦通訊與控制研究所
90
In this thesis, we proposed new hardware architecture to implement the Grey Predictor IC using FPGA. To calculate the nature exponential that is the most complex circuit in this predictor, we use Tayler serious to find out the approximate solution of the nature exponential. Although Floating-point processing is more complex than Fixed-point processing, it could increase the accuracy of prediction. Furthermore, the performance of this system is much better than past system, and it has been approved by simulation result. The execute time of Grey Predictor only needs about 128 clock cycles and its operation frequency is 3.769MHz. This Grey Predictor could greatly reduce the load of processor in control system, and it is very suitable to the application of real time control system.

碩士
中原大學
電機工程研究所
98
Abstract This paper proposes a hardware circuit design to carry out the image data hiding method on FPGA. Through the parallel mechanism of the hardware design, the data-hiding process can be completed in fewer clock cycles to achieve a faster outcome. Most of researches which relate to the technology of the image data hiding focus on designing the algorithm of the image data hiding, then accomplish the algorithm in the software. But the processing speed will be slow. To overcome this shortcoming, a process improved the image data hiding process by the embedded system to the faster outcome of the data-hiding process is presented in this paper. The hardware design of image data hiding method is based on the OPAP (Optimal Pixel Adjustment Process) algorithm. Make an optimal adjustiment according to the character between the pixel of cover-image and the pixel of stego-image by LSB method to carry out the image data hiding method. The pixels of cover-image and the secret information are transmitted from PC to FPGA via RS232 for hardware processing. By using parallel compute, the data-hiding process can be improved. Then, the pixel of stego-image is transmitted from FPGA to PC via RS232 and stored in the computer. Experimental results show that the quality of the stego-image and the correctness of the extracted secret information are the same as software-implemented results. The execution speed of the proposed scheme is compared with that of the software-implemented scheme.

碩士
淡江大學
電機工程學系碩士在職專班
100
In this thesis, the concepts of setting AI motor speed track and motion control card technology are combined. The hardware/software co-designed method is applied to design a stepping motor controller and implement it on the FPGA chip. There are three main parts: (1) RS-232 communication module, (2) NIOS II master, and (3) motor controller. In the RS-232 communication module, the packet receive format by Verilog Hardware Description Language (HDL) is designed. The control commands are sent to the NIOS II master through Avalon Bus. In the NIOS II master, the acceleration, maximum speed, deceleration, and three speed execution time are calculated by control commands. The calculation results are sent to the motor controller through Avalon Bus. In the motor controller, the functional design of motion control card is reference to design various functional modules. Each module is mounted to the Avalon Bus, they are free to be mounted or removed in the future. The experimental results illustrate that the motor can be normal operation in any speed. Moreover, the proposed architecture and design can let the inexperienced users operate it easily.

碩士
國立成功大學
資訊工程學系
102
Packet parsing has been a necessary facility at all points in the modern networking infrastructure, to support packet classification and security functions. Increasing bandwidth and security requirements for high-speed networks rely on advanced hardware packet processing solutions. The future of the fast Internet needs powerful routers to support abundant network functionalities, such as firewall processing, quality of service, virtual private networks, and other services. To provide these services, the routers need to classify the packets into different categories based on a set of predefined rules, so-called multi-field packet classification. Traditional packet classification method that usually considersonly5tuple fields is not sufficient for today's complicated network management requirements. OpenFlow switch was born to take care of these complex requirements by using a rule set with rich definition as the software-hardware interface. Our proposed scheme called Enhanced Range Lookup (ERL) scheme for packet classification optimize Bit-Vector algorithm in order to support range field matching. This paper considers OpenFlow1.0 as our experimental rule sets, consisting of 12 tuple header fields[2].To show the performance and compare with other proposed schemes, we implement the proposed ERL scheme on multiple version of Field Programmable Gate Array (FPGA) devices. Experimental results show that our method can handle 5K OpenFlow rules. To our knowledge, our proposed scheme is the first range supported method that can sustain the clock rate of more than 380 MHz.

碩士
國立高雄第一科技大學
電腦與通訊工程系
90
Digital filters designs are one of the two main topics in digital signal processing, while FPGA has become a new trend of the ASIC design. So in this thesis we will apply FPGA technique to implement several filters including one-dimensional filters, two-dimensional filters, all-pass filters and two-channel two-dimensional filter banks. Moreover, we will realize two-dimensional filters using one-dimensional architecture by McClellan transformation. 　　Coefficient quantization is the main problem while implementing the filters, and in this thesis we will use the iterative Lagrange multiplier approach to achieve sub-optimal quantized coefficients; or the coefficients can be expressed as signed-powers-of-two and the implementation can be achieved without using multipliers, which will reduce the complication of the hardware and increase the speed. In this thesis, we also implement two-dimensional filters using one-dimensional architecture by McClellan transformation techniques, and the shape of the designed filters can be changed with renewing a few coefficients. As to the implementation of two-channel two-dimensional filter banks, we combine the analysis filter banks and synthesis filter banks in a single chip, so the designed chip can be used as a coder or a decoder. 　　All the above filters have been implemented by using Verilog hardware description language and FPGA technique, and the simulation shows that the performances are satisfied and the designed systems can be applied in real-time systems.

碩士
國立交通大學
資訊科學學系
86
Process technology advances will soon make the one-million gate FPGA a reality.A key issue that needs to be solved for the large-scale FPGAs to realize theirfull potential lies in the design of their segmentation architectures [10].One-dimensional segmentation designs have been studied to some degree in much ofthe literature, most of the previously proposed methods are based on Stochasticor analytical analysis. In this thesis, we address a new direction for studyingsegmentation architectures. Our method is based on graph-theoretic formulation.We first formulate a net matching problem and present a polynomial- timealgorithm to solve the problem. Based on the solution to the problem, we developan effective and efficient matching based algorithm for FPGA segmentation designs. Experimental results show that our method significantly outperforms the previous work. For example, our method achieves averages of 18.0% and 8.9% improvements in routability, compared with the work in [14] and the most recentwork in [7], respectively. More importantly, our approaches are very flexibleand can readily extend to high- order segmentation designs (eg., two- or three-dimensional segmentation design, etc), which is crucialto the design of large-scale FPGAs.

碩士
國立中正大學
電機工程研究所
88
A group of n VC-2 signals is called VC-2-nc signal. The data rate of VC-2-nc will be n times than VC-2. The broadband signals of Frame based or cell based services can be adapted to VC-2-nc format and transported in the SDH network. In this thesis, VC-2-5c mapper is designed by Xilinx FPGAs for transmit and receive devices and verified by Xilinx simulation tools in this thesis. An E3 circuit that satisfies ITU-T G.832 is used to Generate signal for testing the VC-2-5c mapper.

碩士
中華技術學院
電子工程研究所碩士班
93
Field Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital circuits and many commercial products. An FPGA can implement thousands of gates of logic, has no up-front fixed costs and can be programmed by writing into on-chip static memory. The FPGA can be reprogrammed any number of times, providing a versatile platform for rapid hardware implementation. In this paper, we propose a new Polygonal Field Programmable Gate Array (PFPGA) that consists of many logic blocks interconnect by a three-stage three-sided rearrangeable polygonal switching network (PSN3SU). Logic blocks in a PFPGA are grouped into clusters that can be used to implement different logic functions. Since the programmable switches usually have high resistance and capacitance and occupy a large area, we explore the effect of the PSN structure and granularity of cluster logic blocks on the switch efficiency of PFPGA. Besides，we propose a new FPGA with real-time reconfigurable and Run-Time Reconfiguration (RTR) technology. Real-time RTR that can reduce the energy consumed in executing time and enhances the FPGA whole the computation function density. It also can improve performance , cost and time to mark.

碩士
中華大學
電機工程學系(所)
97
Abstract Recently, most of the digital image processing systems are developed based on a personal computer hardware architecture, catching image data through an external connected digital video camera, to use specific digital image processing software to handling and operating the image data to get some specific information. The features of a computer based digital image processing system are large volume, larger power consumption and higher cost. This thesis uses ALTERA’s FPGA (Field Programmable Gate Array) development board (DE1) as a basis, and uses Verilog hardware description language to implement the moving object detection and central coordination display system. The system catch image through an external connected CMOS Image Sensor, to detect the continuous moving object image by comparing the difference of image data and background image data stored in the memory, and mark the moving object image with red block frame displaying in the VGA monitor, also display the central coordination of the moving object in the 7 segment displayer. Finally, through actual experiment test, the results show that the system could detect and trace the moving object real time. Keyword: FPGA, Verilog hardware description language, moving object detection

碩士
國立雲林科技大學
電機工程技術研究所
88
The FPGA realization of the major part of the channel en/decoder in ATSC system is presented in this thesis. The realization process of the transmitter and receiver is focused on the design of the overall error correcting subsystem structure. The correctness of our design has been verified by developing tools. Another emphasis of this thesis is on the implementation of the decoding rule of trellis encoder. Since trellis code is very widely used in communication systems, we put much effort on the investigation and realization Viterbi decoding. We use Altera MAX+PLUS II as the software tool for implementation, verification and simulation. In this thesis the fast realization of a less complicated circuit is also presented.

碩士
中原大學
資訊工程研究所
103
Abstract The software design of Taiwan technology industry is aiming at automobile detecting and parking assistant systems, which are progressed with the developing technology and current trend.Apart from traditionally human direct control, now are using computer to detect and control. The development of this system is more and more diversified. Derived from clustered automobile industry, the detecting and parking assistant system turns out to be a unique electronic software design division of its own. Along with the designer develops faster and more convenient system, the development of software and hardware are catching up. This study is to gaining consumer’s satisfaction with the automobile detecting and parking assistant system under developed. During the recent life style change and GDP growing, public’s dependence on automobile are increased and the requirements of car purchasing are raised to higher standard. The comfortable room space and advanced electronic devices are the must. The increased usage of electronic devices required the “sensor” to be more efficient. The era of automobile detecting and parking assistant system is here now. Refer to the above; the automobile detecting and parking assistant system is in the progress of developing, this study is to understanding it better. By studying the background and environment of system design industry is to improve the accuracy of detecting and assisting devices. Avoiding any blindsides of car is to make the drivers, motorcyclists, bikers and pedestrians safer on the road.

碩士
國立臺北科技大學
電腦與通訊研究所
94
Due to the technology of integrated circuit progress rapidly, the number of transistors increase in a system-on-a-chip. Therefore, a FPGA (Field Programmable Gate Array) chip can contains more and more logic element components. How to verification and design in FPGA systems is a significant issue. The step of verification in system design can make sure the correctness of system function and reduce the system development time. There have several kinds of verification method from abstract level to physical level. In this thesis, we develop a FPGA system automatically functional verification tool, namely FVT (Functional Verification Tool). We use a functional verification method which can quickly verify a lot of signals among system test pattern, and the results of system simulation and emulation. In this verification tool, we propose a functional verification algorithm and a graphical user interface (GUI) to speed up the FPGA verification. When designer finished the system hardware design, then output data will be generated by system simulation and system emulation. For reducing the errors from comparison of the results of system simulation and emulation by manual, the system designer can build a system test pattern for in system specification to automatically verify the results from simulation and emulation. Finally, two verification examples, LCD (Liquid Crystal Display) module and ADPCM (Adaptive Pulse Code Modulation) module, are used to illustrate the correctness and feasibility of our proposed verification tool.