Relevant bibliographies by topics / FPGA design

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'FPGA design'

Author: Grafiati
Published: 4 June 2021
Last updated: 25 April 2022

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Journal articles on the topic "FPGA design"

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LEE, HANHO, and GERALD E. SOBELMAN. "VLSI DESIGN OF DIGIT-SERIAL FPGA ARCHITECTURE." Journal of Circuits, Systems and Computers 13, no. 01 (February 2004): 17–52. http://dx.doi.org/10.1142/s021812660400126x.

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This paper presents a novel application-specific field-programmable gate array (FPGA) architecture that satisfies efficient implementation of digit-serial DSP architectures on a digit wide basis. Digit-serial DSP designs have been an effective implementation method for FPGAs. To efficiently realize a digit-serial DSP design on FPGAs, one must create an FPGA architecture optimized for those types of systems. We examine the various circuits used in digit-serial DSP designs to extract their key features that should be reflected in the new FPGA architecture. We explain the design methodology, layout and implementation of the new digit-serial FPGA architecture. Digit-serial DSP designs using the digit-serial FPGA (DS-FPGA) are compared to those implemented on Xilinx FPGAs. We have estimated that the DS-FPGA are about 2.5~3 times more efficient in area and faster than the equivalent digit-serial DSP architectures implemented using Xilinx FPGAs.
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Oliveira, Duarte L., Marius Strum, and Sandro S. Sato. "Burst-Mode Asynchronous Controllers on FPGA." International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/926851.

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FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.
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Wu, Chang Fu. "Analysis and Realization of Critical Points on Hardware Design of FPGA." Advanced Materials Research 950 (June 2014): 133–38. http://dx.doi.org/10.4028/www.scientific.net/amr.950.133.

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FPGA is one kind of important devices that can realize many functions. As the development of communication technology and computer science, more and more technologies are invented and more and more hardware design technologies are sifted out. Therefore, the hardware design based on ASIC can be not fit on the new theories realization. As a new device, FPGA has many advantages including strength function, shorter design circle, less money, more flexible and more intelligent design tools. More and More hardware designs of FPGA are pay more attentions. Therefore, it is significant to make analysis on hardware design of FPGA. The hardware design for FPGA will be related to the FPGA device. In the market Altera and Xilinx FPGAs are used frequently by engineers. Therefore, in this dissertation will be make analysis and realization the critical points in hardware design based on Xilinx FPGA. In this dissertation, the critical point of Hardware Design of FPGA will be described. It will include power source, impedance matching and clock circuit design. There are many hardware design tools used for hardware design including Altium Designer, Protel, Cadence and others. Compared with other design tools, Cadence will have more advantages. Therefore, in this dissertation, Cadence will be used as the design tool for hardware design analysis and realization. With the help of Cadence, one hardware design and signal transmission simulation will be made analysis. With the development of the micro-electronics technology and computer science, the hardware design about FPGA will be taken more and more attentions.
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Trinh, Nguyen, Anh Le Thi Kim, Hung Nguyen, and Linh Tran. "Algorithmic TCAM on FPGA with data collision approach." Indonesian Journal of Electrical Engineering and Computer Science 22, no. 1 (April 1, 2021): 89. http://dx.doi.org/10.11591/ijeecs.v22.i1.pp89-96.

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<span>Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.</span>
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Cahill, Eli, Brad Hutchings, and Jeffrey Goeders. "Approaches for FPGA Design Assurance." ACM Transactions on Reconfigurable Technology and Systems 15, no. 3 (September 30, 2022): 1–29. http://dx.doi.org/10.1145/3491233.

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Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design. In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design. We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.
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Hosseinghorban, Ali, and Akash Kumar. "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications." Electronics 11, no. 7 (March 22, 2022): 978. http://dx.doi.org/10.3390/electronics11070978.

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Rapid and continuous evolution in telecommunication standards and applications has increased the demand for a platform with high parallelization capability, high flexibility, and low power consumption. FPGAs are known platforms that can provide all these requirements. However, the evaluation of approaches, architectures, and scheduling policies in this era requires a suitable and open-source benchmark suite that runs on FPGA. This paper harnesses high-level synthesis tools to implement high-performance, resource-efficient, and easy-maintenance kernels for FPGAs. We provide various implementations of each kernel of PHY-Bench and WiBench, which are the most well-known benchmark suites for telecommunication applications on FPGAs. We analyze the execution time and power consumption of different kernels on ARM processors and FPGA. We have made all sources and documentation public for the benefit of the research community. The codes are flexible, and all kernels can easily be regenerated for different sizes. The results show that the FPGA can increase the speed by up to 19.4 times. Furthermore, we show that the power consumption of the FPGA can be reduced by up to 45% by partially reconfiguring a kernel that fits the size of the input data instead of using a large kernel that supports all inputs. We also show that partial reconfiguration can improve the execution time for processing a sub-frame in the uplink application by 33% compared to an FPGA-based approach without partial reconfiguration.
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Yu, Hoyoung, Hansol Lee, Sangil Lee, Youngmin Kim, and Hyung-Min Lee. "Recent Advances in FPGA Reverse Engineering." Electronics 7, no. 10 (October 12, 2018): 246. http://dx.doi.org/10.3390/electronics7100246.

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In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products.
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Coli, Vincent J. "FPGA design technology." Microprocessors and Microsystems 17, no. 7 (September 1993): 383–89. http://dx.doi.org/10.1016/0141-9331(93)90060-k.

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Heinz, Carsten, Jaco Hofmann, Jens Korinth, Lukas Sommer, Lukas Weber, and Andreas Koch. "The TaPaSCo Open-Source Toolflow." Journal of Signal Processing Systems 93, no. 5 (May 2021): 545–63. http://dx.doi.org/10.1007/s11265-021-01640-8.

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AbstractThe integration of FPGA-based accelerators into a complete heterogeneous system is a challenging task faced by many researchers and engineers, especially now that FPGAs enjoy increasing popularity as implementation platforms for efficient, application-specific accelerators for domains such as signal processing, machine learning and intelligent storage. To lighten the burden of system integration from the developers of accelerators, the open-source TaPaSCo framework presented in this work provides an automated toolflow for the construction of heterogeneous many-core architectures from custom processing elements, and a simple, uniform programming interface to utilize spatially distributed, parallel computation on FPGAs. TaPaSCo aims to increase the scalability and portability of FPGA designs through automated design space exploration, greatly simplifying the scaling of hardware designs and facilitating iterative growth and portability across FPGA devices and families. This work describes TaPaSCo with its primary design abstractions and shows how TaPaSCo addresses portability and extensibility of FPGA hardware designs for systems-on-chip. A study of successful projects using TaPaSCo shows its versatility and can serve as inspiration and reference for future users, with more details on the usage of TaPaSCo presented in an in-depth case study and a short overview of the workflow.
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Zhang, Qian Li, Fang Yu, Yan Li, Ming Li, Yan Zhao, and Liang Chen. "Architecture-Specific Mapping Tool for SOI-Based FPGA." Advanced Materials Research 159 (December 2010): 438–43. http://dx.doi.org/10.4028/www.scientific.net/amr.159.438.

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This paper addresses several key issues in the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process, with particular emphasis on FPGA architecture interrelated mapping step and packing method for CAD tool. Considering the routability and testability of the FPGA and the CAD tool, the algorithm combines the FPGA structure with the object netlist, mapping the basic elements into basic building blocks in order to reduce the resource usage. The result is proven in extensive test circuits used in our FPGA design.
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Dissertations / Theses on the topic "FPGA design"

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Leaver, Andrew C. "FPGA design and systems compilation." Thesis, University of Oxford, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.296767.

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New, Wesley. "Python based FPGA design-flow." Master's thesis, University of Cape Town, 2016. http://hdl.handle.net/11427/20339.

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This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures.
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Sheng, Cheng. "Synchronous Latency Insensitive Design in FPGA." Thesis, Linköping University, Department of Electrical Engineering, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2767.

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A design methodology to mitigate timing problems due to long wire delays is proposed. The timing problems are taking care of at architecture level instead of layout level in this design method so that no change is needed when the whole design goes to backend design. Hence design iterations are avoided by using this design methodology. The proposed design method is based on STARI architecture, and a novel initialization mechanism is proposed in this paper. Low frequency global clock is used to synchronize the communication and PLLs are used to provide high frequency working clocks. The feasibility of new design methodology is proved on FPGA test board and the implementation details are also described in this paper. Only standard library cells are used in this design method and no change is made to the traditional design flow. The new design methodology is expected to reduce the timing closure effort in high frequency and complex digital design in deep submicron technologies.

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Lajevardi, Payam. "Design of a 3-dimension FPGA." Thesis, Massachusetts Institute of Technology, 2005. http://hdl.handle.net/1721.1/34365.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
Includes bibliographical references (p. 67-71).
The intercornnect delay in the new generations of integrated circuits imposes a significant limitation on the performance of ICs. 3-Dimensional integration of integrated circuits had been proposed to improve the interconnect delay. In this research, the effect of 3-D integration on the delay and power of FPGA chips is analyzed. Different physical partitioning of FPGAs is proposed for 3-D integration and one is analyzed in detail. The size of 3-D FPGAs differs from the size of 2-D FPGAs because of the overhead of 3-1D connections and different connectivity in switch blocks. Layout of 2-D and 3-D FPGAs is prepared to compare their size. To compare 3-D and 2-D FPGAs properly, two basic routability metrics are proposed to compare the routability of 3-D and 2-D circuits. Then, the delay of a 2-D and a 3-D FPGA with the same routability is compared. It is shown that 20%-29% delay improvement can be achieved by using a 3-D FPGA. In addition, the power consumption of 3-D FPGAs is analyzed. It is shown that if the supply voltage and the operating frequency of a 3-D FPGA are held to be the same as a 2-D FPGA, 17%-22% power improvement can be achieved. However, 3-D FPGAs can run faster since their delay is improved as well. If the delay improvement is traded off for more power saving by lowering the supply voltage, 35%-39% power improvement can be expected. Finally, to reduce the magnitude of supply current required for an integrated circuit, the method of stacking logic circuits is analyzed. This method requires level conversion between different supply domains. In this research, the architecture of several level converters are described and their delays are compared.
by Payam Lajevardi.
S.M.
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Lavin, Christopher Michael. "Using Hard Macros to Accelerate FPGA Compilation for Xilinx FPGAs." BYU ScholarsArchive, 2012. https://scholarsarchive.byu.edu/etd/2933.

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Field programmable gate arrays (FPGAs) offer an attractive compute platform because of their highly parallel and customizable nature in addition to the potential of being reconfigurable to any almost any desired circuit. However, compilation time (the time it takes to convert user design input into a functional implementation on the FPGA) has been a growing problem and is stifling designer productivity. This dissertation presents a new approach to FPGA compilation that more closely follows the software compilation model than that of the application specific integrated circuit (ASIC). Instead of re-compiling every module in the design for each invocation of the compilation flow, the use of pre-compiled modules that can be "linked" in the final stage of compilation are used. These pre-compiled modules are called hard macros and contain the necessary physical information to ultimately implement a module or building block of a design. By assembling hard macros together, a complete and fully functional implementation can be created within seconds. This dissertation describes the process of creating a rapid compilation flow based on hard macros for Xilinx FPGAs. First, RapidSmith, an open source framework that enabled the creation of custom CAD tools for this work is presented. Second, HMFlow, the hard macro-based rapid compilation flow is described and presented as tuned to compile Xilinx FPGA designs as fast as possible. Finally, several modifications to HMFlow are made such that it produces circuits with clock rates that run at more than 75% of Xilinx-produced implementations while compiling more than 30X faster than the Xilinx tools.
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Siltu, (celebi) Tugba. "Design And Fpga Implementation Of Hash Processor." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/12609078/index.pdf.

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In this thesis, an FPGA based hash processor is designed and implemented using a hardware description language
VHDL. Hash functions are among the most important cryptographic primitives and used in the several fields of communication integrity and signature authentication. These functions are used to obtain a fixed-size fingerprint or hash value of an arbitrary long message. The hash functions SHA-1 and SHA2-256 are examined in order to find the common instructions to implement them using same hardware blocks on the FPGA. As a result of this study, a hash processor supporting SHA-1 and SHA2-256 hashing and having a standard UART serial interface is proposed. The proposed hash processor has 14 instructions. Among these instructions, 6 of them are special instructions developed for SHA-1 and SHA-256 hash functions. The address length of the instructions is six bits. The data length is 32 bits. The proposed instruction set can be extended for other hash algorithms and they can be implemented over the same architecture. The hardware is described in VHDL and verified on Xilinx FPGAs. The advantages and open issues of implementing hash functions using a processor structure are also discussed.
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Love, Andrew R. "A Modular Flow for Rapid FPGA Design Implementation." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/51608.

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This dissertation proposes an alternative FPGA design compilation flow to reduce the back-end time required to implement an FPGA design to below the level at which the user's attention is lost. To do so, this flow focuses on enforcing modular design for both productivity and code reuse, while minimizing reliance on standard tools. This can be achieved by using a library of precompiled modules and associated meta-data to enable bitstream-level assembly of desired designs. In so doing, assembly would occur in a fraction of the time of traditional back-end tools. Modules could be bound, placed, and routed using custom bitstream assembly with the primary objective of rapid compilation while preserving performance. This turbo flow (TFlow) aims to enable software-like turn-around time for faster prototyping by leveraging precompiled components. As a result, large device compilations would be assembled in seconds, within the deadline imposed by the human attention span.
Ph. D.
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Frangieh, Tannous. "A Design Assembly Technique for FPGA Back-End Acceleration." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/29225.

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Long wait times constitute a bottleneck limiting the number of compilation runs performed in a day, thus risking to restrict Field-Programmable Gate Array (FPGA) adaptation in modern computing platforms. This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity. The practical tasks of logic partitioning, placement and routing are examined and a resulting assembly framework, Quick Flow (qFlow), is implemented. Experiments show up to 10x speed-ups using the proposed paradigm compared to vendor tool flows.
Ph. D.
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Ulas, Yaman. "Design Of Advanced Motion Command Generators Utilizing Fpga." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/3/12612054/index.pdf.

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In this study, universal motion command generator systems utilizing a Field Programmable Gate Array (FPGA) and an interface board for Robotics and Computer Numerical Control (CNC) applications have been developed. These command generation systems can be classified into two main groups as polynomial approximation and data compression based methods. In the former type of command generation methods, the command trajectory is firstly divided into segments according to the inflection points. Then, the segments are approximated using various polynomial techniques. The sequence originating from modeling error can be further included to the generated series. In the second type, higher-order differences of a given trajectory (i.e. position) are computed and the resulting data are compressed via lossless data compression techniques. Besides conventional approaches, a novel compression algorithm is also introduced in the study. This group of methods is capable of generating trajectory data at variable rates in forward and reverse directions. The generation of the commands is carried out according to the feed-rate (i.e. the speed along the trajectory) set by the external logic dynamically. These command generation techniques are implemented in MATLAB and then the best ones from each group are realized using FPGAs and their performances are assessed according to the resources used in the FPGA chip, the speed of command generation, and the memory size in Static Random Access Memory (SRAM) chip located on the development board.
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Ek, Tobias. "GALS,Design och simulering för FPGA med VHDL." Thesis, Linköping University, Department of Electrical Engineering, 2004. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2644.

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Heat, clock scew and frequency optimization are some of the problems a semiconductor designer must face. By splitting a synchrounous block into multiple pieces which comunicates asynchronously with eachother and provide them with independent clocks, these problems may be reduced.

GALS (Global Asynchronous Local Synchronous) is a wrapper that wraps a synchronous block and provides it with a clock. Multiple GALS-elements will make the whole system. The clockfrequency may be independently adjusted between each block. The clocks may be started and halted independantly depending on the workload.

Describing the system in a hardware language as VHDL, and implement it into an FPGA (Field Programmable Grid Array), makes the development of applications fast and cheap.

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Books on the topic "FPGA design"

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Simpson, Philip Andrew. FPGA Design. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7.

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Simpson, Philip. FPGA Design. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0.

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Corporation, Actel. The FPGA design guide. Sunnyvale, CA: Actel Corporation, 1991.

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Chen, Deming. FPGA design automation: A survey. Boston: Now, 2006.

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Huffmire, Ted. Handbook of FPGA design security. Dordrecht: Springer, 2010.

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Huffmire, Ted, Cynthia Irvine, Thuy D. Nguyen, Timothy Levin, Ryan Kastner, and Timothy Sherwood. Handbook of FPGA Design Security. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9157-4.

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K, Kokula Krishna Hari, ed. System Design using FPGA: ICIEMS 2014. India: Association of Scientists, Developers and Faculties, 2014.

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Real world FPGA design with Verilog. Upper Saddle River, NJ: Prentice Hall PTR, 2000.

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David E. Van den Bout. FPGA workout: Beginning exercises with the Intel FLEXlogic FPGA. Apex, N.C: X Engineering Software Systems Corp., 1994.

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Advanced FPGA design: Architecture, implementation, and optimization. Hoboken, NJ: Wiley-Interscience, 2007.

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Book chapters on the topic "FPGA design"

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Simpson, Philip. "Design Specification." In FPGA Design, 9–13. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_3.

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Simpson, Philip. "Design Environment." In FPGA Design, 23–28. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_5.

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Simpson, Philip. "Board Design." In FPGA Design, 29–40. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_6.

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Simpson, Philip. "RTL Design." In FPGA Design, 51–78. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_8.

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Simpson, Philip Andrew. "RTL Design." In FPGA Design, 91–139. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_10.

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Simpson, Philip Andrew. "Embedded Design." In FPGA Design, 157–78. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_12.

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Simpson, Philip Andrew. "Design Specification." In FPGA Design, 9–13. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_3.

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Simpson, Philip Andrew. "Design Environment." In FPGA Design, 39–51. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_6.

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Simpson, Philip Andrew. "Board Design." In FPGA Design, 53–65. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-17924-7_7.

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Simpson, Philip. "Best Practices for Successful FPGA Design." In FPGA Design, 1–3. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-6339-0_1.

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Conference papers on the topic "FPGA design"

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Caponetto, R., G. Dongola, and A. Gallo. "FPGA Implementation of Self-Tuning Regulators." In ASME 2009 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/detc2009-87351.

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The paper presents an hardware realization of a self-tuning control system implemented on a development board, Field Programmable Gate Arrays (FPGAs) based, able to adapt the control rules for an uncertain and disturbance affected plant. In the paper the on-line estimation of the plant parameters is realized by applying the “Recursive Least Squares with exponential forgetting” method and the control law is designed by using the “Pole Placement” procedure. These algorithms require a greater computational load, justifying therefore the FPGA utilization, especially in the case of high speed variation of the plant parameters. In order to test the FPGA hardware implementation of Self-Tuning regulators the process is implemented on DSPACE and the parameter variations are produced via an Human Machine Interface (HMI) console. Besides, thanks to the reprogrammability of FPGAs, these devices allow the use of such adaptive control systems in hazardous area.
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Jiang, Cindy X., Tom T. Hartley, and Joan E. Carletta. "High Performance Low Cost Implementation of FPGA-Based Fractional-Order Operators." In ASME 2005 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2005. http://dx.doi.org/10.1115/detc2005-84796.

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Hardware implementation of fractional-order differentiators and integrators requires careful consideration of issues of system quality, hardware cost, and speed. This paper proposes using field programmable gate arrays (FPGAs) to implement fractional-order systems, and demonstrates the advantages that FPGAs provide. As an illustration, the fundamental operators to a real power is approximated via the binomial expansion of the backward difference. The resulting high-order FIR filter is implemented in a pipelined multiplierless architecture on a low-cost Spartan-3 FPGA. Unlike common digital implementations in which all filter coefficients have the same word length, this approach exploits variable word length for each coefficient. Our system requires twenty percent less hardware than a system of comparable quality generated by Xilinx’s System Generator on its most area-efficient multiplierless setting. The work shows an effective way to implement a high quality, high throughput approximation to a fractional-order system, while maintaining less cost than traditional FPGA-based designs.
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Stephen Trimberger. "Effects of FPGA Architecture on FPGA Routing." In 32nd Design Automation Conference. ACM, 1995. http://dx.doi.org/10.1109/dac.1995.250012.

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McNelles, Phillip, and Lixuan Lu. "Lab-Scale Design, Demonstration and Safety Assessment of an FPGA-Based Post Accident Monitoring System for Westinghouse AP1000 Nuclear Power Plants." In 2014 22nd International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2014. http://dx.doi.org/10.1115/icone22-30457.

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A Field Programmable Gate Array (FPGA) is a type of integrated circuit (IC), which is programmed after it is manufactured. FPGAs are referred to as a form of programmable hardware, as there is typically no software or operating system running on the FPGA itself. A significant amount of design work has been performed regarding the application of FPGAs in the nuclear field in recent years, with much of that work centered around safety related Instrumentation and Control (I&C) systems and safety systems. These new FPGA based systems are considered to be viable alternatives to replace many old I&C systems that are commonly used in Nuclear Power Plants (NPPs). Many of these older analog and digital systems are obsolete, and it has become increasingly difficult to maintain and repair them. FPGAs possess certain advantages over traditional analog circuits, PLCs and microprocessors, when considering nuclear I&C and safety system applications. This paper describes how FPGA technology has been used to construct a lab-scale implementation of a Post-Accident Monitoring System (PAMS), for a Westinghouse AP1000 Nuclear Power Plant, using a National Instruments “cRIO” chassis and I/O modules. This system will perform the major functions of the existing PAMS, including monitoring the vital values such as temperature, water level, pressure, flow rate, radiation levels and neutron flux in the event of a serious reactor accident. These values are required in standards such as United States Nuclear Regulatory Commission (NRC), Canadian Nuclear Safety Commission (CNSC), International Electrotechnical Commission (IEC), and Institute of Electrical and Electronics Engineers (IEEE). All of the input signals are read and processed using the FPGA, which includes alarms if the values go beyond the specified range, or if the values change rapidly. The values were then output to the computer through the FPGA interface to provide information to the operator, as well as being sent through analog and digital output modules for further processing. The system was tested using both simulated and real inputs from sensors. Furthermore, the reliability of the new system has also been analyzed, using the Dynamic Flowgraph Methodology (DFM). DFM has been successfully applied in both the nuclear and aerospace fields, and has been described as one of the best methodologies for modeling software/hardware interactions, by the scientific literature as well as in NRC reports. DFM was applied to fine-tune the design parameters by determining the potential causes of faults in the design, as well as to highlight the effectiveness of DFM in nuclear and in FPGA applications.
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Matilainen, Lauri, Erno Salminen, and Timo D. Hämäläinen. "MCAPI abstraction on FPGA based SoC design." In the Annual FPGA Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2451636.2451641.

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Svyd, Iryna, Oleksandr Vorgul, Valerii Semenets, Oleg Zubkov, Valeriia Chumak, and Natalia Boiko. "SPECIAL FEATURES OF THE EDUCATIONAL COMPONENT DESIGN OF DEVICES ON MICROCONTROLLERS AND FPGA." In MC&FPGA-2020. 2020. http://dx.doi.org/10.35598/mcfpga.2020.017.

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Langhammer, Martin. "Teraflop FPGA Design." In 2011 IEEE 20th Symposium on Computer Arithmetic (ARITH). IEEE, 2011. http://dx.doi.org/10.1109/arith.2011.32.

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Trimberger, Steve, and Jason Moore. "FPGA Security." In the The 51st Annual Design Automation Conference. New York, New York, USA: ACM Press, 2014. http://dx.doi.org/10.1145/2593069.2602555.

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Babeshko, Eugene, Ievgenii Bakhmach, Vyacheslav Kharchenko, Eugene Ruchkov, and Oleksandr Siora. "Operating Reliability Assessment of FPGA-Based NPP I&C Systems: Approach, Technique and Implementation." In 2017 25th International Conference on Nuclear Engineering. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/icone25-66862.

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Operating reliability assessment of instrumentation and control systems (I&Cs) is always one of the most important activities, especially for critical domains like nuclear power plants (NPPs). Intensive use of relatively new technologies like field programmable gate arrays (FPGAs) in I&C which appear in upgrades and in newly built NPPs makes task to develop and validate advanced operating reliability assessment methods that consider specific technology features very topical. Increased integration densities make the reliability of integrated circuits the most crucial point in modern NPP I&Cs. Moreover, FPGAs differ in some significant ways from other integrated circuits: they are shipped as blanks and are very dependent on design configured into them. Furthermore, FPGA design could be changed during planned NPP outage for different reasons. Considering all possible failure modes of FPGA-based NPP I&C at design stage is a quite challenging task. Therefore, operating reliability assessment is one of the most preferable ways to perform comprehensive analysis of FPGA-based NPP I&Cs. This paper summarizes our experience on operating reliability analysis of FPGA based NPP I&Cs.
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Kalupahana, Ayanga, Nisal Hemadasa, Nipun Wijerathne, Anuranga Ranasinghe, and Ajith Pasqual. "FPAA and FPGA based universal sensor node design." In 2017 Eleventh International Conference on Sensing Technology (ICST). IEEE, 2017. http://dx.doi.org/10.1109/icsenst.2017.8304452.

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Reports on the topic "FPGA design"

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Hutchings, Brad, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, and Mike Rytting. A CAD Suite for High-Performance FPGA Design. Fort Belvoir, VA: Defense Technical Information Center, January 1999. http://dx.doi.org/10.21236/ada450475.

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Graham, Paul, Brad Hutchings, and Brent Nelson. Improving the FPGA Design Process Through Determining and Applying Logical-to-Physical Design Mappings. Fort Belvoir, VA: Defense Technical Information Center, January 2000. http://dx.doi.org/10.21236/ada451583.

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Wirthlin, Michael, Brent Nelson, Brad Hutchings, Peter Athanas, and Shawn Bohner. Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows. Fort Belvoir, VA: Defense Technical Information Center, July 2008. http://dx.doi.org/10.21236/ada492273.

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Maumder, Pinaki. Ultra - Low - Power Asynchronous Processor and FPGA Design using Straintronics Nanomagnets. Fort Belvoir, VA: Defense Technical Information Center, May 2013. http://dx.doi.org/10.21236/ada584514.

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Sasao, Tsutomu, and Jon T. Butler. A Design Method for Look-up Table Type FPGA by Pseudo-Kronecker Expansion. Fort Belvoir, VA: Defense Technical Information Center, April 1994. http://dx.doi.org/10.21236/ada593069.

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Foote, David. The Design, Realization and Testing of the ILU of the CCM2 Using FPGA Technology. Portland State University Library, January 2000. http://dx.doi.org/10.15760/etd.6587.

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Support for development of a custom VLSI and FPGA logic chips based on a VHDL top-down design approach. Final report. Office of Scientific and Technical Information (OSTI), June 1994. http://dx.doi.org/10.2172/10159138.

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