Relevant bibliographies by topics / Formal verification

Academic literature on the topic 'Formal verification'

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Published: 4 June 2021
Last updated: 20 July 2024

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Journal articles on the topic "Formal verification"

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Meenakshi, B. "Formal verification." Resonance 10, no. 5 (May 2005): 26–38. http://dx.doi.org/10.1007/bf02871329.

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Bjesse, Per. "What is formal verification?" ACM SIGDA Newsletter 35, no. 24 (December 15, 2005): 1. http://dx.doi.org/10.1145/1113792.1113794.

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Schlipf, T., T. Buechner, R. Fritz, M. Helms, and J. Koehl. "Formal verification made easy." IBM Journal of Research and Development 41, no. 4.5 (July 1997): 567–76. http://dx.doi.org/10.1147/rd.414.0567.

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Sauvage, Laurent, Tarik Graba, and Thibault Porteboeuf. "Multi-level formal verification." Journal of Cryptographic Engineering 7, no. 1 (November 22, 2016): 87–95. http://dx.doi.org/10.1007/s13389-016-0144-3.

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Niculaescu, Oana. "What's formal software verification?" XRDS: Crossroads, The ACM Magazine for Students 25, no. 4 (July 9, 2019): 64–65. http://dx.doi.org/10.1145/3341815.

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Flores, Sonia, Salvador Lucas, and Alicia Villanueva. "Formal Verification of Websites." Electronic Notes in Theoretical Computer Science 200, no. 3 (May 2008): 103–18. http://dx.doi.org/10.1016/j.entcs.2008.04.095.

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Xie, Guojun, Huanhuan Yang, Hao Deng, Zhengpu Shi, and Gang Chen. "Formal Verification of Robot Rotary Kinematics." Electronics 12, no. 2 (January 11, 2023): 369. http://dx.doi.org/10.3390/electronics12020369.

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With the widespread application of robots in aerospace, medicine, automation, and other fields, their motion safety is essential for the well-being of humans and the accomplishment of vital socially beneficial programs. Conventional robot hardware and software designs mainly rely on experiential knowledge and manual testing to ensure safety, but this fails to cover all possible testing paths and adds risks. Alternatively, formal, mathematically rigorous verifications can provide predictable and reliable guarantees of robot motion safety. To demonstrate the feasibility of this approach, we formalize the mathematical coordinate transformation of a robot’s rigid-body kinematics using the Coq Proof Assistant to verify the correctness of its theoretical design. First, based on record-type matrix formalization, we define and verify a robot’s spatial geometry by constructing formal expressions of the matrix’ Frobenius norm, trace, and inner product. Second, we divide rotary motion into revolution and rotation construct and provide their formal definitions. Next, we formally verify the rotational matrices of angle conventions (e.g., roll–pitch–yaw and Euler), and we complete the formal verification of the Rodriguez formula to formally verify the correctness of the motion theory in specific rotating kinematics problems. The formal work of this paper has a variety of essential applications and provides a generalizable kinematics analysis framework for robot control system verification. Moreover, it paves the way for automatic programming capabilities.
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Greengard, Samuel. "Formal software verification measures up." Communications of the ACM 64, no. 7 (July 2021): 13–15. http://dx.doi.org/10.1145/3464933.

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Michael, James Bret, Doron Drusinsky, and Duminda Wijesekera. "Formal Verification of Cyberphysical Systems." Computer 54, no. 9 (September 2021): 15–24. http://dx.doi.org/10.1109/mc.2021.3055883.

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Qian, Junyan, and Baowen Xu. "Formal Verification for C Program." Informatica 18, no. 2 (January 1, 2007): 289–304. http://dx.doi.org/10.15388/informatica.2007.178.

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Dissertations / Theses on the topic "Formal verification"

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Tristan, Jean-Baptiste. "Formal verification of translation validators." Phd thesis, Université Paris-Diderot - Paris VII, 2009. http://tel.archives-ouvertes.fr/tel-00437582.

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Comme tout logiciel, les compilateurs, et tout particulièrement les compilateurs optimisant, peuvent être défectueux. Il est donc possible qu'ils changent la sémantique du programme compilé, et par conséquent ses propriétés. Dans le cadre de développement de logiciels critiques, où des méthodes formelles sont utilisées pour s'assurer qu'un programme satisfait certaines propriétés, et cela avant qu'il soit compilé, cela pose un problème de fond. Une solution à ce problème est de vérifier le compilateur en s'assurant qu'il préserve la sémantique des programmes compilés. Dans cette thèse, nous évaluons une méthode nouvelle pour développer des passes de compilations sûres: la vérification formelle de validateurs de traduction. D'une part, cette méthode utilise la vérification formelle à l'aide d'assistant de preuve afin d'offrir le maximum de garanties de sûreté sur le compilateur. D'autre part, elle repose sur l'utilisation de la validation de traduction, où chaque exécution du compilateur est validée a posteriori, une méthode de vérification plus pragmatique qui a permis de vérifier des optimisations avancées. Nous montrons que cette approche nouvelle du problème de la vérification de compilateur est viable, et même avantageuse dans certains cas, à travers quatre exemples d'optimisations réalistes et agressives: le list scheduling, le trace scheduling, le lazy code motion et enfin le software pipelining.
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Trinh, Cong Quy. "Formal Verification of Skiplist Algorithms." Thesis, Uppsala universitet, Institutionen för informationsteknologi, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-160314.

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Dragomir, Ciprian. "Formal verification of P systems." Thesis, University of Sheffield, 2016. http://etheses.whiterose.ac.uk/15452/.

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Membrane systems, also known as P systems, constitute an innovative computational paradigm inspired by the structure and dynamics of the living cell. A P system consists of a hierarchical arrangement of compartments and a finite set of multiset rewriting and communication rules, which operate in a maximally parallel manner. The organic vision of concurrent dynamics captured by membrane systems stands in antithesis with conventional formal modelling methods which focus on algebraic descriptions of distributed systems. As a consequence, verifying such models in a mathematically rigorous way is often elusive and indeed counter-intuitive when considering established approaches, which generally require sequential process representations or highly abstract theoretical frameworks. The prevalent investigations with this objective in the field of membrane computing are ambivalent and inconclusive in the wider application scope of P systems. In this thesis we directly address the formal verification of membrane systems by means of model checking. A fundamental distinction between the agnostic perspective on parallelism, advocated by process calculi, and P systems' emblematic maximally parallel execution strategy is identified. On this basis, we establish that an intuitional translation to traditional process models is inadequate for the purpose of formal verification, due to a state space growth disparity. The observation is essential for this research project: on one hand it implies the feasibility of model checking P systems, and on the other hand it underlines the suitability of this formal verification technique in the context of membrane computing. Model checking entails an exhaustive state space exploration and does not derive inferences based on the independent instructions comprising a state transition. In this respect, we define a new sequential modelling strategy which is optimal for membrane systems and targets the SPIN formal verification tool. We introduce elementary P systems, a distributed computational model which subsumes the feature diversity of the membrane computing paradigm and distils its functional vocabulary. A suite of supporting software tools which gravitate around this formalism has also been developed, comprising of 1. the eps modelling language for elementary P systems; 2. a parser for the eps specification; 3. a model simulator and 4. a translation tool which targets the Promela specification of the SPIN model checker. The formal verification approach proposed in this thesis is progressively demonstrated in four heterogeneous case studies, featuring 1. a parallel algorithm applicable to a structured model; 2. a linear time solution to an NP-complete problem; 3. an innovative implementation of the Dining Philosophers scenario (a synchronisation problem) using an elementary P system and 4. a quantitative analysis of a simple random process implemented without the support of a probabilistic model.
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Hurd, J. "Formal verification of probabilistic algorithms." Thesis, University of Cambridge, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604823.

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We begin with an extensive foundational development of probability, creating a higher-order logic formalization of mathematical measure theory. This allows the definition of the probability space we use to model a random bit generator, which informally is a stream of coin-flips, or technically an infinite sequence of IID Bernoulli( 1/2 ) random variables. Probabilistic programs are modified using the state-transformer monad familiar from functional programming, where the random bit generator is passed around in the computation. Functions remove random bits from the generator to perform their calculation, and then pass back the changed random bit generator with the result. Our probability space modelling the random bit generator allows us to give precise probabilistic specifications of such programs, and then verify them in the theorem prover. We also develop technical support designed to expedite verification: probabilistic quantifiers; a compositional property subsuming measurability and independence; a probabilistic while loop together with a formal concept of termination with probability 1. We also introduce a technique for reducing properties of a probabilistic while loop to properties of programs that are guaranteed to terminate: these can then be established using induction and standard methods of program correctness. We demonstrate the formal framework with some example probabilistic programs, samples algorithms for four probability distributions; some optimal procedures for generating dice rolls from coin flips; the symmetric simple random walk. In addition, we verify the Miller-Rabin primality test, a well-known and commercially used probabilistic algorithm. Our fundamental perspective allows us to define a version with strong properties, which we can execute in the logic to prove compositeness of numbers.
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Botinčan, Matko. "Formal verification-driven parallelisation synthesis." Thesis, University of Cambridge, 2018. https://www.repository.cam.ac.uk/handle/1810/274136.

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Concurrency is often an optimisation, rather than intrinsic to the functional behaviour of a program, i.e., a concurrent program is often intended to achieve the same effect of a simpler sequential counterpart, just faster. Error-free concurrent programming remains a tricky problem, beyond the capabilities of most programmers. Consequently, an attractive alternative to manually developing a concurrent program is to automatically synthesise one. This dissertation presents two novel formal verification-based methods for safely transforming a sequential program into a concurrent one. The first method---an instance of proof-directed synthesis---takes as the input a sequential program and its safety proof, as well as annotations on where to parallelise, and produces a correctly-synchronised parallelised program, along with a proof of that program. The method uses the sequential proof to guide the insertion of synchronisation barriers to ensure that the parallelised program has the same behaviour as the original sequential version. The sequential proof, written in separation logic, need only represent shape properties, meaning we can parallelise complex heap-manipulating programs without verifying every aspect of their behaviour. The second method proposes specification-directed synthesis: given a sequential program, we extract a rich, stateful specification compactly summarising program behaviour, and use that specification for parallelisation. At the heart of the method is a learning algorithm which combines dynamic and static analysis. In particular, dynamic symbolic execution and the computational learning technique grammar induction are used to conjecture input-output specifications, and counterexample-guided abstraction refinement to confirm or refute the equivalence between the conjectured specification and the original program. Once equivalence checking succeeds, from the inferred specifications we synthesise code that executes speculatively in parallel---enabling automated parallelisation of irregular loops that are not necessary polyhedral, disjoint or with a static pipeline structure.
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Jobredeaux, Romain J. "Formal verification of control software." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53841.

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In a context of heightened requirements for safety-critical embedded systems and ever-increasing costs of verification and validation, this research proposes to advance the state of formal analysis for control software. Formal methods are a field of computer science that uses mathematical techniques and formalisms to rigorously analyze the behavior of programs. This research develops a framework and tools to express and prove high level properties of control law implementations. One goal is to bridge the gap between control theory and computer science. An annotation language is extended with symbols and axioms to describe control-related concepts at the code level. Libraries of theorems, along with their proofs, are developed to enable an interactive proof assistant to verify control-related properties. Through integration in a prototype tool, the process of verification is made automatic, and applied to several example systems.In a context of heightened requirements for safety-critical embedded systems and ever-increasing costs of verification and validation, this research proposes to advance the state of formal analysis for control software. Formal methods are a field of computer science that uses mathematical techniques and formalisms to rigorously analyze the behavior of programs. This research develops a framework and tools to express and prove high level properties of control law implementations. One goal is to bridge the gap between control theory and computer science. An annotation language is extended with symbols and axioms to describe control-related concepts at the code level. Libraries of theorems, along with their proofs, are developed to enable an interactive proof assistant to verify control-related properties. Through integration in a prototype tool, the process of verification is made automatic, and applied to several example systems.
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Parikh, Ankur. "Abstraction Guided Semi-formal Verification." Thesis, Virginia Tech, 2007. http://hdl.handle.net/10919/33596.

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Abstraction-guided simulation is a promising semi-formal framework for design validation in which an abstract model of the design is used to guide a logic simulator towards a target property. However, key issues still need to be addressed before this framework can truly deliver on it's promise. Concretizing, or finding a real trace from an abstract trace, remains a hard problem. Abstract traces are often spurious, for which no corresponding real trace exits. This is a direct consequence of the abstraction being an over-approximation of the real design. Further, the way in which the abstract model is constructed is an open-ended problem which has a great impact on the performance of the simulator. In this work, we propose a novel approaches to address these issues. First, we present a genetic algorithm to select sets of state variables directly from the gate-level net-list of the design, which are highly correlated to the target property. The sets of selected variables are used to build the Partition Navigation Tracks (PNTs). PNTs capture the behavior of expanded portions of the state space as they related to the target property. Moreover, the computation and storage costs of the PNTs is small, making them scale well to large designs. Our experiments show that we are able to reach many more hard-to-reach states using our proposed techniques, compared to state-of-the-art methods. Next, we propose a novel abstraction strengthening technique, where the abstract design is constrained to make it more closely resemble the concrete design. Abstraction strengthening greatly reduces the need to refine the abstract model for hard to reach properties. To achieve this, we efficiently identify sequentially unreachable partial sates in the concrete design via intelligent partitioning, resolution and cube enlargement. Then, these partial states are added as constraints in the abstract model. Our experiments show that the cost to compute these constraints is low and the abstract traces obtained from the strengthened abstract model are far easier to concretize.
Master of Science
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Bubel, Richard. "Formal verification of recursive predicates." [S.l. : s.n.], 2007. http://digbib.ubka.uni-karlsruhe.de/volltexte/1000008366.

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Suresh, Amrita. "Formal Verification of Communicating Automata." Electronic Thesis or Diss., université Paris-Saclay, 2022. http://www.theses.fr/2022UPASG092.

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Les systèmes distribués concernent des processus qui s’exécutent indépendamment et communiquent de manière asynchrone. Bien qu’ils couvrent un large éventail de cas d’utilisation et soient donc omniprésents dans notre monde, il est particulièrement difficile de garantir leur exactitude. Dans cette thèse, nous modélisons de tels systèmes en utilisant une formulation mathématique et logique, et nousles vérifions algorithmiquement. En particulier, nous nous concentrons sur les automates FIFO (First In First Out), et plus précisément sur des systèmes à un ou plusieurs automates finis qui communiquent via des canaux FIFO fiables pouvant contenir des mots de longueur arbitrairement grande. Comme la plupart des problèmes de vérification sont connus pour être indécidables pour les automates FIFO, nous nous concentrons sur diverses sous-classes et approximations du modèle. Le premier modèle que nous considérons est celui des systèmes de transition bien structurés sur les branches d’états accessibles (branch-WSTS), une classe qui inclut strictement la classe des WSTS. Nous étudions les problèmes de finitude des canaux et de terminaison pour de tels systèmes, et nous en montrons quelques exemples. Nous définissons également une autre classe de systèmes où la condition de monotonie est relâchée et nous montrons qu’une variante du problème de couerture est décidable sous des conditions naturelles d’effectivité. Nous étudions ensuite la restriction de la limitation de l’entrée (input-boundedness) sur les canaux FIFO et nous montrons que l’accessibilité rationnelle et diverses autres propriétés sont décidables pour les automates FIFO. Ce faisant, nous répondons à une question ouverte concernant l’accessibilité des automates FIFO limités en entrée. Nous dérivons également certaines bornes de complexité en considérant le cas le plus simple, un automate FIFO avec un seul canal. Une autre restriction que nous étudions est la synchronisabilité dans les systèmes communicants. En particulier, nous étudions cette notion pour les MSCs (Message Sequence Charts), qui est un modèle pour représenter les exécutions d’un système communicant. Nous montrons que si un ensemble quelconque de MSC satisfait les deux propriétés suivantes, à savoir la définissabilité MSO (Monadic Second-order Logic) et la (spécial) largeur d’arbre (tree-width) bornée, alors la synchronisabilité est décidable. De plus, l’accessibilité et le model checking sont également décidables dans ce cadre. Nous unifions alors certaines classes de la littérature à l’aide de ce cadre, et pour certaines autres classes, nous montrons leur indécidabilité
Distributed systems involve processes that run independently and communicate asynchronously. While they capture a wide range of use cases and are hence, ubiquitous in our world, it is also particularly difficult to ensure their correctness. In this thesis, we model such systems using mathematical and logical formulation, and try to algorithmically verify them. In particular, we focus on FIFO (First In First Out) machines, with one or more finite-state machines communicating via unbounded reliable FIFO buffers.As most verification problems are known to be undecidable for FIFO machines, we focus on various subclasses and approximations of the model. The first model we consider are branch-well structured transition systems (branch-WSTS), a class which strictly includes the well-known class of WSTS. We study the problems of boundedness and termination for such systems, and demonstrate some examples of them. We also define another class of systems where the monotony condition is relaxed and show that a variant of the coverability problem is decidable under effectivity conditions.We then study the restriction of input-boundedness on FIFO machines, and show that rational reachability and various other properties are decidable for FIFO machines under the input-bounded restriction. In doing so, we answer a long standing open question regarding the reachability for input-bounded FIFO machines. We also derive some complexity bounds by considering the simplest case, a FIFO machine with a single channel.Another restriction that we study is synchronizability in communicating systems. In particular, we study this notion for MSCs (Message Sequence Charts), which is a model to represent executions of a communicating system. We show that if any set of MSCs can satisfy two properties, namely MSO (Monadic Second-order Logic) definability and bounded (special-)tree width, then synchronizability is decidable. Moreover, reachability and model-checking are also decidable within this framework. We also unify some classes from the literature using this framework, and for some other classes, show their undecidability
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Wei, Jijie. "Formal verification of a digital PLL." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/50048.

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Common AMS circuit are composed from blocks that can be modeled accurately using linear differential inclusions to enable verification of important properties using reachability analysis. This dissertation presents a formal verification of Digital Phase Locked Loop (PLL) using reachability techniques. PLLs are ubiquitous in analog mixed signal (AMS) designs and are widely used in modern communication equipment, clock generation for CPUs in computers, clock-acquisition in high-speed links etc. The most important property of a PLL is convergence, which means starting from any possible initial conditions, the PLL will eventually lock to the desired equilibrium. We model the digital PLL as a set of Ordinary Differential equation (ODEs), and discretize the weakly non-linear ODEs to linear differential inclusions. The transformation not only provides us an over approximation of the verification problem but also provides the basis for a sound proof. We present the verification of a digital PLL using real tools, SpaceEx and Coho. In particular, we show how each component of the digital PLL can be modelled as a hybrid automaton. Due to the large number of transitions caused by the model, the whole proof is established by several lemmas. Interesting problems such as a timing glitch in the Phase Frequency Detector (PFD) are discussed and triggering conditions are formally proved in the dissertation. Global convergence is demonstrated by both tools. Based on the digital PLL circuit and the challenges that arose during our verification, the error bounds, limitations, implementation differences and usability of the two leading tools are carefully evaluated. SpaceEx provides a graphical user interface that makes it easy to get started with simple examples but requires extensive user interaction for larger problems. The interface to Coho is a MATLAB API. While this lacks the packaged-tool feel of SpaceEx, it provides a flexible way to break a large verification problem into smaller lemmas and allows the proof to be ''re-executed'' simply by re-executing the MATLAB script.
Science, Faculty of
Computer Science, Department of
Graduate
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Books on the topic "Formal verification"

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Kropf, Thomas, ed. Formal Hardware Verification. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63475-4.

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Drechsler, Rolf, ed. Advanced Formal Verification. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/b105236.

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Drechsler, Rolf, ed. Formal System Verification. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-57685-5.

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Rolf, Drechsler, ed. Advanced formal verification. Boston: Kluwer Academic Publishers, 2004.

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Drechsler, Rolf. Formal Verification of Circuits. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3184-2.

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Drechsler, Rolf. Formal Verification of Circuits. Boston, MA: Springer US, 2000.

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Boulanger, Jean-Louis. Industrial used of formal method: Formal verification. London: ISTE, 2012.

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Kropf, Thomas. Introduction to Formal Hardware Verification. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999.

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Bernardo, Marco, and Alessandro Cimatti, eds. Formal Methods for Hardware Verification. Berlin, Heidelberg: Springer Berlin Heidelberg, 2006. http://dx.doi.org/10.1007/11757283.

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Ray, Sandip. Scalable Techniques for Formal Verification. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-5998-0.

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Book chapters on the topic "Formal verification"

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Rülling, Wolfgang. "Formal Verification." In The Electronic Design Automation Handbook, 329–38. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_14.

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Bernadeschi, Cinzia, Alessandro Fantechi, and Stefania Gnesi. "Formal Verification." In A Generic Fault-Tolerant Architecture for Real-Time Dependable Systems, 139–55. Boston, MA: Springer US, 2001. http://dx.doi.org/10.1007/978-1-4757-3353-2_8.

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Weik, Martin H. "formal verification." In Computer Science and Communications Dictionary, 630. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_7435.

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Staunstrup, Jørgen. "Formal Verification." In A Formal Approach to Hardware Design, 47–80. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2764-0_3.

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Lin, Hai, and Panos J. Antsaklis. "Formal Verification." In Advanced Textbooks in Control and Signal Processing, 65–155. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-78731-8_3.

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Walter, Marcel, Robert Wille, Frank Sill Torres, and Rolf Drechsler. "Formal Verification." In Design Automation for Field-coupled Nanotechnologies, 135–49. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-89952-3_8.

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Nielson, Flemming, and Hanne Riis Nielson. "Program Verification." In Formal Methods, 31–46. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-05156-3_3.

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Coelho, Claudionor Nunes, and Harry D. Foster. "Assertion-Based Verification." In Advanced Formal Verification, 167–204. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/1-4020-2530-0_5.

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Hazelhurst, Scott, and Carl-Johan H. Seger. "Symbolic trajectory evaluation." In Formal Hardware Verification, 3–78. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63475-4_1.

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Cerny, E., F. Corella, M. Langevin, X. Song, S. Tahar, and Z. Zhou. "Automated verification with abstract state machines using multiway decision graphs." In Formal Hardware Verification, 79–113. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/3-540-63475-4_2.

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Conference papers on the topic "Formal verification"

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Wolfsthal, Yaron, and Rebecca M. Gott. "Formal verification." In the 42nd annual conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1065579.1065755.

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Dill, David, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev Ranjan, Gunnar Stålmarck, and Curt Widdoes. "Formal verification methods." In the 39th conference. New York, New York, USA: ACM Press, 2002. http://dx.doi.org/10.1145/513918.514064.

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Drechsler, Rolf, and Alireza Mahzoon. "Polynomial Formal Verification." In ICCAD '22: IEEE/ACM International Conference on Computer-Aided Design. New York, NY, USA: ACM, 2022. http://dx.doi.org/10.1145/3508352.3561104.

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Beers, Robert. "Pre-RTL formal verification." In the 45th annual conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1391469.1391675.

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Jang, Jae-Young, Shaz Qadeer, Matt Kaufmann, and Carl Pixley. "Formal verification of FIRE." In the 34th annual conference. New York, New York, USA: ACM Press, 1997. http://dx.doi.org/10.1145/266021.266059.

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Doghri, Ines. "Formal verification of WAHS." In the 8th international conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1416729.1416754.

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"Session 6: Formal verification." In 2007 IEEE International High Level Design Validation and Test Workshop. IEEE, 2007. http://dx.doi.org/10.1109/hldvt.2007.4392795.

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"Session 4: Formal verification." In 2008 IEEE International High Level Design Validation and Test Workshop. IEEE, 2008. http://dx.doi.org/10.1109/hldvt.2008.4695872.

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Agrawal, Arpan, Emily First, Zhanna Kaufman, Tom Reichel, Shizhuo Zhang, Timothy Zhou, Alex Sanchez-Stern, Talia Ringer, and Yuriy Brun. "PRoofster: Automated Formal Verification." In 2023 IEEE/ACM 45th International Conference on Software Engineering: Companion Proceedings (ICSE-Companion). IEEE, 2023. http://dx.doi.org/10.1109/icse-companion58688.2023.00018.

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Yang, Jin, and Avi Puder. "Tightly integrate dynamic verification with formal verification." In the 2005 conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1120725.1120860.

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Reports on the topic "Formal verification"

1

Ernst, Michael. Verification Games: Crowd-Sourced Formal Verification. Fort Belvoir, VA: Defense Technical Information Center, March 2016. http://dx.doi.org/10.21236/ad1006471.

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Andronick, June, and Gerwin Klein. Formal System Verification - Extension 2. Fort Belvoir, VA: Defense Technical Information Center, August 2012. http://dx.doi.org/10.21236/ada570949.

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Mayer, Barbara A., and Monica M. Lu. Guidelines for Formal Verification Systems. Fort Belvoir, VA: Defense Technical Information Center, April 1989. http://dx.doi.org/10.21236/ada385357.

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Punnoose, Ratish J., Robert C. Armstrong, Matthew H. Wong, and Mayo Jackson. Survey of Existing Tools for Formal Verification. Office of Scientific and Technical Information (OSTI), December 2014. http://dx.doi.org/10.2172/1166644.

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Andronick, June, and Gerwin Klein. Formal System Verification for Trustworthy Embedded Systems. Fort Belvoir, VA: Defense Technical Information Center, April 2011. http://dx.doi.org/10.21236/ada541318.

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Berry, Daniel M. Formal Specification and Verification of Concurrent Programs. Fort Belvoir, VA: Defense Technical Information Center, February 1993. http://dx.doi.org/10.21236/ada265201.

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Chavan, Anand, Byoung Woo Min, and Shiu-Kai Chin. HOL2GDT a Formal Verification-Based Design Methodology. Fort Belvoir, VA: Defense Technical Information Center, April 2001. http://dx.doi.org/10.21236/ada387742.

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Meadows, Catherine A. Formal Verification of Cryptographic Protocols: A Survey. Fort Belvoir, VA: Defense Technical Information Center, January 1995. http://dx.doi.org/10.21236/ada464292.

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Brackin, Stephen H., and Ian Sutherland. Formal Verification of Mathematical Software. Volume 2. Fort Belvoir, VA: Defense Technical Information Center, May 1990. http://dx.doi.org/10.21236/ada223633.

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Dill, David L. A Federal Approach to Formal Hardware Design Verification. Fort Belvoir, VA: Defense Technical Information Center, April 2002. http://dx.doi.org/10.21236/ada400999.

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