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Journal articles on the topic 'Floating Gate Memory'

Author: Grafiati

Published: 6 September 2023

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1

Rajput, Renu, and Rakesh Vaid. "Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review." Facta universitatis - series: Electronics and Energetics 33, no. 2 (2020): 155–67. http://dx.doi.org/10.2298/fuee2002155r.

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Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge car

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2

Li, Bei, Jianlin Liu, G. F. Liu, and J. A. Yarmoff. "Ge∕Si heteronanocrystal floating gate memory." Applied Physics Letters 91, no. 13 (2007): 132107. http://dx.doi.org/10.1063/1.2793687.

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3

Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (2019): 643. http://dx.doi.org/10.3390/mi10100643.

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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts i

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4

Noor, Fatimah Arofiati, Gilang Mardian Kartiwa, and Muhammad Amin Sulthoni. "Studi Elektrostatik Elektroda Runcing dan Aplikasinya pada Perangkat Floating Gate Memory." POSITRON 11, no. 1 (2021): 1. http://dx.doi.org/10.26418/positron.v11i1.44881.

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Pada penelitian ini, potensial elektrostatik dari struktur floating gate runcing dalam sel memori split gate dipelajari secara analitik dan numerik. Penelitian ini bertujuan memberikan pendekatan sederhana untuk mempelajari diagram pita energi pada perangkat memori. Diagram energi yang dihasilkan dapat digunakan untuk mempelajari transmitansi elektron dan rapat arus terobosan. Pada studi ini, floating gate runcing dimodelkan sebagai elektroda berbentuk segitiga. Profil potensial elektrostatik elektroda segitiga ini dihitung secara analitik dengan menyelesaikan nilai batas dari persamaan Laplac

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5

Lingalugari, Murali, Evan Heller, Barath Parthasarathy, John Chandy, and Faquir Jain. "Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing." International Journal of High Speed Electronics and Systems 27, no. 01n02 (2018): 1840006. http://dx.doi.org/10.1142/s0129156418400062.

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This paper presents an approach to enhance floating gate quantum dot nonvolatile random access memory (QDNVRAM) cells in terms of higher-speed and lower-voltage Erase not possible with conventional floating gate nonvolatile memories. It is achieved by directly accessing the floating gate layer with a Ge quantum dot access channel via an additional drain (D2) during the Erase and/or Write operation. Quantum mechanical simulations in GeOx-cladded Ge quantum dot layers functioning as the floating gate as well access channel to facilitate Erase and Write are presented. Experimental data on fabrica

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6

Zhang, Pengfei, Dong Li, Mingyuan Chen, et al. "Floating-gate controlled programmable non-volatile black phosphorus PNP junction memory." Nanoscale 10, no. 7 (2018): 3148–52. http://dx.doi.org/10.1039/c7nr08515j.

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By designing and tailoring the structure of the floating gate, a special floating-gate field-effect transistor configuration has been proposed for the design of programmable non-volatile black phosphorus PNP junction memory.

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7

Lee, Boong-Joo. "Operating characteristics of Floating Gate Organic Memory." Journal of the Korea Academia-Industrial cooperation Society 15, no. 8 (2014): 5213–18. http://dx.doi.org/10.5762/kais.2014.15.8.5213.

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8

Park, Byoungjun, Kyoungah Cho, Sungsu Kim, and Sangsig Kim. "Transparent nano-floating gate memory on glass." Nanotechnology 21, no. 33 (2010): 335201. http://dx.doi.org/10.1088/0957-4484/21/33/335201.

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9

Cellere, G., P. Pellati, A. Chimenton, et al. "Radiation effects on floating-gate memory cells." IEEE Transactions on Nuclear Science 48, no. 6 (2001): 2222–28. http://dx.doi.org/10.1109/23.983199.

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10

Lee, Jang-Sik. "Review paper: Nano-floating gate memory devices." Electronic Materials Letters 7, no. 3 (2011): 175–83. http://dx.doi.org/10.1007/s13391-011-0901-5.

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11

Jang, Sukjae, Euyheon Hwang, Jung Heon Lee, Ho Seok Park, and Jeong Ho Cho. "Graphene-Graphene Oxide Floating Gate Transistor Memory." Small 11, no. 3 (2014): 311–18. http://dx.doi.org/10.1002/smll.201401017.

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12

Nagashio, Kosuke. "(Invited, Digital Presentation) 50 Ns Ultrafast Memory Operation in 2D Heterostructured Non-Volatile Memory Device." ECS Meeting Abstracts MA2022-01, no. 10 (2022): 785. http://dx.doi.org/10.1149/ma2022-0110785mtgabs.

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2D heterostructures have been extensively investigated as next-generation non-volatile memory (NVM) devices. In the last decade, drastic performance improvements and further advanced functionalities have been demonstrated. However, this progress is not sufficiently supported by the understanding of their operations, obscuring the material and device structure design policy. Here, detailed operation mechanisms are elucidated by exploiting the floating gate voltage (V FG) trajectory measurements [1,2]. Systematic comparisons of MoTe2, WSe2, and MoS2 channel devices revealed that the tunneling be

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13

Chen, Yi-Yueh, Feng-Ming Lee, Yu-Yu Lin, et al. "New n-p Junction Floating Gate to Enhance the Operation Performance of a Semiconductor Memory Device." Materials 15, no. 10 (2022): 3640. http://dx.doi.org/10.3390/ma15103640.

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To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the ch

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14

Sasaki, Taro, Keiji Ueno, Takashi Taniguchi, Kenji Watanabe, Tomonori Nishimura, and Kosuke Nagashio. "Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage." Small 16, no. 47 (2020): 2004907. http://dx.doi.org/10.1002/smll.202004907.

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15

Pei, Yan Li, Tatsuro Hiraki, Toshiya Kojima, Takafumi Fukushima, Mitsumasa Koyanagi, and Tetsu Tanaka. "Energy Band Engineering of Metal Nanodots for High Performance Nonvolatile Memory Application." Key Engineering Materials 470 (February 2011): 140–45. http://dx.doi.org/10.4028/www.scientific.net/kem.470.140.

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In this work, high density and small size metal nanodots (MND) with different work-functions were fabricated as a floating gate of nonvolatile memory (NVM) devices by self-assembled nanodot deposition (SAND). The energy band engineering of NVM was demonstrated through controlling MND work-function. For single MND layer floating gate NVM, the retention time was improved by choosing high work-function MND. Furthermore, we proposed a new type NVM with a double stacked MND floating gate. Here, the high work-function MND are placed on the top layer and the low work-function MND are placed on the bo

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16

Jang, Sukjae, Euyheon Hwang, and Jeong Ho Cho. "Graphene nano-floating gate transistor memory on plastic." Nanoscale 6, no. 24 (2014): 15286–92. http://dx.doi.org/10.1039/c4nr04117h.

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A transparent flexible graphene nano-floating gate transistor memory (NFGTM) device was developed by combining a single-layered graphene active channel with gold nanoparticle (AuNP) charge trap elements.

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17

Chen, C. D., Y. Nakamura, and J. S. Tsai. "Aluminum single-electron nonvolatile floating gate memory cell." Applied Physics Letters 71, no. 14 (1997): 2038–40. http://dx.doi.org/10.1063/1.119780.

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18

Snyder, E. S., P. J. McWhorter, T. A. Dellin, and J. D. Sweetman. "Radiation response of floating gate EEPROM memory cells." IEEE Transactions on Nuclear Science 36, no. 6 (1989): 2131–39. http://dx.doi.org/10.1109/23.45415.

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19

Hasaneen, El-Sayed, E. Heller, R. Bansal, W. Huang, and F. Jain. "Modeling of nonvolatile floating gate quantum dot memory." Solid-State Electronics 48, no. 10-11 (2004): 2055–59. http://dx.doi.org/10.1016/j.sse.2004.05.073.

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20

Martins, Rodrigo, P. Barquinha, L. Pereira, et al. "Selective floating gate non-volatile paper memory transistor." physica status solidi (RRL) - Rapid Research Letters 3, no. 9 (2009): 308–10. http://dx.doi.org/10.1002/pssr.200903268.

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21

Wang, Shuopei, Congli He, Jian Tang, et al. "New Floating Gate Memory with Excellent Retention Characteristics." Advanced Electronic Materials 5, no. 4 (2019): 1800726. http://dx.doi.org/10.1002/aelm.201800726.

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22

Sun, Sheng, and Shengdong Zhang. "Nanoparticle floating-gate transistor memory based on solution-processed ambipolar organic semiconductor." E3S Web of Conferences 185 (2020): 04071. http://dx.doi.org/10.1051/e3sconf/202018504071.

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Organic thin-film transistor memory based on nano-floating-gate nonvolatile memory was demonstrated by a simple method. The gold nanoparticle that fabricated by thermally evaporated acted as the floating gate. Spin coated PMMA film acted as the tunneling layer. A solution-processed ambipolar semiconductor acted as the active layer. Because of the existence of both hole and electron carriers in bipolar semiconductor materials, it is more conducive to the editing and erasing of memories under positive and negative pressure. The memory based on metal nanoparticles and organic bipolar semiconducto

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23

Dolicanin, Edin. "Gamma ray effects on flash memory cell arrays." Nuclear Technology and Radiation Protection 27, no. 3 (2012): 284–89. http://dx.doi.org/10.2298/ntrp1203284d.

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Information stored in flash memories is physically represented by the absence or presence of charge on electrically isolated floating gates. Interaction of gamma rays with the insulators surrounding the floating gate produces effects that degrade the properties of memory cells, possibly leading to the corruption of the stored content. The cumulative nature of these effects is expressed through the total ionizing dose deposited by the gamma rays in the insulators surrounding the floating gate. Relying on both theory and experiment, we examine how the properties of cells in commercially availabl

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24

Gan, Lu-Rong, Ya-Rong Wang, Lin Chen, Hao Zhu, and Qing-Qing Sun. "A Floating Gate Memory with U-Shape Recessed Channel for Neuromorphic Computing and MCU Applications." Micromachines 10, no. 9 (2019): 558. http://dx.doi.org/10.3390/mi10090558.

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We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO2 high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the b

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25

Jang, Sukjae, Euyheon Hwang, Jung Heon Lee, Ho Seok Park, and Jeong Ho Cho. "Memory: Graphene-Graphene Oxide Floating Gate Transistor Memory (Small 3/2015)." Small 11, no. 3 (2015): 261. http://dx.doi.org/10.1002/smll.201570014.

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26

ZHANG, YUEGANG. "CARBON NANOTUBE BASED NONVOLATILE MEMORY DEVICES." International Journal of High Speed Electronics and Systems 16, no. 04 (2006): 959–75. http://dx.doi.org/10.1142/s0129156406004107.

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The technology progress and increasing high density demand have driven the nonvolatile memory devices into nanometer scale region. There is an urgent need of new materials to address the high programming voltage and current leakage problems in the current flash memory devices. As one of the most important nanomaterials with excellent mechanical and electronic properties, carbon nanotube has been explored for various nonvolatile memory applications. While earlier proposals of "bucky shuttle" memories and nanoelectromechanical memories remain as concepts due to fabrication difficulty, recent stu

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27

Gong, Liang, Rui Ming Li, Qi Xiong, and Shao Hua Zhou. "The Equivalent Circuit Model of Floating-Gate Single-Electron Memorizer." Applied Mechanics and Materials 416-417 (September 2013): 1721–25. http://dx.doi.org/10.4028/www.scientific.net/amm.416-417.1721.

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Based on the introduction of floating-gate silicon quantum dot single-electron memorizers structure and working principle, this paper builds corresponding lumping current and capacitance model to calculate the current with memory in the circumstance of linearity, saturation and sub-threshold. Taking advantage of the single-electron devices Threshold Voltage Shift educes different storage condition of nanostorage with different threshold voltage. The simulation shows, this model can precisely simulate memorys read and write state.

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28

Hu, Hongsheng, Zhongyuan Ma, Xinyue Yu, et al. "Controlling the Carrier Injection Efficiency in 3D Nanocrystalline Silicon Floating Gate Memory by Novel Design of Control Layer." Nanomaterials 13, no. 6 (2023): 962. http://dx.doi.org/10.3390/nano13060962.

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Three-dimensional NAND flash memory with high carrier injection efficiency has been of great interest to computing in memory for its stronger capability to deal with big data than that of conventional von Neumann architecture. Here, we first report the carrier injection efficiency of 3D NAND flash memory based on a nanocrystalline silicon floating gate, which can be controlled by a novel design of the control layer. The carrier injection efficiency in nanocrystalline Si can be monitored by the capacitance–voltage (C–V) hysteresis direction of an nc-Si floating-gate MOS structure. When the cont

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29

Chen, Hongye, Ye Zhou, and Su‐Ting Han. "Recent advances in metal nanoparticle‐based floating gate memory." Nano Select 2, no. 7 (2021): 1245–65. http://dx.doi.org/10.1002/nano.202000268.

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30

Jiyan Y. Dai and Pui-Fai Lee. "Recent Patents in Semiconductor Nanocluster Floating Gate Flash Memory." Recent Patents on Nanotechnology 1, no. 2 (2007): 91–97. http://dx.doi.org/10.2174/187221007780859636.

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31

Kim, H. S., B. J. Lee, and P. K. Shin. "Floating Gate Organic Memory Device with Tunneling Layer's Thickness." Journal of the Korean Vacuum Society 21, no. 6 (2012): 354–61. http://dx.doi.org/10.5757/jkvs.2012.21.6.354.

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32

Li, Bei, and Jianlin Liu. "Nonvolatile Memory With Ge/Si Heteronanocrystals as Floating Gate." IEEE Transactions on Nanotechnology 10, no. 2 (2011): 284–90. http://dx.doi.org/10.1109/tnano.2009.2039488.

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33

Chan, K. C., P. F. Lee, and J. Y. Dai. "Mesoscopic phenomena in Au nanocrystal floating gate memory structure." Applied Physics Letters 95, no. 11 (2009): 113109. http://dx.doi.org/10.1063/1.3229885.

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34

Chen, F. Y., Y. K. Fang, M. J. Sun, and Jiann‐Ruey Chen. "A nonvolatile ferroelectric memory device with a floating gate." Applied Physics Letters 69, no. 21 (1996): 3275–76. http://dx.doi.org/10.1063/1.118034.

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35

Bleiker, C., and H. Melchior. "A four-state EEPROM using floating-gate memory cells." IEEE Journal of Solid-State Circuits 22, no. 3 (1987): 460–63. http://dx.doi.org/10.1109/jssc.1987.1052751.

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36

Yin, Cheng-Kuan, Ji-Chel Bea, Youn-Gi Hong, et al. "New Magnetic Flash Memory with FePt Magnetic Floating Gate." Japanese Journal of Applied Physics 45, no. 4B (2006): 3217–21. http://dx.doi.org/10.1143/jjap.45.3217.

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37

Wang, Wei, Jiawei Shi, and Dongge Ma. "Organic Thin-Film Transistor Memory With Nanoparticle Floating Gate." IEEE Transactions on Electron Devices 56, no. 5 (2009): 1036–39. http://dx.doi.org/10.1109/ted.2009.2016031.

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38

Wang, Wei, Dongge Ma, and Qiang Gao. "Organic thin-film transistor memory with Ag floating-gate." Microelectronic Engineering 91 (March 2012): 9–13. http://dx.doi.org/10.1016/j.mee.2011.11.006.

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39

Carley, L. R. "Trimming analog circuits using floating-gate analog MOS memory." IEEE Journal of Solid-State Circuits 24, no. 6 (1989): 1569–75. http://dx.doi.org/10.1109/4.44992.

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40

Yamauchi, Yoshimitsu, Yoshinari Kamakura, and Toshimasa Matsuoka. "Scalable Virtual-Ground Multilevel-Cell Floating-Gate Flash Memory." IEEE Transactions on Electron Devices 60, no. 8 (2013): 2518–24. http://dx.doi.org/10.1109/ted.2013.2270565.

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41

Bagatin, Marta, and Simone Gerardin. "Soft errors in floating gate memory cells: A review." Microelectronics Reliability 55, no. 1 (2015): 24–30. http://dx.doi.org/10.1016/j.microrel.2014.10.016.

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42

Zhu, Yan, Dengtao Zhao, Ruigang Li, and Jianlin Liu. "Threshold voltage shift of heteronanocrystal floating gate flash memory." Journal of Applied Physics 97, no. 3 (2005): 034309. http://dx.doi.org/10.1063/1.1847700.

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43

Kuruoğlu, Furkan, Murat Çalışkan, Merih Serin, and Ayşe Erol. "Well-ordered nanoparticle arrays for floating gate memory applications." Nanotechnology 31, no. 21 (2020): 215203. http://dx.doi.org/10.1088/1361-6528/ab7043.

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44

Cellere, G., L. Larcher, A. Paccagnella, A. Visconti, and M. Bonanomi. "Radiation induced leakage current in floating gate memory cells." IEEE Transactions on Nuclear Science 52, no. 6 (2005): 2144–52. http://dx.doi.org/10.1109/tns.2005.860725.

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45

Fujita, O., and Y. Amemiya. "A floating-gate analog memory device for neural networks." IEEE Transactions on Electron Devices 40, no. 11 (1993): 2029–35. http://dx.doi.org/10.1109/16.239745.

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46

Makwana, J. J., and D. K. Schroder. "Nonvolatile floating-gate memory programming enhancement using well bias." IEEE Transactions on Electron Devices 53, no. 2 (2006): 258–62. http://dx.doi.org/10.1109/ted.2005.861723.

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47

Lisoni, Judit G., Laurent Breuil, Pieter Blomme, et al. "Material selection for hybrid floating gate NAND memory applications." physica status solidi (a) 213, no. 2 (2016): 237–44. http://dx.doi.org/10.1002/pssa.201532829.

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48

QIN, Shi-xian, Chao MA, Jun-jie XING, Bo-wen LI, and Guo-cheng ZHANG. "Transparent organic memory based on quantum dots floating gate." Chinese Journal of Liquid Crystals and Displays 38, no. 7 (2023): 919–25. http://dx.doi.org/10.37188/cjlcd.2023-0041.

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49

Yoon, Jong-Hwan. "Memory properties of Al-based nanoparticle floating gate for nonvolatile memory applications." Journal of the Korean Physical Society 61, no. 5 (2012): 799–802. http://dx.doi.org/10.3938/jkps.61.799.

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50

Jin, Risheng, Jin Wang, Keli Shi, et al. "Multilevel storage and photoinduced-reset memory by an inorganic perovskite quantum-dot/polystyrene floating-gate organic transistor." RSC Advances 10, no. 70 (2020): 43225–32. http://dx.doi.org/10.1039/d0ra08021g.

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A novel floating-gate organic transistor memory with photoinduced-reset and multilevel storage function is demonstrated. The device has a large memory window (≈90 V), ultrahigh memory on/off ratio (over 10<sup>7</sup>) and long retention time (over 10 years).

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