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Ostraat, Michele L. Atwater Harry Albert. "Synthesis and characterization of aerosol silicon nanoparticle nonvolatile floating gate memory devices /." Diss., Pasadena, Calif. : California Institute of Technology, 2001. http://resolver.caltech.edu/CaltechETD:etd-04072005-081230.
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Fakher, Sundes Juma. "Advanced study of pentacene-based organic memory structures." Thesis, Bangor University, 2014. https://research.bangor.ac.uk/portal/en/theses/advanced-study-of-pentacenebased-organic-memory-structures(5319a571-2c4c-4f90-a26c-fa5e7da82cfb).html.
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A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.
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Couto, Andre Luis do. "Caracterização de memorias analogicas implementadas com transistores MOS floating gate." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.
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Orientador: Carlos Alberto dos Reis FilhoDissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
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Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área
Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Marron, Dominique. "Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche." Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.
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Afin d'accroitre la complexite des composants electroniques, leur architecture utilise des elements redondants. On pallie ainsi les problemes de rendements. Cette these traite d'un element de reconfiguration, le transistor a grille flottante, et de sa programmation par un faisceau d'electrons. Les conditions de programmation, la tenue dans le temps de la charge deposee ainsi que les problemes pratiques rencontres sont etudies. Ce transistor est ensuite utilise dans la conception d'une memoire sram de 4. 5 mbit reconfigurable integree sur une tranche d=100. Les contraintes pratiques et l'architecture sont exposees de meme que la partie realisation et test. Cette etude est en fait une etude de faisabilite pour des circuits de type wsi industriels
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Marzaki, Abderrezak. "Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4768.
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La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de technologie existante, la technologie CMOS est la plus utilisée. Dans le cadre du développement de la technologie CMOS 90nm à double niveau de poly, des recherches sur l’introduction de techniques innovantes de procédé de fabrication et d’une nouvelle architecture de transistor MOS à tension de seuil ajustable ont été menées dans le but d’améliorer les performances des ICs. Une première étude sur l’implémentation des effets de pointe dans les ICs, en particulier pour les mémoires non volatiles est entreprise. Un nouveau procédé de fabrication permettant d’obtenir des pointes dans un matériau est proposé. Il est démontré le gain en courant tunnel obtenu sur une structure pointue par rapport à une structure plane. Une seconde étude est orientée sur le développement d’une nouvelle technique de « patterning ». Les techniques de « patterning » permettent de réduire les dimensions de la photolithographie sans utiliser de masque ayant des dimensions agressives. Les avantages de cette nouvelle technique aux niveaux de sa mise en œuvre et de la suppression des problèmes d’alignement sont présentés. Une dernière étude sur le développement d’un transistor à tension de seuil ajustable est développée. Il est démontré l’avantage de ce composant par rapport aux autres composants à tension de seuil ajustable. La réalisation du modèle et des premières simulations électriques de circuit élémentaire à base de se composant sont présentés. L’amélioration de certaines performances des circuits élémentaire est démontréeThe component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first electrical simulations of elementary circuits composed with this new component are presented. The performance improvement of some elementary circuits is demonstrated
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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.
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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.
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Liu, Yueran 1975. "Novel flash memory with nanocrystal floating gate." Thesis, 2006. http://hdl.handle.net/2152/2819.
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ZHAO, CHUAN-ZHEN, and 趙傳珍. "Floating-gate mos transistors as analog memory devices." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/33712669387087189947.
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Lee, Jong Jin Kwong Dim-Lee. "A study on the nanocrystal floating-gate nonvolatile memory." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1975/leej77040.pdf.
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Lee, Jong Jin. "A study on the nanocrystal floating-gate nonvolatile memory." Thesis, 2005. http://hdl.handle.net/2152/1975.
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Chang, Hsuan-Chun, and 張亘鈞. "Floating-gate Material Systems for Transistor-type Memory Devices." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/23690571512168087481.
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博士國立臺灣大學
化學工程學研究所
103
Abstract Organic-based memory devices have received extensive scientific interest due to their advantages of flexibility, scalability, and material variety. A typical type of charge-trapping OFET memory is organic floating-gate memory. In this device, charges are stored in a metal or in a semiconducting layer called a floating gate, located within the insulating gate dielectric, and completely surrounded by insulator. However, there is no systematic study on the above structure effects. In this thesis, we report the effects of self-assembled monolayer (SAM) modification on the electrical memory characteristics. We further explored the organic heterojunction transistor with donor/acceptor interface on the electrical characteristics of transistor-type memory devices. Additionally, the C60 Needle/CuPc Nanoparticle Double Floating-Gate for the low-voltage nonvolatile memory devices were also investigated. The following summarize the important discovery of this thesis. 1. Improving the characteristics of an organic nano floating gate memory by a self-assembled monolayer (Chapter 2): SAM-based interfacial engineering significantly improved the hysteresis, memory window, and on/off ratio of a nano floating gate memory (NFGM) at zero gate voltage. This NFGM showed a large memory window of up to 190 V and on/off current ratio of 105 during writing and erasing with an operation voltage of 100 V of gate bias in a short time, less than 1 s. Furthermore, the devices show excellent nonvolatile behavior for bistable switching. The ON and OFF state can be stably maintained for 103 s with an Ion/Ioff current ratio of 106 for a pentafluorophenyl trimethoxysilane (FB-SAM) modified device. 2. Nonvolatile Organic Thin Film Transistor Memory Devices Based on Hybrid Nanocomposites of Semiconducting Polymers: Gold Nanoparticles (Chapter 3): Organic thin film transistor (OTFT)-based nonvolatile memory devices using the hybrid nanocomposites of semiconducting poly(9,9-dioctylfluorene-alt-bithiophene) (F8T2) and ligand-capped Au nanoparticles (NPs), thereby serving as a charge storage medium. Electrical bias sweep/excitation effectively modulates the current response of hybrid memory devices through the charge transfer between F8T2 channel and functionalized Au NPs trapping sites. The electrical performance of the hybrid memory devices can be effectively controlled though the loading concentrations (0−9 %) of Au NPs and organic thiolate ligands on Au NP surfaces with different carbon chain lengths (Au-L6, Au-L10, and Au-L18). The memory window induced by voltage sweep is considerably increased by the high content of Au NPs or short carbon chain on the ligand. The hybrid nanocomposite of F8T2 : 9% Au-L6 provides the OTFT memories with a memory window of ∼41 V operated at ±30 V and memory ratio of ∼1 × 103 maintained for 1 × 104 s. 3. Flexible Nonvolatile Transistor Memory Devices Based on One-dimensional Electrospun P3HT:Au Hybrid Nanofibers (Chapter 4): A novel flexible nonvolatile flash transistor memory devices on flexible polyethylene naphthalate (PEN) substrate using one-dimensional (1D) electrospun nanofiber of poly(3-hexylthiophene) (P3HT):gold nanoparticles (Au NPs) hybrid as the channel. The Au NPs are functionalized with self-assembled monolayer (SAM) of para-substituted amino (Au-NH2), methyl (Au-CH3) or trifluoromethyl (Au-CF3) tail groups on the benzenethiol moiety. With the low operation voltage of ±5 V, the hybrid nanofiber transistor memories exhibit a 3.5~10.6 V threshold voltage shifting and at least 104 s data retention, with a minimum effect on ~100 programmed/erased stress endurances. The devices remain reliable and stable even under the bending conditions (radius: 5~30 mm) or 1000 repetitive bending cycles. 4. One-Dimensional Electrospun Nanofiber Channel for Organic Field Effect Transistor using Donor/Acceptor Planar Heterojunction Architecture (Chapter 5): Organic planar p-n heterojunction transistors based on electronspun poly(3-hexlthiophene) (P3HT) nanofibers/thermally deposited copper hexadecafluorophthalocyanine (F16CuPc) active layer have been developed for unipolar p-type nonvolatile memory and ambipolar device through simple tuning of top F16CuPc capping layer thickness. 5. Single-Crystal C60 Needle/CuPc Nanoparticle Double Floating-Gate for Low-Voltage Organic Transistor Based Non-volatile Memory Devices (Chapter 6): The double floating-gate device structure was formed from the semiconducting channel and heterostructured dual chargeable layers of CuPc NPs/single crystal C60 needles (N-C60) covered by crosslinking poly(4-vinylphenol) (c-PVP) tunneling barrier. Discrete p-type CuPc NPs and n-type N-C60 were independently selected as the hole and electron trapping sites for the above double floating-gate transistor memory to further enhance memory window and related data storage capacity. N-C60 trapping sites (diameters~590±15 nm) were first fabricated and then thermal-evaporated CuPc NPs (~15±3 nm) were deposited discretely on the N-C60 or the HfO2 interface. A systematic investigation on memory characteristics of double floating-gate devices were impartially compared to those of individual single floating-gate memory structure (N-C60 or CuPc-only devices) Our study revealed the significance of the self-assembled monolayer, donor/acceptor heterojunction architecture and double floating gate on the OFET memory characteristics for advanced data storage applications.
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Liu, Hai 1977. "Floating gate engineering for novel nonvolatile flash memories." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-05-1132.
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The increasing demands on higher density, lower cost, higher speed, better endurance and longer retention has push flash memory technology, which is predominant and the driving force of the semiconductor nonvolatile memory market in recent years, to the position facing great challenges. However, the conventional flash memory technology using continuous highly doped polysilicon as floating gate, which is the most common in today’s commercial market, can't satisfy these demands, with the transistor size continuously scaling down beyond 32 nm. Nanocrystal floating gate flash memory and SONOS-type flash memory are considered among the most promising approaches to extend scalability and performance improvement for next generation flash memory. This dissertation addresses the issues that have big effects on nanocrystal floating gate flash memory and SONOS-type flash memory performances. New device structures and new material compatible to CMOS flow are proposed and demonstrated as potential solutions for further device performance improvement. First, the effect of nanocrystal-high k dielectric interface quality on nanocrystal flash memory performance is studied. By using germanium-silicon core-shell nanocrystals or ruthenium nanocrystals buried in HfO₂ as charge storage nodes, high interface quality has been achieved, leading to promising memory device performance. Next, another crucial challenge for nanocrystal flash memory on how to deposit uniformly distributed nanocrystal matrix in good shape and size control with high density is discussed. Using protein GroEL to obtain well ordered high density nanocrystal pattern, a flash memory device with Ni nanocrystals buried in HfO₂ is demonstrated. For this technique, the nanocrystal size is restricted to the GroEL's central cavity size and the density is limited by protein template. To overcome this limitation, a novel method using self-assembled Co-SiO₂ nanocrystals as charge storage nodes is demonstrated. Separated by thin SiO₂, these nanocrystals can form close packed form to achieve ultrahigh density. Finally, charge trapping layer band engineering is proposed for SONOS-type memory for better memory performance. By manipulating the pulse ratio of Hf and Al precursor during ALD deposition, the band diagram of Hf[subscript x]Al[subscript y]O charge trapping layer is optimized to have a Hf : Al ratio 3:1 at bottom and 1:3 at the top, leading to better trade-off between programming and retention for the of memory device.text
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Tang, Shan 1975. "Protein-mediated nanocrystal assembly for floating gate flash memory fabrication." 2008. http://hdl.handle.net/2152/18156.
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As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work.text
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Chang, Tsung-Hsien, and 張宗憲. "Study of Nitridation on Floating Gate for Nonvolatile Memory Devices." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/24307782979217963803.
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碩士國立清華大學
工程與系統科學系
90
`In this thesis, nitridation on floating gate of nonvolatile memory devices is used to improve tunneling oxide quality and reliability. Samples, nitridized by NH3 with additional N2O annealing on poly-oxynitride (poly I) and then deposited with a CVD TEOS and a post deposition RTA N2O annealing, show excellent electrical properties in term of electric breakdown field, charge to breakdown, low electron trapping rate, and reliability characteristics. In addition, the CVD TEOS oxide deposited on the phosphorus in-situ doped polysilicon nitrided with NH3 and followed with an N2O RTA treatment shows better performance inter-dielectric than control samples. This structure is a very promise for the interpoly dielectric of EEPROM and flash memory devices.
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廖述穎. "Study on Floating-Gate Molybdenum Nanocrystals for Nonvolatile Memory Application." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/70508556572636753949.
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碩士國立交通大學
電子工程系所
96
Current requirements of nonvolatile memory (NVM) are the high density cells, low-power consumption, high-speed operation and good reliability for the scaling down devices. However, all of the charges stored in the floating gate will leak into the substrate if the tunnel oxide has a leakage path in the conventional NVM during endurance test. Therefore, the tunnel oxide thickness is difficult to scale down in terms of charge retention and endurance characteristics. The nonvolatile nanocrystal memories are one of promising candidates to substitute for conventional floating gate memory, because the discrete storage nodes as the charge storage media have been effectively improve data retention under endurance test for the scaling down device. Many methods have been developed recently for the formation of nanocrystal. Generally, most methods need thermal treatment with high temperature and long duration. This procedure will influence thermal budget and throughput in current manufacture technology of semiconductor industry. In this thesis, an ease fabrication technique of molybdenum nanocrystals was demonstrated for the application of nonvolatile memory. The nonvolatile memory structure of molybdenum nanocrystals embedded in the dielectric layer was fabricated by co-evaporating molybdenum and dielectric which like SiOx, SiNx and AlOx at room temperature. It can be considered that the annealing tamperature plays a critical role during sputter process for the formation of nanocrystal. In addition, the high density (~1011 cm-2) nanocrystal can be simple and uniform to be fabricated in our study. We also proposed a formation of molybdenum nanocrystals embedded in AlOx by co-evaporating molybdenum and AlOx at room temperature. It was also found that high density Mo nanocrystals embedded in theAlOx and larger memory effect. These fabrication techniques for the application of nonvolatile nanocrystal memory can be compatible with current manufacture process of the integrated circuit manufacture.
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Huang, Guo-Zhou, and 黃國洲. "Study on Reliability Improvement for Nonvolatile Floating Gate Flash Memory." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/81028794536685812981.
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碩士國立交通大學
電子工程系所
97
Manufacture the nonvolatile memory uses poly-silicon layer treated as election storage layer named floating gate (FG). Electron injection to this layer from channel will influence the threshold voltage. Two states threshold voltage constitute logic “0” and “1”. For FG structure, the oxide has a defect because of electron impact repetitively during the write/erase cycles. Then all of the charge stored in FG layer will be loss. In the near future, the device will be scaling down for the cost. At the same time, the thickness of tunneling oxide will decrease. It causes the reliability of the memory to be worse. In order to deal with demand for high density memory in the future, the scientists make great efforts to research and develop various kinds of nonvolatile memory to replace FG memory. For instance PCM , FeRAM , MRAM ,etc. But nobody can confirm that what kind of structure can replace FG memory. How can we use existing technology to lead Flash memory continuously scale-down. We use the oxynitride to replace the traditional thermal oxide as the tunneling oxide. First, chemical oxide as a starting oxide can provide a better controllability in film thickness. Following that, the chemical oxide was nitrided using a furnace in low-pressure NH3 ambient to transfer high-nitrogen oxynitride. The nitrided chemical oxide was then placed in atmospheric O2 ambient to form a robust oxynitride. The process proposed here is simple and fully compatible with current process technology and improve the reliability of the memory.
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林年興. "Investigation of various operations of dual floating gate flash memory." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/92636650442233565736.
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Khan, Faraz I. "Endurance characterization and improvement of floating gate semiconductor memory devices." 2009. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051734.
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Peng, Yen-Ming, and 彭彥明. "Low Voltage and High Speed Floating Gate Flash Memory Cells." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/48881826598698326143.
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碩士國立清華大學
電子工程研究所
97
The objectives of this thesis is to explore in depth the feasibility of low-voltage, high-speed Floating-Gate (FG) Flash memory cell through the proper minimizations of tunneling oxide and inter-poly dielectric (IPD) layers. Here, high-k materials and metal control gate are adopted in stacked gate to promote the control gate coupling ratio. Detailed investigations of device parameters in FG Flash cells are performed with two-dimensional device simulations and real silicon fabrications to attain the possible high-speed and low-power Flash cell design.
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Yang, Ming-Hsuan, and 楊明軒. "Organic Nonvolatile Memory Devices with Nanoparticles as the Floating Gate." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/24790155247841830253.
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碩士國立臺灣海洋大學
電機工程學系
101
This thesis studies the performance of the organic nonvolatile memory device using the metal nanopaticles as the floating gate. The devices used indium tin oxide (ITO) substrate as the gate electrode. Then tantalum pentoxide (Ta2O5) was evaporated dire- ctly onto the substrate to form a control layer, followed by metals sputtered or evapo- rated to form the nanoparticle as the floating gate. Poly(4-vinyl-phenol) (PVP) and re- gio-regular Poly(3-hexylthiophene) (rr-P3HT) were spin-coated sequentially to form a tunnel layer and an active layer, respectively. Finally, Gold (Au) source/drain electro- des were sputtered atop. The organic field-effect transistor with the floating gate was verified to be workable by investigating the hysterestic phenomena, current-voltage characteristics, retention time, and endurance of the device. Owing to the easy oxide- tion of aluminum (Al), the Al nanoparticle is prepared by sputtering, and then annea- led under the ambient condition to form a shell of Al2O3 on the surface, which can act as the tunnel layer without the PVP layer. The performance of floating gates with and without the overcoat layers of PVP are measured for the comparison in details. The experimental results show that both devices exhibit the hysteristic phenomena, indica- ting that Al nanoparticles can store the charge, but the charge-storage ability is better for the former than the latter, because the former shows a wider memory window. For the respect of the retention time, the residue quantity of stored charges for devices with the PVP layer is 81.2% of the initial one after 3200 s; in contrast, the device without the PVP layer has the residue charges of 43.4% after the same time. For the performance of endurance, the memory window of devices with the PVP layer re- mains 59.6% of the initial one after 50 program/erase cycles; but the remaining me- mory window of devices without the PVP layer is 6% of the initial one. All these re- sults indicate that we have successfully fabricated the organic nonvolatile memory de- vice using the Al nanoparticle as the floating gate in the present work, and we found that the performance of the memory device with the PVP layer is superior to that of the one without the PVP layer.
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Shi, Po-Xu, and 石博旭. "Design and Implementation of a Quasi Floating-Gate Memory Controlled Oscillator." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/mb6kbm.
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碩士國立中山大學
電機工程學系研究所
106
This thesis realizes an application-specific integrated circuit (ASIC) implementation of adjustable frequency clock generator which combination of a one-bit quasi floating gate memory as reference voltage generator for the relaxation oscillator with frequency divider at the output stage in TSMC 2P4M 0.35 μm CMOS technology. Quasi floating gate memory can make similar memory behavior with standard cell at a relatively low cost but the effect is compromised. Using the feature which store the data without the power of the quasi floating gate memory, the system can program an oscillator frequency by quasi floating gate memory which keeps the program state even without power but only for an hour. The clock generator can provide oscillating frequency between 462 KHz to 549 KHz. The measured power consumption is 5.1 mW during the quasi floating gate memory operates in program state and the oscillating frequency variation with VDD is about ±1.2%. The chip active area is about 0.069 mm2.
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Fang, Ding-Hua, and 房定樺. "Numerical Simulation of High-k/Metal Gate Floating Gate Flash Memory Characteristics and Device Scaling." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/68581600306689963594.
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碩士國立交通大學
電子研究所
100
In this dissertation a simulation method to simulate the transient behavior of programming and erasing in high-k/metal gate planar floating gate flash memory is developed. We also simulate the electric field distribution under different channel length by ISE TCAD and compared the program/erase efficiency in channel length is 20 nm of planar floating gate flash memory with edge fringing field effect. From our simulation result, the program/erase efficiency will be degraded by edge fringing field effect. As a result, edge fringing field effect plays an important role in the scaling course of planar floating flash memory. To improve the program/erase efficiency, we have to simulate program characteristics and change other high-k materials as blocking layer. We also simulated erase characteristics under different gate material. From our simulation result, lanthanum oxide as blocking layer could effectively promote program/erase efficiency in planar FG.
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Peng, Tzu-Hsuan, and 彭子瑄. "A Study of Memory Transistor Comprised of Thin-film Transistor and Nonvolatile Floating Gate Memory." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/62890518263582294112.
Full textAbstract:
碩士國立交通大學
材料科學與工程學系所
103
Preparation and characterizations of the memory transistor (MT) with 1-transistor-and-1-capacitor device structure by combining the InGaZnO (IGZO) thin-film transistor and the nonvolatile floating gate memory (NFGM) containing AgInSbTe (AIST)-SiO2 nanocomposite layer as the charge storage layer are investigated. First, Si wafer as the substrate and thermally grown SiO2 gate dielectric layer were utilized to prepare MT sample in order to verify that the feasibility of IGZO TFT and AIST NFGM to MT architecture. Secondly, the FTO glass substrate and SiNx/SiO2 composite gate dielectric grown by plasma-enhanced chemical vapor deposition were adopted for MT preparation. It was found that, with an annealing at 200C for 60 sec, MT sample containing SiNx(10 nm)/SiO2(90 nm) composite gate dielectric structure exhibits the best electrical properties of Ig = 0.11 A, VTH = 2 V, on/off ratio = 4.3×104, sat = 8.2 cm2V−1sec−1, SS = 2.5 Vdecade−1 and VTH,MT = 8.7. In addition, a fairly good retention property of 22.7% degradation of memory window (VTH,MT) was observed after the retention test for 104 sec. In third part of study, the source/drain electrodes of MT samples accomplished previously were replaced by Mo/ITO layer so as to fabricate the fully transparent MT device. With an about 70% transparency in visible-light wavelength range, the MT device somehow exhibited an inferior electrical performance compared with the device with Al as the electrodes, i.e., Ig = 0.68 A, VTH = 3.8 V, On/Off Ratio = 6.5×102, sat = 0.38 cm2V−1sec−1, SS = 4.8 Vdecade−1, VTH,MT = 2.4 V. The degradation of electrical properties was ascribed to the increment of contact resistance at the interface of Mo and IGZO. X-ray photoelectron spectroscopy revealed the annealing at 200C might effectively reduce the crystalline defects in the samples and improve the electrical properties; nevertheless, the annealing at 300C caused the oxidization of Sb in AIST nanocrystals and jeopardized the memory capability of MT samples.
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Shih, Hung-Sheng, and 施宏昇. "High Program Efficiency of P-Type Floating Gate in N-Channel Split-Gate Embedded Flash Memory." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/59631914528415782831.
Full textAbstract:
碩士國立清華大學
電子工程研究所
97
Recently, the Split Gate Flash Memory has been widely discussed and employed in nonvolatile semiconductor memories. For the design of advanced Flash Memories, the performance and reliability are the major concern. In the past, the design of flash memories is mainly focused on the development of the novel cell structure, the source/drain engineering, the floating gate engineering, and the operation methods. In this thesis, we focus on the idea of floating gate engineering to improve the device characteristics, to propose for the first time a new design of P-type floating gate on N channel split gate flash memory. We change the floating gate doping from N-type to P-type with different P-type doping concentration. Based on the experimental results, the N-type floating-gate split gate flash cell has much better performance and reliability than the conventional n-type floating-gate one. In other words, the P-type floating-gate split gate flash cell has faster programming/erasing speed, larger operation window, and better endurance characteristics. Finally, a 2Mbits embedded Flash IP was been successfully implemented statistically compared. The new p-doped split gate structure provides a very promising solution for advanced embedded split-gate Flash memory beyond the 90nm node.
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Kang, An-Chi, and 康安祺. "A Reliability Study of P-Type Floating Gate in N-Channel Split-Gate Embedded Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/82919623160919206032.
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張正熙. "An Asymmetrical Split Floating Gate Flash Memory Cell for Multi-Level Operation." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/63887979460726149718.
Full textAbstract:
碩士國立中興大學
電機工程學系
92
Abstract A memory cell storing more than one bit per cell is termed multilevel memory. Several techniques to implement multilevel flash cells have been proposed. The first category consists of controlling the amounts of charge stored in the single floating gate for multilevel operation, but the peripheral circuit becomes more complicated. The second category consists of the store charges in different locations of a flash cell. We design an asymmetrical split floating gate (ASFG) of multilevel flash memory devices belonged to the second category. The structure of ASFG is like the split gate flash. The ASFG use FN tunneling method to store different amounts of the charge in different floating gates, and to generate different threshold voltage to achieve 4-level operation. It uses FN (tunneling mechanism) for programming and erasure operation in order to low power consumption. In addition, in the reading way, the data can be read from the same electrode. In another way, it does require different electrodes to identify different logic levels. Therefore, the access time of the data from the same electrodes is less. So, we design the structure of ASFG that is reading in the same electrode.
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Ostraat, Michele Louisa. "Synthesis and characterization of aerosol silicon nanoparticle nonvolatile floating gate memory devices." Thesis, 2001. https://thesis.library.caltech.edu/1285/1/Ostraat_ml_2001.pdf.
Full textAbstract:
NOTE: Text or symbols not renderable in plain ASCII are indicated by [...]. Abstract is included in .pdf document.
Silicon nanoparticle-based floating gate metal-oxide-semiconductor (MOS) field effect devices have potential for terabit [...] density nonvolatile memory applications. Aerosol synthesis of silicon nanoparticles is an important route toward the formation of discontinuous silicon nanoparticle floating gate structures that affords excellent control over particle size and size distribution, particle density, and oxide passivation. We have fabricated nanoparticle memory devices in a conventional MOS ultra-large scale integration (ULSI) process with channel lengths from 0.2 - 10 [...] with a silicon nanoparticle floating gate fabricated by aerosol deposition.
SiO2 passivated silicon nanoparticles have been synthesized in an ultra clean two-stage aerosol reactor that is interfaced to a 200 mm wafer deposition chamber in a class 100 cleanroom. We synthesize silicon nanoparticles by thermal decomposition of silane gas at 950°C to produce single crystal, nonagglomerated nanoparticles. The second reactor stage passivated the silicon nanoparticles with a thin thermal oxide grown at 1050°C. Particles are thermophoretically deposited onto 200 mm silicon wafers with densities from [...] particles [...] at the wafer center to [...] particles [...] at the wafer edge in tens of minutes. We have fabricated floating gate memory devices in which the dielectric layer contains a discontinuous nanoparticle layer containing either (i) 2 -4 nm crystalline core diameter with 1 nm thermal oxide; or (ii) 6 - 15 nm crystalline core diameter with 2 nm thermal oxide. Cross-sectional transmission electron microscopy (TEM) verifies the presence of a silicon nanoparticle floating gate layer and planar TEM confirms nanoparticle morphology, size, and density.
Aerosol floating gate devices exhibit normal transistor behavior and have promising nonvolatile device performance. Aerosol nanoparticle devices with 0.2 mm channel lengths exhibit threshold voltages < 5 V with large threshold voltage shifts (~ 2 V), submicrosecond program times and millisecond erase times. No degradation in program/erase threshold voltage swing was observed during [...] program and erase cycles, although some threshold voltage shift due to charge trapping was observed. Electrostatic modeling indicates when a discontinuous nanoparticle layer can be modeled as a continuous sheet charge embedded within oxide and when it should be modeled as individual nanoparticles in an array.
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Yu, Rui-Hsiu, and 游瑞修. "A Piezoelectric Energy Harvester and MOS Floating Gate Memory towards Wearable Strain Metering." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/ee4643.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
104
With increasing levels of health awareness among people, the importance of long-term medical monitoring has increased along with the need for body detection at any given time and place. To serve these needs, wearable circuits, often in form of a body area network (BAN), are possible solutions. However, for long-term wearable monitoring the energy supply remains a critical issue. An energy harvesting circuit is studied in this thesis which extracts energy from a piezoelectric device. The device may eventually be energized by compression such as when worn under a shoe or by gravity oscillation when worn on the body. In this study a test circuit is built to measure the voltage rise on a storage capacitor in response to mechanically nudging the piezo device. The circuit is bench tested and compared with analytical results obtained for a model of this system showing close agreement. The harvested power is also measured. It depends on the actual strength and duration pattern of the piezoelectric compression. For the actual setup studied here, the harvested power is in the range of 1.46uW. Since this power is small, this study further investigates a potentially useful circuit that can be energized by the harvester. A candidate circuit is the MOS floating gate memory cell which is suitable to store an analog value corresponding to applied signal energy. A memory cell is realized in TSMC 0.35um integrated process technology with an active are of 136.375 µm*131.525 µm. Measured results are presented and show the response to a programming current. Erasure of the rewritable cell needs about 10 minutes using CMOS compatible voltage levels. According to the programmed voltage, an on-chip comparator can read the memory state and provide a binary logic output. Measurement shows that programming the cell with the energy of the piezoelectric device of this study enables battery-less piezo strain recording over a time period of about 100 minutes.
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Lin, Hsin-I., and 林欣逸. "Study of Characteristics and Reliability of Floating-gate and SONOS Nonvolatile Memory Devices." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/54606759434788612280.
Full textAbstract:
碩士國立交通大學
電機學院碩士在職專班電子與光電組
96
In this work, we fabricated and characterized n-channel floating-gate (FG) and silicon-oxide-nitride-oxide-silicon (SONOS) flash non-volatile memory devices. Major focus is paid on operation characteristics like programming and erasing, as well as the associated reliability issue. Worse short-channel effect (SCE) is observed for the FG devices, owing to gate-to-drain coupling issues. This phenomenon could be relaxed using the SONOS structure, thanks to the thin ONO layer between the control gate and the channel. We also investigated the impact of thermal stress on the data retention and the related charge loss paths. Furthermore, significant direct tunneling (DT) charge loss effect from the thinner top oxide of the ONO layer of the SONOS devices is observed. On the other hand, as P/E cycle number increases, significant electron trapping events occur in the FG devices, resulting in shrinkage of threshold voltage window. In addition, interface states generated during programming procedure are observed for the two types of devices, especially for the SONOS devices. Although channel initiated secondary electron (CHISEL) programming of the SONOS devices would greatly increase interface state density, and result in subthreshold swing (SS) and transconductance (GM) degradation, our results indicate that an acceptable threshold voltage window retains even after a great number of P/E cycles.
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Hsu, Chia-Ling, and 許嘉玲. "Differential Multiple-Time-Programming Memory Cells by Laterally Coupled Floating Metal Gate FinFETs." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/8p95h4.
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Girish, M. "Monodisperse Gold Nanoparticles : Synthesis, Self-Assembly and Fabrication of Floating Gate Memory Devices." Thesis, 2013. http://etd.iisc.ac.in/handle/2005/3443.
Full textAbstract:
The emergence of novel electronic, optical and magnetic properties in ordered two-dimensional (2D) nanoparticle ensembles, due to collective dipolar interactions of surface plasmons or excitons or magnetic moments have motivated intense research efforts into fabricating functional nanostructure assemblies. Such functional assemblies (i.e., highly-integrated and addressable) have great potential in terms of device performance and cost benefits. Presently, there is a paradigm shift from lithography based top-down approaches to bottom-up approaches that use self-assembly to engineer addressable architectures from nanoscale building blocks. The objective of this dissertation was to develop appropriate processing tools that can overcome the common challenges faced in fabricating floating gate memory devices using self-assembled 2D metal nanoparticle arrays as charge storage nodes. The salient challenges being to synthesize monodisperse nanoparticles, develop large scale guided self-assembly processes and to integrate with Complementary Metal Oxide Semiconductor (CMOS) memory device fabrication processes, thereby, meeting the targets of International Technology Roadmap for Semiconductors (ITRS) – 2017, for non-volatile memory devices.
In the first part of the thesis, a simple and robust process for the formation of wafer-scale, ordered arrays using dodecanethiol capped gold nanoparticles is reported. Next, the results of ellipsometric measurements to analyze the effect of excess ligand on the self-assembly of dodecanethiol coated gold nanoparticles at the air-water interface are discussed. In a similar vein, the technique of drop-casting colloidal solution is extended for tuning the interparticle spacing in the sub-20 nm regime, by altering the ligand length, through thiol-functionalized polystyrene molecules of different molecular weights. The results of characterization, using the complementary techniques of Atomic Force Microscopy (AFM) and Field-Emission Scanning Electron Microscopy (FESEM), of nanoparticle arrays formed by polystyrene thiol (average molecular weight 20,000 g/mol) grafted gold nanoparticles (7 nm diameter) on three different substrates and also using different solvents is then reported. The substrate interactions were found to affect the interparticle spacing in arrays, changing from 20 nm on silicon to 10 nm on a water surface; whereas, the height of the resultant thin film was found to be independent of substrate used and to correlate only with the hydrodynamic diameter of the polymer grafted nanoparticle in solution. Also, the mechanical properties of the nanoparticle thin films were found to be significantly altered by such compression of the polymer ligands. Based on the experimental data, the interparticle spacing and packing structure in these 2D arrays, were found to be controlled by the substrate, through modulation of the disjoining pressure in the evaporating thin film (van der Waals interaction); and by the solvent used for drop casting, through modulation of the hydrodynamic diameter. This is the first report on the ability to vary interparticle spacing of metal nanoparticle arrays by tuning substrate interactions alone, while maintaining the same ligand structure. A process to fabricate arrays with square packing based on convective shearing at a liquid surface induced by miscibility of colloidal solution with the substrate is proposed. This obviates the need for complex ligands with spatially directed molecular binding properties. Fabrication of 3D aggregates of polymer-nanoparticle composite by manipulating solvent-ligand interactions is also presented.
In flash memory devices, charges are stored in a floating gate separated by a tunneling oxide layer from the channel, and the tunneling oxide thickness is scaled down to minimize power consumption. However, reduction in tunneling oxide thickness has reached a stage where data loss can occur due to random defects in the oxide. Using metal nanoparticles as charge-trapping nodes will minimize the data loss and enhance reliability by compartmentalizing the charge storage. In the second part of the thesis, a scalable and CMOS compatible process for fabricating next-generation, non-volatile, flash memory devices using the self-assembled 2D arrays of gold nanoparticles as charge storage nodes were developed. The salient features of the fabricated devices include: (a) reproducible threshold voltage shifts measured from devices spread over cm2 area, (b) excellent retention (>10 years) and endurance characteristics (>10000 Program/Erase cycles). The removal of ligands coating the metal nanoparticles using mild RF plasma etching was found, based on FESEM characterization as well as electrical measurements, to be critical in maintaining both the ordering of the nanoparticles and charge storage capacity. Results of Electrostatic Force Microscope (EFM) measurements are presented, corroborating the need for ligand removal in obtaining reproducible memory characteristics and reducing vertical charge leakage. The effect of interparticle spacing on the memory characteristics of the devices was also studied. Interestingly, the arrays with interparticle spacing of the order of nanoparticle diameter (7 nm) gave rise to the largest memory window, in comparison with arrays with smaller (2 nm) or larger interparticle spacing (20 nm). The effect of interparticle spacing and ligand removal on memory characteristics was found to be independent of different top-oxide deposition processes employed in device fabrication, namely, Radio-frequency magnetron sputtering (RF sputtering), Atomic Layer Deposition (ALD) and electron-beam evaporation.
In the final part of the thesis, a facile method for transforming polydisperse citrate capped gold nanoparticles into monodisperse gold nanoparticles through the addition of excess polyethylene glycol (PEG) molecules is presented. A systematic study was conducted in order to understand the role of excess ligand (PEG) in enabling size focusing. The size focusing behavior due to PEG coating of nanoparticles was found to be different for different metals. Unlike the digestive ripening process, the presence of PEG was found to be critical, while the thiol functionalization was not needed. Remarkably, the amount of adsorbed carboxylate-PEG mixture was found to play a key role in this process. The stability of the ordered nanoparticle films under vacuum was also reported. The experimental results of particle ripening draw an analogy with the well-established Pechini process for synthesizing metal oxide nanostructures. The ability to directly self-assemble nanoparticles from the aqueous phase in conjunction with the ability to transfer these arrays to any desired substrate using microcontact printing can foster the development of applications ranging from flexible electronics to sensors. Also, this approach in conjunction with roll-to-roll processing approaches such as doctor-blade casting or convective assembly can aid in realizing the goal of large scale nanostructure fabrication without the utilization of organic solvents.
32
Girish, M. "Monodisperse Gold Nanoparticles : Synthesis, Self-Assembly and Fabrication of Floating Gate Memory Devices." Thesis, 2013. http://etd.iisc.ernet.in/2005/3443.
Full textAbstract:
The emergence of novel electronic, optical and magnetic properties in ordered two-dimensional (2D) nanoparticle ensembles, due to collective dipolar interactions of surface plasmons or excitons or magnetic moments have motivated intense research efforts into fabricating functional nanostructure assemblies. Such functional assemblies (i.e., highly-integrated and addressable) have great potential in terms of device performance and cost benefits. Presently, there is a paradigm shift from lithography based top-down approaches to bottom-up approaches that use self-assembly to engineer addressable architectures from nanoscale building blocks. The objective of this dissertation was to develop appropriate processing tools that can overcome the common challenges faced in fabricating floating gate memory devices using self-assembled 2D metal nanoparticle arrays as charge storage nodes. The salient challenges being to synthesize monodisperse nanoparticles, develop large scale guided self-assembly processes and to integrate with Complementary Metal Oxide Semiconductor (CMOS) memory device fabrication processes, thereby, meeting the targets of International Technology Roadmap for Semiconductors (ITRS) – 2017, for non-volatile memory devices.
In the first part of the thesis, a simple and robust process for the formation of wafer-scale, ordered arrays using dodecanethiol capped gold nanoparticles is reported. Next, the results of ellipsometric measurements to analyze the effect of excess ligand on the self-assembly of dodecanethiol coated gold nanoparticles at the air-water interface are discussed. In a similar vein, the technique of drop-casting colloidal solution is extended for tuning the interparticle spacing in the sub-20 nm regime, by altering the ligand length, through thiol-functionalized polystyrene molecules of different molecular weights. The results of characterization, using the complementary techniques of Atomic Force Microscopy (AFM) and Field-Emission Scanning Electron Microscopy (FESEM), of nanoparticle arrays formed by polystyrene thiol (average molecular weight 20,000 g/mol) grafted gold nanoparticles (7 nm diameter) on three different substrates and also using different solvents is then reported. The substrate interactions were found to affect the interparticle spacing in arrays, changing from 20 nm on silicon to 10 nm on a water surface; whereas, the height of the resultant thin film was found to be independent of substrate used and to correlate only with the hydrodynamic diameter of the polymer grafted nanoparticle in solution. Also, the mechanical properties of the nanoparticle thin films were found to be significantly altered by such compression of the polymer ligands. Based on the experimental data, the interparticle spacing and packing structure in these 2D arrays, were found to be controlled by the substrate, through modulation of the disjoining pressure in the evaporating thin film (van der Waals interaction); and by the solvent used for drop casting, through modulation of the hydrodynamic diameter. This is the first report on the ability to vary interparticle spacing of metal nanoparticle arrays by tuning substrate interactions alone, while maintaining the same ligand structure. A process to fabricate arrays with square packing based on convective shearing at a liquid surface induced by miscibility of colloidal solution with the substrate is proposed. This obviates the need for complex ligands with spatially directed molecular binding properties. Fabrication of 3D aggregates of polymer-nanoparticle composite by manipulating solvent-ligand interactions is also presented.
In flash memory devices, charges are stored in a floating gate separated by a tunneling oxide layer from the channel, and the tunneling oxide thickness is scaled down to minimize power consumption. However, reduction in tunneling oxide thickness has reached a stage where data loss can occur due to random defects in the oxide. Using metal nanoparticles as charge-trapping nodes will minimize the data loss and enhance reliability by compartmentalizing the charge storage. In the second part of the thesis, a scalable and CMOS compatible process for fabricating next-generation, non-volatile, flash memory devices using the self-assembled 2D arrays of gold nanoparticles as charge storage nodes were developed. The salient features of the fabricated devices include: (a) reproducible threshold voltage shifts measured from devices spread over cm2 area, (b) excellent retention (>10 years) and endurance characteristics (>10000 Program/Erase cycles). The removal of ligands coating the metal nanoparticles using mild RF plasma etching was found, based on FESEM characterization as well as electrical measurements, to be critical in maintaining both the ordering of the nanoparticles and charge storage capacity. Results of Electrostatic Force Microscope (EFM) measurements are presented, corroborating the need for ligand removal in obtaining reproducible memory characteristics and reducing vertical charge leakage. The effect of interparticle spacing on the memory characteristics of the devices was also studied. Interestingly, the arrays with interparticle spacing of the order of nanoparticle diameter (7 nm) gave rise to the largest memory window, in comparison with arrays with smaller (2 nm) or larger interparticle spacing (20 nm). The effect of interparticle spacing and ligand removal on memory characteristics was found to be independent of different top-oxide deposition processes employed in device fabrication, namely, Radio-frequency magnetron sputtering (RF sputtering), Atomic Layer Deposition (ALD) and electron-beam evaporation.
In the final part of the thesis, a facile method for transforming polydisperse citrate capped gold nanoparticles into monodisperse gold nanoparticles through the addition of excess polyethylene glycol (PEG) molecules is presented. A systematic study was conducted in order to understand the role of excess ligand (PEG) in enabling size focusing. The size focusing behavior due to PEG coating of nanoparticles was found to be different for different metals. Unlike the digestive ripening process, the presence of PEG was found to be critical, while the thiol functionalization was not needed. Remarkably, the amount of adsorbed carboxylate-PEG mixture was found to play a key role in this process. The stability of the ordered nanoparticle films under vacuum was also reported. The experimental results of particle ripening draw an analogy with the well-established Pechini process for synthesizing metal oxide nanostructures. The ability to directly self-assemble nanoparticles from the aqueous phase in conjunction with the ability to transfer these arrays to any desired substrate using microcontact printing can foster the development of applications ranging from flexible electronics to sensors. Also, this approach in conjunction with roll-to-roll processing approaches such as doctor-blade casting or convective assembly can aid in realizing the goal of large scale nanostructure fabrication without the utilization of organic solvents.
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Yang, Cheng-Hsun, and 楊承勳. "A Study of Nanocomposite Thin Films Containing Sb2Te Nanoparticles Applied to Nonvolatile Floating Gate Memory." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/95736203086568319026.
Full textAbstract:
碩士國立交通大學
材料科學與工程學系
100
Nanocomposite thin films containing nano-scale Sb2Te chalcogenide particles embedded in SiO2 matrix were prepared by target-attachment sputtering method at various nitrogen/argon (N2/Ar) inlet gas flow ratios. Accordingly, the nanocomposite layers were implanted in the nonvolatile floating gate memory (NFGM) devices and the correlations of electrical properties to microstructures and chemical status of elements were investigated. As revealed by the C-V measurement, the N2-free NFGM samples subjected to a post-annealing at 450?aC for 4 min exhibited a flatband voltage (ΔVFB) shift = 0.4 V at ±7 V gate voltage sweep and charge storage density = 3.1×1011 cm?{2. As to the sample prepared at the condition of N2/Ar ratio = 0.1, it achieved a maximum ΔVFB shifts = 4.4 V and the charge density = 4.21×1012 cm?{2 under ±7 V gate voltage sweep. The retention time analysis also observed a ΔVFB shift about 1.8 V and the charge loss about 26.8% under ±5 V voltage stress after 104 sec. The satisfied electrical and retention properties are ascribed to the suppression of oxygen vacancies and antimony oxides due to the N2 incorporation which leads to the enhancement of charge trapping capability on Sb2Te nanoparticles and low leakage current in the sample. Hence, the sole Sb2Te-SiO2 nanocomposite is a feasible programming layer for NFGM devices.
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Lin, Li-Hua, and 林歷樺. "Fabrication and Characterizations of Asymmetric Schottky Barrier Thin-Film Transistors and Floating Gate Memory Devices." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/92368562969661525060.
Full textAbstract:
碩士國立交通大學
電子研究所
99
In this thesis, asymmetric Schottky barrier (ASSB) thin film transistors (TFTs) are successfully fabricated by utilizing a novel and low-cost double patterning technique. The method involves twice the lithography with an I-line stepper and subsequent etching process steps to define the real gate pattern, which is not only a promising scheme for achieving nanoscale gate length but also feasible for fabricating devices with asymmetric source/drain (S/D) junctions. The novel ASSB-TFT devices operated in forward mode featuring a NiSi Schottky contact at the source side and a phosphorous-doped drain can significantly lower leakage current and thus the ambipolar conduction is largely mitigated. Moreover, a two-step subthreshold transfer characteristic is also observed and the carrier injection mechanisms are analyzed. When the NiSi layer is used as the source, the phenomenon of a source-side hot electron injection triggered by the sharp energy band bending is investigated. A large gate current and the negative-differential conductance (NDC) behavior are simultaneously observed, which is attributed to hot electron generated at the Schottky source side and dynamic hot electron trapping in the oxide. Based on this unique ASSB structure, floating-gate (FG) device for Flash memory is also successfully fabricated and characterized. The sharp Schottky barrier at the source side can induce hot electrons, and it can be used to provide high injection efficiency at low voltage rather than conventional drain-side channel hot electron injection. Compared with a conventional TFT-FG memory device, the ASSB TFT-FG memory device exhibits high-speed programming at low voltage.
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Wang, Tai-Min, and 王泰閔. "P-channel Differential Multiple-Time Programmable Memory Cells by Laterally Coupled Floating Metal Gate FinFETs." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6em795.
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Teo, L. W., Van Tai Ho, M. S. Tay, Y. Lei, Wee Kiong Choi, Wai Kin Chim, Dimitri A. Antoniadis, and Eugene A. Fitzgerald. "Charge Storage Mechanism and Size Control of Germanium Nanocrystals in a Tri-layer Insulator Structure of a MIS Memory Device." 2003. http://hdl.handle.net/1721.1/3712.
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A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.Singapore-MIT Alliance (SMA)
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Tseng, Jiun-Yi, and 曾駿逸. "A Study of Pt Nanocrystals in Metal-Oxide-Semiconductor Structures for Nonvolatile Floating Gate Memory Applications." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/f2un9s.
Full textAbstract:
博士國立清華大學
材料科學工程學系
93
Abstract The nonvolatile memory characteristics of metal-oxide-semiconductor structures containing Pt nanocrystals in SiO2 gate oxide were studied. In this work, a novel, simple and reliable self-assembly process of Pt nanocrystals formation from the reduction of an ultrathin PtOx layer embedded in SiO2 matrix is developed successfully, which is fully compatible with Si technology nowadays. The self-assembled array of uniformly-dispersed and well-isolated Pt nanocrystals with the high spatial density (~2.16×1012 cm-2) and a narrow size distribution in the range of 2-3 nm was obtained by vacuum annealing at 425 ℃ for 25 min. A large hysteresis loop was found in the capacitance-voltage (C-V) relation indicating this significant memory effect. However, two different charge storage mechanisms were found for the Pt nanocrystals in the devices with different tunnel oxide thickness. One is denoted by the counterclockwise hysteresis resulting from substrate injection for the devices made with a thin tunnel oxide layer of 2.5~5.0 nm thick, and the other is characterized by the clockwise hysteresis attributed to the defect injection from the overlaid sputtered gate oxide for the devices having a tunnel oxide layer of 7.5 nm thick. The two mechanisms, substrate injection and defect injection, coexist at the same time but compete with each other. For tunnel oxide being thick enough (≧ 7.5 nm), the substrate injection would be significantly suppressed, and thus the defect injection becomes dominant. A model of defect injection is proposed to explain the clockwise hysteresis. The relatively stable memory characteristics of Pt nanocrystals resulting from substrate injection were also demonstrated. In Chapter 6, the effects of annealing time on the microstructure and electrical characteristics of the self-assembled Pt nanocrystals in SiO2 matrix are clear and significant. For a long enough annealing time, not only the Pt nanocrystals are well isolated and uniformly dispersed, but also the defects in the sputtered oxide are recovered. The superior charge storage and retention characteristics can be obtained due to the small lateral charge loss and the suppression of defect injection. Moreover, according to the gate-voltage dependence of charge storage and the result of the conductance-voltage (G-V) measurement, the macroscopic single-electron transfer due to the Coulomb blockade effect in the MOS device with embedded Pt nanocrystals is successfully demonstrated at room temperature in this research.
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Wu, Tung-Han, and 吳東翰. "Analysis and Modeling of Edge Effect on Inter-Poly Dielectric Layer of Floating Gate Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/29512279502310702623.
Full textAbstract:
碩士國立清華大學
電子工程研究所
99
The “edge effect” means that edge of oxide would be abnormal after performing high temperature process, and the efficiency of device will degrade. Edge effect on inter-poly dielectric (IPD) layer of floating gate flash memory occurs when re-oxidation restores the damage of edge of IPD layer which is due to defining gate pattern of floating gate flash memory, re-oxidation would lead to thickening of oxide edge, and program speed of memory will become lower. The contribution of this thesis is to propose a model which can analyze edge effect on inter-poly dielectric (IPD) layer of floating gate flash memory and compare them to the edge effect on tunneling oxide. Simulation by MEDICI and proposed model shows that when IPD edge thickens 6nm, memory window reduces 0.3-0.9V; when tunneling oxide edge thickens 2nm, memory window reduces 0.1-2.2V, it shows that program speed variation due to edge effect on tunneling oxide is larger than on IPD layer. Besides, there are two shapes of edge in proposed model: linear edge and parabolic edge. When IPD edge thickens 6nm and edge encroachment is not overlapped, we adopt linear edge to analyze variation of program speed. We find that memory window is 0.2V smaller than the result which is analyzed by parabolic edge, so variation of program speed of linear edge is larger than of parabolic edge when edge encroachment is not overlapped. Thinner edge can increase program speed. The simulation shows that memory window increases 0.5-0.8V when thickness of IPD edge reduces 4nm, but too thinner edge on IPD layer could result in program saturation.
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Chi, Hui-yen, and 紀卉彥. "Self-Assembly Block Copolymers/Small Molecules Hybrid Nano-Floating Gate Memory: Device Fabrication and Performance Evaluation." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/55428500565687924454.
Full textAbstract:
碩士國立中央大學
化學工程與材料工程學系
102
Organic nano-floating gate memory devices were fabricated using self-assembly supramolecular block copolymer hybrid thin films of poly(styrene-block-4-vinylpyridine) (PS-b-P4VP) and ferrocenemethanol (FM) small molecules as charge trapping layer, and pentacene as organic semiconductor on SiO2/Si substrate. The FM small molecules selectively hydrogen bonded with pyridine moieties of PS-b-P4VP block copolymer can be well dispersed within P4VP microdomain without significant aggregation. The nanoscale thin film morphologies and memory characteristics can be fully optimized and compared depending on the loading ratio of small molecules and the segment ratio of block copolymers.
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Teo, L. W., Van Tai Ho, M. S. Tay, Wee Kiong Choi, Wai Kin Chim, Dimitri A. Antoniadis, and Eugene A. Fitzgerald. "Dependence of nanocrystal formation and charge storage/retention performance of a tri-layer memory structure on germanium concentration and tunnel oxide thickness." 2003. http://hdl.handle.net/1721.1/3799.
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The effect of germanium (Ge) concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal-insulator-semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon (Si) substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO₂ co-sputtered middle layer (i.e., lower Ge concentration), a higher charge storage capability was obtained than with devices with a thinner RTO layer, and the charge retention time was found to be less than in devices with a thicker RTO layer.Singapore-MIT Alliance (SMA)
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Tsai, Hao-Wei, and 蔡皓偉. "Improvement of the Performance and the Reliability in P-channel Flash Memory with Various Floating-gate Materials." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/04633359128219843549.
Full textAbstract:
碩士國立交通大學
電子工程系
89
Recently, the flash memory has been wildly used for mass data storage. In the past, n-channel flash memories were used in the design of flash memory products. However, low power operation has become the major trend of a flash memory. P-channel flash cell is one of the best candidate. On the other hand, the performance and reliability are another major concern for designing low power flash memories. However, previous studies are mainly focused on the development of novel cell structure, the source/drain engineering, the channel engineering, and the operation methods. In this thesis, we proposed a different design concept based on the floating-gate engineering. The p-channel flash memory cell is developed with various types of floating-gate materials. From the experimental results, several studies have been made in this work. First, the basic performance of n- and p-type floating-gate flash memories has been compared. Since the tunnel oxide electric field in the p-type floating-gate cell is larger (smaller) during programming (erasing), it has faster program speed but slower erase speed. Second, for both n- and p-type floating-gate cells, the programming/erase cycling endurance characteristics are almost identical. Third, p-type floating-gate cell has better gate disturb characteristic, better read disturb characteristic, and a larger lifetime tolerance voltage.In particular, a 3-order improvement of the drain disturb can be achieved by using a p-type doped floating-gate in p-channel cell. Fourth, the p-type floating-gate cell also exhibits better data retention characteristics. In short, p-channel flash memories with p-type floating-gate structure are most advantageous for highly reliable cell design and in particular a good candidate for future memory applications.
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Chiang, Kuo-Chang, and 蔣國璋. "A Study of Chalcogenide Nanocomposite Thin Films Applied to Nonvolatile Floating Gate Memory and Hydrogen Gas Sensor." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/48748277631591338072.
Full textAbstract:
博士國立交通大學
材料科學與工程學系
101
This thesis study investigates the applicability of chalcogenide nanocomposite thin films to the nonvolatile floating gate memory (NFGM) and the hydrogen (H2) gas sensor. The AgInSbTe (AIST)-SiO2 nanocomposite thin films were prepared by the target-attachment sputtering method. Tranmission electron microscopy (TEM) and x-ray photoelectron microscopy (XPS) revealed the AIST nanocrystals (NCs) about 5 nm in diameter uniformly dispersed in SiO2 matrix and, in the part regarding of the study of NC-based NFGM, the AIST NCs may serve as the charge trapping sites in the programming layer of NFGM. The capacitance-voltage (C-V) measurement observed a counterclockwise hysteresis loop in the device containing a sole AIST-SiO2 nanocomposite layer, indicating the saturated substrate injection of charges into the AIST NCs. Moreover, the good data retention property also illustrated the feasibility of AIST-SiO2 nanocomposite to NC-based NFGM. Analytical results also found that the appropriate nitrogen incorporation during the sputtering deposition and the post annealing at 400°C benefit the NFGM characteristics. It not only suppressed the oxidation of AIST phase, but also promoted the reduction of antimony oxides to form the metallic Sb2Te phase to improve the charge-storage capacity in nanocomposite layer. The study of blocking oxide layer of NFGMs found that the capping of HfO2/SiO2 composite layer may achieve an extremely large memory window shift (VFB shift) about 30.7 V and high charge storage density of 2.3 ×10^13 cm^-2 at ±23 V gate voltage sweep. Due to the deep trap sites formed by high-density AIST NCs in the nanocomposite layer and high barrier height feature of composite blocking oxide layer, the good retention property and low leakage current were also achieved. Though the capping of a sole HfO2 layer might also improve the NFGM performance, diffusion of HfO2 into the nanocomposite layer generated the HfSiO2 phase and oxygen defects. This induced the current leakage paths and deteriorated the charge trapping efficiency of AIST NCs. The Hf diffusion could be inhibited by inserting the SiO2 layer deposited by plasma-enhanced chemical vapor deposition (PECVD), leading to the enhancement of Coulomb blockade effect and charge storage capacility of AIST NCs. Analytical results demonstrated not only the feasibility of AIST-SiO2 nanocomposite layer to NFGM, but also a simplified device structure and processing method in comparison with previous NC-based NFGM studies. In the part regarding of the H2 gas sensor, the device containing about 30-nm thick AIST-SiO2 nanocomposite layer exhibited a maximum sensitivity of 61.3 % with fast 90% response time about 75 sec and recovery time about 50 sec in a 200-ppm H2 gas ambient at 75°C. The n-type sensing behavior of the AIST-SiO2 nanocomposite layer was ascribed to the presence of Sb2O5 clad on the nano-scale AIST phase as revealed by relevant microstructure and composition analyses. The adsorbed H2 molecules might induce the reduction of Sb2O5 into the metallic Sb2Te or the non-stoichiometry reaction of Sb2O5 to increase the electrical conduction in nanocomposite layer when it is exposed to the H2 gas. Due to the high specific surface area (SSA) feature of nano-scale AIST phase embedded in SiO2 matrix, a high H2 sensing capability could thus be achieved. A simplified device structure and fabrication process for H2 gas sensor is also illustrated by this study since the sensing layer could be easily prepared by conventional sputtering process.
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Huang, Yao-Hsien, and 黃耀賢. "Performance and Reliability Evaluation of a Low Voltage and High Speed P-channel Floating Gate Flash Memory." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/76186610002771102861.
Full textAbstract:
碩士國立交通大學
電機學院微電子奈米科技產業專班
95
Recently, the flash memory has become the main stream of nonvolatile semiconductor memory products. High performance and reliability are two major issues for the design and manufacturing. The goal of research and development of flash memory cells is to lower the operational voltage and to enhance the performance and reliability. Two approaches are widely used to reach the goal: one is to improve the cell structure, and the other is to change the operation scheme. This thesis is to develop an operation scheme to achieve low voltage, low power consumption, and high reliability. P-channel flash memories are studies in this work. We propose a new programming scheme to inject electrons into the floating gate. It is called Forward Bias Assisted Drain Hot Electron Injection (FBADHE). First, we apply a small positive drain bias on the Drain-Substrate junction. Then, we apply an appropriate negative bias and switch the junction to reverse-bias. The change of the mode of p-n junction causes more impact ionization in the deep depletion region and more electron-hole pairs are generated. Carriers are then injected into the floating gate via the assistance of vertical electric field due to positive gate voltage. We compare the performance and reliability of this new operation scheme with other traditional ones used on p-channel flash memories: Band-To-Band Induced Hot Electron Injection (BBHE) and Drain Avalanche Hot Electron Injection (DAHE). Finally, in order to improve the major reliability problem of p-channel flash memories, the drain disturb, we propose an alternative way to solve the problem by applying a moderate negative substrate bias on unselected cell, but a new structure is needed.
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Mondal, Sandip. "Fully Solution Processed Flash Memory." Thesis, 2017. http://etd.iisc.ac.in/handle/2005/4131.
Full textAbstract:
The field of advanced solution processed spin-coated electronics has rapidly expanded over the last few decades towards the development of low-cost, large area and low power consumer electronics for the design of system-on-panel, system-on-glass, and system-on-chip circuits. They have diverse applications such as wearable and textile integrated devices, seamless and twistable systems, soft skin systems, as well as roll-to-roll light-weight, transparent, conformable, stretchable, and even biodegradable systems. So far, all demonstration of solution processed electronics use thin lm transistors (TFT) without any memory. However, memory is an essential electronic component of all systems and it is important to realize floating gate ash memory devices using similar spin-coated solution processing compatible technique. The first demonstration of floating memory by Kahng and Size in 1967 on transparent glass substrates utilized floating metal gate charge storage layers deposited by high temperature vacuum technology. Since then, there has been intensive research on floating gate technology. However, the high temperature and high vacuum technology is incompatible with large area, flexible and low cost electronics due to the process integration issue. Hence the alternative challenge was taken up on developing solution processed spin-coated memory devices for sol-gel electronics.
In this thesis we first introduce different solution processed dielectrics and oxide semi-conductors, thin lm deposition, and behavior at different processing temperatures. Further, we also demonstrate how the band structure of the dielectric, particularly the electron a finity, changes with annealing temperature. Then we propose and demonstrate a new high speed measurement technique for two terminal capacitive devices. In particular, we show that the entire capacitance-voltage curve can be measured in 2.5 s. The measurement is useful for characterization of two terminal capacitive memory devices in terms speed, endurance and retention. This achievement is followed by its application to newly developed fully solution processed, nanoparticle based, robust two terminal memory devices. The link between device performance and its structural and processing parameters such as annealing temperature, thickness of memory layer, supporting dielectric layer and substrate materials, is highlighted. In addition, a detailed analysis and comparison of performance of solution processed memory with regard to state-of-the art processing techniques as well as the selection of materials is presented. This work was extended to achieve the worlds first three terminal fully solution processed inorganic material-based robust ash memory devices with different kinds of solution processed charge trapping layers. We also discuss the advantage of this technology over previously reported sophisticated ultra high vacuum technology based three terminal ash memory devices. Afterwards, we report the discovery of deep level intrinsic traps in solution processed aluminium oxide phosphate. It is also shown that the traps are tunable with the processing temperature. Using XPS and UPS characterization techniques, the origin of these traps is linked with the molecular structure. Utilizing this trap behavior we have fabricated the worlds first fully solution processed ash memory device without tunneling and blocking layers at below 200 C. This discovery may be a breakthrough for large area, solution processed, and flexible electronics applications. Finally, conclusions are drawn on the performance of the memory stack with respect to other processing techniques, along with an outlook for this field and predictions for the future of this technology.
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Jiang, Bo-Shiun, and 姜伯勳. "Nonvolatile Memory Effect with Au@CdS Core/Shell Nanoparticles as Floating Gates." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/95342301601877907205.
Full textAbstract:
碩士國立交通大學
奈米科技研究所
97
In recent years, metal nanoparticles (NPs) floating gate memory has already attracted a lot of attention by research teams worldwide. The metal nanoparticle owns numerous properties such as high work function and high charge trapping state compared to semiconductor materials; which make it becomes the best candidate materials for charge trapping center in flash memory. In this thesis, we fabricated metal oxide semiconductor (MOS) memory devices featuring either Au core-only NPs or Au@CdS core/shell NPs within the SiO2 layer. Self-assembly of the chemically synthesized Au and Au@CdS NPs led to their immobilization onto the amine-terminal modified tunnel oxide. Also, we compared the retention time and charge storage capability of nonvolatile memory devices incorporating floating gates containing Au nanoparticles (NPs) and Au@CdS core/shell NPs. The charge remaining of the Au@CdS NP-based memory device was 83 % at 104 s, compared with 36 % for the Au NP-based memory device, presumably because of the Au@CdS NPs’ quantum well structure and larger tunneling barrier. Moreover, the charge storage capability of the Au@CdS NP-based memory device is higher than that of the Au NP-based memory device.
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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, 2009. https://tud.qucosa.de/id/qucosa%3A25930.
Full textAbstract:
Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.:Kurzfassung
Abstract
1 Einleitung
2 Grundlagen aktiver Halbleiterelemente
2.1 Die MOS-Struktur
2.2 Der MOS-Feldeffekt-Transistor
2.3 Nichtflüchtige Festkörperspeicher
2.4 Speicherarchitekturen
2.5 Charakterisierungsmethoden von Halbleiter-Speicherelementen
3 Defektbasierte Ladungsspeicherung in dielektrischen Schichten
3.1 Physikalische Grundlagen von Haftstellen
3.2 Betrachtung der vertikalen Ladungsverteilung mit Hilfe von Simulationen
3.3 Ableitung der vertikalen Ladungsverteilung aus Messungen
4 Elektrisches Verhalten einer haftstellen-basierten Speicherzelle
4.1 Auswirkung von inhomogen verteilter Ladung in der Speicherschicht
4.2 Auswirkungen von Al2O3-Topoxid auf das Zellverhalten
4.3 Auswirkung des Steuerelektrodenmaterials auf das Zellverhalten
4.4 Einfluss von Kanal- und Source/Drain-Dotierung
5 Integration in eine stark skalierte NAND Architektur
5.1 Auswirkung struktureller Effekte auf die Speicherzelle
5.2 Störmechanismen beim Betrieb von stark skalierten NAND-Speichern
6 Zusammenfassung und Ausblick
6.1 Zusammenfassung
6.2 Ausblick
Danksagung
Lebenslauf
Symbol- und Abkürzungsverzeichnis
Literaturverzeichnis