Relevant bibliographies by topics / Floating Gate Memory

Academic literature on the topic 'Floating Gate Memory'

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Published: 6 September 2023

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Journal articles on the topic "Floating Gate Memory"

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Rajput, Renu, and Rakesh Vaid. "Flash memory devices with metal floating gate/metal nanocrystals as the charge storage layer: A status review." Facta universitatis - series: Electronics and Energetics 33, no. 2 (2020): 155–67. http://dx.doi.org/10.2298/fuee2002155r.

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Traditional flash memory devices consist of Polysilicon Control Gate (CG) - Oxide-Nitride-Oxide (ONO - Interpoly Dielectric) - Polysilicon Floating Gate (FG) - Silicon Oxide (Tunnel dielectric) - Substrate. The dielectrics have to be scaled down considerably in order to meet the escalating demand for lower write/erase voltages and higher density of cells. But as the floating gate dimensions are scaled down the charge stored in the floating gate leak out more easily via thin tunneling oxide below the floating gate which causes serious reliability issues and the whole amount of stored charge carrying information can be lost. The possible route to eliminate this problem is to use high-k based interpoly dielectric and to replace the polysilicon floating gate with a metal floating gate. At larger physical thickness, these materials have similar capacitance value hence avoiding tunneling effect. Discrete nanocrystal memory has also been proposed to solve this problem. Due to its high operation speed, excellent scalability and higher reliability it has been shown as a promising candidate for future non-volatile memory applications. This review paper focuses on the recent efforts and research activities related to the fabrication and characterization of non-volatile memory device with metal floating gate/metal nanocrystals as the charge storage layer.
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Li, Bei, Jianlin Liu, G. F. Liu, and J. A. Yarmoff. "Ge∕Si heteronanocrystal floating gate memory." Applied Physics Letters 91, no. 13 (September 24, 2007): 132107. http://dx.doi.org/10.1063/1.2793687.

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Al-shawi, Amjad, Maysoon Alias, Paul Sayers, and Mohammed Fadhil Mabrook. "Improved Memory Properties of Graphene Oxide-Based Organic Memory Transistors." Micromachines 10, no. 10 (September 25, 2019): 643. http://dx.doi.org/10.3390/mi10100643.

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To investigate the behaviour of the organic memory transistors, graphene oxide (GO) was utilized as the floating gate in 6,13-Bis(triisopropylsilylethynyl)pentacene (TIPS-pentacene)-based organic memory transistors. A cross-linked, off-centre spin-coated and ozone-treated poly(methyl methacrylate) (cPMMA) was used as the insulating layer. High mobility and negligible hysteresis with very clear transistor behaviour were observed for the control transistors. On the other hand, memory transistors exhibited clear large hysteresis which is increased with increasing programming voltage. The shifts in the threshold voltage of the transfer characteristics as well as the hysteresis in the output characteristics were attributed to the charging and discharging of the floating gate. The counter-clockwise direction of hysteresis indicates that the process of charging and discharging the floating gate take place through the semiconductor/insulator interface. A clear shift in the threshold voltage was observed when different voltage pulses were applied to the gate. The non-volatile behaviour of the memory transistors was investigated in terms of charge retention. The memory transistors exhibited a large memory window (~30 V), and high charge density of (9.15 × 1011 cm−2).
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Noor, Fatimah Arofiati, Gilang Mardian Kartiwa, and Muhammad Amin Sulthoni. "Studi Elektrostatik Elektroda Runcing dan Aplikasinya pada Perangkat Floating Gate Memory." POSITRON 11, no. 1 (October 15, 2021): 1. http://dx.doi.org/10.26418/positron.v11i1.44881.

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Pada penelitian ini, potensial elektrostatik dari struktur floating gate runcing dalam sel memori split gate dipelajari secara analitik dan numerik. Penelitian ini bertujuan memberikan pendekatan sederhana untuk mempelajari diagram pita energi pada perangkat memori. Diagram energi yang dihasilkan dapat digunakan untuk mempelajari transmitansi elektron dan rapat arus terobosan. Pada studi ini, floating gate runcing dimodelkan sebagai elektroda berbentuk segitiga. Profil potensial elektrostatik elektroda segitiga ini dihitung secara analitik dengan menyelesaikan nilai batas dari persamaan Laplace dalam koordinat polar. Profil potensial dari perhitungan analitik ini lalu dibandingkan dengan profil potensial dari simulasi numerik. Dari hasil perhitungan diperoleh bahwa profil diagram energi yang dihitung secara analitik cukup sesuai dengan yang diperoleh dari simulasi numerik. Adapun terdapat sedikit perbedaan antara profil diagram pita analitik dan numerik dikarenakan elektroda segitiga diasumsikan terbuat dari logam sehingga pembentukan sumur kuantum pada permukaan floating gate diabaikan. Dari hasil permodelan analitik diperoleh bahwa sumur kuantum yang terbentuk pada tegangan sekitar 10 V (sesuai dengan tegangan hapus perangkat memori flash) adalah cukup dangkal, sehingga profil potensial yang terbentuk menjadi sangat mendekati hasil simulasi numerik. Dari hasil perhitungan diperoleh pula bahwa rapat arus terobosan yang dihitung menggunakan model kami memberikan hasil yang sangat dekat dengan hasil perhitungan dari model injektor silinder yang digunakan oleh peneliti dari Silicon Storage Technology (SST) sebagai produsen produk flash memory dengan floating gate berbentuk runcing.
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Lingalugari, Murali, Evan Heller, Barath Parthasarathy, John Chandy, and Faquir Jain. "Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing." International Journal of High Speed Electronics and Systems 27, no. 01n02 (March 2018): 1840006. http://dx.doi.org/10.1142/s0129156418400062.

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This paper presents an approach to enhance floating gate quantum dot nonvolatile random access memory (QDNVRAM) cells in terms of higher-speed and lower-voltage Erase not possible with conventional floating gate nonvolatile memories. It is achieved by directly accessing the floating gate layer with a Ge quantum dot access channel via an additional drain (D2) during the Erase and/or Write operation. Quantum mechanical simulations in GeOx-cladded Ge quantum dot layers functioning as the floating gate as well access channel to facilitate Erase and Write are presented. Experimental data on fabricated long channel nonvolatile random access memory cell with SiOx-cladded Si dots is presented. Quantum simulations show lower voltage operation for GeOx-cladded Ge QD floating gate than SiOx-cladded Si dots. The Erase time is orders of magnitude faster than flash and is comparable to competing NVRAMs.
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Zhang, Pengfei, Dong Li, Mingyuan Chen, Qijun Zong, Jun Shen, Dongyun Wan, Jingtao Zhu, and Zengxing Zhang. "Floating-gate controlled programmable non-volatile black phosphorus PNP junction memory." Nanoscale 10, no. 7 (2018): 3148–52. http://dx.doi.org/10.1039/c7nr08515j.

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By designing and tailoring the structure of the floating gate, a special floating-gate field-effect transistor configuration has been proposed for the design of programmable non-volatile black phosphorus PNP junction memory.
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Lee, Boong-Joo. "Operating characteristics of Floating Gate Organic Memory." Journal of the Korea Academia-Industrial cooperation Society 15, no. 8 (August 31, 2014): 5213–18. http://dx.doi.org/10.5762/kais.2014.15.8.5213.

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Park, Byoungjun, Kyoungah Cho, Sungsu Kim, and Sangsig Kim. "Transparent nano-floating gate memory on glass." Nanotechnology 21, no. 33 (July 26, 2010): 335201. http://dx.doi.org/10.1088/0957-4484/21/33/335201.

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Cellere, G., P. Pellati, A. Chimenton, J. Wyss, A. Modelli, L. Larcher, and A. Paccagnella. "Radiation effects on floating-gate memory cells." IEEE Transactions on Nuclear Science 48, no. 6 (2001): 2222–28. http://dx.doi.org/10.1109/23.983199.

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Lee, Jang-Sik. "Review paper: Nano-floating gate memory devices." Electronic Materials Letters 7, no. 3 (September 2011): 175–83. http://dx.doi.org/10.1007/s13391-011-0901-5.

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Dissertations / Theses on the topic "Floating Gate Memory"

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Ostraat, Michele L. Atwater Harry Albert. "Synthesis and characterization of aerosol silicon nanoparticle nonvolatile floating gate memory devices /." Diss., Pasadena, Calif. : California Institute of Technology, 2001. http://resolver.caltech.edu/CaltechETD:etd-04072005-081230.

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Fakher, Sundes Juma. "Advanced study of pentacene-based organic memory structures." Thesis, Bangor University, 2014. https://research.bangor.ac.uk/portal/en/theses/advanced-study-of-pentacenebased-organic-memory-structures(5319a571-2c4c-4f90-a26c-fa5e7da82cfb).html.

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A systematic approach has been used to optimise the fabrication process of pentacene-based nonvolatile organic thin film memory transistors (OTFMTs) operating at low programming voltages. In the first part of this work, reliable, reproducible and hysteresis free organic metal-insulator-semiconductor (OMIS) devices and organic thin film transistors (OTFTs) were fabricated and characterised. All devices were based on poly(methyl methacrylate) (PMMA) and poly(vinyl phenol) (PVP) as the organic insulators. The second part of this work focused on optimising the evaporation parameters to fabricate high-performance pentacene-based devices. About 50 nm thickness of pentacene film with a deposition rate of 0.03 nm s-1 on ~ 300 nm of PMMA was found to produce large, uniform and condense grains leading to high quality devices. OTFTs with high mobility of 1.32 cm2 V−1 s−1, on/off current ratio of 106, and negligible hysteresis and leakage current were demonstrated. The effect of the environment on the OTFTs obehaviour was also investigated. The bias stress effect was also investigated in terms of threshold voltage shift ΔVT at various conditions and times. The results show ΔVT increases with the increase of stress voltage. A negligible hysteresis is evident between the forward and reverse direction of the transfer characteristics and the shape of the transfer characteristics does not change with the bias stress. Floating gate memory structures with thin layer of gold, gold nanoparticles (AuNPs) and single walled carbon nanotubes (SWCNTs) were fabricated and characterised during this investigation. Hysteresis in memory structures was a clear indication of the memory effect and charge storage in these devices. Also, the hysteresis was centred close to 0 V for SWCNTs-based structures, which indicate that a low operation voltage is needed to charge the devices. A memory window of about 40 V was observed for AuNPs-based memory devices based on PVP; while the memory windows for devices based on PMMA with thin layer of Au and AuNPs floating gates were 22 V and 32 V, respectively. The electrical properties of the OTFMTs were improved by the use of the Au nanoparticles as the floating gate compared with that of an Au thin film. Using appropriate negative or positive voltages, the floating gate was charged and discharged, resulting in a clear shift in the threshold voltage of the memory transistors. Negative and positive pulses of 1 V resulted in clear write and erase states, respectively. Additionally, these organic memory transistors exhibited rather high carrier mobility of about μ = 0.319 cm2 V-1 s-1. Furthermore the data retention and endurance measurements confirmed the non-volatile memory properties of the memory devices fabricated in this study.
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Couto, Andre Luis do. "Caracterização de memorias analogicas implementadas com transistores MOS floating gate." [s.n.], 2005. http://repositorio.unicamp.br/jspui/handle/REPOSIP/260078.

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Orientador: Carlos Alberto dos Reis Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Eletrica e de Computação
Made available in DSpace on 2018-08-07T11:14:24Z (GMT). No. of bitstreams: 1 Couto_AndreLuisdo_M.pdf: 2940356 bytes, checksum: 959908541a3bc46b7b7035eb035de186 (MD5) Previous issue date: 2005
Resumo: A integração de memórias e circuitos analógicos em um mesmo die oferece diversas vantagens: redução de espaço nas placas, maior confiabilidade, menor custo. Para tanto, prescindir-se de tecnologia específica à confecção de memórias e utilizar-se somente de tecnologia CMOS convencional é requisito para tal integração. Essa pode ser tanto mais eficiente quanto maior a capacidade de armazenagem de dados, ou seja, maior a densidade de informação. Para isso, memórias analógicas mostram-se bem mais adequadas, posto que em uma só célula (um ou dois transistores) podem ser armazenados dados que precisariam de diversas células de memórias digitais e, portanto, de maior área. Neste trabalho, transistores MOS com porta flutuante mostraram-se viáveis de serem confeccionados e resultados de caracterização como tipos de programação, retenção de dados e endurance foram obtidos. O trabalho apresenta as principais características dos FGMOS (Floating Gate MOS) e presta-se como referência à futuros trabalhos na área
Abstract:Monolithic integration of memories and analog circuits ,in the same die offers interesting advantages like: smaller application boards, higher robustness and mainly lower costs. Today, a profitable integration of these kind of circuit can only be possible using conventional CMOS technology, which allows efficiently extraordinary levels of integration. Thus, the possibility of integrating analog memories looks more suitable since one single cell (usually use one or two transistors) serves for storing the same data stored by few digital memory cells, therefore, they requiring less area. In this work, it was implemented different memory cells together with few devices using floating gate MOS transistors and manufactured by a conventional CMOS technology. Differemt sort of programrning', data retention, and endurance were characterized as well as the main characteristics of the FGMOS (Floating Gate MOS) were obtained. The results of their characterization reveal that is possible to make and' to program fIoating gate MOSFETS analog memories and must serve as starting-point and reference for new academic studies
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica
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Marron, Dominique. "Etude des transistors à grille flottante et application à la conception d'une mémoire reconfigurable intégrée sur tranche." Grenoble 1, 1989. http://www.theses.fr/1989GRE10080.

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Afin d'accroitre la complexite des composants electroniques, leur architecture utilise des elements redondants. On pallie ainsi les problemes de rendements. Cette these traite d'un element de reconfiguration, le transistor a grille flottante, et de sa programmation par un faisceau d'electrons. Les conditions de programmation, la tenue dans le temps de la charge deposee ainsi que les problemes pratiques rencontres sont etudies. Ce transistor est ensuite utilise dans la conception d'une memoire sram de 4. 5 mbit reconfigurable integree sur une tranche d=100. Les contraintes pratiques et l'architecture sont exposees de meme que la partie realisation et test. Cette etude est en fait une etude de faisabilite pour des circuits de type wsi industriels
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Marzaki, Abderrezak. "Développement de technique de procédé de fabrication innovante et de nouvelle architecture de transistor MOS." Thesis, Aix-Marseille, 2013. http://www.theses.fr/2013AIXM4768.

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La miniaturisation des composants et l’amélioration des performances des circuits intégrés (ICs) sont dues aux progrès liés au procédé de fabrication. Malgré le nombre de technologie existante, la technologie CMOS est la plus utilisée. Dans le cadre du développement de la technologie CMOS 90nm à double niveau de poly, des recherches sur l’introduction de techniques innovantes de procédé de fabrication et d’une nouvelle architecture de transistor MOS à tension de seuil ajustable ont été menées dans le but d’améliorer les performances des ICs. Une première étude sur l’implémentation des effets de pointe dans les ICs, en particulier pour les mémoires non volatiles est entreprise. Un nouveau procédé de fabrication permettant d’obtenir des pointes dans un matériau est proposé. Il est démontré le gain en courant tunnel obtenu sur une structure pointue par rapport à une structure plane. Une seconde étude est orientée sur le développement d’une nouvelle technique de « patterning ». Les techniques de « patterning » permettent de réduire les dimensions de la photolithographie sans utiliser de masque ayant des dimensions agressives. Les avantages de cette nouvelle technique aux niveaux de sa mise en œuvre et de la suppression des problèmes d’alignement sont présentés. Une dernière étude sur le développement d’un transistor à tension de seuil ajustable est développée. Il est démontré l’avantage de ce composant par rapport aux autres composants à tension de seuil ajustable. La réalisation du modèle et des premières simulations électriques de circuit élémentaire à base de se composant sont présentés. L’amélioration de certaines performances des circuits élémentaire est démontrée
The component miniaturization and the circuit performance improvement are due to the progress related to the manufacturing process. Despite the number of existing technology, the CMOS technology is the most used. In the 90nm CMOS technology development, with a double poly-silicon level, the research on the introduction of innovative manufacturing process techniques and a new architecture of MOS transistor with an adjustable threshold voltage are carried out to improve the integrated circuit performances. A first study, on the peak effect implementation in the integrated circuits, particularly in the non-volatile memories is undertaken. A new process to obtain a peak effect in a material is proposed. It is shown the tunnel current gain obtained on a peak structure compared with a planar structure. A second study is focused on the development of a new patterning technique. The patterning techniques allow to reduce the photolithography dimensions without using an aggressive mask. The advantages of this new technique in terms of its implementation and the suppression of alignment problems are presented. A last study on the development of a MOS transistor with an adjustable threshold voltage is developed. It is shown the advantage of this component relative to the other components with an adjustable threshold voltage. The model implementation and the first electrical simulations of elementary circuits composed with this new component are presented. The performance improvement of some elementary circuits is demonstrated
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Melde, Thomas. "Modellierung und Charakterisierung des elektrischen Verhaltens von haftstellen-basierten Flash-Speicherzellen." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-84301.

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Im Rahmen dieser Arbeit werden haftstellen-basierte Speicherzellen als mögliche Alternative zum bestehenden Floating-Gate Konzept untersucht. Hierbei wird zunächst mittels Simulation und ausgewählten Messverfahren das Verständnis der Funktionsweise vertieft. Der darauffolgende Abschnitt befasst sich mit der Verbesserung der elektrischen Eigenschaften, basierend auf Änderungen der verwendeten Materialien und dem räumlichen Aufbau. Abschließend erfolgt die Untersuchung der Anwendbarkeit des Zellkonzeptes in hochdichten Zellenfeldern.
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Liu, Yueran 1975. "Novel flash memory with nanocrystal floating gate." Thesis, 2006. http://hdl.handle.net/2152/2819.

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ZHAO, CHUAN-ZHEN, and 趙傳珍. "Floating-gate mos transistors as analog memory devices." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/33712669387087189947.

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Lee, Jong Jin Kwong Dim-Lee. "A study on the nanocrystal floating-gate nonvolatile memory." 2005. http://repositories.lib.utexas.edu/bitstream/handle/2152/1975/leej77040.pdf.

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Lee, Jong Jin. "A study on the nanocrystal floating-gate nonvolatile memory." Thesis, 2005. http://hdl.handle.net/2152/1975.

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Book chapters on the topic "Floating Gate Memory"

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Zhou, Ye, Su-Ting Han, and Arul Lenus Roy Vellaisamy. "Flexible Floating Gate Memory." In Flexible and Stretchable Medical Devices, 215–28. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2018. http://dx.doi.org/10.1002/9783527804856.ch9.

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Fakher, S., A. Sleiman, A. Ayesh, A. AL-Ghaferi, M. C. Petty, D. Zeze, and Mohammed Mabrook. "Organic Floating Gate Memory Structures." In Charge-Trapping Non-Volatile Memories, 123–56. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-48705-2_4.

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Conte, Antonino, Fabio Disegni, Francesco La Rosa, and Alfonso Maurelli. "Floating-Gate 1Tr-NOR eFlash Memory." In Integrated Circuits and Systems, 75–129. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-55306-1_4.

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Do, Nhan, Hieu Van Tran, Alex Kotov, and Vipin Tiwari. "Split-Gate Floating Poly SuperFlash® Memory Technology, Design, and Reliability." In Integrated Circuits and Systems, 131–78. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-55306-1_5.

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Thean, A., and J. P. Leburton. "Three-Dimensional Self-Consistent Simulation of Silicon Quantum Dot Floating-Gate Flash Memory Device." In Physical Models for Quantum Dots, 807–14. New York: Jenny Stanford Publishing, 2021. http://dx.doi.org/10.1201/9781003148494-51.

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Di Spigna, Neil, Daniel Schinke, Srikant Jayanti, Veena Misra, and Paul Franzon. "Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates." In VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 217–33. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-45073-0_12.

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"Floating Gate Planar Devices." In Nonvolatile Semiconductor Memory Technology. IEEE, 2009. http://dx.doi.org/10.1109/9780470545409.ch2.

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"Floating Gate Nonplanar Devices." In Nonvolatile Semiconductor Memory Technology. IEEE, 2009. http://dx.doi.org/10.1109/9780470545409.ch3.

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"Floating Gate Flash Memories." In Nonvolatile Semiconductor Memory Technology. IEEE, 2009. http://dx.doi.org/10.1109/9780470545409.ch4.

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KAHNG, D., and S. M. SZE. "A Floating Gate and Its Application to Memory Devices." In Semiconductor Devices: Pioneering Papers, 639–46. WORLD SCIENTIFIC, 1991. http://dx.doi.org/10.1142/9789814503464_0082.

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Conference papers on the topic "Floating Gate Memory"

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Martins, R., L. Pereira, P. Barquinha, N. Correia, G. Gonçalves, I. Ferreira, C. Dias, and E. Fortunato. "Floating gate memory paper transistor." In OPTO, edited by Ferechteh H. Teherani, David C. Look, Cole W. Litton, and David J. Rogers. SPIE, 2010. http://dx.doi.org/10.1117/12.841036.

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Chan, N., M. F. Beug, R. Knoefler, T. Mueller, T. Melde, M. Ackermann, S. Riedel, M. Specht, C. Ludwig, and A. T. Tilke. "Metal control gate for sub-30nm floating gate NAND memory." In 2008 9th Annual Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2008. http://dx.doi.org/10.1109/nvmt.2008.4731199.

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Chiang, Pei Wei, Yu Ting Ling, Bo Chih Chen, and Hsiao Tien Chang. "Gate Bridge to Drain Contact Characteristic in Floating Gate Memory." In ISTFA 2013. ASM International, 2013. http://dx.doi.org/10.31399/asm.cp.istfa2013p0456.

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Abstract Gate-to-drain contact short issue in floating gate memory has been studied. Two cases will be discussed, floating-gate to drain contact short, and control-gate to drain contact short, both caused by leakage bridge defect. The abnormal electrical device characteristic combined with modeling gives further insight into the failure mode. Nano-prober measurement results not only provide an evidence of short-contact issue but also measures the current behaviors between drain and gate in floating gate configuration. These results help to predict the defect location and successfully monitor the bridge-failure through electrical analysis.
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Tempel, Georg. "Floating gate type nonvolatile memory reliability issues." In 2003 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2003. http://dx.doi.org/10.7567/ssdm.2003.b-3-1.

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Arai, Fumitaka. "Future Outlook of Floating Gate Flash Memory." In 2006 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2006. http://dx.doi.org/10.7567/ssdm.2006.c-6-1.

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Chang, Chi. "Reliability Issues of Floating Gate Flash Memory." In 1998 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1998. http://dx.doi.org/10.7567/ssdm.1998.b-3-1.

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Motwani, R. "Hierarchical Constrained Coding for Floating-Gate to Floating-Gate Coupling Mitigation in Flash Memory." In 2011 IEEE Global Communications Conference (GLOBECOM 2011). IEEE, 2011. http://dx.doi.org/10.1109/glocom.2011.6134528.

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Li, Bei, Yan Zhu, and Jianlin Liu. "Ge/Si hetero-nanocrystal nonvolatile floating gate memory." In 2007 65th Annual Device Research Conference. IEEE, 2007. http://dx.doi.org/10.1109/drc.2007.4373725.

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Di Spigna, Neil, Daniel Schinke, Srikant Jayanti, Veena Misra, and Paul Franzon. "A novel double floating-gate unified memory device." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.6379005.

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Di Spigna, Neil, Daniel Schinke, Srikant Jayanti, Veena Misra, and Paul Franzon. "A novel double floating-gate unified memory device." In 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC). IEEE, 2012. http://dx.doi.org/10.1109/vlsi-soc.2012.7332076.

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