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Journal articles on the topic 'Flip-flop (electronics)'

Author: Grafiati

Published: 23 June 2022

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1

Mathis, Wolfgang. "100 years multivibrator-history, circuits and mathematical analysis." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 39, no. 3 (January 22, 2020): 725–37. http://dx.doi.org/10.1108/compel-10-2019-0411.

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Purpose This work is intended to historically commemorate the one hundredth anniversary of the invention of a new type of electronic circuit, referred to in 1919 by Abraham and Bloch as a multivibrator and by Eccles and Jordan as a trigger relay (later known as a flip-flop). Design/methodology/approach The author also considers the circuit-technical side of this new type of circuit, considering the technological change as well as the mathematical concepts developed in the context of the analysis of the circuit. Findings The multivibrator resulted in a “circuit shape” which became one of the most applied nonlinear circuits in electronics. It is shown that at the beginning the multivibrator as well as the flip-flop circuits were used because their interesting properties in the frequency domain. Originality/value Therefore, it is a very interesting subject to consider the history of the multivibrator as electronic circuits in different technologies including tube, transistors and integrated circuits as well as the mathematical theory based on the concept from electrical circuit theory.

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2

Lin, Dave Y. W., and Charles H. P. Wen. "A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability." ACM Transactions on Design Automation of Electronic Systems 26, no. 6 (June 28, 2021): 1–12. http://dx.doi.org/10.1145/3462171.

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As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

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3

Ragavendran, U., and M. Ramachandran. "Low Power and Low Complexity Flip-Flop Design using MIFGMOS." International Journal of Engineering & Technology 7, no. 3.1 (August 4, 2018): 183. http://dx.doi.org/10.14419/ijet.v7i3.1.17233.

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Sequential logic is essential in many applications as data processing for speech recognition in cochlear implants. In this paper, a family of latches based on floating-gate MOS (FGMOS) transistors is presented. This family takes advantage on the fact that FGMOS logics process data using mostly passive devices, achieving small area and low-power, requirements of modern electronics. Post-layout SPICE simulations from an ON-Semiconductors 0.5 µm CMOS process technology shows improvements over conventional CMOS logic families, making FGMOS latches ideal for low-power applications.

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4

Guo, Wei Jia, Shu Bao Wang, Gui Jing Mei, and Xiu Mei Zhang. "Swift Self-Starting Design of Sequential Logic Circuit Based on Karnaugh Map." Applied Mechanics and Materials 220-223 (November 2012): 1008–11. http://dx.doi.org/10.4028/www.scientific.net/amm.220-223.1008.

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To make the circuit self-start swiftly in the environment with much disturbance, according to the principle of being propitious to simplify state equation and output equation, assigned a next state for each bound term on Karnaugh map, and the next state must be a state of the valid cycle, at last tested the method by simulation. In the simulation, imitated the disturbance by the set pin or reset pin of flip-flop. The simulation based on electronics workbench 5.0C shows the effectiveness and feasibility of the method.

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Rompis, Lianly. "A RANDOM COUNTER IN USING SHIFT REGISTER AND ENCODER." Jurnal Ilmiah Realtech 14, no. 1 (April 30, 2018): 64–68. http://dx.doi.org/10.52159/realtech.v14i1.118.

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Mostly some specific computer circuits and digital circuit applications need a random counter circuit module for handling specific tasks or operations. To design this kind of circuit, it is more common to use the standard format design of synchronous counter, although this will be more complicated to derive its truth table and karnaugh-maps in order to solve the right output equations for flip-flop inputs. This paper will introduce another way of designing a digital random counter, using shift register and encoder, which is easier to applied and the sequence of this counter can be managed randomly. The methodology being used for this research is mainly tounderstand the basic concept and combine the functions of shift register and encoder, to derive a new and simple form of designing a random counter. Using an Electronics Workbench software, the outputs are shown in logic simulation.

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6

Rahman, Aminur, Ian Jordan, and Denis Blackmore. "Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops." Proceedings of the Royal Society A: Mathematical, Physical and Engineering Sciences 474, no. 2209 (January 2018): 20170111. http://dx.doi.org/10.1098/rspa.2017.0111.

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It has been observed through experiments and SPICE simulations that logical circuits based upon Chua’s circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some discrete dynamical models have been developed using various simplifying assumptions. To create a robust modelling framework for chaotic logical circuits, we developed both deterministic and stochastic discrete dynamical models, which exploit the natural recurrence behaviour, for two chaotic NOR gates and a chaotic set/reset flip-flop. This work presents a complete applied mathematical investigation of logical circuits. Experiments on our own designs of the above circuits are modelled and the models are rigorously analysed and simulated showing surprisingly close qualitative agreement with the experiments. Furthermore, the models are designed to accommodate dynamics of similarly designed circuits. This will allow researchers to develop ever more complex chaotic logical circuits with a simple modelling framework.

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Prema, S., N. Karthikeyan, and S. Karthik. "Ultra-Low Power and High Sensitivity of Joint Clock Gating Based Dual Feedback Edge Triggered Flip Flop for Biomedical Imaging Applications." Journal of Medical Imaging and Health Informatics 11, no. 12 (December 1, 2021): 3215–22. http://dx.doi.org/10.1166/jmihi.2021.3919.

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To adapt to varied working situations, the latest biomedical imaging applications require low energy consumption, high performance, and extensive energy-performance scalability. State-of-the-art electronics with higher sensitivity, higher counting rate, and finer time resolution are required to create higher precision, higher temporal resolution, and maximum contrast biomedical images. In recent days, the system’s power consumption is important critically in modern VLSI circuits particularly for the low power application. In order to decrease the power, a power optimization technique must be used at various design levels. The low power use of logic cells is a proficient technique for decreasing the circuit level power. Dual Feedback edge triggered Flip Flop (DFETFF) is considered for biomedical imaging applications in the proposed system. Initially, the high dynamic range voltage is given as input signal. The comparator output is then retried at the comparator end. The integration capacitor is employed for storing remaining voltage signal. The comparator voltage is then given to the capacitor reset block. In the proposed work, a capacitor-reset block that employs clock signal takes up a dual-feedbackedge-triggered Flip-flop as an alternative of a conventional type for reducing the final output signals errors. Dual feedback loops assure that feedback loops do not tri-state at the time of SET restoration, a scheme that could lead to SEUs in latches if a single delay component and a single feedback loop are used. In digital system, Clock gating is a competent method of lessening the overall consumption of power along with deactivating the clock signal selectively and is useful for controlling the usage of clock signal asynchronously in reference to input-signal current. The integration-control (Vint) signal is employed in controlling the integration time. On the termination of integration, the signal level phase is kept, also similar one is send to arrangement all through read period. As a result, the simulation was carried out after the design layout and the estimations of performance were made and are compared with traditional approaches to prove the proposed mechanism effectiveness for future biomedical applications.

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Hassan, Ahmad, Jean-Paul Noël, Yvon Savaria, and Mohamad Sawan. "Circuit Techniques in GaN Technology for High-Temperature Environments." Electronics 11, no. 1 (December 23, 2021): 42. http://dx.doi.org/10.3390/electronics11010042.

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As a wide bandgap semiconductor, Gallium Nitride (GaN) device proves itself as a suitable candidate to implement high temperature (HT) integrated circuits. GaN500 is a technology available from the National Research Council of Canada to serve RF applications. However, this technology has the potential to boost HT electronics to higher ranges of operating temperatures and to higher levels of integration. This paper summarizes the outcome of five years of research investigating the implementation of GaN500-based circuits to support HT applications such as aerospace missions and deep earth drilling. More than 15 integrated circuits were implemented and tested. We performed the HT characterization of passive elements integrated in GaN500 including resistors, capacitors, and inductors up to 600 °C. Moreover, we developed for the first time several digital circuits based on GaN500 technology, including logic gates (NOT, NAND, NOR), ring oscillators, D Flip-Flop, Delay circuits, and voltage reference circuits. The tested circuits are fabricated on a 4 mm × 4 mm chip to validate their functionality over a wide range of temperatures. The logic gates show functionality at HT over 400 °C, while the voltage reference circuits remain stable up to 550 °C.

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Wang, An Jing, and Yu Zhuo Fu. "Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact." Applied Mechanics and Materials 716-717 (December 2014): 1239–43. http://dx.doi.org/10.4028/www.scientific.net/amm.716-717.1239.

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Recently, Multi-bit flip-flop usage has shown its advantage in dynamic power saving in nowadays commercial electronic design. This paper present a more comprehensive comparison of chip-level synthesis result by using single-bit flip-flop and multi-bit flip-flop standard cell and except for analyzing the power and area benefit from replacement under the maximum speed, this paper give a compromise solution to solve that using multi-bit flip-flop cannot run as the fastest as single-bit with even large area. The trade-off between a multi-bit flip-flop cell driving strength and its area when designing multi-bit standard cell that will greatly influence synthesis result as speed arise are also mentioned. Finally, this research about MBFF further usage improvements may be helpful for designers to know how to take full advantage of multi-bit flip-flops to bring about the wanted benefit.

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10

Komshina, A., S. Telibaev, and B. S. Mikhlin. "ASSEMBLING THE RS FLIP-FLOP ON CHIPS CONTAINING ELEMENTS OF "OR-NOT", "AND-NOT"." Informatics in school, no. 7 (November 17, 2018): 17–25. http://dx.doi.org/10.32517/2221-1993-2018-17-7-17-25.

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The article provides general information about flip-flops, their types, about an asynchronous RS flip-flop. A detailed description of the practical work on assembling the RS flip-flop in two variants is given, based on a chip containing four "2OR-NOT" elements, and based on a chip containing four "2AND-NOT" elements. The details from the electronic set "Micronik" ("Amperka") and the details provided by the site "Let's create together" are used in assembling.

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CHANG, ROBERT C., L. C. HSU, and M. C. SUN. "A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH." Journal of Circuits, Systems and Computers 11, no. 01 (February 2002): 51–55. http://dx.doi.org/10.1142/s0218126602000239.

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A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

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12

Liu, J. M., and Y. C. Chen. "Optical flip-flop." Electronics Letters 21, no. 6 (1985): 236. http://dx.doi.org/10.1049/el:19850169.

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13

Gabrielli, Alessandro, Fabrizio Alfonsi, Alberto Annovi, Alessandra Camplani, and Alessandro Cerri. "Hardware Implementation Study of Particle Tracking Algorithm on FPGAs." Electronics 10, no. 20 (October 18, 2021): 2546. http://dx.doi.org/10.3390/electronics10202546.

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In recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%.

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14

Badugu, Divya Madhuri, Sunithamani S., Javid Basha Shaik, and Ramesh Kumar Vobulapuram. "Design of hardened flip-flop using Schmitt trigger-based SEM latch in CNTFET technology." Circuit World 47, no. 1 (June 1, 2020): 51–59. http://dx.doi.org/10.1108/cw-10-2019-0141.

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Purpose The purpose of this paper is to design novel hardened flip-flop using carbon nanotube field effect transistors (CNTFETs). Design/methodology/approach To design the proposed flip-flop, the Schmitt trigger-based soft error masking and unhardened latches have been used. In the proposed design, the novel mechanism, i.e. hysteresis property is used to enhance the hardness of the single event upset. Findings To obtain the simulation results, all the proposed circuits are extensively simulated in Hewlett simulation program with integrated circuit emphasis software. Moreover, the results of the proposed latches are compared to the conventional latches to show performance improvements. It is noted that the proposed latch shows the performance improvements up to 25.8%, 51.2% and 17.8%, respectively, in terms of power consumption, area and power delay product compared to the conventional latches. Additionally, it is observed that the simulation result of the proposed flip-flop confirmed the correctness with its respective functions. Originality/value The novel hardened flip-flop utilizing ST based SEM latch is presented. This flip-flop is significantly improves the performance and reliability compared to the existing flip-flops.

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15

Majeed, Ali, Esam Alkaldy, Mohd Zainal, and Danial Nor. "Novel Memory Structures in QCA Nano Technology." 3D SCEEER Conference sceeer, no. 3d (July 1, 2020): 119–24. http://dx.doi.org/10.37917/ijeee.sceeer.3rd.17.

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Quantum-dot Cellular Automata (QCA) is a new emerging technology for designing electronic circuits in nanoscale. QCA technology comes to overcome the CMOS limitation and to be a good alternative as it can work in ultra-high-speed. QCA brought researchers attention due to many features such as low power consumption, small feature size in addition to high frequency. Designing circuits in QCA technology with minimum costs such as cells count and the area is very important. This paper presents novel structures of D-latch and D-Flip Flop with the lower area and cell count. The proposed Flip-Flop has SET and RESET ability. The proposed latch and Flip-Flop have lower complexity compared with counterparts in terms of cell counts by 32% and 26% respectively. The proposed circuits are designed and simulated in QCADesigner software.

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Asthana, Amita, Dr Anil Kumar, Dr Preeta Sharan, and Dr Sumita Mishra. "Design of Arm Processor’s Elements Using QCA." International Journal of Engineering & Technology 7, no. 4.36 (December 9, 2018): 306. http://dx.doi.org/10.14419/ijet.v7i4.36.23793.

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Quantum dot Cellular Automata is one of the promising future nano-technology for transistor-less computing which takes advantage of the coulomb force interacting between electrons. The aim of this paper is to consider the logical circuits of ARM processors and further reducing their size in nanometres like 2:1 multiplexer , D Flip Flop, scan Flip Flop, 2:1 multiplexer with enable, encoder, decoder, SR FF, shift register, memory cell and program counter are designed using QCAD tool . Their cell count, area, kink energy are taken in consideration to calculate power and energy dissipation.

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Duraivel, A. N., B. Paulchamy, and K. Mahendrakan. "Proficient Technique for High Performance Very Large-Scale Integration System to Amend Clock Gated Dual Edge Triggered Sense Amplifier Flip-Flop with Less Dissipation of Power Leakage." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (April 1, 2021): 602–11. http://dx.doi.org/10.1166/jno.2021.2984.

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Clocked flip flops are used to memory in synchronous or clocked series networks, adjusting the individual clock signal status. Therefore, at these times of clock signal transfer, the state of the memory unit and the state of the whole electrical structure change. It’s only during signal transfer that the key to a flip-flop being correctly operated. Two transitions from 0 and 1 are followed by a clock pulse, and 1 to 0. The pulse shift is defined by the positive and negative sides of the pulse. The data on or off the clock cycle edges are recorded by a single-edge trigger flip flop (SETFF), but the flip flop with the double-edge sensor amplifier (DETSAFF). Another common technique for dynamic energy consumption reduced when the device is idle is the clock gating. In this document. Sleep is used to reduce the power of the leakage Here are the following: High threshold voltages sleep transistors are used. Among the supply voltage and VDD the sleep pMOS transistor and the pull-up system and between the network and the ground GND a sleep NMOs Transistor is located. With sleep transistors, CG-SAFF can save up to 30% of its power during zero input switching operation. For different sequential device architecture, the proposed flip-flop may be used.

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18

Pal, Amrindra, Santosh Kumar, and Sandeep Sharma. "Design of Optical SR Latch and Flip-Flop Using Electro-Optic Effect Inside Lithium–Niobate-Based Mach–Zehnder Interferometers." Journal of Optical Communications 40, no. 2 (March 26, 2019): 119–34. http://dx.doi.org/10.1515/joc-2017-0053.

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Abstract Set-Reset (SR) latch or flip-flop is bistabile circuit. The circuit maintains a binary state indefinitely until directed by an input signal (clock signal) to switch state. Sequential logic circuits for specific application can be implemented by using SR flip-flop and external gates. In this article, SR latch and SR flip-flop is proposed using electro-optic effect inside lithium–niobate-based Mach–Zehnder interferometers (MZIs). The MZI structures have the powerful capability of switching an optical input signal to a desired output port. The article constitutes a mathematical description of the proposed device and thereafter simulation using MATLAB. The study is verified using beam propagation method (BPM).

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19

Lala, P. K., and A. Walker. "A Fine Grain Configurable Logic Block for Self-checking FPGAs." VLSI Design 12, no. 4 (January 1, 2001): 527–36. http://dx.doi.org/10.1155/2001/83474.

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This paper proposes a logic cell that can be used as a building block for Self-checking FPGAs. The proposed logic cell consists of two 2-to-1 multiplexers, three 4-to-1 multiplexers and a D flip-flop. The cell has been designed using Differential Cascode Voltage Switch Logic. It is self-checking for all single transistor stuck-on and stuck-off faults as well as stuck-at faults at the inputs of each multiplexers and the D flip-flop. The multiplexers and the D flip-flop provide either correct (complementary) output in the absence of above-mentioned faults; otherwise the outputs are identical.

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20

Stephan, G., B. Aissaoui, and A. Kellou. "A flip-flop interferometer." IEEE Journal of Quantum Electronics 23, no. 4 (April 1987): 458–60. http://dx.doi.org/10.1109/jqe.1987.1073366.

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21

Zhuang, N., and H. Wu. "Novel ternary JKL flip-flop." Electronics Letters 26, no. 15 (1990): 1145. http://dx.doi.org/10.1049/el:19900741.

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22

Li, X., S. Jia, X. Liang, and Y. Wang. "Self-blocking flip-flop design." Electronics Letters 48, no. 2 (2012): 82. http://dx.doi.org/10.1049/el.2011.2888.

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23

Park, Jaeyoung, and Young Yim. "Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop." Micromachines 10, no. 6 (June 20, 2019): 411. http://dx.doi.org/10.3390/mi10060411.

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An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is 6.9 % normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1 × and the energy by 1.5 × . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

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Xu, Daiguo, Shiliu Xu, and Yuxin Wang. "Improved self‐blocking flip‐flop design." Electronics Letters 52, no. 14 (July 2016): 1207–9. http://dx.doi.org/10.1049/el.2016.0836.

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25

Kanjamala, A. P., and A. F. J. Levi. "Wavelength selective electro-optic flip-flop." Electronics Letters 34, no. 3 (1998): 299. http://dx.doi.org/10.1049/el:19980224.

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Arunabala, Dr C., A. Lohithakshi, D. Jyothsna, CH Pranathi, and A. Navaneetha. "Design of Low Power and High-Speed Cmos D Flipflop using Supply Voltage Level (SVL) Methods." International Journal of Innovative Technology and Exploring Engineering 11, no. 5 (April 30, 2022): 32–36. http://dx.doi.org/10.35940/ijitee.e9850.0411522.

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This Project details about the design of D Flip Flop (DFPFP). This D Flip Flop circuit is analyzed by using the supply voltage level methods. These methods are used mainly to suppress the power consumption caused due to leakage currents. In addition, because of this implemented technique, the time taken for battery backup, and the supply voltage given at standby mode gets minimized. The projected circuit uses a smaller number of transistors, such that power consumption and leakage currents are in prior limit. Mainly, the CMOS D Flip Flops are designed to use them in binary counters, shift registers, Analog and Digital circuit designs. And this circuit design is implemented in 45nm CMOS Technology Cadence Virtuoso Tool.

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Koshak, Essam, Afzel Noore, and Rita Lovassy. "Intelligent reconfigurable universal fuzzy flip-flop." IEICE Electronics Express 7, no. 15 (2010): 1119–24. http://dx.doi.org/10.1587/elex.7.1119.

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Monga, Kanika, Nitin Chaturvedi, and S. Gurunarayanan. "Energy-efficient data retention in D flip-flops using STT-MTJ." Circuit World 46, no. 4 (June 20, 2020): 229–41. http://dx.doi.org/10.1108/cw-09-2018-0073.

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Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

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Saf’yannikov, N. M., and P. N. Bondarenko. "Flip-flop device with state actuation." Russian Microelectronics 38, no. 3 (May 2009): 219–22. http://dx.doi.org/10.1134/s1063739709030093.

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30

Ashis Kumar Mandal. "All-optical Frequency Divider using TOAD based D-Flip-Flop." January 2021 7, no. 01 (January 29, 2021): 152–57. http://dx.doi.org/10.46501/ijmtst070133.

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From the last few decades the optical communication has been established as much easier process than electrical communication. Many optical proposed circuits have already been suggested in many fields in support of this. The optical communication circuits demand frequency dividers capable of operating well above 10 GHz. Here, an all-optical frequency divider using terahertz optical asymmetric demultiplexer (TOAD) based D-flip-flop is proposed in the optical domain in a configuration exactly like the standard electronic setup. It presents a high-speed flip-flop-based frequency divider incorporating a new high-speed latch topology with satisfactory performance. The proposed all-optical frequency division scheme has been theoretically demonstrated in this paper. In this scheme the input and output binary digits are expressed as the presence (1) and the absence (0) of the light pulses. The performance of this proposed optical realization is evaluated by numerical simulation that confirms its feasibility in terms of the choice of the critical parameters.

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HU, YINGBO, and RUNDE ZHOU. "LOW CLOCK-SWING TSPC FLIP-FLOPS FOR LOW-POWER APPLICATIONS." Journal of Circuits, Systems and Computers 18, no. 01 (February 2009): 121–31. http://dx.doi.org/10.1142/s0218126609004971.

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In this paper, two types of Low Clock-Swing True Single Phase Clock (TSPC) Flip-Flops suitable for low-power applications are proposed. One is Low Clock-Swing Edge-Triggered TSPC Flip-Flop (LCSETTFF), constructed with a negative TSPC split out latch and a positive TSPC split out latch. The other is Low Clock-Swing Pulse-Triggered TSPC Flip-Flop (LCSPTTFF), developed in several styles. A double-edge triggered pulse generator is also developed for LCSPTTFF. With low threshold voltage clock transistors adopted, great power efficiency can be obtained in the clock network. Both types of Flip-Flops have advantages of simple structure, low power and much lower clock network power dissipation. All proposed circuits are simulated in HSPICE with 0.18 μm CMOS technology. Simulation results show that the power of LCSETTFF can be reduced by 42%, while the power dissipation, Power-Delay Product (PDP) and Area-Power-Delay Product (APDP) of LCSPTTFF can be reduced by 45–60%, 11–27% and 58–65%, respectively. In addition, the power consumptions of clock network of LCSPTTFF and LCSETTFF are estimated to be reduced by 78% and 56%, respectively, compared with conventional Flip-Flops.

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MONTEIRO, JOSÉ, SRINIVAS DEVADAS, and ABHIJIT GHOSH. "RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER." International Journal of High Speed Electronics and Systems 07, no. 02 (June 1996): 323–40. http://dx.doi.org/10.1142/s0129156496000141.

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Switching activity is a primary cause of power dissipation in combinational and sequential circuits. In this paper, we present a retiming method that targets the power dissipation of a sequential circuit by reducing the switching activity of nodes driving large capacitive loads. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous sequential circuit can be significantly less than the activity at the flip-flop inputs. The method automatically determines positions of flip-flops in the circuit so as to heuristically minimize weighted switching activities summed over all the gates and flip-flops in the circuit. We extend this method to minimize power dissipation with a specified clock period. For this work we need to obtain efficiently an estimation of the switching activity of every node in the circuit. We give an exact method of estimating power in pipelined sequential circuits that accurately models the correlation between the vectors applied to the combinational logic of the circuit. This method is significantly more efficient than methods based on solving Chapman–Kolmogorov equations. Experimental results are presented on a variety of circuits.

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33

Jin-Woo Han, Jae-Hyuk Ahn, and Yang-Kyu Choi. "FinFACT—Fin Flip-Flop Actuated Channel Transistor." IEEE Electron Device Letters 31, no. 7 (July 2010): 764–66. http://dx.doi.org/10.1109/led.2010.2048093.

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34

Bhattacharjee, Pritam, and Alak Majumder. "A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application." Journal of Circuits, Systems and Computers 28, no. 07 (June 27, 2019): 1950108. http://dx.doi.org/10.1142/s0218126619501081.

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Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

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35

Zhao, Xianghong, Longhua Ma, Hongye Su, Jieyu Zhao, and Weiming Cai. "High-Performance Current-Mode Logic Ternary D Flip-Flop Based on Bipolar Complementary Metal Oxide Semiconductor." Journal of Nanoelectronics and Optoelectronics 16, no. 4 (April 1, 2021): 528–33. http://dx.doi.org/10.1166/jno.2021.2976.

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In this paper, a simple-structured and high-performance current-mode logic (CML) ternary D flip-flop based on BiCMOS is proposed. It combines both advantages of BiCMOS and CML circuits, which is with much more high-speed, strong-drive and anti-interference abilities. Utilizing TSMC 180 nm process, results of simulations carried out by HSPICE illustrate the proposed circuit not only has correct logic function, but also gains improvements of 95.6~98.4% in average D-Q delay and 16.2%~70.4 in PDP compared with advanced ternary D flip-flop. When compared at the same information transmission speed, proposed circuit is more competitive. Furthermore, it can perform up to high frequency of 15 GHz and drive heavier load. All the results prove that proposed circuit is high-performance and very suitable for high-speed and high-frequency applications.

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36

Kaplan, A. M., G. P. Agrawal, and D. N. Maywar. "All-optical flip-flop operation of VCSOA." Electronics Letters 45, no. 2 (2009): 127. http://dx.doi.org/10.1049/el:20093124.

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37

Lakys, Y., W. Zhao, J. O. Klein, and C. Chappert. "Low power, high reliability magnetic flip-flop." Electronics Letters 46, no. 22 (2010): 1493. http://dx.doi.org/10.1049/el.2010.2039.

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38

Jian Zhou, Jin Liu, and Dian Zhou. "Reduced setup time static D flip-flop." Electronics Letters 37, no. 5 (2001): 279. http://dx.doi.org/10.1049/el:20010197.

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39

Han, Seon-Ho, Yong-Sik Youn, Cheon-Soo Kim, Hyun-Ku Yu, and Mun-Yang Park. "Prescaler using complementary clocking dynamic flip-flop." Electronics Letters 39, no. 9 (2003): 709. http://dx.doi.org/10.1049/el:20030478.

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40

Kulkarni, G., V. Naware, and M. Govindarajan. "Burst error generator using flip-flop metastability." Electronics Letters 35, no. 2 (1999): 108. http://dx.doi.org/10.1049/el:19990108.

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41

ELGAMEL, M. A. "Noise Metrics in Flip-Flop Designs." IEICE Transactions on Information and Systems E88-D, no. 7 (July 1, 2005): 1501–5. http://dx.doi.org/10.1093/ietisy/e88-d.7.1501.

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42

Wu, Shi De, Jin Feng Yang, and Ze Yu Ma. "A New Regulated Power Supply Design." Applied Mechanics and Materials 380-384 (August 2013): 3031–34. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3031.

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Based on the principle of electronic transformers, a new type of the power supply is designed, and the factors affecting the switching frequency are given. The feedback mechanism of the new power supply is analyzed in detail. Whats more, the pulse width modulation which controls switch tube adopts the RS flip-flop PWM. Finally based on the TL431, a 50W regulated power supply is design, which has a simple structure, small size, and low cost.

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43

Natori, K. "Sensitivity of dynamic MOS flip-flop sense amplifiers." IEEE Transactions on Electron Devices 33, no. 4 (April 1986): 482–88. http://dx.doi.org/10.1109/t-ed.1986.22516.

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44

Shaw, D. I., J. C. Bennett, and A. M. Clements. "Analysis of ‘D type’ flip-flop frequency changers." Electronics Letters 26, no. 24 (1990): 1995. http://dx.doi.org/10.1049/el:19901290.

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45

Cisneros-Sinencio, Luis F., Alejandro Diaz-Sanchez, and Jaime Ramirez-Angulo. "FGMOS flip-flop for low-power signal processing." International Journal of Electronics 100, no. 12 (December 2013): 1683–89. http://dx.doi.org/10.1080/21681724.2013.766994.

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46

Lee, M. "Design of CMOS constant switching current flip-flop." Electronics Letters 47, no. 16 (2011): 909. http://dx.doi.org/10.1049/el.2011.0502.

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47

Wu, X., and J. Wei. "CMOS edge-triggered flip-flop using one latch." Electronics Letters 34, no. 16 (1998): 1581. http://dx.doi.org/10.1049/el:19981095.

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48

Haomin, Wu, and Zhuang Nan. "Research into ternary edge-triggered JKL flip-flop." Journal of Electronics (China) 8, no. 3 (July 1991): 268–75. http://dx.doi.org/10.1007/bf02778378.

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49

Namba, Kazuteru, Takashi Katagiri, and Hideo Ito. "Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop." Journal of Electronic Testing 29, no. 4 (July 19, 2013): 545–54. http://dx.doi.org/10.1007/s10836-013-5392-x.

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50

Weizhong Wang and Haiyan Gong. "Sense amplifier based RADHARD flip flop design." IEEE Transactions on Nuclear Science 51, no. 6 (December 2004): 3811–15. http://dx.doi.org/10.1109/tns.2004.839149.

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