Journal articles: 'Flash Memory Device'

1

Abdullah, Dhuha, and Reyath Mahmood. "Design Flash Memory Programmer Device." AL-Rafidain Journal of Computer Sciences and Mathematics 3, no. 1 (July 1, 2006): 55–83. http://dx.doi.org/10.33899/csmj.2006.164045.

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Alahmadi, Abdulhadi, and Tae Sun Chung. "RSLSP: An Effective Recovery Scheme for Flash Memory Leveraging Shadow Paging." Electronics 11, no. 24 (December 10, 2022): 4126. http://dx.doi.org/10.3390/electronics11244126.

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The flash storage is a non-volatile semiconductor device that is constantly powered and has several advantages such as small size, lower power consumption, fast access, convenient portability, heat dissipation, shock resistance, data retention next to a power off, and random access. Flash memory is presently being incorporated with distinct embedded system devices such as with digital cameras, smart phones, personal digital assistants (PDA), and sensor devices. Nevertheless, a flash memory entails special features such as “erase-before-write” and “wear-leveling”, an FTL (flash translation layer) upon the software layer should be included. Although, the power off recovery plays a significant role in portable devices, most FTL algorithms did not consider the power off recovery scheme. In this paper, we proposed an effective scheme for the recovery of flash memory leveraging the shadow paging concept for storage devices using flash memory. To combat the sudden power off problem, the suggested RSLSP approach saves and keeps the map block data as a combination of two tables, i.e., first is the original block and the second block is a replica for the original one. Our proposed strategy not only improves the capacity of a flash memory device as compared to the state-of-the-art schemes suggested in the literature, but is also compatible with the existing FTL-based schemes.

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Han, Hoonhee, Seokmin Jang, Duho Kim, Taeheun Kim, Hyeoncheol Cho, Heedam Shin, and Changhwan Choi. "Memory Characteristics of Thin Film Transistor with Catalytic Metal Layer Induced Crystallized Indium-Gallium-Zinc-Oxide (IGZO) Channel." Electronics 11, no. 1 (December 24, 2021): 53. http://dx.doi.org/10.3390/electronics11010053.

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The memory characteristics of a flash memory device using c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) thin film as a channel material were demonstrated. The CAAC-IGZO thin films can replace the current poly-silicon channel, which has reduced mobility because of grain-induced degradation. The CAAC-IGZO thin films were achieved using a tantalum catalyst layer with annealing. A thin film transistor (TFT) with SiO2/Si3N4/Al2O3 and CAAC-IGZO thin films, where Al2O3 was used for the tunneling layer, was evaluated for a flash memory application and compared with a device using an amorphous IGZO (a-IGZO) channel. A source and drain using indium-tin oxide and aluminum were also evaluated for TFT flash memory devices with crystallized and amorphous channel materials. Compared with the a-IGZO device, higher on-current (Ion), improved field effect carrier mobility (μFE), a lower body trap (Nss), a wider memory window (ΔVth), and better retention and endurance characteristics were attained using the CAAC-IGZO device.

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Kostadinov, Hristo, and Nikolai Manev. "Integer Codes Correcting Asymmetric Errors in Nand Flash Memory." Mathematics 9, no. 11 (June 1, 2021): 1269. http://dx.doi.org/10.3390/math9111269.

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Memory devices based on floating-gate transistor have recently become dominant technology for non-volatile storage devices like USB flash drives, memory cards, solid-state disks, etc. In contrast to many communication channels, the errors observed in flash memory device use are not random but of special, mainly asymmetric, type. Integer codes which have proved their efficiency in many cases with asymmetric errors can be applied successfully to flash memory devices, too. This paper presents a new construction and integer codes over a ring of integers modulo A=2n+1 capable of correcting single errors of type (1,2),(±1,±2), or (1,2,3) that are typical for flash memory devices. The construction is based on the use of cyclotomic cosets of 2 modulo A. The parity-check matrices of the codes are listed for n≤10.

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Tsoukalas, Dimitris, and Emanuele Verrelli. "Inorganic Nanoparticles for either Charge Storage or Memristance Modulation." Advances in Science and Technology 77 (September 2012): 196–204. http://dx.doi.org/10.4028/www.scientific.net/ast.77.196.

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We present prototype memory devices using metallic and metal oxide nanoparticles obtained by a physical deposition technique. The two memory device examples demonstrated concern the use of platinum nanoparticles for flash-type memories and the use of titanium oxide nanoparticles for resistive memories. Both approaches give interesting device memory properties with resistive memories being still in an early exploratory phase.

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Xu, Guangxia, Lingling Ren, and Yanbing Liu. "Flash-Aware Page Replacement Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/136246.

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Due to the limited main memory resource of consumer electronics equipped with NAND flash memory as storage device, an efficient page replacement algorithm called FAPRA is proposed for NAND flash memory in the light of its inherent characteristics. FAPRA introduces an efficient victim page selection scheme taking into account the benefit-to-cost ratio for evicting each victim page candidate and the combined recency and frequency value, as well as the erase count of the block to which each page belongs. Since the dirty victim page often contains clean data that exist in both the main memory and the NAND flash memory based storage device, FAPRA only writes the dirty data within the victim page back to the NAND flash memory based storage device in order to reduce the redundant write operations. We conduct a series of trace-driven simulations and experimental results show that our proposed FAPRA algorithm outperforms the state-of-the-art algorithms in terms of page hit ratio, the number of write operations, runtime, and the degree of wear leveling.

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Poudel, Prawar, Biswajit Ray, and Aleksandar Milenkovic. "Microcontroller Fingerprinting Using Partially Erased NOR Flash Memory Cells." ACM Transactions on Embedded Computing Systems 20, no. 3 (April 2021): 1–23. http://dx.doi.org/10.1145/3448271.

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Electronic device fingerprints, unique bit vectors extracted from device's physical properties, are used to differentiate between instances of functionally identical devices. This article introduces a new technique that extracts fingerprints from unique properties of partially erased NOR flash memory cells in modern microcontrollers. NOR flash memories integrated in modern systems-on-a-chip typically hold firmware and read-only data, but they are increasingly in-system-programmable, allowing designers to erase and program them during normal operation. The proposed technique leverages partial erase operations of flash memory segments that bring them into the state that exposes physical properties of the flash memory cells through a digital interface. These properties reflect semiconductor process variations and defects that are unique to each microcontroller or a flash memory segment within a microcontroller. The article explores threshold voltage variation in NOR flash memory cells for generating fingerprints and describes an algorithm for extracting fingerprints. The experimental evaluation utilizing a family of commercial microcontrollers demonstrates that the proposed technique is cost-effective, robust, and resilient to changes in voltage and temperature as well as to aging effects.

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Huang, Bai Yi. "A New Write Caching Algorithm for Solid State Disks." Advanced Materials Research 341-342 (September 2011): 700–704. http://dx.doi.org/10.4028/www.scientific.net/amr.341-342.700.

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Flash-based solid state disks (SSD) is a performance based data storage technology that optimizes the use of flash-based technology to implement its data storage capabilities compared with mechanically available data storage technologies. It has been argued in theory and practice that SSD devices are better performers compared with mechanical devices. To improve the efficiency of a flash memory SSD device, it is important for it to be designed to be computationally support parallel operations.

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Wang, Lei, CiHui Yang, Jing Wen, and Shan Gai. "Emerging Nonvolatile Memories to Go Beyond Scaling Limits of Conventional CMOS Nanodevices." Journal of Nanomaterials 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/927696.

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Continuous dimensional scaling of the CMOS technology, along with its cost reduction, has rendered Flash memory as one of the most promising nonvolatile memory candidates during the last decade. With the Flash memory technology inevitably approaching its fundamental limits, more advanced storage nanodevices, which can probably overcome the scaling limits of Flash memory, are being explored, bringing about a series of new paradigms such as FeRAM, MRAM, PCRAM, and ReRAM. These devices have indeed exhibited better scaling capability than Flash memory while also facing their respective physical drawbacks. The consequent tradeoffs therefore drive the information storage device technology towards further advancement; as a result, new types of nonvolatile memories, including carbon memory, Mott memory, macromolecular memory, and molecular memory have been proposed. In this paper, the nanomaterials used for these four emerging types of memories and the physical principles behind the writing and reading methods in each case are discussed, along with their respective merits and drawbacks when compared with conventional nonvolatile memories. The potential applications of each technology are also briefly assessed.

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Jung, Sang-Goo, and Jong-Ho Lee. "Flash Memory Device with `I' Shape Floating Gate for Sub-70 nm NAND Flash Memory." Japanese Journal of Applied Physics 45, No. 45 (November 10, 2006): L1200—L1202. http://dx.doi.org/10.1143/jjap.45.l1200.

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11

Jackson, Riley, Jonathan Gresl, and Ramon Lawrence. "Efficient External Sorting for Memory-Constrained Embedded Devices with Flash Memory." ACM Transactions on Embedded Computing Systems 20, no. 4 (June 2021): 1–21. http://dx.doi.org/10.1145/3446976.

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Embedded devices are ubiquitous in areas of industrial and environmental monitoring, health and safety, and consumer appliances. A common use case is data collection, processing, and performing actions based on data analysis. Although many Internet of Things (IoT) applications use the embedded device simply for data collection, there are benefits to having more data processing done closer to data collection to reduce network transmissions and power usage and provide faster response. This work implements and evaluates algorithms for sorting data on embedded devices with specific focus on the smallest memory devices. In devices with less than 4 KB of available RAM, the standard external merge sort algorithm has limited application as it requires a minimum of three memory buffers and is not flash-aware. The contribution is a memory-optimized external sorting algorithm called no output buffer sort (NOBsort) that reduces the minimum memory required for sorting, has excellent performance for sorted or near-sorted data, and sorts on external memory such as SD cards or raw flash chips. When sorting large datasets, no output buffer sort reduces I/O and execution time by between 20% to 35% compared to standard external merge sort.

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Holt, Joshua S., Karsten Beckmann, Zahiruddin Alamgir, Jean Yang-Scharlotta, and Nathaniel C. Cady. "Effect of Displacement Damage on Tantalum Oxide Resistive Memory." MRS Advances 2, no. 52 (2017): 3011–17. http://dx.doi.org/10.1557/adv.2017.422.

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ABSTRACTThe radiation environment of space poses a challenge for electronic systems, in particular flash memory, which contains multiple radiation-sensitive parts. Resistive memory (RRAM) devices have the potential to replace flash memory, functioning as an inherently radiation resistant memory device. Several studies indicate significant radiation resistance in RRAM devices to a broad range of radiation types and doses. In this study, we focus on the effect of displacement damage on tantalum oxide-based RRAM devices, as this form of damage is likely a worst-case scenario. An Ar+ (170 keV) ion beam was used to minimize any contribution from ionization damage, maximizing the effect of displacement damage. Fluence levels were chosen to generate enough oxygen vacancies such that devices in the high resistance state (HRS) would likely switch to the low resistance state (LRS). More than half of devices tested at the highest fluence level (1.43E13 ions/cm2) switched from HRS to LRS. The devices were then switched for 50 set/reset cycles, after which the radiation-induced resistance shift disappeared. These results suggest that device switching may mitigate radiation damage by accelerating oxygen vacancy-interstitial recombination.

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Sassani (Sarrafpour), Bahman A., Mohammed Alkorbi, Noreen Jamil, M. Asif Naeem, and Farhaan Mirza. "Evaluating Encryption Algorithms for Sensitive Data Using Different Storage Devices." Scientific Programming 2020 (May 31, 2020): 1–9. http://dx.doi.org/10.1155/2020/6132312.

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Sensitive data need to be protected from being stolen and read by unauthorized persons regardless of whether the data are stored in hard drives, flash memory, laptops, desktops, and other storage devices. In an enterprise environment where sensitive data is stored on storage devices, such as financial or military data, encryption is used in the storage device to ensure data confidentiality. Nowadays, the SSD-based NAND storage devices are favored over HDD and SSHD to store data because they offer increased performance and reduced access latency to the client. In this paper, the performance of different symmetric encryption algorithms is evaluated on HDD, SSHD, and SSD-based NAND MLC flash memory using two different storage encryption software. Based on the experiments we carried out, Advanced Encryption Standard (AES) algorithm on HDD outperforms Serpent and Twofish algorithms in terms of random read speed and write speed (both sequentially and randomly), whereas Twofish algorithm is slightly faster than AES in sequential reading on SSHD and SSD-based NAND MLC flash memory. By conducting full range of evaluative tests across HDD, SSHD, and SSD, our experimental results can give better idea for the storage consumers to determine which kind of storage device and encryption algorithm is suitable for their purposes. This will give them an opportunity to continuously achieve the best performance of the storage device and secure their sensitive data.

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Dâna, Aykutlu, Imran Akca, Atilla Aydinli, Rasit Turan, and Terje G. Finstad. "A Figure of Merit for Optimization of Nanocrystal Flash Memory Design." Journal of Nanoscience and Nanotechnology 8, no. 2 (February 1, 2008): 510–17. http://dx.doi.org/10.1166/jnn.2008.a156.

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Nanocrystals can be used as storage media for carriers in flash memories. The performance of a nanocrystal flash memory depends critically on the choice of nanocrystal size and density as well as on the choice of tunnel dielectric properties. The performance of a nanocrystal memory device can be expressed in terms of write/erase speed, carrier retention time and cycling durability. We present a model that describes the charge/discharge dynamics of nanocrystal flash memories and calculate the effect of nanocrystal, gate, tunnel dielectric and substrate properties on device performance. The model assumes charge storage in quantized energy levels of nanocrystals. Effect of temperature is included implicitly in the model through perturbation of the substrate minority carrier concentration and Fermi level. Because a large number of variables affect these performance measures, in order to compare various designs, a figure of merit that measures the device performance in terms of design parameters is defined as a function of write/erase/discharge times which are calculated using the theoretical model. The effects of nanocrystal size and density, gate work function, substrate doping, control and tunnel dielectric properties and device geometry on the device performance are evaluated through the figure of merit. Experimental data showing agreement of the theoretical model with the measurement results are presented for devices that has PECVD grown germanium nanocrystals as the storage media.

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VonBergen, Wade, and Madhu Basude. "A High Temp standalone 4MByte Flash memory with SPI Interface for 210C applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2012, HITEC (January 1, 2012): 000066–71. http://dx.doi.org/10.4071/hitec-2012-tp11.

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This paper covers the internal architecture, testability & performance characterization of Texas Instruments ™ High-Temp 210C 4MByte standalone Flash storage device. It will be available in a 14-pin ceramic dual Flat pack package as well as a Known Good Die (KGD) option. The device is manufactured in TI's 180nm 1.8V flash process with 3.3V IOs. The design implements 8 banks of flash organized into 2M × 16 bits surrounded by a SPI controller. The SPI controller interfaces asynchronously with an internal flash controller. The flash controller is clocked by FCLK, and controls the flash charge pump to access & operate the flash to program, read, erase, validate etc. The SPI controller is responsible for translating and executing the high level SPI protocol commands to the internal flash controller & its registers. A simple and flexible protocol was developed to access the flash array via the SPI supporting various commands and configuration capabilities. Testability of critical parameters for reliable 210C flash operation is ensured with the implementation of an internal test port accessible through a parallel interface (for TI Internal use only). The test port, and a SPI initiated BIST controller are used to provide full & comprehensive characterization of the flash bit cell array, as well as the flash-pump across temperature & frequencies. The form factor, size, and pin out of this flash device is primarily focused on data logging for narrow & space limited extreme harsh environments such as the down-hole drilling industry.

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Alahmadi, Abdulhadi, and Tae Sun Chung. "Crash Recovery Techniques for Flash Storage Devices Leveraging Flash Translation Layer: A Review." Electronics 12, no. 6 (March 16, 2023): 1422. http://dx.doi.org/10.3390/electronics12061422.

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The flash storage is a type of nonvolatile semiconductor device that is operated continuously and has been substituting the hard disk or secondary memory in several storage markets, such as PC/laptop computers, mobile devices, and is also used as an enterprise server. Moreover, it offers a number of benefits, including compact size, low power consumption, quick access, easy mobility, heat dissipation, shock tolerance, data preservation during a power outage, and random access. Different embedded system products, including digital cameras, smartphones, personal digital assistants (PDA), along with sensor devices, are currently integrating flash memory. However, as flash memory requires unique capabilities such as “erase before write” as well as “wear-leveling”, a FTL (flash translation layer) is added to the software layer. The FTL software module overcomes the problem of performance that arises from the erase before write operation and wear-leveling, i.e., flash memory does not allow for an in-place update, and therefore a block must be erased prior to overwriting upon the present data. In the meantime, flash storage devices face challenges of failure and thus they must be able to recover metadata (as well as address mapping information), including data after a crash. The FTL layer is responsible for and intended for use in crash recovery. Although the power-off recovery technique is essential for portable devices, most FTL algorithms do not take this into account. In this paper, we review various schemes of crash recovery leveraging FTL for flash storage devices. We illustrate the classification of the FTL algorithms. Moreover, we also discuss the various metrics and parameters evaluated for comparison with other approaches by each scheme, along with the flash type. In addition, we made an analysis of the FTL schemes. We also describe meaningful considerations which play a critical role in the design development for power-off recovery employing FTL.

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Barrett, Michael. "Gone in a Flash." New Electronics 52, no. 8 (April 23, 2019): 30–31. http://dx.doi.org/10.12968/s0047-9624(22)61007-1.

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Yang, Yanhua, Jing-Cheng Xia, Youxuan Zheng, Yingzhong Shen, and Gaozhang Gou. "Synthesis and non-volatile electrical memory characteristics of triphenylamine-based polyimides with flexibility segments." New Journal of Chemistry 42, no. 23 (2018): 19008–19. http://dx.doi.org/10.1039/c8nj04103b.

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Two triphenylamine-based polyimides (PI(TPA-PMDA) and PI(TPA-BPDA)) containing a flexibility segments were prepared. The memory device of ITO/PI(TPA-PMDA)/Al exhibited write-once read-many-times (WORM) memory behavior, however, the memory device of PI(TPA-BPDA) demonstrated flash-type memory characteristics.

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Naqi, Muhammad, Nayoung Kwon, Sung Jung, Pavan Pujar, Hae Cho, Yong Cho, Hyung Cho, Byungkwon Lim, and Sunkook Kim. "High-Performance Non-Volatile InGaZnO Based Flash Memory Device Embedded with a Monolayer Au Nanoparticles." Nanomaterials 11, no. 5 (April 24, 2021): 1101. http://dx.doi.org/10.3390/nano11051101.

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Non-volatile memory (NVM) devices based on three-terminal thin-film transistors (TFTs) have gained extensive interest in memory applications due to their high retained characteristics, good scalability, and high charge storage capacity. Herein, we report a low-temperature (<100 °C) processed top-gate TFT-type NVM device using indium gallium zinc oxide (IGZO) semiconductor with monolayer gold nanoparticles (AuNPs) as a floating gate layer to obtain reliable memory operations. The proposed NVM device exhibits a high memory window (ΔVth) of 13.7 V when it sweeps from −20 V to +20 V back and forth. Additionally, the material characteristics of the monolayer AuNPs (floating gate layer) and IGZO film (semiconductor layer) are confirmed using transmission electronic microscopy (TEM), atomic force microscopy (AFM), and x-ray photoelectron spectroscopy (XPS) techniques. The memory operations in terms of endurance and retention are obtained, revealing highly stable endurance properties of the device up to 100 P/E cycles by applying pulses (±20 V, duration of 100 ms) and reliable retention time up to 104 s. The proposed NVM device, owing to the properties of large memory window, stable endurance, and high retention time, enables an excellent approach in futuristic non-volatile memory technology.

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Zhevnyak, O. G., V. M. Borzdov, A. V. Borzdov, and A. N. Petlitsky. "Monte Carlo Simulation of Flash Memory Elements’ Electrophysical Parameters." Devices and Methods of Measurements 13, no. 4 (December 22, 2022): 276–80. http://dx.doi.org/10.21122/2220-9506-2022-13-4-276-280.

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Operation of modern flash memory elements is based on electron transport processes in the channel of silicon MOSFETs with floating gate. The aim of this work was calculation of electron mobility and study of the influence of phonon and ionized impurity scattering mechanisms on the mobility, as well as calculation of parasitic tunneling current and channel current in the conductive channel of flash memory element. Numerical simulation during the design stage of flash memory element allows working out guidelines for optimization of device parameters defining its performance and reliability.In the work such electrophysical parameters, characterizing electron transport, as mobility and average electron energy, as well as tunneling current and current in the channel of the flash memory element are studied via the numerical simulation by means of Monte Carlo method. Influence of phonon and ionized impurity scattering processes on electron mobility in the channel has been analyzed. It is shown that in the vicinity of drain region a sufficient decrease of electron mobility defined by phonon scattering processes occurs and the growth of parasitic tunneling current is observed which have a negative influence on device characteristics.The developed simulation program may be used in computer-aided design of flash memory elements for the purpose of their structure optimization and improvement of their electrical characteristics.

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Tsoukalas, D. "From silicon to organic nanoparticle memory devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1905 (October 28, 2009): 4169–79. http://dx.doi.org/10.1098/rsta.2008.0280.

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After introducing the operational principle of nanoparticle memory devices, their current status in silicon technology is briefly presented in this work. The discussion then focuses on hybrid technologies, where silicon and organic materials have been combined together in a nanoparticle memory device, and finally concludes with the recent development of organic nanoparticle memories. The review is focused on the nanoparticle memory concept as an extension of the current flash memory device. Organic nanoparticle memories are at a very early stage of research and have not yet found applications. When this happens, it is expected that they will not directly compete with mature silicon technology but will find their own areas of application.

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Li, Chao, Bo Lei, Wendy Fan, Daihua Zhang, M. Meyyappan, and Chongwu Zhou. "Molecular Memory Based on Nanowire–Molecular Wire Heterostructures." Journal of Nanoscience and Nanotechnology 7, no. 1 (January 1, 2007): 138–50. http://dx.doi.org/10.1166/jnn.2007.18011.

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This article reviews the recent research of molecular memory based on self-assembled nanowire–molecular wire heterostructures. These devices exploit a novel concept of using redox-active molecules as charge storage flash nodes for nanowire transistors, and thus boast many advantages such as room-temperature processing and nanoscale device area. Various key elements of this technology will be reviewed, including the synthesis of the nanowires and molecular wires, and fabrication and characterization of the molecular memory devices. In particular, multilevel memory has been demonstrated using In2O3 nanowires with self-assembled Fe-bis(terpyridine) molecules, which serve to multiple the charge storage density without increasing the device size. Furthermore, in-depth studies on memory devices made with different molecules or with different functionalization techniques will be reviewed and analyzed. These devices represent a conceptual breakthrough in molecular memory and may work as building blocks for future beyond-CMOS nanoelectronic circuits.

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Tang, X., X. Baie, J. P. Colinge, A. Crahay, B. Katschmarsyj, V. Scheuren, D. Spôte, N. Reckinger, F. Van de Wiele, and V. Bayot. "Self-aligned silicon-on-insulator nano flash memory device." Solid-State Electronics 44, no. 12 (December 2000): 2259–64. http://dx.doi.org/10.1016/s0038-1101(00)00221-5.

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Vladimirov, S., and D. Berestovoy. "IoT Device Identification Protocol based on Degraded Flash Memory." Telecom IT 8, no. 2 (June 2020): 20–31. http://dx.doi.org/10.31854/2307-1303-2020-8-2-20-31.

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Research subject. The article presents a protocol for identifying IoT devices developed by the authors and the results of its testing. Method. Simulation was performed to determine the probabilistic charac-teristics of 8-bit error-correcting codes. The principles of their coding and decoding are considered. Core results. The features of the developed identification protocol when transmitting packets over the transport protocols TCP and UDP are determined. Practical relevance. The application of the devel-oped protocol for identifying network devices of the Internet of things in local and global communication networks is proposed.

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Marent, A., T. Nowozin, M. Geller, and D. Bimberg. "The QD-Flash: a quantum dot-based memory device." Semiconductor Science and Technology 26, no. 1 (December 9, 2010): 014026. http://dx.doi.org/10.1088/0268-1242/26/1/014026.

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Wu, Chien-Hung, Song-Nian Kuo, Kow-Ming Chang, Yi-Ming Chen, Yu-Xin Zhang, Ni Xu, Wu-Yang Liu, and Albert Chin. "Investigation of Microwave Annealing on Resistive Random Access Memory Device with Atmospheric Pressure Plasma Enhanced Chemical Vapor Deposition Deposited IGZO Layer." Journal of Nanoscience and Nanotechnology 20, no. 7 (July 1, 2020): 4244–47. http://dx.doi.org/10.1166/jnn.2020.17561.

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Non-volatile memory (NVM) is essential in almost every consumer electronic products. The most prevalent NVM used nowadays is flash memory (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Letters, 9(1), p.526). However, some bottlenecks of flash memory have been identified, such as high operation voltage, low operation speed, and poor retention time. Resistive random access memory (RRAM) is considered to be the most promising one to become the next generation NVM device since its simple structure, fast program/erase speed, and low power consumption. In this experiment, the RRAM device is fabricated, and its IGZO (memory) layer is deposited with AP-PECVD technique which can reduce cost of the process. Microwave annealing (MWA) is used to enhance electrical characteristics of the RRAM device (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In–Ga– Zn–O TFT. Thin Solid Films, 520, pp.1489–1494). Experiment results show that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics under bipolar operation, all forming/set/reset voltage for RRAM device is simultaneously lowered.

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Hong, Yunshu, Yiyu Pan, and Zhongfu Xu. "Based on the comparison with other kinds of storage devices to predict the future development of STT-MRAM." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 197–204. http://dx.doi.org/10.54097/hset.v46i.7704.

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Now day with the development of technology, our electronic device is upgraded. Which will bring more data to storage. This causes the development of memory device. Now we already have SRAM flash memory are being widely used. But as the we use it for long time, the disadvantage of these memory device is shown, therefore, a new memory device --STT-MRAM are been created, which is we are going to introduce, we will show you how it basic structure which is MRAM work and the mechanism of the magnetic tunnel junction (the part it storage messages) and how spin electron influence the MTJ to make it more effective. Follow that we will list and make a comparison of the advantage of STT-MRAM and the disadvantage of flash memory, SRAM and DRAM to show the potential of the STT-MRAM. After mentioned about the benefit of STT-MRAM, we will mention about the disadvantages of it such as hard to maintain high thermal stability barrier. We will give the possible solutions follow that. This text intended to introduce this new type of memory device-STT-MRAM and show the potential of it in the future.

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Sharma, Anju, Preeth Sivakumar, Andrew Feigel, In Tae Bae, Lawrence P. Lehman, Joseph Gregor, James Cash, and Joseph Kolly. "Effects of x-ray exposure on NOR and NAND flash memories during high-resolution 2D and 3D x-ray inspection." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000660–65. http://dx.doi.org/10.4071/isom-2016-thp53.

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Abstract In this paper, we present a detailed study on the effects of x-ray exposure on data corruption in commercially available NOR and NAND flash memory devices during x-ray inspection with a high-resolution Phoenix Nanomex system from GE. We investigated role of the x-ray tube voltage, tube current, device orientation, x-ray filters and photon energy. We explored the low exposure regime in detail when the first byte errors start occurring and also determined the absorbed dose for 100% byte errors. No data corruption was observed after the normal 2D x-ray inspection and CT scans of the NOR and NAND flash memory devices under study. However, increase in the tube voltage, tube current and/or the x-ray beam size resulted in byte errors which increased exponentially with the exposure time. The byte error rate was found to be much more sensitive to the tube voltage than the tube current. It was also affected by the device orientation with respect to the x-ray beam. The NAND flash memories were found to be more susceptible to data corruption from x-ray exposure than the NOR devices examined in this work. Some NOR devices were irradiated with the monochromatic x-rays from the CHESS synchrotron facility at Cornell University. Of all the photon energies used in this study, 12 keV x-ray irradiation resulted in the highest byte error rate. In this paper, we thus present a direct proof that it is the low-energy photon absorption that plays a major role in introducing bit errors in flash memories. Commonly available low-energy x-ray filters such as Cu and Al foils were found to be effective in preventing data corruption in such devices for long exposure time. Use of lower tube voltage, lower tube current, smaller x-ray spot size, short exposure time and low-energy x-ray filters, is recommended to prevent data corruption during 2D and 3D x-ray inspection of flash memory devices and other semiconductor devices in general.

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Yang, Seung Dong, Ho Jin Yun, Kwang Seok Jeong, Yu Mi Kim, Sang Youl Lee, Jae Sub Oh, Hi Deok Lee, and Ga Won Lee. "The analysis of 3-Level Charge Pumping in SOHOS Flash Memory." Advanced Materials Research 658 (January 2013): 658–61. http://dx.doi.org/10.4028/www.scientific.net/amr.658.658.

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This paper discusses the 3-level charge pumping method in planar-type Silicon-Oxide-High-k-Oxid e-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason for degradation of data retention properties. In the CP thechnique, a pulse is applied to the gate of the MOSFET which alternately fills the traps withe electrons and holes, thereby causing a recombination current Icp to flow in the substrate. A 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

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Mativenga, Ronnie, Prince Hamandawana, Tae-Sun Chung, and Jongik Kim. "FTRM: A Cache-Based Fault Tolerant Recovery Mechanism for Multi-Channel Flash Devices." Electronics 9, no. 10 (September 27, 2020): 1581. http://dx.doi.org/10.3390/electronics9101581.

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Flash memory prevalence has reached greater extents with its performance and compactness capabilities. This enables it to be easily adopted as storage media in various portable devices which includes smart watches, cell-phones, drones, and in-vehicle infotainment systems to mention but a few. To support large flash storage in such portable devices, existing flash translation layers (FTLs) employ a cache mapping table (CMT), which contains a small portion of logical page number to physical page number (LPN-PPN) mappings. For robustness, it is of importance to consider the CMT reconstruction mechanisms during system recovery. Currently, existing approaches cannot overcome the performance penalty after experiencing unexpected power failure. This is due to the disregard of the delay caused by inconsistencies between the cached page-mapping entries in RAM and their corresponding mapping pages in flash storage. Furthermore, how to select proper pages for reconstructing the CMT when rebooting a device needs to be revisited. In this study we address these problems and propose a fault tolerant power-failure recovery mechanism (FTRM) for flash memory storage systems. Our empirical study shows that FTRM is an efficient recovery and robust protocol.

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Xin, Ying, Xiaofeng Zhao, Xiankai Jiang, Qun Yang, Jiahe Huang, Shuhong Wang, Rongrong Zheng, Cheng Wang, and Yanjun Hou. "Bistable electrical switching and nonvolatile memory effects by doping different amounts of GO in poly(9,9-dioctylfluorene-2,7-diyl)." RSC Advances 8, no. 13 (2018): 6878–86. http://dx.doi.org/10.1039/c8ra00029h.

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Liu, Shi Min, Xuan Yu Qian, Cheng Zhou, and Xiao Juan Guan. "The Design of an Embedded File System Based on the Flash." Advanced Materials Research 791-793 (September 2013): 1872–75. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.1872.

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Analyzed the unique characteristics of reading and writing the flash memory, and researched the ways of designing a file system. The target embedded file system has the advantages of the traditional file system and the sequential file system. It is able to adapt to the unique characteristics of reading and writing the flash memory. It can solve the inconsistent data problem in the embedded device when power down. And it can solve the bad blocks of the flash which are generated by erase operations also.

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Hudgens, S., and B. Johnson. "Overview of Phase-Change Chalcogenide Nonvolatile Memory Technology." MRS Bulletin 29, no. 11 (November 2004): 829–32. http://dx.doi.org/10.1557/mrs2004.236.

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AbstractPhase-change nonvolatile semiconductor memory technology is based on an electrically initiated, reversible rapid amorphous-to-crystalline phase-change process in multicomponent chalcogenide alloy materials similar to those used in rewriteable optical disks. Long cycle life, low programming energy, and excellent scaling characteristics are advantages that make phase-change semiconductor memory a promising candidate to replace flash memory in future applications. Phase-change technology is being commercialized by a number of semiconductor manufacturers. Fundamental processes in phase-change semiconductor memory devices, device performance characteristics, and progress toward commercialization of the technology are reviewed.

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He, Yu Ru, Pei Bang Dai, Ji Wen Xu, Yue Qun Lu, and Hua Wang. "Synthesis and Resistive Switching Characteristics of Ethyl Methacrylate /N, N'-4, 4'-Diphenylmethane-Bismaleimide Copolymer." Advanced Materials Research 788 (September 2013): 159–63. http://dx.doi.org/10.4028/www.scientific.net/amr.788.159.

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The Ethyl Methacrylate (EMA)/N, N-4, 4-Diphenylmethane-bismaleimide (BMI) copolymer was synthesized by the conventional free radical polymerization. The resulting copolymer was fully characterized by FTIR, TG, DSC and the film exhibited excellent film-forming property, high thermal and dimensional stability. The devices based on EMA/ BMI copolymer possess a sandwich structure comprising bottom indiumtin oxide (ITO) electrode and top Ag electrode. The as-fabricated device exhibits the nonvolatile rewritable flash type memory characteristics. The ITO/(EMA/BMI copolymer)/Ag memory device also demonstrates ON/OFF-current ratio of about 1 × 102 and lower switching threshold voltage of about 0.98V.

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CHONG, CHEE CHING, KAI HONG ZHOU, PING BAI, ER PING LI, and GANESH S. SAMUDRA. "SELF-CONSISTENT SIMULATION OF QUANTUM DOT FLASH MEMORY DEVICE WITH SiO2 AND HfO2 DIELECTRICS." International Journal of Nanoscience 04, no. 02 (April 2005): 171–78. http://dx.doi.org/10.1142/s0219581x05003036.

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Flash memory structure in which a silicon quantum dot embedded in the gate dielectric region between the channel and the control gate is considered. A self-consistent simulation for such memory devices is performed and aims to understand the relationship between the device structure and the meaningful quantities, as required for an efficient device operation. In this study, both the traditional SiO2 and HfO2 high-k dielectrics are being explored, and their results are compared and contrasted. In particular, the superiority of HfO2 over the SiO2 is demonstrated through various interlocking investigations on the relationships between the tunneling current, dielectric thickness, barrier height, programming and retention times.

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Lin, Wei, Yan Yuan Zhang, and Zhan Huai Li. "A Real-Time Flash Memory Storage System in Embedded Environment." Advanced Materials Research 341-342 (September 2011): 807–10. http://dx.doi.org/10.4028/www.scientific.net/amr.341-342.807.

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Recently, flash memory is becoming a popular data storage device in most of the electronic consumer devices. It has lots of attractive features such as small size and light weight nature, zero noise, solid-state reliability, low power consumption, and better shock resistant. To make it suitable for real-time embedded applications, this paper presents the design of an object based file system that uses parallel operations to guarantee bounded read-write access latencies to real-time tasks, in the presence of requests from non real-time tasks. The proposed scheme requires minimal support from the underlying operating system.

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Shim, Won Bo, Seongjae Cho, Jung Hoon Lee, Dong Hua Li, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, et al. "Stacked Gated Twin-Bit (SGTB) SONOS Memory Device for High-Density Flash Memory." IEEE Transactions on Nanotechnology 11, no. 2 (March 2012): 307–13. http://dx.doi.org/10.1109/tnano.2011.2172217.

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Park, Jonghyeok, Soyee Choi, Gihwan Oh, Soojun Im, Moon-Wook Oh, and Sang-Won Lee. "FlashAlloc: Dedicating Flash Blocks by Objects." Proceedings of the VLDB Endowment 16, no. 11 (July 2023): 3266–78. http://dx.doi.org/10.14778/3611479.3611524.

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For a write request, today's flash storage cannot distinguish the logical object it comes from ( e.g. , SSTables in RocksDB). In such object-oblivious flash devices, concurrent writes from different objects are simply packed in their arrival order to flash memory blocks; hence data pages from multiple objects with different lifetimes are multiplexed onto the same flash blocks. This multiplexing incurs write amplification, worsening the performance. Tackling the multiplexing problem, we propose a novel interface for flash storage, FlashAlloc. It is used to pass the logical address ranges of objects to the underlying flash device and thus to enlighten the device to stream writes by objects. The object-aware flash storage can now de-multiplex concurrent writes from multiple objects with distinct deathtimes into per-object dedicated flash blocks. In essence, the interface enables the per-object fine-grained write streaming. Given that popular data stores tend to separate writes by logical objects, we can achieve, compared to the existing solutions, transparent streaming just by calling FlashAlloc upon object creation. Also, FlashAlloc is adaptive to workload changes, and liberates the stream conflicts in the multi-tenant environment. Our experimental results using an open-source SSD prototype demonstrate that FlashAlloc can reduce the device-level write amplification factor (WAF) under RocksDB, F2FS, and MySQL by 1.5, 2.5, and 0.3, respectively and improve their throughput by 2.7x, 1.8x, and 1.2x, respectively. Also, FlashAlloc can mitigate the WAF interference among tenants: when running RocksDB and MySQL together on the same SSD, FlashAlloc reduced WAF from 2.5 to 1.6 and doubled their throughputs.

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Lin, Chan-Ching, Kuei-Shu Chang-Liao, Tzung-Bin Huang, Cheng-Jung Yu, and Hsueh-Chao Ko. "A new erase method for scaled NAND flash memory device." Microelectronics Reliability 72 (May 2017): 34–38. http://dx.doi.org/10.1016/j.microrel.2017.03.031.

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Hwang, Eun Suk, Jun Shik Kim, Seok Min Jeon, Seung Jun Lee, Younjin Jang, Deok-Yong Cho, and Cheol Seong Hwang. "In2Ga2ZnO7oxide semiconductor based charge trap device for NAND flash memory." Nanotechnology 29, no. 15 (February 23, 2018): 155203. http://dx.doi.org/10.1088/1361-6528/aaadf7.

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Kim, Bo-Kyeong, Gun-Woo Kim, and Dong-Ho Lee. "A Novel B-Tree Index with Cascade Memory Nodes for Improving Sequential Write Performance on Flash Storage Devices." Applied Sciences 10, no. 3 (January 21, 2020): 747. http://dx.doi.org/10.3390/app10030747.

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Flash storage devices such as solid-state drives and multimedia cards have been widely used in various applications because of their fast access speed, low power consumption, and high reliability. They consist of NAND flash memories that perform slow block erasures before overwriting data on a prewritten page. This characteristic can lead to performance degradation when applying the original B-tree on the flash storage device without any changes. Although various B-trees have been proposed for flash memory, they still require many flash operations that degrade overall performance. To address the problem, we propose a novel B-tree index structure that reduces the number of write operations and improves the sequential writes by employing cascade memory nodes. The proposed B-tree index structure delays the updates for the modified B-tree nodes and later performs batch writes in a cascade manner. Also, when records with continuous key values are sequentially inserted, the proposed B-tree index structure does not split the leaf node so that it improves write throughput and page utilization. Through mathematical analysis and experimental results, we show that the proposed B-tree index structure always yields better performance than existing techniques.

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Jeong, Jun-Kyo, Jae-Young Sung, Woon-San Ko, Ki-Ryung Nam, Hi-Deok Lee, and Ga-Won Lee. "Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory." Micromachines 12, no. 11 (November 15, 2021): 1401. http://dx.doi.org/10.3390/mi12111401.

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In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

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Gordon, Holden, Jack Edmonds, Soroor Ghandali, Wei Yan, Nima Karimian, and Fatemeh Tehranipoor. "Flash-Based Security Primitives: Evolution, Challenges and Future Directions." Cryptography 5, no. 1 (February 4, 2021): 7. http://dx.doi.org/10.3390/cryptography5010007.

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Over the last two decades, hardware security has gained increasing attention in academia and industry. Flash memory has been given a spotlight in recent years, with the question of whether or not it can prove useful in a security role. Because of inherent process variation in the characteristics of flash memory modules, they can provide a unique fingerprint for a device and have thus been proposed as locations for hardware security primitives. These primitives include physical unclonable functions (PUFs), true random number generators (TRNGs), and integrated circuit (IC) counterfeit detection. In this paper, we evaluate the efficacy of flash memory-based security primitives and categorize them based on the process variations they exploit, as well as other features. We also compare and evaluate flash-based security primitives in order to identify drawbacks and essential design considerations. Finally, we describe new directions, challenges of research, and possible security vulnerabilities for flash-based security primitives that we believe would benefit from further exploration.

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Wu, Enxiu, Yuan Xie, Shijie Wang, Daihua Zhang, Xiaodong Hu, and Jing Liu. "Multi-level flash memory device based on stacked anisotropic ReS2–boron nitride–graphene heterostructures." Nanoscale 12, no. 36 (2020): 18800–18806. http://dx.doi.org/10.1039/d0nr03965a.

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Chae, Suk-Joo, Ronnie Mativenga, Joon-Young Paik, Muhammad Attique, and Tae-Sun Chung. "DSFTL: An Efficient FTL for Flash Memory Based Storage Systems." Electronics 9, no. 1 (January 12, 2020): 145. http://dx.doi.org/10.3390/electronics9010145.

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Flash memory is widely used in solid state drives (SSD), smartphones and so on because of their non-volatility, low power consumption, rapid access speed, and resistance to shocks. Due to the hardware features of flash memory that differ from hard disk drives (HDD), a software called FTL (Flash Translation Layer) was presented. The function of FTL is to make flash memory device appear as a block device to its host. However, due to the erase before write features of flash memory, flash blocks need to be constantly availed through the garbage collection (GC) of invalid pages, which incurs high-priced overhead. In the previous hybrid mapping schemes, there are three problems that cause GC overhead. First, operation of partial merge causes more page copies than operation of switch merge. However, many authors just concentrate on reducing operation of full merge. Second, the availability between a data block and a log block makes the space availability of the log block lower, and it also generates a very high-priced operation of full merge. Third, the space availability of the data block is low because the data block, which has many free pages, is merged. Therefore, we propose a new FTL named DSFTL (Dynamic Setting for FTL). In this FTL, we use many SW (sequential write) log blocks to increase operation of switch merge and to decrease operation of partial merge. In addition, DSFTL dynamically handles the data blocks and log blocks to reduce the operations of erase and the high-priced operation of full merge. Additionally, our scheme prevents the data block with many free pages from being merged to increase the space availability of the data block. Our extensive experimental results prove that our proposed approach (DSFTL) reduces the count of erase and increases the operation of switch merge. As a result, DSFTL decreases the garbage collection overhead.

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Nguyen, The-Nghia, Sunghyun Park, and Donghwa Shin. "Extraction of Device Fingerprints Using Built-in Erase-Suspend Operation of Flash Memory Devices." IEEE Access 8 (2020): 98637–46. http://dx.doi.org/10.1109/access.2020.2995891.

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Liu, W. J., L. Chen, P. Zhou, Q. Q. Sun, H. L. Lu, S. J. Ding, and David W. Zhang. "Chemical-Vapor-Deposited Graphene as Charge Storage Layer in Flash Memory Device." Journal of Nanomaterials 2016 (2016): 1–6. http://dx.doi.org/10.1155/2016/6751497.

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We demonstrated a flash memory device with chemical-vapor-deposited graphene as a charge trapping layer. It was found that the average RMS roughness of block oxide on graphene storage layer can be significantly reduced from 5.9 nm to 0.5 nm by inserting a seed metal layer, which was verified by AFM measurements. The memory window is 5.6 V for a dual sweep of ±12 V at room temperature. Moreover, a reduced hysteresis at the low temperature was observed, indicative of water molecules or −OH groups between graphene and dielectric playing an important role in memory windows.

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Jiang, Dandan, Lei Jin, and Zongliang Huo. "A Quantitative Approach to Characterize Total Ionizing Dose Effect of Periphery Device for 65 nm Flash Memory." Nanoscience and Nanotechnology Letters 10, no. 3 (March 1, 2018): 378–82. http://dx.doi.org/10.1166/nnl.2018.2604.

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To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized. For a W =10 μm HVN device, the main transistor Vth shows a shift of <0.1 V with a TID of 100 krad (Si), while the parasitic transistor shows shift >0.5 V with 100 krad (Si) radiation. It is concluded that the net positive charge accumulating in the shallow trench isolation oxide is responsible for the TID induced leakage and the Vth shift in the flash technology periphery device.

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Jeon, Sanghun. "Thermal Stability and Memory Characteristics of HfON Trapping Layer for Flash Memory Device Applications." Electrochemical and Solid-State Letters 12, no. 11 (2009): H412. http://dx.doi.org/10.1149/1.3212683.

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Zhang, Kai, Xinyi Zhu, Yafen Yang, and Hao Zhu. "Polarization of Bi₂Se₃ thin film toward non-volatile memory applications." AIP Advances 12, no. 8 (August 1, 2022): 085104. http://dx.doi.org/10.1063/5.0093212.

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In recent years, topological insulators have drawn growing interest as a unique electronic state of matter toward quantum information technology. Despite the logic devices with magnetization switching through spin–orbit torque or the topological magneto-electric effect, realizing memory devices based on topological insulators has been urged in quantum computing applications. In this work, we report the design and fabrication of a non-volatile memory device that employs polarization of Bi2Se3 thin films achieving fast memory speed, sufficient memory window, and good reliability. The Bi2Se3 film polarizes under an external electrical field with charges accumulated on the top and bottom surfaces separating the electrons and holes. Such polarization is much faster than the carrier tunneling in conventional floating-gate flash memory and ferroelectric-based memory devices. In addition, good memory retention and endurance properties have also been obtained, showing great potential in high-performance memory application in future topological insulator-involved information technology.

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Journal articles on the topic 'Flash Memory Device'

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