Dissertations / Theses on the topic 'Flash Memory Device'
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Mih, Thomas Attia. "A novel low-temperature growth method of silicon structures and application in flash memory." Thesis, De Montfort University, 2011. http://hdl.handle.net/2086/5183.
Full textOrdosgoitti, Jorhan Rainier. "Development of a Non-Volatile Memristor Device Based on a Manganese-Doped Titanium Oxide Material." University of Toledo / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1290131827.
Full textMariščák, Igor. "Mechanismus pro upgrade BIOSu v Linuxu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235970.
Full textYuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.
Full textCossentine, Tyler Andrew. "An efficient external sorting algorithm for flash memory embedded devices." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/40208.
Full textTao, Qingbo, and 陶庆波. "A study on the dielectrics of charge-trapping flash memory devices." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196488.
Full textpublished_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
Garud, Niharika Triplett Gregory Edward. "Shallow trench isolation process in microfabrication for flash (NAND) memory." Diss., Columbia, Mo. : University of Missouri-Columbia, 2008. http://hdl.handle.net/10355/5622.
Full textThe entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.
Chan, Chun Keung. "A study on non-volatile memory scaling in the sub-100nm regime /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20CHAN.
Full textBryer, Bevan. "Protection unit for radiation induced errors in flash memory systems." Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/50070.
Full textENGLISH ABSTRACT: Flash memory and the errors induced in it by radiation were studied. A test board was then designed and developed as well as a radiation test program. The system was irradiated. This gave successful results, which confirmed aspects of the study and gave valuable insight into flash memory behaviour. To date, the board is still being used to test various flash devices for radiation-harsh environments. A memory protection unit (MPU) was conceptually designed and developed to morntor flash devices, increasing their reliability in radiation-harsh environments. This unit was designed for intended use onboard a micro-satellite. The chosen flash device for this study was the K9F1208XOA model from SAMSUNG. The MPU was designed to detect, maintain, mitigate and report radiation induced errors in this flash device. Most of the design was implemented in field programmable gate arrays and was realised using VHDL. Simulations were performed to verify the functionality of the design subsystems. These simulations showed that the various emulated errors were handled successfully by the MPU. A modular design methodology was followed, therefore allowing the chosen flash device to be replaced with any flash device, following a small reconfiguration. This also allows parts of the system to be duplicated to protect more than one device.
AFRIKAANSE OPSOMMING: 'n Studie is gemaak van" Flash" geheue en die foute daarop wat deur radiasie veroorsaak word. 'n Toetsbord is ontwerp en ontwikkel asook 'n radiasie toetsprogram waarna die stelsel bestraal is. Die resultate was suksesvol en het aspekte van die studie bevestig en belangrike insig gegee ten opsigte van "flash" komponente in radiasie intensiewe omgewmgs. 'n Geheue Beskermings Eenheid (GBE) is konseptueel ontwerp en ontwikkelom die "flash" komponente te monitor. Dit verhoog die betroubaarheid in radiasie intensiewe omgewings. Die eenheid was ontwerp met die oog om dit aan boord 'n mikro-satelliet te gebruik. Die gekose "flash" komponent vir die studie was die K9F1208XOA model van SAMSUNG. Die GBE is ontwerp om foute wat deur radiasie geïnduseer word in die "flash" komponent te identifiseer, herstel en reg te maak. Die grootste deel van die implementasie is gedoen in "field programmable gate arrays" and is gerealiseer deur gebruik te maak van VHDL. Simulasies is gedoen om die funksionaliteit van die ontwikkelde substelsels te verifieer. Hierdie simulasies het getoon dat die verskeie geëmuleerde foute suksesvol deur die GBE hanteer is. 'n Modulre ontwerpsmetodologie is gevolg sodat die gekose "flash" komponent deur enige ander flash komponent vervang kan word na gelang van 'n eenvoudige herkonfigurasie. Dit stelook dele van die sisteem in staat om gedupliseer te word om sodoende meer as een komponent te beskerm.
ZAIDI, SYED AZHAR ALI. "Design of LDPC Decoder for Error Correction in Memory Devices." Doctoral thesis, Politecnico di Torino, 2015. http://hdl.handle.net/11583/2595161.
Full textBalasubramanian, Mahesh. "Phase change memory : array development and sensing circuits using delta-sigma modulation /." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/44/.
Full textGrürmann, Kai [Verfasser]. "Radiation Characterization of Highly Integrated NAND-Flash Memory Devices for Spaceborne Mass Storage Applications / Kai Grürmann." München : Verlag Dr. Hut, 2015. http://d-nb.info/1080754466/34.
Full textWu, Guanying. "Performance and Reliability Study and Exploration of NAND Flash-based Solid State Drives." VCU Scholars Compass, 2013. http://scholarscompass.vcu.edu/etd/3159.
Full textChen, Chih-Wei, and 陳志緯. "A Design Methodology for Flash EEPROM Memory Device." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/06876517035184081031.
Full text國立交通大學
電子研究所
84
A design methodology for high-speed and high-reliable flash EEPROM is presented in this thesis. By modifying a 1-D substrate injection model, agate injection probability model for 2-D numerical analysis is introduced,in which a channel hot-electron enhanced barrier lowering term is used to represent the 2-D injection probability. With this model, the writing speedand the generation of oxide-trapped-charges for various drain structures aresimulated. The simulation results have shown that in order to obtain a high-speed and high-reliable EEPROM cell, the distributin of hot-carriers under writing condition must be widened and a p-pocket-surrounded asymmetric LDDstructure has been shown to satisfy the requirement.
Chung-Chieh, Chen, and 陳仲杰. "A Study of the Device Design in the Flash Memory." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/28168834721182950943.
Full text大葉大學
電機工程研究所
86
The influence of bias conditions for program,erase operation and reliability for the flash memory device will be developed in ourstudy. The flash memory cell structure is a simple self-aligned doublepolysilicon with the stacked gate structure without any select transistor and a ONO layer were fabricated between the poly gates. Three kinds of device reliability contraints are examined for hot electrondegradation, hot electron avalanche breakdown, and time-dependent dielectric breakdown. Also, we will draw out an optimum design region of oxide thickness and channel length when the drain bias is 5V. Meanwhile, in our work, we will study the influences of program and erase operation under various bias situations, in which the operations are the channel hot electron injection,the source-side Fowler-Nordhiem erasing, the channel Fowler-Nordheim program and erasing, and the negative gate erasing. Eventually, we will hope that ourstudy in this work may be helpful in the next generation design.
Chun-PaoChuang and 莊竣堡. "Effects of Device Dimension on Characteristics and Reliability of Peripheral Devices in NAND Flash Memory." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/47628294475599989959.
Full text國立成功大學
微電子工程研究所
102
Recent years, NAND flash memory device which has been widely applied to 3C mobile products is suitable for mass storage devices because of high storage density, high access speed, and low unit cost. The main purpose of this thesis is about reliability and performance of peripheral devices in NAND flash memory. Since NAND flash memory cell needs high voltage for program - erase cycle, the peripheral device of cell, word line driver circuit, has to transmit high voltage to memory cell from superior circuit. The device transmitting signals receives a large VDS and VSB for substrate. This thesis investigated about reliability of high voltage peripheral devices affected by hot carrier effect with high voltage signals and body bias during transmitting condition. The peripheral device would pass through some specific bias in the process of switching, such as high drain bias and high substrate bias, or the generating large substrate current condition. We did hot carrier stress experiments in these situations and found out degradation mechanisms, reliability, and lifetime of device. These results were verified by TCAD simulations. Results indicated that a high drain bias led to hot carrier effect resulting in significant degradation of drain current in linear region(IDlin), and a high substrate bias led to second impact ionization under channel resulting in a threshold voltage(VTH) shift owing to increased vertical electric field inside device. The other part of this thesis, we research the different LDD(Lightly Doped Drain) length of for the impact of the reliability of devices. After stressing different LDD length devices, the experimental results conformed to expectation that the degradation mechanisms were the same, and characteristics resembled in short channel devices, the shorter the LDD length, the poor the immunity to stress. We also defined the lifetime of devices to investigate impact on lifetime in different dimension. The last part gave evidence for result that two devices with the same total LDD length but different length in source and drain region have the same characteristics but obtain different degradation after stress.
陳瑋頡. "Characteristics of SiGe Buried Channel on Nanowire Poly-Si Flash Memory Device." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/yb8n4z.
Full textTsai, Cheng-Yu, and 蔡政育. "The study of charge trap flash memory device with band engineered trapping layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/47291991120299568898.
Full text國立清華大學
工程與系統科學系
98
1.Improvement of P/E speed for NAN structure trapping layer higher charge tunneling efficiency lower Ig 2.Trapped charge detrap easier for HfO2 compared with Si3N4,but that’s a trade-off : erasing speed ? retention 3.Improvement of endurance characteristics for NAN structure compared with single Si3N4 trapping layer barrier oxide(Al2O3) reduces the trap generation during cycling 4.Simultaneous improvement in P/E speed and retention for Si3N4/Al2O3/HfO2 structure
Chang, Yet-fun, and 張逸凡. "A Study of Device and Reliability Measurements in the 0.25μm Split Gate Flash Memory." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/54339177142656867686.
Full text國立聯合大學
電子工程學系碩士班
94
The needful characteristics of a flash memory are small volume, high speed and high capacity. In the future, how to get the good working efficiency in the high capacity is a very important topic. In this thesis, under varying the length between floating gate and drain, and the different oxygen concentration in substrate, the charge characteristic in the floating gate is investigated. And, the working efficiency of a split gate flash memory will be studied in this work. Meanwhile, in the thesis we propose the high efficiency combination system (HECS) model to enhance flash memory efficiency when it processes too much data quantity under high capacity. Finally, when we analyze the oxide layer structure, the charge distributes non-uniformly under the oxide layer, the interface trap density (Dit) will be produced a negative value by Terman method.
Tsai, Tzu-Ting, and 蔡姿婷. "Effects of Stacked High-K Charge trapping layers on Charge Trapping-type Flash Memory Device." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/00933864216135054107.
Full textFang, Ding-Hua, and 房定樺. "Numerical Simulation of High-k/Metal Gate Floating Gate Flash Memory Characteristics and Device Scaling." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/68581600306689963594.
Full text國立交通大學
電子研究所
100
In this dissertation a simulation method to simulate the transient behavior of programming and erasing in high-k/metal gate planar floating gate flash memory is developed. We also simulate the electric field distribution under different channel length by ISE TCAD and compared the program/erase efficiency in channel length is 20 nm of planar floating gate flash memory with edge fringing field effect. From our simulation result, the program/erase efficiency will be degraded by edge fringing field effect. As a result, edge fringing field effect plays an important role in the scaling course of planar floating flash memory. To improve the program/erase efficiency, we have to simulate program characteristics and change other high-k materials as blocking layer. We also simulated erase characteristics under different gate material. From our simulation result, lanthanum oxide as blocking layer could effectively promote program/erase efficiency in planar FG.
Yu, Ching-Shuang, and 游景祥. "Study of lateral charge distribution for SONOS flash memory device by modified Charge Pumping technique." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/55490443600988155387.
Full textHo, Hao-Wei, and 何浩維. "Characteristics of Bandgap-Engineered Trapping Layer on Poly-Si Flash Memory Device with Nanowire Channel." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/67693596678905210258.
Full textLee, Tackhwi. "Device characterization and reliability of Dysprosium (Dy) incorporated HfO₂ CMOS devices and its application to high-k NAND flash memory." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2397.
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Liu, Te-Chiang, and 劉得強. "Operation Characteristic of Charge-Trapping-type Flash Memory Device with Charge-trapping layer of stacked dielectrics." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48553041687300820363.
Full textYang, Dong-Wei, and 楊東偉. "Investigation of MoN Metal-gate and Stacked Dielectric Layer Applied on SONOS-type Flash Memory Device." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/57065096713865216135.
Full textTsai, Jeng-Lin, and 蔡政霖. "Improved Operation of CT Flash Memory Device with Band Engineering in Blocking Layer and Trapping Layer." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/54420050407554027060.
Full textKatsuno, Ian. "SD Storage Array: Development and Characterization of a Many-device Storage Architecture." Thesis, 2013. http://hdl.handle.net/1807/42978.
Full textLin, Steven, and 林東陽. "Program Charge Effect on Random Telegraph Noise Amplitude and Its Device Structural Dependence in SONOS Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/9nqs24.
Full text國立交通大學
電子研究所
98
Nitride program charge effect on the amplitude of random telegraph noise (RTN) in SONOS flash cells is investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitudes after programming while a floating gate flash cell has identical RTN amplitudes in erase and program states. The spread of program-state RTN in a planar SONOS is attributed to a current-path percolation effect caused by random discrete nitride charges. Consequently, program charge effect has to be taken into consideration while establishing RTN model in SONOS. The RTN amplitude spread can be significantly reduced in a surrounding gate structure, such as FinFET SONOS, due to a higher degree of symmetry in a program charge distribution.
Lai, Sin-Hong, and 賴信宏. "Characteristic Analysis of SiN Gate Dielectric Layer MIS-HEMT Device and Investigation of MOS-HEMT Flash Memory." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24505796689449958478.
Full text龍華科技大學
電子工程系碩士班
103
Gallium nitride compared with other materials has the advantage with wide bandgap, high breakdown electric field and high electron saturation velocity, etc. Gallium nitride is a good material for high power, high frequency and optics applications. Metal semiconductor junction high electron mobility transistor can't effectively suppress gate leakage current in high bias due to its limited barrier height properties. Therefore, we adopt metal oxide semiconductor structure high electron mobility transistors to reduce gate leakage and surface states density. In this thesis, we proposed in-situ silicon nitride as gate dielectric layer, and changed deposition conditions of silicon nitride to investigate the variety of deposition conditions of silicon nitride thin film for effect of device performance. Conventionally AlGaN/GaN HEMT device which operating mode is the depletion mode. Depletion mode of device for circuit design has high complexity and fail-safe problem in high power operation. For this reason, there are some methods to make device in enhancement mode. In this thesis, we proposed charge trapping method to confine electrons in the charge storage layer, to change space charge of device, so that threshold voltage toward positive voltage shift.
Huang, Chien Pang, and 黃建邦. "Characteristics of Germanium Buried Channel and Low-Temperature Formed Stacked Trapping Layers on Poly Silicon Nanowire Flash Memory device." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/s89f6w.
Full text國立清華大學
工程與系統科學系
104
With the recent development of Big Data, the demand of nonvolatile memory increases rapidly. Therefore, nonvolatile memory devices of high storage density with high performance and reliability are necessary. In order to improve the efficiency, high- concentration germanium buried channel is considered as a promising way to enhance the performance, while preserving the scaling-down ability. This thesis proposes an implementation of Ge buried channel on the surface of poly silicon nanowire channels and investigates its electrical characteristics. Three experiments are carried out to test the performance of flash memory devices with the proposed the IM and JL mode components. In the first experiment, germanium is grown on nanowire channel of inversion mode flash memory device. Three different conditions are compared: 1) the growth of Ge and silicon cap-layer, 2) the growth of SiGe and silicon cap-layer, and 3) devices without any growth. Results show that devices with Ge growth have the fast programming and erasing speed. No obvious differences of retention characteristics were seen among the three conditions. The devices with epitaxial growth (condition 1 & 2) exhibit better endurance characteristics because their faster P/E speed reduces the damage of tunneling layer. The second experiment studies low temperature formed HfO2/SiNx stacked trapping layer on three channel structures described in the first experiment. The nitride thin film was deposited by inductively coupled plasma chemical vapor deposition at 450 ℃ in order to reduce thermal cycles in fabrication processes of the devices with Ge containing, which achieves the enhancement of P/E speed and endurance. Results of the second experiment show that the low temperature formed HfO2/SiNx stacked trapping layer can further improve the retention characteristics as compared to results in the first experiment. The third experiment investigates junctionless nanowire flash memory devices with stacked trapping layer in the second experiment. The junctionless devices with Ge buried channel and those without ones are compared. Results show that whatever modes (JL / IM) they are, the program, erase speed and endurance performance can be effectively improved by buried channel. The retention characteristics of devices with buried channels can be still similar as compared to those without ones.
Liu, Yueran 1975. "Novel flash memory with nanocrystal floating gate." Thesis, 2006. http://hdl.handle.net/2152/2819.
Full textTsung-HanLu and 呂宗翰. "Reliability of Devices in NAND Flash Memory Periphery Circuitry." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/80883942352840542816.
Full text國立成功大學
微電子工程研究所碩博士班
101
Recent years, NAND flash storage drive is one of the most important products used in mobile electric products. The NAND Flash device is with the advantages which are high integrated and fast storage speed. The main purpose of this thesis is about the reliability studies of NAND Flash Periphery devices. Since the NAND flash needs high voltage around 18V during program / erase operation, The Devices in NAND Flash Memory Periphery Circuitry in this thesis is word-line driver circuits, the devices have to pass high voltage from superior circuit to cell devices. The first part research in this thesis focused on the reliability issue which took place in the transition of the devices from OFF-state to ON-state, and last part, we discussed the impact of reliability on different channel length devices. The second stage is the word-line driver circuit which used enhanced-mode NMOSFET. The devices operated in the transition from OFF-state to ON-state incessantly. In this switching process, the devices will be operated at high VDS and high VBS. From the experimental results, there is a critical impact ionization in the drain side drift region which caused by hot-carrier effect when device operated at high VDS, it will induced that interface state (Nit) are generate in the Si/SiO2 surface and cause IDlin degradation. The experimental results are verified by TCAD simulation. On the other hand, the vertical electric field inside device will increase when device operated at high VBS and induced secondary impact ionization below the region of channel and drift region, this mechanism will cause more carrier generation and may cause electrons injection into gate oxide, and resulting in the formation of defects inside the gate oxide, the gate control of the channel decreased and caused VTH increased. The other part of this thesis, we research the different channel length of for the impact of the reliability of devices. We stressed the devices which are different channel length devices, as the experimental results, the degraded mechanism in different channel length devices are the same, and as we expected that the sustainable capability of the short-channel device is relatively poor, in short channel devices, IDlin degradation and VTH shift are relatively large. Besides, we defined the lifetime of devices and summarized the influence of different channel the length on the lifetime.
Sarkar, Joy 1977. "Non-volatile memory devices beyond process-scaled planar Flash technology." Thesis, 2007. http://hdl.handle.net/2152/3666.
Full text陳佳壕. "Research of Silicon Nitride layer on SONOS Flash Memory Devices." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/tpg683.
Full textShun-Tai, Chung, and 鍾順泰. "A study of simulation and analysis in flash memory devices." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/71048223645530066343.
Full text大葉大學
電機工程研究所
86
In submicronmeter flash memory devices, the almost injection models for programming operation is no more accurate to evaluate injection current.Therefor, we will present a novel model to simulate the charge injection in the flash momory. For erasing operation, a well-known model, F-N Electron Tunneling Model,will be used during theoretical simulation.
Moreira, André Ricardo Araújo. "Reliability study of advanced 2T-FNFN-NOR embedded memory devices." Master's thesis, 2009. http://hdl.handle.net/10216/66710.
Full textTese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
Moreira, André Ricardo Araújo. "Reliability study of advanced 2T-FNFN-NOR embedded memory devices." Dissertação, 2009. http://hdl.handle.net/10216/66710.
Full textTese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
Tang, Shan 1975. "Protein-mediated nanocrystal assembly for floating gate flash memory fabrication." 2008. http://hdl.handle.net/2152/18156.
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Lu, Kuo-Yuan, and 呂國源. "Characteristics and Investigation of Next Generation Low Power Flash Memory Devices." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/68773591165143247998.
Full text國立交通大學
電子工程系所
94
For the system-on-chip (SOC) application, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPDs) for electrically-erasable programmable read-only-memory (EEPROM) and stacked-gate flash memory is needed to obtain high density and low operation voltage. But when oxide thickness is less than 10 nm, the charge stored in the floating gate forming leakage path easily due to defects in the oxide, thus induces data error. To overcome the limits of the conventional FG structure, other kinds of nonvolatile memories such as SONOS and nanocrystal memories which stored electrons in discrete traps are mostly mentioned, hence several characteristics such as scaling down and good storage maintenance can be reached. In this thesis, we successfully fabricated nanocrystal memory devices by using different high-k materials. First, a praseodymium oxide (PrO2) layer was deposited on the oxide by Dual E-gun Evaporation System with Praseodymium oxide targets. After that, the wafer was subjected to RTA treatment in O2 ambient at 900℃ for 1 minute. When the film is RTA treated to provide enough energy and surface mobility, the thin Praseodymium oxide will self-assemble into nano dot. By using this method, we obtains nonvolatile memory devices with excellent characteristics: low applied voltages, large memory window, high program/erase speed, fine endurance. And, we can use these devices in 2-bit operations. Consequently, we consider, it is potential material as nanocrystal memory devices by using PrO2. A Lanthanum aluminate (LaAlO3) layer was also deposited on the oxide by Dual E-gun Evaporation System with Praseodymium oxide targets. We obtain similar results after our measurements: low applied voltages, large memory window, high program/erase speed, fine endurance. it is potential candidate as nanocrystal memory devices by using LaAlO3.
Li, Hao Chieh, and 李豪捷. "Chemical Dry Etching and N2O anneal on SONOS Flash Memory Devices." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/81590781610269005168.
Full textShih, Jui-Lung, and 施瑞隆. "The Design of Flash Memory Data Management for Portable Storage Devices." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/78694437101664778264.
Full text國立中正大學
資訊工程研究所
91
Flash memory has attractive features such as shock resistance, low power consumption, non-volatility, small size, light weight, and fast access speed. However, it has drawbacks such as a write-once/bulk-erase device, no in-place update, and limited erase cycles. Because of so many advantages, flash memory always plays the part of data storage systems in mobile devices and embedded systems. Meanwhile, digital content is getting more and more important in our life. The issues of usage rights management of digital content are usually discussed. Therefore, we propose a new system for managing digital content. Moreover, flash memory is used popularly for storing digital content. We focus on the performance and the reliability of flash memory. Furthermore, we propose a new architecture of using multiple buses and ECC groups. The multiple buses architecture is for improving the I/O performance of flash memory. And the ECC groups on flash memory are for recovering more errors and providing higher reliability.
YU-LUN-HU and 胡毓倫. "A Data Sanitization Method for Mobile Devices with NAND Flash Memory." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6j6ba7.
Full text國立臺灣科技大學
電子工程系
106
Recently, NAND flash memory has been widely used in wearable mobile devices. Data erasure is one of most important issue in Wearable Mobile Devices, the instruction of deletion from file system is not able to delete data completely in NAND flash memory, it still can use data recovery software to recover data. In the thesis, first, we will introduce NAND Flash Memory, and then we will proposes an application with various algorithm and compare each algorithm. In the end, we will conclude an algorithm which can delete data completely in NAND flash memory.
Yao, Yu-Yuan, and 姚裕源. "A Novel Coupling-Ratios Extraction Technique for Split-Gate Flash Memory Devices." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/02331943560174352650.
Full text國立清華大學
電機工程學系
87
Today, no practical coupling ratios extracting technique is proposed in split-gate Flash memory. But there are many proposed coupling ratios extraction methods for stacked-gate Flash memory. The main differences between split-gate and stacked-gate Flash memory are the special control-gate structure (split structure) and read operation (no threshold voltage definition) of split-gate Flash memory. So many coupling ratios extracting technique in stacked-gate Flash memory are not suitable for split-gate Flash memory. This paper introduces a novel coupling ratios extracting technique to extract the most important coupling ratios, control-gate coupling ratio and source coupling ratio, of split-gate Flash memory. From the source side Constant Ramp Rate Programming (CRRP) method, we can extract the source coupling ratio. According to the simulation results of MEDICI 2D potential contour distribution, when the device is under programming operation, after the floating-gate potential reaching the convergent point, the bulk voltage has no influence on the surface potential distribution in the region under the floating-gate. And the depletion region of high voltage source replaces the contact area of bulk to floating-gate. The coupling ratio of bulk is small enough to be negelected. According to the capacitance model of split-gate device, and the assumption of bulk couplig ratio is small under programming operation, control-gate coupling ratio and source coupling ratio are knowen. Based on these coupling ratios, we can construct the electrical model of split-gate Flash memory. The electrical model is useful in improveing the device''s characteristic and operation condition of split-gate Flash memory. And it will play a important role in the design of next generation device in the future. Accroding to the experimential results, a new coupling ratio extraction scheme is proposed for spilt-gate Flash memories with advantages of : 1. In sti extraction under programming operation 2. Feasible extracting measurement 3. De-couple the source coupling ratio from the others 4. Insensitive to measuring parameters 5. Reflection of devices'' geometric dimensions
Tseng, Der-Jang, and 曾德彰. "A Study of Characterization and Analysis in P-Channel Flash Memory Devices." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/32845505898014326879.
Full text大葉大學
電機工程研究所
87
Abstract The flash memory is a better choice than others in the nonvolatile memory market, therefore, it will be much valuable for us to investigate its characteristics, and there are lots of researches about it. Recently, the research of flash memory, the focus is always concentrated on the threshold voltage shift due to programming or erasing operation, data retention time, data endurance, programming efficiency, erasing speed, and so on. This benifits higher device reliability, speed, and integrity. The nonvolatile memory devices have the capability to store the informations. The most used programming method is F-N tunneling scheme or channel-hot-electron(CHE) scheme overcoming the floating gate barrier. It is very convenient for N-channel flash memory to program by positive gate bias. So that P-channel flash memory is less attracted to researchers. The data storage is mainly determined by the charges on the floating gate. Such that if the change of charge on the floating gate can be accurate to predict, then the shifting of devices threshold voltage and the data storage or not can be discriminated. Therefore in this thesis, we will investigate the threshold voltage alteration during the programming and erasing operation of the submicron P-channel flash memory. And, a comparison in both types is also maded. In this submicronmeter P-channel flash memory devices, the programming model, which is called Channel-Hot-Hole-Induced-Hot-Electron Current Model, to simulate the charge injection in the flash memory is used. For erasing operation, a well-known model, Fowler-Nordheim Electron Tunneling Model, will be used during theoretical simulation.
Hong, Peng-Yun, and 洪鵬雲. "Research on the Flash Memory Management and Cleaning Policies in Mobile Devices." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/53970614320165445036.
Full text國立暨南國際大學
資訊管理學系
89
Since flash memory has some attractive features, such as low power consumption, non-volatility, shock resistance, high data density, therefore, it is good for mobile devices. Furthermore, with advanced semi-conductor manufacture technology, flash memory is becoming larger and faster, so it is promising to replace Hard disk drives in most applications. However, flash memory comes with some hardware restrictions, such as requiring erasure before it can be rewritten and can be erased only a limited number of times.So a new storage management schema is needed for maintaining the flash memory. In this thesis, we design a new storage management system to solve the non-rewritable problem and reduce the number of erase times for power saving and ensure longer flash memory lifetime
Khan, Faraz I. "Endurance characterization and improvement of floating gate semiconductor memory devices." 2009. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051734.
Full textShiu, Feng-Wen, and 許逢文. "Effects of Stacked High-k Blocking Layer on Charge-Trapping Flash Memory Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/09742273730644922957.
Full text國立清華大學
工程與系統科學系
98
When floaging gate device can't satisfy smaller device, SONOS-Type is the one of candidate to replace it. SONOS-Type device tunneling layer thickness is about 30A ,it is a problem for retention. How to improve our device performance is very important. In our experiment, using various high-k dielectrics as stacked SONOS-Type blocking layer. Different materials has different performances , matching stacked structure by nitrogen treatment with distinct doses(2mins , 4mins, 8mins) , bandgap-engineering, k-value as a excellent blocking oxide layer. For tunneling oxide, the application of multilayer dielectric stacks is promising to realize tunnel barrier engineering. With a suitable combination of stacked tunneling oxide(low-k/high-k),a lower operation voltage can be achieve. Using Al2O3/HfAlO as blocking layer has better performance than other stacked structures. Take high bandgap material as first layer blocking layer ,and secondly stack higher k material can improve device performance. Stacking a high quality film as blocking layer first and then stack various high-k materials by PIII nitrogen treatment can reduce crystallize and enhance retention , promote device reliability after high temperature annealing process.
Wang, Szu-Yu, and 王嗣裕. "Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory Devices." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/40805732839760983092.
Full text國立清華大學
電子工程研究所
96
電荷捕捉記憶體元件預期將成為快閃記憶體於40奈米以下世代產品的解決方案。於1960年代末期發明之矽-氧-氮-氧-矽(SONOS)元件就是其中一種型態的電荷捕捉記憶體元件。該種元件是將電荷儲存在氮化矽材料當中。然而,傳統的SONOS記憶體元件存在著一種應用上的限制,就是我們無法找到一個合適的穿隧氧化層厚度來同時達到優良的抹除速度以及資料保存能力。 最近這幾年一種新的電荷捕捉快閃記憶體元件被提出具有克服傳統SONOS元件應用上限制的能力。該種記憶體元件稱作能帶隙工程矽-氧-氮-氧-矽(BE-SONOS)元件。在採用非常薄的氧-氮-氧穿隧阻障層(一般來說各層厚度約在13/20/25 埃)的情況下,高電場下的電荷穿隧距離會因為能帶隙消除效應而有效降低。此時幾乎僅存第一層超薄氧化層扮演有效之電荷穿隧障礙,因此大大提高了電洞穿隧電流。另一方面當電荷儲存狀態的低電場條件下,不論電子自儲存層中逸失或是電洞穿隧進入儲存層之能力皆會因為整個氧-氮-氧穿隧阻障層的阻擋而顯著降低。 本論文將針對此新開發的BE-SONOS記憶體元件在基本元件概念、各介電層之製程效應、電荷捕捉層工程效應、以及介電層微縮能力在可靠度特性上之研究提供詳細的說明。從這些研究結果我們認為在次世代的非揮發性記憶體,特別是資料儲存式快閃記憶體(NAND Flash)的應用上,BE-SONOS是目前電荷捕捉記憶體元件當中的最佳解決方案。
Chun-PoChang and 張鈞博. "Breakdown Voltage and Reliability Studies of Devices in NAND Flash Memory Periphery Circuitry." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/58759552904041180838.
Full text國立成功大學
微電子工程研究所
102
In this thesis, we study the high-voltage device which is depletion-mode lateral diffused metal-oxide-semiconductor (LDMOS). The HV device in the periphery circuit is applied to NAND Flash Cell for Program/Erase operation. In periphery circuit, the high off-state breakdown voltage (off-state VBD) is an important requirement for this device. Therefore, the LDMOS breakdown mechanism with different BF2 implant by varying implant dosage in N- region is investigated. As expected, the off-state breakdown voltage increase with the raise of BF2 concentration. Experimental data and technology computer aided design simulations show that gate-induced-drain-leakage (GIDL) and PN junction breakdown are responsible for the variation of breakdown voltage. Moreover, in the circuit operating environment, there might be hot carrier degradation in the device. The damage will happen while device is programming or erasing data. Generally, the ISUB peak will be the index of the HCI degradation. However, in our study, the measurement results contradict pervious study because the distribution of the impact ionization peak would dominant the hot carrier degradation instead of the amount of the ISUB current. The impact ionization which is located near drain side is greater with higher BF2 concentration. In conclusion, the device with higher BF2 implant suffers worse HCI degradation because of more high energy carrier injection. According to the results in this study, care should be taken when we implant the BF2 into the drift region, since there is a trade-off between VBD and HCI reliability issue.