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1

Mih, Thomas Attia. "A novel low-temperature growth method of silicon structures and application in flash memory." Thesis, De Montfort University, 2011. http://hdl.handle.net/2086/5183.

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Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon.
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2

Ordosgoitti, Jorhan Rainier. "Development of a Non-Volatile Memristor Device Based on a Manganese-Doped Titanium Oxide Material." University of Toledo / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1290131827.

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3

Mariščák, Igor. "Mechanismus pro upgrade BIOSu v Linuxu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235970.

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This work provides overview of creating of a simple driver for the BIOS flash memory by accessing the physical computer memory. Although, the BIOS is one of a system's core components, there is no standardized update mechanism approach. Purpose of thesis is to create module driver by taking advantage of existing interface subsystem MTD, to suggest and implement driver for one specific device to Linux kernel operating system. Also explains technique allowing write access to registers of the flash memory with utilization of configuration file.
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4

Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.

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5

Cossentine, Tyler Andrew. "An efficient external sorting algorithm for flash memory embedded devices." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/40208.

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Many embedded systems applications involve storing and querying large datasets. Existing research in this area has focused on adapting and applying conventional database algorithms to embedded devices. Algorithms designed for processing queries on embedded devices must be able to execute given the small amount of available memory and energy constraints. Sorting is a fundamental algorithm used frequently in databases. Flash memory has unique performance characteristics. Page writes to flash memory are much more expensive than reads. In addition, random reads from flash memory can be performed at nearly the same speed as sequential reads. External sorting can be optimized for flash memory embedded devices by favoring page reads over writes. This thesis describes the Flash MinSort algorithm that, given little memory, takes advantage of fast random reads and generates an index at runtime to sort a dataset. The algorithm adapts its performance to the memory available and performs best for data that is temporally clustered. Experimental results show that Flash MinSort is two to ten times faster than previous approaches for small memory sizes where external merge sort is not executable.
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6

Tao, Qingbo, and 陶庆波. "A study on the dielectrics of charge-trapping flash memory devices." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196488.

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Discrete charge-trapping flash memory is being developed for the next-generation commercial flash-memory applications due to its advantages over the traditional floating-gate counterpart. Currently, Si3N4 is widely used as charge-trapping layer (CTL). However, Si3N4 has low dielectric constant and small conduction-band offset with respect to the SiO2 tunneling layer, imposing limitation on further applications. Therefore, this research emphasized on investigating new dielectrics with appropriate fabrication methods to replace Si3N4 as CTL for achieving improved memory performance. Firstly, GeON CTL annealed at different temperatures was investigated. The memory device with post-deposition annealing at 600 0C exhibited the largest memory window, the best charge retention performance, and the highest reliability. These good results are due to the fact that optimal annealing temperature could suppress shallow traps and also produce new traps with desirable energy levels in the CTL. Since ZnON has a negative conduction-band offset (NCBO) with respect to Si, the traps located in the bandgap of ZnON should have deep energy levels. The memory performances of ZrON film with and without Zn doping were studied. Experimental results showed that ZrZnON film had higher program speed and better charge retention performance due to many deeper trap levels induced by the Zn doping, as well as higher erase speed due to the direct recombination of electrons at these deeper trap levels with incoming holes and the intermediary role of these deeper trap levels under erase mode. MoO3 is another NCBO dielectric with a high K value and many oxygen vacancies. La2O3, a rare-earth metal oxide, is a promising dielectric as CTL. To combine the advantages of both La2O3 and MoO3, Mo-doped La2O3 was proposed as a new CTL. Compared to the device with pure La2O3, the one with LaMoO film as CTL had significantly larger C-V hysteresis window, much higher P/E speeds, and better charge retention due to the deeper-level traps and deeper quantum wells created by the LaMoO film. Nitrogen incorporation is a popular approach to increase the trap density in the bulk of CTL. In this research, the memory performances of GdTiO films with and without nitrogen incorporation were compared. Since the nitrogen incorporation induced smaller equivalent oxide thickness, produced nitride-related traps with desirable energy level and larger cross-section for charge capture, the GdTiON film possessed better memory performance than the GdTiO film. Finally, fluorine plasma was employed to improve the quality of blocking layer. The memory device with AlOF blocking layer obtained higher program speed, better reliability and better charge retention than that based on AlO blocking layer. The improved performance was due to the fact that the fluorine incorporation passivated the defects and removed the excess oxygen in the bulk of the blocking layer. In summary, dielectric plays important roles in the performance of charge-trapping flash memory. Memory devices with GeON, ZrZnON, LaMoO, or GdTiON as charge trapping layer and AlOF as blocking layer can produce large memory window, high program/erase speed and good charge retention.
published_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
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7

Garud, Niharika Triplett Gregory Edward. "Shallow trench isolation process in microfabrication for flash (NAND) memory." Diss., Columbia, Mo. : University of Missouri-Columbia, 2008. http://hdl.handle.net/10355/5622.

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Thesis (M.S.)--University of Missouri-Columbia, 2008.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.
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8

Chan, Chun Keung. "A study on non-volatile memory scaling in the sub-100nm regime /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20CHAN.

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9

Bryer, Bevan. "Protection unit for radiation induced errors in flash memory systems." Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/50070.

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Thesis (MScEng)--University of Stellenbosch, 2004.
ENGLISH ABSTRACT: Flash memory and the errors induced in it by radiation were studied. A test board was then designed and developed as well as a radiation test program. The system was irradiated. This gave successful results, which confirmed aspects of the study and gave valuable insight into flash memory behaviour. To date, the board is still being used to test various flash devices for radiation-harsh environments. A memory protection unit (MPU) was conceptually designed and developed to morntor flash devices, increasing their reliability in radiation-harsh environments. This unit was designed for intended use onboard a micro-satellite. The chosen flash device for this study was the K9F1208XOA model from SAMSUNG. The MPU was designed to detect, maintain, mitigate and report radiation induced errors in this flash device. Most of the design was implemented in field programmable gate arrays and was realised using VHDL. Simulations were performed to verify the functionality of the design subsystems. These simulations showed that the various emulated errors were handled successfully by the MPU. A modular design methodology was followed, therefore allowing the chosen flash device to be replaced with any flash device, following a small reconfiguration. This also allows parts of the system to be duplicated to protect more than one device.
AFRIKAANSE OPSOMMING: 'n Studie is gemaak van" Flash" geheue en die foute daarop wat deur radiasie veroorsaak word. 'n Toetsbord is ontwerp en ontwikkel asook 'n radiasie toetsprogram waarna die stelsel bestraal is. Die resultate was suksesvol en het aspekte van die studie bevestig en belangrike insig gegee ten opsigte van "flash" komponente in radiasie intensiewe omgewmgs. 'n Geheue Beskermings Eenheid (GBE) is konseptueel ontwerp en ontwikkelom die "flash" komponente te monitor. Dit verhoog die betroubaarheid in radiasie intensiewe omgewings. Die eenheid was ontwerp met die oog om dit aan boord 'n mikro-satelliet te gebruik. Die gekose "flash" komponent vir die studie was die K9F1208XOA model van SAMSUNG. Die GBE is ontwerp om foute wat deur radiasie geïnduseer word in die "flash" komponent te identifiseer, herstel en reg te maak. Die grootste deel van die implementasie is gedoen in "field programmable gate arrays" and is gerealiseer deur gebruik te maak van VHDL. Simulasies is gedoen om die funksionaliteit van die ontwikkelde substelsels te verifieer. Hierdie simulasies het getoon dat die verskeie geëmuleerde foute suksesvol deur die GBE hanteer is. 'n Modulre ontwerpsmetodologie is gevolg sodat die gekose "flash" komponent deur enige ander flash komponent vervang kan word na gelang van 'n eenvoudige herkonfigurasie. Dit stelook dele van die sisteem in staat om gedupliseer te word om sodoende meer as een komponent te beskerm.
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10

ZAIDI, SYED AZHAR ALI. "Design of LDPC Decoder for Error Correction in Memory Devices." Doctoral thesis, Politecnico di Torino, 2015. http://hdl.handle.net/11583/2595161.

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NAND flash memories are used in large number of electronic devices for storing data. The ever increasing demand of the high storage in these devices has resulted in high density NAND flash memories. The high density is achieved through the process of continuous technology scaling and the use of multilevel cell (MLC) technology. In multilevel cell technology more than one bits are stored in a single cell of the flash memory. However, this increased storage density has come at a price of reduced reliability. The raw bit error rate has increased rapidly in high density flash memories, therefore, demanding more powerful error correcting codes. The bit error rate (BER) requirements in NAND flash memories are reported to be 10^−13 to 10^−16, after applying the error correcting code. The current practice is to use the hard decision error correcting codes in NAND flash memories, such as BCH codes. However, as the raw bit error rate is getting worse, these hard decision codes will not be able to achieve the BER requirements of these memories. Therefore, more powerful error correcting codes with soft decision decoding algorithm are required. Among the soft decision codes, low density parity check codes (LDPC) can be a promising candidate for error correction in high density NAND flash memories due to their excellent error correction performance close to the Shannon limit. LDPC codes employed in NAND flash memories have large block lengths and very high code rate and should show good error correcting and error floor performance. Evaluating the error floor performance of these codes at very low frame error rates, typically around 10^−9 to 10^−10, require the use of high speed hardware simulators. Due to the reconfigurability and high speed, field programmable gate arrays (FPGAs) are largely used for evaluating the performance of LDPC codes. This thesis presents an FPGA based simulator system for evaluating the error correction and error floor performance of regular quasi cyclic (QC) LDPC Codes, for the application of large page size MLC NAND flash memories. Particularly, we targeted the algebraic QC-LDPC codes, which have high code rates and good error correcting and error floor performance. A generalized, high throughput and resource efficient hardware implementation of the QC-LDPC encoder and the decoder is given on FPGA. The proposed decoder can decode any regular QC-LDPC code including very high circulant weight QC-LDPC codes, such as euclidean geometry (EG) LDPC codes. The generalized and high throughput implementation of such large circulant weight QC-LDPC codes is not reported previously in the open literature. Moreover, the encoder and decoder hardware implementations are given on FPGA for very large page size (8 KB) of NAND flash memory, which are also not dealt previously in the open literature. A high speed and high quality floating point additive white Gaussian noise channel is implemented on FPGA using the high level synthesis method. The high level synthesis is used to rapidly prototype the channel on FPGA and to lower the development time of the LDPC simulator system. The very low consumption of the logic resources by the channel also enabled us to instantiate many channel modules in parallel, resulting in high throughput of the simulator. This thesis also presents the FPGA implementation and simulation results of two algebraic QC-LDPC codes for the page size 8 KB of NAND flash memory. Simulation results show good error correcting and error floor performance of the developed codes making them a promising candidate for error correction in NAND flash memories.
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11

Balasubramanian, Mahesh. "Phase change memory : array development and sensing circuits using delta-sigma modulation /." [Boise, Idaho] : Boise State University, 2009. http://scholarworks.boisestate.edu/td/44/.

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12

Grürmann, Kai [Verfasser]. "Radiation Characterization of Highly Integrated NAND-Flash Memory Devices for Spaceborne Mass Storage Applications / Kai Grürmann." München : Verlag Dr. Hut, 2015. http://d-nb.info/1080754466/34.

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13

Wu, Guanying. "Performance and Reliability Study and Exploration of NAND Flash-based Solid State Drives." VCU Scholars Compass, 2013. http://scholarscompass.vcu.edu/etd/3159.

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The research that stems from my doctoral dissertation focuses on addressing essential challenges in developing techniques that utilize solid-state memory technologies (with emphasis on NAND flash memory) from device, circuit, architecture, and system perspectives in order to exploit their true potential for improving I/O performance in high-performance computing systems. These challenges include not only the performance quirks arising from the physical nature of NAND flash memory, e.g., the inability to modify data in-place, read/write performance asymmetry, and slow and constrained erase functionality, but also the reliability drawbacks that limits solid state drives (SSDs) from widely deployed. To address these challenges, I have proposed, analyzed, and evaluated the I/O scheduling schemes, strategies for storage space virtualization, and data protection methods, to boost the performance and reliability of SSDs.
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14

Chen, Chih-Wei, and 陳志緯. "A Design Methodology for Flash EEPROM Memory Device." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/06876517035184081031.

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碩士
國立交通大學
電子研究所
84
A design methodology for high-speed and high-reliable flash EEPROM is presented in this thesis. By modifying a 1-D substrate injection model, agate injection probability model for 2-D numerical analysis is introduced,in which a channel hot-electron enhanced barrier lowering term is used to represent the 2-D injection probability. With this model, the writing speedand the generation of oxide-trapped-charges for various drain structures aresimulated. The simulation results have shown that in order to obtain a high-speed and high-reliable EEPROM cell, the distributin of hot-carriers under writing condition must be widened and a p-pocket-surrounded asymmetric LDDstructure has been shown to satisfy the requirement.
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15

Chung-Chieh, Chen, and 陳仲杰. "A Study of the Device Design in the Flash Memory." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/28168834721182950943.

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碩士
大葉大學
電機工程研究所
86
The influence of bias conditions for program,erase operation and reliability for the flash memory device will be developed in ourstudy. The flash memory cell structure is a simple self-aligned doublepolysilicon with the stacked gate structure without any select transistor and a ONO layer were fabricated between the poly gates. Three kinds of device reliability contraints are examined for hot electrondegradation, hot electron avalanche breakdown, and time-dependent dielectric breakdown. Also, we will draw out an optimum design region of oxide thickness and channel length when the drain bias is 5V. Meanwhile, in our work, we will study the influences of program and erase operation under various bias situations, in which the operations are the channel hot electron injection,the source-side Fowler-Nordhiem erasing, the channel Fowler-Nordheim program and erasing, and the negative gate erasing. Eventually, we will hope that ourstudy in this work may be helpful in the next generation design.
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16

Chun-PaoChuang and 莊竣堡. "Effects of Device Dimension on Characteristics and Reliability of Peripheral Devices in NAND Flash Memory." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/47628294475599989959.

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碩士
國立成功大學
微電子工程研究所
102
Recent years, NAND flash memory device which has been widely applied to 3C mobile products is suitable for mass storage devices because of high storage density, high access speed, and low unit cost. The main purpose of this thesis is about reliability and performance of peripheral devices in NAND flash memory. Since NAND flash memory cell needs high voltage for program - erase cycle, the peripheral device of cell, word line driver circuit, has to transmit high voltage to memory cell from superior circuit. The device transmitting signals receives a large VDS and VSB for substrate. This thesis investigated about reliability of high voltage peripheral devices affected by hot carrier effect with high voltage signals and body bias during transmitting condition.   The peripheral device would pass through some specific bias in the process of switching, such as high drain bias and high substrate bias, or the generating large substrate current condition. We did hot carrier stress experiments in these situations and found out degradation mechanisms, reliability, and lifetime of device. These results were verified by TCAD simulations. Results indicated that a high drain bias led to hot carrier effect resulting in significant degradation of drain current in linear region(IDlin), and a high substrate bias led to second impact ionization under channel resulting in a threshold voltage(VTH) shift owing to increased vertical electric field inside device.   The other part of this thesis, we research the different LDD(Lightly Doped Drain) length of for the impact of the reliability of devices. After stressing different LDD length devices, the experimental results conformed to expectation that the degradation mechanisms were the same, and characteristics resembled in short channel devices, the shorter the LDD length, the poor the immunity to stress. We also defined the lifetime of devices to investigate impact on lifetime in different dimension. The last part gave evidence for result that two devices with the same total LDD length but different length in source and drain region have the same characteristics but obtain different degradation after stress.
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17

陳瑋頡. "Characteristics of SiGe Buried Channel on Nanowire Poly-Si Flash Memory Device." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/yb8n4z.

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18

Tsai, Cheng-Yu, and 蔡政育. "The study of charge trap flash memory device with band engineered trapping layer." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/47291991120299568898.

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碩士
國立清華大學
工程與系統科學系
98
1.Improvement of P/E speed for NAN structure trapping layer higher charge tunneling efficiency lower Ig 2.Trapped charge detrap easier for HfO2 compared with Si3N4,but that’s a trade-off : erasing speed ? retention 3.Improvement of endurance characteristics for NAN structure compared with single Si3N4 trapping layer barrier oxide(Al2O3) reduces the trap generation during cycling 4.Simultaneous improvement in P/E speed and retention for Si3N4/Al2O3/HfO2 structure
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19

Chang, Yet-fun, and 張逸凡. "A Study of Device and Reliability Measurements in the 0.25μm Split Gate Flash Memory." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/54339177142656867686.

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碩士
國立聯合大學
電子工程學系碩士班
94
The needful characteristics of a flash memory are small volume, high speed and high capacity. In the future, how to get the good working efficiency in the high capacity is a very important topic. In this thesis, under varying the length between floating gate and drain, and the different oxygen concentration in substrate, the charge characteristic in the floating gate is investigated. And, the working efficiency of a split gate flash memory will be studied in this work. Meanwhile, in the thesis we propose the high efficiency combination system (HECS) model to enhance flash memory efficiency when it processes too much data quantity under high capacity. Finally, when we analyze the oxide layer structure, the charge distributes non-uniformly under the oxide layer, the interface trap density (Dit) will be produced a negative value by Terman method.
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20

Tsai, Tzu-Ting, and 蔡姿婷. "Effects of Stacked High-K Charge trapping layers on Charge Trapping-type Flash Memory Device." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/00933864216135054107.

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21

Fang, Ding-Hua, and 房定樺. "Numerical Simulation of High-k/Metal Gate Floating Gate Flash Memory Characteristics and Device Scaling." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/68581600306689963594.

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碩士
國立交通大學
電子研究所
100
In this dissertation a simulation method to simulate the transient behavior of programming and erasing in high-k/metal gate planar floating gate flash memory is developed. We also simulate the electric field distribution under different channel length by ISE TCAD and compared the program/erase efficiency in channel length is 20 nm of planar floating gate flash memory with edge fringing field effect. From our simulation result, the program/erase efficiency will be degraded by edge fringing field effect. As a result, edge fringing field effect plays an important role in the scaling course of planar floating flash memory. To improve the program/erase efficiency, we have to simulate program characteristics and change other high-k materials as blocking layer. We also simulated erase characteristics under different gate material. From our simulation result, lanthanum oxide as blocking layer could effectively promote program/erase efficiency in planar FG.
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22

Yu, Ching-Shuang, and 游景祥. "Study of lateral charge distribution for SONOS flash memory device by modified Charge Pumping technique." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/55490443600988155387.

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23

Ho, Hao-Wei, and 何浩維. "Characteristics of Bandgap-Engineered Trapping Layer on Poly-Si Flash Memory Device with Nanowire Channel." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/67693596678905210258.

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24

Lee, Tackhwi. "Device characterization and reliability of Dysprosium (Dy) incorporated HfO₂ CMOS devices and its application to high-k NAND flash memory." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-12-2397.

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Dy-incorporated HfO₂ gate oxide with TaN gate electrode nMOS device has been developed for high performance CMOS applications in 22nm node technology. DyO /HfO bi-layer structure shows thin EOT with reduced leakage current and less charge trapping compared to HfO₂. Excellent electrical performance of the DyO-capped HfO₂ oxide n-MOSFET such as lower V[subscript TH], higher drive current, and improved channel electron mobility are reported. DyO/HfO samples also show better immunity for V[subscript TH] instability and less severe charge trapping characteristics. Its charge trapping characteristics, conduction mechanisms and dielectric reliability have been investigated in this work. As an application to memory device, HfON charge trapping layered NAND flash memory is developed and characterized. First, temperature-dependent Dy diffusion and the diffusion-driven Dy dipole formation process are discussed to clarify the origin of V[subscript TH] shift, and eventually modulate the effective work function in Dy-Hf-O/SiO₂ system. The Dy-induced dipoles are closely related to the Dy-silicate formation at the high-k/SiO₂ interfaces since the V[subscript FB] shift in Dy₂O₃ is caused by the dipole and coincides with the Dy-silicate formation. Dipole formation is a thermally activated process, and more dipoles are formed at a higher temperature with a given Dy content. The Dy-silicate related bonding structure at the interface is associated with the strength of the Dy dipole moment, and becomes dominant in controlling the V[subscript FB]/V[scubscript TH] shift during high temperature annealing in the Dy- Hf-O/SiO₂ gate oxide system. Dy-induced dipole reduces the degradation of the electron mobility. Second, to understand the reduced leakage current of the DyO/HfO sample, the effective barrier height of Dy₂O₃ was calculated from FN tunneling models, and the band diagram was estimated. The higher effective barrier height of Dy₂O₃, which is around 2.32 eV calculated from the F-N plot, accounts for the reduced leakage current in Dy incorporated HfO₂ nMOS devices. The lower barrier height of HfO₂ result in increased electron tunneling currents enhanced by the buildup of hole charges trapped in the oxide, which causes a severe increase of stress-induced leakage current (SILC), leading to oxide breakdown. However, the increased barrier height in Dy incorporated HfO₂ inhibits a further increase of the electron tunneling from the TaN gate, and trapped holes lessen the hole tunneling currents, resulting in a negligible SILC. The lower trap generation rate by the reduced hole trap density and the reduced hole tunneling of the Dy-doped HfO₂ dielectric demonstrates the high dielectric breakdown strength by weakening the charge trapping and defect generation during the stress. Based on these fundamental studies of the dielectric breakdown, modeling of time-dependent dielectric breakdown (TDDB) was done. The intrinsic TDDB of the Dy-doped HfO₂ gate oxide having 1 nm EOT is characterized by the progressive breakdown (PBD) model. At high temperature, the PBD becomes severe, since thermal energy causes carrier hopping between the localized weak spots. The voltage acceleration factor derived from the power law shows a realistic prediction in comparison with those from the 1/E model. The increase of the voltage acceleration factor at lower stress voltage is due to the lower trap generation rate in Dy- incorporated HfO₂. This voltage acceleration factor can be easily extended to include temperature dependency, and the effective activation energy derived from the power law is voltage dependent. Lastly, I studied the device characteristics of thin HfON charge-trap layer nonvolatile memory in a TaN/Al₂O₃/HfON/SiO₂/p-Si (TANOS) structure. A large memory window and fast erase speed, as well as good retention time, were achieved by using the NH₃ nitridation technique to incorporate nitrogen into the thin HfO₂ layer, which causes a high electron-trap density in the HfON layer. The higher dielectric constant of the HfON charge-trap layer induces a higher electric field in the tunneling oxide at the same voltage compared to non-nitrided films and, thus, creates a high Fowler-Nordheim (FN) tunneling current to increase the erase and programming speed. The trap-level energy in the HfON layer was calculated by using an amphoteric model.
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25

Liu, Te-Chiang, and 劉得強. "Operation Characteristic of Charge-Trapping-type Flash Memory Device with Charge-trapping layer of stacked dielectrics." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/48553041687300820363.

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26

Yang, Dong-Wei, and 楊東偉. "Investigation of MoN Metal-gate and Stacked Dielectric Layer Applied on SONOS-type Flash Memory Device." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/57065096713865216135.

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27

Tsai, Jeng-Lin, and 蔡政霖. "Improved Operation of CT Flash Memory Device with Band Engineering in Blocking Layer and Trapping Layer." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/54420050407554027060.

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28

Katsuno, Ian. "SD Storage Array: Development and Characterization of a Many-device Storage Architecture." Thesis, 2013. http://hdl.handle.net/1807/42978.

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Transactional workloads have storage request streams consisting of many small, independent, random requests. Flash memory is well suited to these types of access patterns, but is not always cost-effective. This thesis presents a novel storage architecture called the SD Storage Array (SDSA), which adopts a many-device approach. It utilizes many flash storage devices in the form of an array of Secure Digital (SD) cards. This approach leverages the commodity status of SD cards to pursue a cost-effective means of providing the high throughput that transactional workloads require. Characterization of a prototype revealed that when the request stream was 512B randomly addressed reads, the SDSA provided 1.5 times the I/O operations per second (IOPS) of a top-of-the-line solid state drive, provided there were at least eight requests in-flight. A scale-out simulation showed the IOPS should scale with the size of the array, provided there are no upstream bottlenecks.
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29

Lin, Steven, and 林東陽. "Program Charge Effect on Random Telegraph Noise Amplitude and Its Device Structural Dependence in SONOS Flash Memory." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/9nqs24.

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碩士
國立交通大學
電子研究所
98
Nitride program charge effect on the amplitude of random telegraph noise (RTN) in SONOS flash cells is investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitudes after programming while a floating gate flash cell has identical RTN amplitudes in erase and program states. The spread of program-state RTN in a planar SONOS is attributed to a current-path percolation effect caused by random discrete nitride charges. Consequently, program charge effect has to be taken into consideration while establishing RTN model in SONOS. The RTN amplitude spread can be significantly reduced in a surrounding gate structure, such as FinFET SONOS, due to a higher degree of symmetry in a program charge distribution.
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30

Lai, Sin-Hong, and 賴信宏. "Characteristic Analysis of SiN Gate Dielectric Layer MIS-HEMT Device and Investigation of MOS-HEMT Flash Memory." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/24505796689449958478.

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碩士
龍華科技大學
電子工程系碩士班
103
Gallium nitride compared with other materials has the advantage with wide bandgap, high breakdown electric field and high electron saturation velocity, etc. Gallium nitride is a good material for high power, high frequency and optics applications. Metal semiconductor junction high electron mobility transistor can't effectively suppress gate leakage current in high bias due to its limited barrier height properties. Therefore, we adopt metal oxide semiconductor structure high electron mobility transistors to reduce gate leakage and surface states density. In this thesis, we proposed in-situ silicon nitride as gate dielectric layer, and changed deposition conditions of silicon nitride to investigate the variety of deposition conditions of silicon nitride thin film for effect of device performance. Conventionally AlGaN/GaN HEMT device which operating mode is the depletion mode. Depletion mode of device for circuit design has high complexity and fail-safe problem in high power operation. For this reason, there are some methods to make device in enhancement mode. In this thesis, we proposed charge trapping method to confine electrons in the charge storage layer, to change space charge of device, so that threshold voltage toward positive voltage shift.
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31

Huang, Chien Pang, and 黃建邦. "Characteristics of Germanium Buried Channel and Low-Temperature Formed Stacked Trapping Layers on Poly Silicon Nanowire Flash Memory device." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/s89f6w.

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碩士
國立清華大學
工程與系統科學系
104
With the recent development of Big Data, the demand of nonvolatile memory increases rapidly. Therefore, nonvolatile memory devices of high storage density with high performance and reliability are necessary. In order to improve the efficiency, high- concentration germanium buried channel is considered as a promising way to enhance the performance, while preserving the scaling-down ability. This thesis proposes an implementation of Ge buried channel on the surface of poly silicon nanowire channels and investigates its electrical characteristics. Three experiments are carried out to test the performance of flash memory devices with the proposed the IM and JL mode components. In the first experiment, germanium is grown on nanowire channel of inversion mode flash memory device. Three different conditions are compared: 1) the growth of Ge and silicon cap-layer, 2) the growth of SiGe and silicon cap-layer, and 3) devices without any growth. Results show that devices with Ge growth have the fast programming and erasing speed. No obvious differences of retention characteristics were seen among the three conditions. The devices with epitaxial growth (condition 1 & 2) exhibit better endurance characteristics because their faster P/E speed reduces the damage of tunneling layer. The second experiment studies low temperature formed HfO2/SiNx stacked trapping layer on three channel structures described in the first experiment. The nitride thin film was deposited by inductively coupled plasma chemical vapor deposition at 450 ℃ in order to reduce thermal cycles in fabrication processes of the devices with Ge containing, which achieves the enhancement of P/E speed and endurance. Results of the second experiment show that the low temperature formed HfO2/SiNx stacked trapping layer can further improve the retention characteristics as compared to results in the first experiment. The third experiment investigates junctionless nanowire flash memory devices with stacked trapping layer in the second experiment. The junctionless devices with Ge buried channel and those without ones are compared. Results show that whatever modes (JL / IM) they are, the program, erase speed and endurance performance can be effectively improved by buried channel. The retention characteristics of devices with buried channels can be still similar as compared to those without ones.
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32

Liu, Yueran 1975. "Novel flash memory with nanocrystal floating gate." Thesis, 2006. http://hdl.handle.net/2152/2819.

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33

Tsung-HanLu and 呂宗翰. "Reliability of Devices in NAND Flash Memory Periphery Circuitry." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/80883942352840542816.

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碩士
國立成功大學
微電子工程研究所碩博士班
101
Recent years, NAND flash storage drive is one of the most important products used in mobile electric products. The NAND Flash device is with the advantages which are high integrated and fast storage speed. The main purpose of this thesis is about the reliability studies of NAND Flash Periphery devices. Since the NAND flash needs high voltage around 18V during program / erase operation, The Devices in NAND Flash Memory Periphery Circuitry in this thesis is word-line driver circuits, the devices have to pass high voltage from superior circuit to cell devices. The first part research in this thesis focused on the reliability issue which took place in the transition of the devices from OFF-state to ON-state, and last part, we discussed the impact of reliability on different channel length devices. The second stage is the word-line driver circuit which used enhanced-mode NMOSFET. The devices operated in the transition from OFF-state to ON-state incessantly. In this switching process, the devices will be operated at high VDS and high VBS. From the experimental results, there is a critical impact ionization in the drain side drift region which caused by hot-carrier effect when device operated at high VDS, it will induced that interface state (Nit) are generate in the Si/SiO2 surface and cause IDlin degradation. The experimental results are verified by TCAD simulation. On the other hand, the vertical electric field inside device will increase when device operated at high VBS and induced secondary impact ionization below the region of channel and drift region, this mechanism will cause more carrier generation and may cause electrons injection into gate oxide, and resulting in the formation of defects inside the gate oxide, the gate control of the channel decreased and caused VTH increased. The other part of this thesis, we research the different channel length of for the impact of the reliability of devices. We stressed the devices which are different channel length devices, as the experimental results, the degraded mechanism in different channel length devices are the same, and as we expected that the sustainable capability of the short-channel device is relatively poor, in short channel devices, IDlin degradation and VTH shift are relatively large. Besides, we defined the lifetime of devices and summarized the influence of different channel the length on the lifetime.
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34

Sarkar, Joy 1977. "Non-volatile memory devices beyond process-scaled planar Flash technology." Thesis, 2007. http://hdl.handle.net/2152/3666.

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Mainstream non-volatile memory technology dominated by the planar Flash transistor with continuous floating-gate has been historically improved in density and performance primarily by means of process scaling, but is currently faced with significant hindrances to its future scaling due to fundamental constraints of electrostatics and reliability. This dissertation is based on exploring two pathways for circumventing scaling limitations of the state-of-the-art Flash memory technology. The first part of the dissertation is based on demonstrating a vertical Flash memory transistor with nanocrystal floating-gate, while the second part is based on developing fundamental understanding of the operation of Phase Change Memory. A vertical Flash transistor can allow the theoretical minimum cell area and a nanocrystal floating-gate on the sidewalls is shown to allow a thinner gate-stack further conducive to scaling while still providing good reliability. Subsequently, the application of a technique of protein-mediated assembly of preformed nanocrystals to the sidewalls of the vertical Flash transistor is also demonstrated and characterized. This technique of ordering pre-formed nanocrystals is beneficial towards achieving reproducible nanocrystal size uniformity and ordering especially in a highly scaled vertical Flash cell, rendering it more amenable to scaling and manufacturability. In both forms, the vertical Flash memory cell is shown to have good electrical characteristics and reliability for the viability of this cell design and implementation. In the remaining part of this dissertation, studies are undertaken towards developing fundamental understanding of the operational characteristics of Phase Change Memory (PCM) technology that is expected to replace floating-gate Flash technology based on its potential for scaling. First, a phenomenon of improving figures of merit of the PCM cell with operational cycles is electrically characterized. Based on the electrical characterization and published material characterization data, a physical model of an evolving "active region" of the cell is proposed to explain the improvement of the cell parameters with operational cycles. Then, basic understanding is developed on early and erratic retention failure in a statistically significant number of cells in a large array and, electrical characterization and physical modeling is used to explain the mechanism behind the early retention failure.
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35

陳佳壕. "Research of Silicon Nitride layer on SONOS Flash Memory Devices." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/tpg683.

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36

Shun-Tai, Chung, and 鍾順泰. "A study of simulation and analysis in flash memory devices." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/71048223645530066343.

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碩士
大葉大學
電機工程研究所
86
In submicronmeter flash memory devices, the almost injection models for programming operation is no more accurate to evaluate injection current.Therefor, we will present a novel model to simulate the charge injection in the flash momory. For erasing operation, a well-known model, F-N Electron Tunneling Model,will be used during theoretical simulation.
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37

Moreira, André Ricardo Araújo. "Reliability study of advanced 2T-FNFN-NOR embedded memory devices." Master's thesis, 2009. http://hdl.handle.net/10216/66710.

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Estágio realizado na NXP Semiconductor, Nijmegen (Holanda) e orientado pelo Doutor Guoqiao Tao
Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
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38

Moreira, André Ricardo Araújo. "Reliability study of advanced 2T-FNFN-NOR embedded memory devices." Dissertação, 2009. http://hdl.handle.net/10216/66710.

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Estágio realizado na NXP Semiconductor, Nijmegen (Holanda) e orientado pelo Doutor Guoqiao Tao
Tese de mestrado integrado. Engenharia Electrotécnica e de Computadores (Major Telecomunicações). Faculdade de Engenharia. Universidade do Porto. 2009
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39

Tang, Shan 1975. "Protein-mediated nanocrystal assembly for floating gate flash memory fabrication." 2008. http://hdl.handle.net/2152/18156.

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As semiconductor device scaling is reaching the 45 nm node, the need for novel device concept, architecture and new materials has never been so pressing as today. Flash memories, the driving force of semiconductor memory market in recent years, also face the same or maybe more severe challenges to meet the demands for high-density, low-cost, low-power, high-speed, better endurance and longer retention time. As traditional continuous floating gate flash struggles to balance the trade-off between high speed and retention requirement, nanocrystal (NC) floating gate flash has attracted more and more interest recently due to its advantages over traditional flash memories in many areas such as better device scaling, lower power consumption and improved charge retention. However, there are still two major challenges remaining for embedded NC synthesis: the deposition method and the size and distribution control. Nowadays using bio-nano techniques such as DNA, virus or protein for NC synthesis and assembly has become a hot topic and feasible for actual electronic device fabrication. In this dissertation a new method for NC deposition wherein a colloidal suspension of commercially-available NCs was organized using a self-assembled chaperonin array. The chaperonin array was applied as a scaffold to mediate NCs into an assembly with uniform spatial distribution on Si wafers. By using this method, we demonstrated that colloidal PbSe and Co NCs in suspension can self-assemble into ordered arrays with a high density of up to 10¹²cm⁻². MOSCAP and MOSFET memory devices were successfully fabricated with the chaperonin protein mediated NCs, showing promising memory functions such as a large charge storage capacity, long retention time and good endurance. The charge storage capacity with respect to material work function, NC size and density was explored. In addition to NC engineering, the tunnel barrier was engineered by replacing traditional SiO₂ by high-k material HfO₂, giving a higher write/erase speed with a reduced effective oxide thickness (EOT). Suggestions for future research in this direction are presented in the last part of this work.
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40

Lu, Kuo-Yuan, and 呂國源. "Characteristics and Investigation of Next Generation Low Power Flash Memory Devices." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/68773591165143247998.

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碩士
國立交通大學
電子工程系所
94
For the system-on-chip (SOC) application, a continuously scaling of the gate dielectrics for complementary metal oxide semiconductor (CMOS) and inter-poly dielectrics (IPDs) for electrically-erasable programmable read-only-memory (EEPROM) and stacked-gate flash memory is needed to obtain high density and low operation voltage. But when oxide thickness is less than 10 nm, the charge stored in the floating gate forming leakage path easily due to defects in the oxide, thus induces data error. To overcome the limits of the conventional FG structure, other kinds of nonvolatile memories such as SONOS and nanocrystal memories which stored electrons in discrete traps are mostly mentioned, hence several characteristics such as scaling down and good storage maintenance can be reached. In this thesis, we successfully fabricated nanocrystal memory devices by using different high-k materials. First, a praseodymium oxide (PrO2) layer was deposited on the oxide by Dual E-gun Evaporation System with Praseodymium oxide targets. After that, the wafer was subjected to RTA treatment in O2 ambient at 900℃ for 1 minute. When the film is RTA treated to provide enough energy and surface mobility, the thin Praseodymium oxide will self-assemble into nano dot. By using this method, we obtains nonvolatile memory devices with excellent characteristics: low applied voltages, large memory window, high program/erase speed, fine endurance. And, we can use these devices in 2-bit operations. Consequently, we consider, it is potential material as nanocrystal memory devices by using PrO2. A Lanthanum aluminate (LaAlO3) layer was also deposited on the oxide by Dual E-gun Evaporation System with Praseodymium oxide targets. We obtain similar results after our measurements: low applied voltages, large memory window, high program/erase speed, fine endurance. it is potential candidate as nanocrystal memory devices by using LaAlO3.
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41

Li, Hao Chieh, and 李豪捷. "Chemical Dry Etching and N2O anneal on SONOS Flash Memory Devices." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/81590781610269005168.

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42

Shih, Jui-Lung, and 施瑞隆. "The Design of Flash Memory Data Management for Portable Storage Devices." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/78694437101664778264.

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碩士
國立中正大學
資訊工程研究所
91
Flash memory has attractive features such as shock resistance, low power consumption, non-volatility, small size, light weight, and fast access speed. However, it has drawbacks such as a write-once/bulk-erase device, no in-place update, and limited erase cycles. Because of so many advantages, flash memory always plays the part of data storage systems in mobile devices and embedded systems. Meanwhile, digital content is getting more and more important in our life. The issues of usage rights management of digital content are usually discussed. Therefore, we propose a new system for managing digital content. Moreover, flash memory is used popularly for storing digital content. We focus on the performance and the reliability of flash memory. Furthermore, we propose a new architecture of using multiple buses and ECC groups. The multiple buses architecture is for improving the I/O performance of flash memory. And the ECC groups on flash memory are for recovering more errors and providing higher reliability.
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43

YU-LUN-HU and 胡毓倫. "A Data Sanitization Method for Mobile Devices with NAND Flash Memory." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/6j6ba7.

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碩士
國立臺灣科技大學
電子工程系
106
Recently, NAND flash memory has been widely used in wearable mobile devices. Data erasure is one of most important issue in Wearable Mobile Devices, the instruction of deletion from file system is not able to delete data completely in NAND flash memory, it still can use data recovery software to recover data. In the thesis, first, we will introduce NAND Flash Memory, and then we will proposes an application with various algorithm and compare each algorithm. In the end, we will conclude an algorithm which can delete data completely in NAND flash memory.
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44

Yao, Yu-Yuan, and 姚裕源. "A Novel Coupling-Ratios Extraction Technique for Split-Gate Flash Memory Devices." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/02331943560174352650.

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碩士
國立清華大學
電機工程學系
87
Today, no practical coupling ratios extracting technique is proposed in split-gate Flash memory. But there are many proposed coupling ratios extraction methods for stacked-gate Flash memory. The main differences between split-gate and stacked-gate Flash memory are the special control-gate structure (split structure) and read operation (no threshold voltage definition) of split-gate Flash memory. So many coupling ratios extracting technique in stacked-gate Flash memory are not suitable for split-gate Flash memory. This paper introduces a novel coupling ratios extracting technique to extract the most important coupling ratios, control-gate coupling ratio and source coupling ratio, of split-gate Flash memory. From the source side Constant Ramp Rate Programming (CRRP) method, we can extract the source coupling ratio. According to the simulation results of MEDICI 2D potential contour distribution, when the device is under programming operation, after the floating-gate potential reaching the convergent point, the bulk voltage has no influence on the surface potential distribution in the region under the floating-gate. And the depletion region of high voltage source replaces the contact area of bulk to floating-gate. The coupling ratio of bulk is small enough to be negelected. According to the capacitance model of split-gate device, and the assumption of bulk couplig ratio is small under programming operation, control-gate coupling ratio and source coupling ratio are knowen. Based on these coupling ratios, we can construct the electrical model of split-gate Flash memory. The electrical model is useful in improveing the device''s characteristic and operation condition of split-gate Flash memory. And it will play a important role in the design of next generation device in the future. Accroding to the experimential results, a new coupling ratio extraction scheme is proposed for spilt-gate Flash memories with advantages of : 1. In sti extraction under programming operation 2. Feasible extracting measurement 3. De-couple the source coupling ratio from the others 4. Insensitive to measuring parameters 5. Reflection of devices'' geometric dimensions
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45

Tseng, Der-Jang, and 曾德彰. "A Study of Characterization and Analysis in P-Channel Flash Memory Devices." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/32845505898014326879.

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碩士
大葉大學
電機工程研究所
87
Abstract The flash memory is a better choice than others in the nonvolatile memory market, therefore, it will be much valuable for us to investigate its characteristics, and there are lots of researches about it. Recently, the research of flash memory, the focus is always concentrated on the threshold voltage shift due to programming or erasing operation, data retention time, data endurance, programming efficiency, erasing speed, and so on. This benifits higher device reliability, speed, and integrity. The nonvolatile memory devices have the capability to store the informations. The most used programming method is F-N tunneling scheme or channel-hot-electron(CHE) scheme overcoming the floating gate barrier. It is very convenient for N-channel flash memory to program by positive gate bias. So that P-channel flash memory is less attracted to researchers. The data storage is mainly determined by the charges on the floating gate. Such that if the change of charge on the floating gate can be accurate to predict, then the shifting of devices threshold voltage and the data storage or not can be discriminated. Therefore in this thesis, we will investigate the threshold voltage alteration during the programming and erasing operation of the submicron P-channel flash memory. And, a comparison in both types is also maded. In this submicronmeter P-channel flash memory devices, the programming model, which is called Channel-Hot-Hole-Induced-Hot-Electron Current Model, to simulate the charge injection in the flash memory is used. For erasing operation, a well-known model, Fowler-Nordheim Electron Tunneling Model, will be used during theoretical simulation.
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46

Hong, Peng-Yun, and 洪鵬雲. "Research on the Flash Memory Management and Cleaning Policies in Mobile Devices." Thesis, 2001. http://ndltd.ncl.edu.tw/handle/53970614320165445036.

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碩士
國立暨南國際大學
資訊管理學系
89
Since flash memory has some attractive features, such as low power consumption, non-volatility, shock resistance, high data density, therefore, it is good for mobile devices. Furthermore, with advanced semi-conductor manufacture technology, flash memory is becoming larger and faster, so it is promising to replace Hard disk drives in most applications. However, flash memory comes with some hardware restrictions, such as requiring erasure before it can be rewritten and can be erased only a limited number of times.So a new storage management schema is needed for maintaining the flash memory. In this thesis, we design a new storage management system to solve the non-rewritable problem and reduce the number of erase times for power saving and ensure longer flash memory lifetime
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Khan, Faraz I. "Endurance characterization and improvement of floating gate semiconductor memory devices." 2009. http://hdl.rutgers.edu/1782.2/rucore10001600001.ETD.000051734.

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48

Shiu, Feng-Wen, and 許逢文. "Effects of Stacked High-k Blocking Layer on Charge-Trapping Flash Memory Devices." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/09742273730644922957.

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碩士
國立清華大學
工程與系統科學系
98
When floaging gate device can't satisfy smaller device, SONOS-Type is the one of candidate to replace it. SONOS-Type device tunneling layer thickness is about 30A ,it is a problem for retention. How to improve our device performance is very important. In our experiment, using various high-k dielectrics as stacked SONOS-Type blocking layer. Different materials has different performances , matching stacked structure by nitrogen treatment with distinct doses(2mins , 4mins, 8mins) , bandgap-engineering, k-value as a excellent blocking oxide layer. For tunneling oxide, the application of multilayer dielectric stacks is promising to realize tunnel barrier engineering. With a suitable combination of stacked tunneling oxide(low-k/high-k),a lower operation voltage can be achieve. Using Al2O3/HfAlO as blocking layer has better performance than other stacked structures. Take high bandgap material as first layer blocking layer ,and secondly stack higher k material can improve device performance. Stacking a high quality film as blocking layer first and then stack various high-k materials by PIII nitrogen treatment can reduce crystallize and enhance retention , promote device reliability after high temperature annealing process.
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49

Wang, Szu-Yu, and 王嗣裕. "Reliability and Processing Effects of Bandgap Engineered SONOS (BE-SONOS) Flash Memory Devices." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/40805732839760983092.

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博士
國立清華大學
電子工程研究所
96
電荷捕捉記憶體元件預期將成為快閃記憶體於40奈米以下世代產品的解決方案。於1960年代末期發明之矽-氧-氮-氧-矽(SONOS)元件就是其中一種型態的電荷捕捉記憶體元件。該種元件是將電荷儲存在氮化矽材料當中。然而,傳統的SONOS記憶體元件存在著一種應用上的限制,就是我們無法找到一個合適的穿隧氧化層厚度來同時達到優良的抹除速度以及資料保存能力。 最近這幾年一種新的電荷捕捉快閃記憶體元件被提出具有克服傳統SONOS元件應用上限制的能力。該種記憶體元件稱作能帶隙工程矽-氧-氮-氧-矽(BE-SONOS)元件。在採用非常薄的氧-氮-氧穿隧阻障層(一般來說各層厚度約在13/20/25 埃)的情況下,高電場下的電荷穿隧距離會因為能帶隙消除效應而有效降低。此時幾乎僅存第一層超薄氧化層扮演有效之電荷穿隧障礙,因此大大提高了電洞穿隧電流。另一方面當電荷儲存狀態的低電場條件下,不論電子自儲存層中逸失或是電洞穿隧進入儲存層之能力皆會因為整個氧-氮-氧穿隧阻障層的阻擋而顯著降低。 本論文將針對此新開發的BE-SONOS記憶體元件在基本元件概念、各介電層之製程效應、電荷捕捉層工程效應、以及介電層微縮能力在可靠度特性上之研究提供詳細的說明。從這些研究結果我們認為在次世代的非揮發性記憶體,特別是資料儲存式快閃記憶體(NAND Flash)的應用上,BE-SONOS是目前電荷捕捉記憶體元件當中的最佳解決方案。
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50

Chun-PoChang and 張鈞博. "Breakdown Voltage and Reliability Studies of Devices in NAND Flash Memory Periphery Circuitry." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/58759552904041180838.

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Abstract:
碩士
國立成功大學
微電子工程研究所
102
In this thesis, we study the high-voltage device which is depletion-mode lateral diffused metal-oxide-semiconductor (LDMOS). The HV device in the periphery circuit is applied to NAND Flash Cell for Program/Erase operation. In periphery circuit, the high off-state breakdown voltage (off-state VBD) is an important requirement for this device. Therefore, the LDMOS breakdown mechanism with different BF2 implant by varying implant dosage in N- region is investigated. As expected, the off-state breakdown voltage increase with the raise of BF2 concentration. Experimental data and technology computer aided design simulations show that gate-induced-drain-leakage (GIDL) and PN junction breakdown are responsible for the variation of breakdown voltage. Moreover, in the circuit operating environment, there might be hot carrier degradation in the device. The damage will happen while device is programming or erasing data. Generally, the ISUB peak will be the index of the HCI degradation. However, in our study, the measurement results contradict pervious study because the distribution of the impact ionization peak would dominant the hot carrier degradation instead of the amount of the ISUB current. The impact ionization which is located near drain side is greater with higher BF2 concentration. In conclusion, the device with higher BF2 implant suffers worse HCI degradation because of more high energy carrier injection. According to the results in this study, care should be taken when we implant the BF2 into the drift region, since there is a trade-off between VBD and HCI reliability issue.
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