Relevant bibliographies by topics / Flash Memory Device

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Flash Memory Device'

Author: Grafiati
Published: 6 September 2023

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Journal articles on the topic "Flash Memory Device"

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Abdullah, Dhuha, and Reyath Mahmood. "Design Flash Memory Programmer Device." AL-Rafidain Journal of Computer Sciences and Mathematics 3, no. 1 (July 1, 2006): 55–83. http://dx.doi.org/10.33899/csmj.2006.164045.

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Alahmadi, Abdulhadi, and Tae Sun Chung. "RSLSP: An Effective Recovery Scheme for Flash Memory Leveraging Shadow Paging." Electronics 11, no. 24 (December 10, 2022): 4126. http://dx.doi.org/10.3390/electronics11244126.

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The flash storage is a non-volatile semiconductor device that is constantly powered and has several advantages such as small size, lower power consumption, fast access, convenient portability, heat dissipation, shock resistance, data retention next to a power off, and random access. Flash memory is presently being incorporated with distinct embedded system devices such as with digital cameras, smart phones, personal digital assistants (PDA), and sensor devices. Nevertheless, a flash memory entails special features such as “erase-before-write” and “wear-leveling”, an FTL (flash translation layer) upon the software layer should be included. Although, the power off recovery plays a significant role in portable devices, most FTL algorithms did not consider the power off recovery scheme. In this paper, we proposed an effective scheme for the recovery of flash memory leveraging the shadow paging concept for storage devices using flash memory. To combat the sudden power off problem, the suggested RSLSP approach saves and keeps the map block data as a combination of two tables, i.e., first is the original block and the second block is a replica for the original one. Our proposed strategy not only improves the capacity of a flash memory device as compared to the state-of-the-art schemes suggested in the literature, but is also compatible with the existing FTL-based schemes.
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Han, Hoonhee, Seokmin Jang, Duho Kim, Taeheun Kim, Hyeoncheol Cho, Heedam Shin, and Changhwan Choi. "Memory Characteristics of Thin Film Transistor with Catalytic Metal Layer Induced Crystallized Indium-Gallium-Zinc-Oxide (IGZO) Channel." Electronics 11, no. 1 (December 24, 2021): 53. http://dx.doi.org/10.3390/electronics11010053.

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The memory characteristics of a flash memory device using c-axis aligned crystal indium gallium zinc oxide (CAAC-IGZO) thin film as a channel material were demonstrated. The CAAC-IGZO thin films can replace the current poly-silicon channel, which has reduced mobility because of grain-induced degradation. The CAAC-IGZO thin films were achieved using a tantalum catalyst layer with annealing. A thin film transistor (TFT) with SiO2/Si3N4/Al2O3 and CAAC-IGZO thin films, where Al2O3 was used for the tunneling layer, was evaluated for a flash memory application and compared with a device using an amorphous IGZO (a-IGZO) channel. A source and drain using indium-tin oxide and aluminum were also evaluated for TFT flash memory devices with crystallized and amorphous channel materials. Compared with the a-IGZO device, higher on-current (Ion), improved field effect carrier mobility (μFE), a lower body trap (Nss), a wider memory window (ΔVth), and better retention and endurance characteristics were attained using the CAAC-IGZO device.
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Kostadinov, Hristo, and Nikolai Manev. "Integer Codes Correcting Asymmetric Errors in Nand Flash Memory." Mathematics 9, no. 11 (June 1, 2021): 1269. http://dx.doi.org/10.3390/math9111269.

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Memory devices based on floating-gate transistor have recently become dominant technology for non-volatile storage devices like USB flash drives, memory cards, solid-state disks, etc. In contrast to many communication channels, the errors observed in flash memory device use are not random but of special, mainly asymmetric, type. Integer codes which have proved their efficiency in many cases with asymmetric errors can be applied successfully to flash memory devices, too. This paper presents a new construction and integer codes over a ring of integers modulo A=2n+1 capable of correcting single errors of type (1,2),(±1,±2), or (1,2,3) that are typical for flash memory devices. The construction is based on the use of cyclotomic cosets of 2 modulo A. The parity-check matrices of the codes are listed for n≤10.
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Tsoukalas, Dimitris, and Emanuele Verrelli. "Inorganic Nanoparticles for either Charge Storage or Memristance Modulation." Advances in Science and Technology 77 (September 2012): 196–204. http://dx.doi.org/10.4028/www.scientific.net/ast.77.196.

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We present prototype memory devices using metallic and metal oxide nanoparticles obtained by a physical deposition technique. The two memory device examples demonstrated concern the use of platinum nanoparticles for flash-type memories and the use of titanium oxide nanoparticles for resistive memories. Both approaches give interesting device memory properties with resistive memories being still in an early exploratory phase.
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Xu, Guangxia, Lingling Ren, and Yanbing Liu. "Flash-Aware Page Replacement Algorithm." Mathematical Problems in Engineering 2014 (2014): 1–11. http://dx.doi.org/10.1155/2014/136246.

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Due to the limited main memory resource of consumer electronics equipped with NAND flash memory as storage device, an efficient page replacement algorithm called FAPRA is proposed for NAND flash memory in the light of its inherent characteristics. FAPRA introduces an efficient victim page selection scheme taking into account the benefit-to-cost ratio for evicting each victim page candidate and the combined recency and frequency value, as well as the erase count of the block to which each page belongs. Since the dirty victim page often contains clean data that exist in both the main memory and the NAND flash memory based storage device, FAPRA only writes the dirty data within the victim page back to the NAND flash memory based storage device in order to reduce the redundant write operations. We conduct a series of trace-driven simulations and experimental results show that our proposed FAPRA algorithm outperforms the state-of-the-art algorithms in terms of page hit ratio, the number of write operations, runtime, and the degree of wear leveling.
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Poudel, Prawar, Biswajit Ray, and Aleksandar Milenkovic. "Microcontroller Fingerprinting Using Partially Erased NOR Flash Memory Cells." ACM Transactions on Embedded Computing Systems 20, no. 3 (April 2021): 1–23. http://dx.doi.org/10.1145/3448271.

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Electronic device fingerprints, unique bit vectors extracted from device's physical properties, are used to differentiate between instances of functionally identical devices. This article introduces a new technique that extracts fingerprints from unique properties of partially erased NOR flash memory cells in modern microcontrollers. NOR flash memories integrated in modern systems-on-a-chip typically hold firmware and read-only data, but they are increasingly in-system-programmable, allowing designers to erase and program them during normal operation. The proposed technique leverages partial erase operations of flash memory segments that bring them into the state that exposes physical properties of the flash memory cells through a digital interface. These properties reflect semiconductor process variations and defects that are unique to each microcontroller or a flash memory segment within a microcontroller. The article explores threshold voltage variation in NOR flash memory cells for generating fingerprints and describes an algorithm for extracting fingerprints. The experimental evaluation utilizing a family of commercial microcontrollers demonstrates that the proposed technique is cost-effective, robust, and resilient to changes in voltage and temperature as well as to aging effects.
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Huang, Bai Yi. "A New Write Caching Algorithm for Solid State Disks." Advanced Materials Research 341-342 (September 2011): 700–704. http://dx.doi.org/10.4028/www.scientific.net/amr.341-342.700.

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Flash-based solid state disks (SSD) is a performance based data storage technology that optimizes the use of flash-based technology to implement its data storage capabilities compared with mechanically available data storage technologies. It has been argued in theory and practice that SSD devices are better performers compared with mechanical devices. To improve the efficiency of a flash memory SSD device, it is important for it to be designed to be computationally support parallel operations.
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Wang, Lei, CiHui Yang, Jing Wen, and Shan Gai. "Emerging Nonvolatile Memories to Go Beyond Scaling Limits of Conventional CMOS Nanodevices." Journal of Nanomaterials 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/927696.

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Continuous dimensional scaling of the CMOS technology, along with its cost reduction, has rendered Flash memory as one of the most promising nonvolatile memory candidates during the last decade. With the Flash memory technology inevitably approaching its fundamental limits, more advanced storage nanodevices, which can probably overcome the scaling limits of Flash memory, are being explored, bringing about a series of new paradigms such as FeRAM, MRAM, PCRAM, and ReRAM. These devices have indeed exhibited better scaling capability than Flash memory while also facing their respective physical drawbacks. The consequent tradeoffs therefore drive the information storage device technology towards further advancement; as a result, new types of nonvolatile memories, including carbon memory, Mott memory, macromolecular memory, and molecular memory have been proposed. In this paper, the nanomaterials used for these four emerging types of memories and the physical principles behind the writing and reading methods in each case are discussed, along with their respective merits and drawbacks when compared with conventional nonvolatile memories. The potential applications of each technology are also briefly assessed.
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Jung, Sang-Goo, and Jong-Ho Lee. "Flash Memory Device with `I' Shape Floating Gate for Sub-70 nm NAND Flash Memory." Japanese Journal of Applied Physics 45, No. 45 (November 10, 2006): L1200—L1202. http://dx.doi.org/10.1143/jjap.45.l1200.

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Dissertations / Theses on the topic "Flash Memory Device"

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Mih, Thomas Attia. "A novel low-temperature growth method of silicon structures and application in flash memory." Thesis, De Montfort University, 2011. http://hdl.handle.net/2086/5183.

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Flash memories are solid-state non-volatile memories. They play a vital role especially in information storage in a wide range of consumer electronic devices and applications including smart phones, digital cameras, laptop computers, and satellite navigators. The demand for high density flash has surged as a result of the proliferation of these consumer electronic portable gadgets and the more features they offer – wireless internet, touch screen, video capabilities. The increase in the density of flash memory devices over the years has come as a result of continuous memory cell-size reduction. This size scaling is however approaching a dead end and it is widely agreed that further reduction beyond the 20 nm technological node is going to be very difficult, as it would result to challenges such as cross-talk or cell-to-cell interference, a high statistical variation in the number of stored electrons in the floating gate and high leakage currents due to thinner tunnel oxides. Because of these challenges a wide range of solutions in form of materials and device architectures are being investigated. Among them is three-dimensional (3-D) flash, which is widely acclaimed as the ideal solution, as they promise the integration of long-time retention and ultra-high density cells without compromising device reliability. However, current high temperature (>600 °C) growth techniques of the Polycrystalline silicon floating gate material are incompatible with 3-D flash memory; with vertically stacked memory layers, which require process temperatures to be ≤ 400 °C. There already exist some low temperature techniques for producing polycrystalline silicon such as laser annealing, solid-phase crystallization of amorphous silicon and metal-induced crystallization. However, these have some short-comings which make them not suitable for use in 3-D flash memory, e.g. the high furnace annealing temperatures (700 °C) in solid-phase crystallization of amorphous silicon which could potentially damage underlying memory layers in 3-D flash, and the metal contaminants in metal-induced crystallization which is a potential source of high leakage currents. There is therefore a need for alternative low temperature techniques that would be most suitable for flash memory purposes. With reference to the above, the main objective of this research was to develop a novel low temperature method for growing silicon structures at ≤ 400 °C. This thesis thus describes the development of a low-temperature method for polycrystalline silicon growth and the application of the technique in a capacitor-like flash memory device. It has been demonstrated that silicon structures with polycrystalline silicon-like properties can be grown at ≤ 400 °C in a 13.56 MHz radio frequency (RF) plasma-enhanced chemical vapour deposition (PECVD) reactor with the aid of Nickel Formate Dihydrate (NFD). It is also shown that the NFD coated on the substrates, thermally decomposes in-situ during the deposition process forming Ni particles that act as nucleation and growth sites of polycrystalline silicon. Silicon films grown by this technique and without annealing, have exhibited optical band gaps of ~ 1.2 eV compared to 1.78 eV for films grown under identical conditions but without the substrate being coated. These values were determined from UV-Vis spectroscopy and Tauc plots. These optical band gaps correspond to polycrystalline silicon and amorphous silicon respectively, meaning that the films grown on NFD-coated substrates are polycrystalline silicon while those grown on uncoated substrates remain amorphous. Moreover, this novel technique has been used to fabricate a capacitor-like flash memory that has exhibited hysteresis width corresponding to charge storage density in the order of 1012 cm-2 with a retention time well above 20 days for a device with silicon films grown at 300 °C. Films grown on uncoated films have not exhibit any significant hysteresis, and thus no flash memory-like behaviour. Given that all process temperatures throughout the fabrication of the devices are less than 400 °C and that no annealing of any sort was done on the material and devices, this growth method is thermal budget efficient and meets the crucial process temperature requirements of 3-D flash memory. Furthermore, the technique is glass compatible, which could prove a major step towards the acquisition of flash memory-integrated systems on glass, as well as other applications requiring low temperature polycrystalline silicon.
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Ordosgoitti, Jorhan Rainier. "Development of a Non-Volatile Memristor Device Based on a Manganese-Doped Titanium Oxide Material." University of Toledo / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1290131827.

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Mariščák, Igor. "Mechanismus pro upgrade BIOSu v Linuxu." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2008. http://www.nusl.cz/ntk/nusl-235970.

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This work provides overview of creating of a simple driver for the BIOS flash memory by accessing the physical computer memory. Although, the BIOS is one of a system's core components, there is no standardized update mechanism approach. Purpose of thesis is to create module driver by taking advantage of existing interface subsystem MTD, to suggest and implement driver for one specific device to Linux kernel operating system. Also explains technique allowing write access to registers of the flash memory with utilization of configuration file.
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Yuen, Kam Hung. "A nano-scale double-gate flash memory /." View abstract or full-text, 2003. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202003%20YUEN.

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Cossentine, Tyler Andrew. "An efficient external sorting algorithm for flash memory embedded devices." Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/40208.

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Many embedded systems applications involve storing and querying large datasets. Existing research in this area has focused on adapting and applying conventional database algorithms to embedded devices. Algorithms designed for processing queries on embedded devices must be able to execute given the small amount of available memory and energy constraints. Sorting is a fundamental algorithm used frequently in databases. Flash memory has unique performance characteristics. Page writes to flash memory are much more expensive than reads. In addition, random reads from flash memory can be performed at nearly the same speed as sequential reads. External sorting can be optimized for flash memory embedded devices by favoring page reads over writes. This thesis describes the Flash MinSort algorithm that, given little memory, takes advantage of fast random reads and generates an index at runtime to sort a dataset. The algorithm adapts its performance to the memory available and performs best for data that is temporally clustered. Experimental results show that Flash MinSort is two to ten times faster than previous approaches for small memory sizes where external merge sort is not executable.
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Tao, Qingbo, and 陶庆波. "A study on the dielectrics of charge-trapping flash memory devices." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196488.

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Discrete charge-trapping flash memory is being developed for the next-generation commercial flash-memory applications due to its advantages over the traditional floating-gate counterpart. Currently, Si3N4 is widely used as charge-trapping layer (CTL). However, Si3N4 has low dielectric constant and small conduction-band offset with respect to the SiO2 tunneling layer, imposing limitation on further applications. Therefore, this research emphasized on investigating new dielectrics with appropriate fabrication methods to replace Si3N4 as CTL for achieving improved memory performance. Firstly, GeON CTL annealed at different temperatures was investigated. The memory device with post-deposition annealing at 600 0C exhibited the largest memory window, the best charge retention performance, and the highest reliability. These good results are due to the fact that optimal annealing temperature could suppress shallow traps and also produce new traps with desirable energy levels in the CTL. Since ZnON has a negative conduction-band offset (NCBO) with respect to Si, the traps located in the bandgap of ZnON should have deep energy levels. The memory performances of ZrON film with and without Zn doping were studied. Experimental results showed that ZrZnON film had higher program speed and better charge retention performance due to many deeper trap levels induced by the Zn doping, as well as higher erase speed due to the direct recombination of electrons at these deeper trap levels with incoming holes and the intermediary role of these deeper trap levels under erase mode. MoO3 is another NCBO dielectric with a high K value and many oxygen vacancies. La2O3, a rare-earth metal oxide, is a promising dielectric as CTL. To combine the advantages of both La2O3 and MoO3, Mo-doped La2O3 was proposed as a new CTL. Compared to the device with pure La2O3, the one with LaMoO film as CTL had significantly larger C-V hysteresis window, much higher P/E speeds, and better charge retention due to the deeper-level traps and deeper quantum wells created by the LaMoO film. Nitrogen incorporation is a popular approach to increase the trap density in the bulk of CTL. In this research, the memory performances of GdTiO films with and without nitrogen incorporation were compared. Since the nitrogen incorporation induced smaller equivalent oxide thickness, produced nitride-related traps with desirable energy level and larger cross-section for charge capture, the GdTiON film possessed better memory performance than the GdTiO film. Finally, fluorine plasma was employed to improve the quality of blocking layer. The memory device with AlOF blocking layer obtained higher program speed, better reliability and better charge retention than that based on AlO blocking layer. The improved performance was due to the fact that the fluorine incorporation passivated the defects and removed the excess oxygen in the bulk of the blocking layer. In summary, dielectric plays important roles in the performance of charge-trapping flash memory. Memory devices with GeON, ZrZnON, LaMoO, or GdTiON as charge trapping layer and AlOF as blocking layer can produce large memory window, high program/erase speed and good charge retention.
published_or_final_version
Electrical and Electronic Engineering
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Doctor of Philosophy
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Garud, Niharika Triplett Gregory Edward. "Shallow trench isolation process in microfabrication for flash (NAND) memory." Diss., Columbia, Mo. : University of Missouri-Columbia, 2008. http://hdl.handle.net/10355/5622.

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Thesis (M.S.)--University of Missouri-Columbia, 2008.
The entire dissertation/thesis text is included in the research.pdf file; the official abstract appears in the short.pdf file (which also appears in the research.pdf); a non-technical general description, or public abstract, appears in the public.pdf file. Title from title screen of research.pdf file (viewed on September 2, 2008) Includes bibliographical references.
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Chan, Chun Keung. "A study on non-volatile memory scaling in the sub-100nm regime /." View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20CHAN.

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Bryer, Bevan. "Protection unit for radiation induced errors in flash memory systems." Thesis, Stellenbosch : Stellenbosch University, 2004. http://hdl.handle.net/10019.1/50070.

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Thesis (MScEng)--University of Stellenbosch, 2004.
ENGLISH ABSTRACT: Flash memory and the errors induced in it by radiation were studied. A test board was then designed and developed as well as a radiation test program. The system was irradiated. This gave successful results, which confirmed aspects of the study and gave valuable insight into flash memory behaviour. To date, the board is still being used to test various flash devices for radiation-harsh environments. A memory protection unit (MPU) was conceptually designed and developed to morntor flash devices, increasing their reliability in radiation-harsh environments. This unit was designed for intended use onboard a micro-satellite. The chosen flash device for this study was the K9F1208XOA model from SAMSUNG. The MPU was designed to detect, maintain, mitigate and report radiation induced errors in this flash device. Most of the design was implemented in field programmable gate arrays and was realised using VHDL. Simulations were performed to verify the functionality of the design subsystems. These simulations showed that the various emulated errors were handled successfully by the MPU. A modular design methodology was followed, therefore allowing the chosen flash device to be replaced with any flash device, following a small reconfiguration. This also allows parts of the system to be duplicated to protect more than one device.
AFRIKAANSE OPSOMMING: 'n Studie is gemaak van" Flash" geheue en die foute daarop wat deur radiasie veroorsaak word. 'n Toetsbord is ontwerp en ontwikkel asook 'n radiasie toetsprogram waarna die stelsel bestraal is. Die resultate was suksesvol en het aspekte van die studie bevestig en belangrike insig gegee ten opsigte van "flash" komponente in radiasie intensiewe omgewmgs. 'n Geheue Beskermings Eenheid (GBE) is konseptueel ontwerp en ontwikkelom die "flash" komponente te monitor. Dit verhoog die betroubaarheid in radiasie intensiewe omgewings. Die eenheid was ontwerp met die oog om dit aan boord 'n mikro-satelliet te gebruik. Die gekose "flash" komponent vir die studie was die K9F1208XOA model van SAMSUNG. Die GBE is ontwerp om foute wat deur radiasie geïnduseer word in die "flash" komponent te identifiseer, herstel en reg te maak. Die grootste deel van die implementasie is gedoen in "field programmable gate arrays" and is gerealiseer deur gebruik te maak van VHDL. Simulasies is gedoen om die funksionaliteit van die ontwikkelde substelsels te verifieer. Hierdie simulasies het getoon dat die verskeie geëmuleerde foute suksesvol deur die GBE hanteer is. 'n Modulre ontwerpsmetodologie is gevolg sodat die gekose "flash" komponent deur enige ander flash komponent vervang kan word na gelang van 'n eenvoudige herkonfigurasie. Dit stelook dele van die sisteem in staat om gedupliseer te word om sodoende meer as een komponent te beskerm.
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ZAIDI, SYED AZHAR ALI. "Design of LDPC Decoder for Error Correction in Memory Devices." Doctoral thesis, Politecnico di Torino, 2015. http://hdl.handle.net/11583/2595161.

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NAND flash memories are used in large number of electronic devices for storing data. The ever increasing demand of the high storage in these devices has resulted in high density NAND flash memories. The high density is achieved through the process of continuous technology scaling and the use of multilevel cell (MLC) technology. In multilevel cell technology more than one bits are stored in a single cell of the flash memory. However, this increased storage density has come at a price of reduced reliability. The raw bit error rate has increased rapidly in high density flash memories, therefore, demanding more powerful error correcting codes. The bit error rate (BER) requirements in NAND flash memories are reported to be 10^−13 to 10^−16, after applying the error correcting code. The current practice is to use the hard decision error correcting codes in NAND flash memories, such as BCH codes. However, as the raw bit error rate is getting worse, these hard decision codes will not be able to achieve the BER requirements of these memories. Therefore, more powerful error correcting codes with soft decision decoding algorithm are required. Among the soft decision codes, low density parity check codes (LDPC) can be a promising candidate for error correction in high density NAND flash memories due to their excellent error correction performance close to the Shannon limit. LDPC codes employed in NAND flash memories have large block lengths and very high code rate and should show good error correcting and error floor performance. Evaluating the error floor performance of these codes at very low frame error rates, typically around 10^−9 to 10^−10, require the use of high speed hardware simulators. Due to the reconfigurability and high speed, field programmable gate arrays (FPGAs) are largely used for evaluating the performance of LDPC codes. This thesis presents an FPGA based simulator system for evaluating the error correction and error floor performance of regular quasi cyclic (QC) LDPC Codes, for the application of large page size MLC NAND flash memories. Particularly, we targeted the algebraic QC-LDPC codes, which have high code rates and good error correcting and error floor performance. A generalized, high throughput and resource efficient hardware implementation of the QC-LDPC encoder and the decoder is given on FPGA. The proposed decoder can decode any regular QC-LDPC code including very high circulant weight QC-LDPC codes, such as euclidean geometry (EG) LDPC codes. The generalized and high throughput implementation of such large circulant weight QC-LDPC codes is not reported previously in the open literature. Moreover, the encoder and decoder hardware implementations are given on FPGA for very large page size (8 KB) of NAND flash memory, which are also not dealt previously in the open literature. A high speed and high quality floating point additive white Gaussian noise channel is implemented on FPGA using the high level synthesis method. The high level synthesis is used to rapidly prototype the channel on FPGA and to lower the development time of the LDPC simulator system. The very low consumption of the logic resources by the channel also enabled us to instantiate many channel modules in parallel, resulting in high throughput of the simulator. This thesis also presents the FPGA implementation and simulation results of two algebraic QC-LDPC codes for the page size 8 KB of NAND flash memory. Simulation results show good error correcting and error floor performance of the developed codes making them a promising candidate for error correction in NAND flash memories.
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Books on the topic "Flash Memory Device"

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Dace, Andrea. The flash memory market. Saratoga, Calif: Electronic Trend Publications, 1993.

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Matas, Brian. Memory 1997: Complete coverage of DRAM, SRAM, EPROM, and flash memory ICs. Scottsdale, AZ: Integrated Circuit Engineering Corp., 1997.

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Non-Volatile Semiconductor Memory Workshop (23rd 2008 Opio, France). 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design: Proceedings : May 18th-22nd, 2008 Opio, France. Piscataway, NJ: IEEE, 2008.

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Markus, Levy, ed. Designing with flash memory: The definitive guide to designing flash memory hardware and software for components and PCMCIA cards. San Diego, CA: Annabooks, 1993.

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Non-Volatile, Semiconductor Memory Workshop (21st 2006 Monterey Calif ). 21st IEEE Non-Volatile Semiconductor Memory Workshop : IEEE NVSMW 2006. New York City, NY: IEEE, 2006.

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Non-Volatile Semiconductor Memory Workshop (22nd 2007 Monterey, Calif.). 22nd IEEE Non-Volatile Semiconductor Memory Workshop: Proceedings : August 26th-30th, 2007, Monterey, California. Piscataway, NJ: IEEE, 2007.

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Non-Volatile Memory Technology Symposium (9th 2008 Pacific Grove, CA). 2008 9th Annual Non-Volatile Memory Technology Symposium: Proceedings : Pacific Grove, California, 11-14 November 2008. Piscataway, NJ: IEEE, 2008.

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Minn.) Annual Non-Volatile Memory Technology Symposium (13th 2013 Minneapolis. 2013 13th Non-Volatile Memory Technology Symposium (NVMTS 2013): Minneapolis, Minnesota, USA, 12-14 August 2013. Piscataway, NJ: IEEE, 2013.

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Non-Volatile Memory Technology Symposium (5th 2004 Orlando, Fla.). 2004 Non-Volatile Memory Technology Symposium: Proceedings : 15-17 November, 2004, Crowne Plaza Universal Hotel, Orlando, Florida. Piscataway, N.J: IEEE, 2004.

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IEEE, International Nonvolatile Memory Technology Conference (7th 1998 Albuquerque New Mexico). Seventh biennial IEEE Nonvolatile Memory Technology Conference: Proceedings : 1998 conference : June 22-24, 1998, Albuquerque, NM, USA. Piscataway, N.J: IEEE, 1998.

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Book chapters on the topic "Flash Memory Device"

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Butterfield, Andrew, and Art Ó Catháin. "Concurrent Models of Flash Memory Device Behaviour." In Lecture Notes in Computer Science, 70–83. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10452-7_6.

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Prabhu, Pravin, Ameen Akel, Laura M. Grupp, Wing-Kei S. Yu, G. Edward Suh, Edwin Kan, and Steven Swanson. "Extracting Device Fingerprints from Flash Memory by Exploiting Physical Variations." In Trust and Trustworthy Computing, 188–201. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-21599-5_14.

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Guan, Lele, Jun Zheng, Chenyang Li, and Dianxin Wang. "Research on Data Recovery Technology Based on Flash Memory Device." In Algorithms and Architectures for Parallel Processing, 263–71. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-05054-2_20.

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Shimizu, Kenichi, and Tomoaki Mitani. "Application Example 28: Cross-Sectional Examination of a Flash Memory Device." In New Horizons of Applied Scanning Electron Microscopy, 115–21. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-03160-1_29.

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Kim, Moonzoo, Yunja Choi, Yunho Kim, and Hotae Kim. "Formal Verification of a Flash Memory Device Driver – An Experience Report." In Model Checking Software, 144–59. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-85114-1_12.

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Bohara, Pooja, and S. K. Vishvakarma. "Independent Gate Operation of NAND Flash Memory Device with Improved Retention Characteristics." In Springer Proceedings in Physics, 567–70. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-97604-4_88.

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Thean, A., and J. P. Leburton. "Three-Dimensional Self-Consistent Simulation of Silicon Quantum Dot Floating-Gate Flash Memory Device." In Physical Models for Quantum Dots, 807–14. New York: Jenny Stanford Publishing, 2021. http://dx.doi.org/10.1201/9781003148494-51.

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Yu, Shimeng. "Flash Memory." In Semiconductor Memory Devices and Circuits, 83–132. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003138747-4.

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Skorobogatov, Sergei. "Data Remanence in Flash Memory Devices." In Cryptographic Hardware and Embedded Systems – CHES 2005, 339–53. Berlin, Heidelberg: Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11545262_25.

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Kovács, Annamária, Ulrich Meyer, Gabriel Moruz, and Andrei Negoescu. "Online Paging for Flash Memory Devices." In Algorithms and Computation, 352–61. Berlin, Heidelberg: Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-10631-6_37.

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Conference papers on the topic "Flash Memory Device"

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Guo, Jie, Chuhan Min, Tao Cai, Hai Li, and Yiran Chen. "Objnandsim: object-based NAND flash device simulator." In 2016 5th Non-Volatile Memory Systems and Applications Symposium (NVMSA). IEEE, 2016. http://dx.doi.org/10.1109/nvmsa.2016.7547179.

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Seokkiu Lee. "Scaling Challenges in NAND Flash Device toward 10nm Technology." In 2012 4th IEEE International Memory Workshop (IMW). IEEE, 2012. http://dx.doi.org/10.1109/imw.2012.6213636.

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Oh, Dongyean, Seungchul Lee, Changsub Lee, Jaihyuk Song, Woonkyung Lee, and Jeonghyuk Choi. "Program Disturb Phenomenon by DIBL in MLC NAND Flash Device." In 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design. IEEE, 2008. http://dx.doi.org/10.1109/nvsmw.2008.7.

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Jang-Gn Yun, Yoon Kim, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, et al. "Fin flash memory cells with separated double gates." In 2007 International Semiconductor Device Research Symposium. IEEE, 2007. http://dx.doi.org/10.1109/isdrs.2007.4422287.

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Liu, Yueran, Shan Tang, Chuanbin Mao, and Sanjay Banerjee. "SiC Nanocrystal Flash Memory Fabricated with Protein-mediated Assembly." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305148.

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Cho, Seongjae, Yoon Kim, Won Bo Shim, Dong Hua Li, Jong-Ho Lee, Hyungcheol Shin, and Byung-Gook Park. "Highly scalable vertical bandgap-engineered NAND flash memory." In 2010 68th Annual Device Research Conference (DRC). IEEE, 2010. http://dx.doi.org/10.1109/drc.2010.5551967.

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Mondai, Sandip, and V. Venkataraman. "Flash memory TFT based on fully solution processed oxide." In 2017 75th Device Research Conference (DRC). IEEE, 2017. http://dx.doi.org/10.1109/drc.2017.7999508.

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Jin-yong Choi, Ki Seok Choi, Sung-Kwan Kim, Sookwan Lee, Eyee Hyun Nam, JiHyuck Yun, Sang Lyul Min, and Yookun Cho. "Flash memory-based storage device for mobile embedded applications." In 2007 IEEE International Conference on Systems, Man and Cybernetics. IEEE, 2007. http://dx.doi.org/10.1109/icsmc.2007.4413967.

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Wu, Chen-Jun, Hang-Ting Lue, Tzu-Hsuan Hsu, Chih-Chang Hsieh, Wei-Chen Chen, Pei-Ying Du, Chia-Jung Chiu, and Chih-Yuan Lu. "Device Characteristics of Single-Gate Vertical Channel (SGVC) 3D NAND Flash Architecture." In 2016 IEEE International Memory Workshop (IMW). IEEE, 2016. http://dx.doi.org/10.1109/imw.2016.7495265.

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Sarkar, J., S. Dey, Y. Liu, D. Shahrjerdi, D. Kelly, and S. Banerjee. "Vertical (3-D) flash memory with SiGe nanocrystal floating gate." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305176.

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