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Journal articles on the topic 'Flash-based FPGA'

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Author: Grafiati

Published: 14 March 2023

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1

Shan, Yueer, Zhengzhou Cao, and Guozhu Liu. "Research on eigenstate current control technology of Flash-based FPGA." Journal of Semiconductors 43, no. 12 (December 1, 2022): 122401. http://dx.doi.org/10.1088/1674-4926/43/12/122401.

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Abstract To solve the Flash-based FPGA in the manufacturing process, the ion implantation process will bring electrons into the floating gate of the P-channel Flash cell so that the Flash switch is in a weak conduction state, resulting in the Flash-based FPGA eigenstate current problem. In this paper, the mechanism of its generation is analyzed, and four methods are used including ultraviolet light erasing, high-temperature baking, X-ray irradiation, and circuit logic control. A comparison of these four methods can identify the circuit design by using circuit logic to control the path of the power supply that is the most suitable and reliable method to solve the Flash-based FPGA eigenstate current problem. By this method, the power-on current of 3.5 million Flash-based FPGA can be reduced to less than 0.3 A, and the chip can start normally. The function and performance of the chip can then be further tested and evaluated, which is one of the key technologies for developing Flash-based FPGA.

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2

Zhang, Zhi Xian, and Yuan Yao. "Platform Flash XCFP PROMs Updating Using JTAG Boundary-Scan." Advanced Materials Research 433-440 (January 2012): 4423–27. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4423.

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This paper demonstrates a method to update design revisions in the Platform Flash XCFP PROMs for configuration of Xilinx® FPGAs. The Platform Flash XCFP PROMs contain boundary-scan(JTAG) facilities that are compatible with IEEE Std 1149.1. Combining the FPGA configuration data (FPGA bitstream) into a PROM from GPIO ports of an embedded microcontroller through JTAG TAP interface of the PROM. The JTAG download method based on the GPIO ports of an embedded microcontroller can be implemented to erase, program, and verify the Platform Flash XCFP PROMs using IEEE Std 1149.1[1]

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3

Arias, Ricardo, Hernán Mediote, and Hernán Tacca. "Flash FPGA-Based Numerical Pulse-Width Modulator." Advances in Power Electronics 2011 (April 4, 2011): 1–6. http://dx.doi.org/10.1155/2011/215376.

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A pulse-width modulator to drive three-phase AC motors is described. It performs a numerical modulation technique, also known as optimum or calculated modulation, but, in order to reduce hardware resources, a hybrid approach merging that calculated modulation with proportional modulation is proposed. The modulator is tested in a flash-based field programmable gate array (FPGA) implementation.

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4

Zhang, Hui Xin, Xiang Jiao Meng, Xiang Hong Li, and Bin Li. "The Design of 12-Channels Acquisition and Storage System Based on FPGA and AD7492." Advanced Materials Research 655-657 (January 2013): 1604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.655-657.1604.

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This paper introduces the principle and realization process of multi-channel data acquisition and storage system based on FPGA, A/D converter, FLASH and USB microcontroller. The system’s controlling core is FPGA. FPGA finished the switch of the multi-channel analog switch、A/D conversion、data compilation and storaging in the FLASH and uploading the data to PC by USB microcontroller. Test result can indicate that the system is simply and practical .The system can finish the real-time acquisition and processing for 12 input signals, sampling rate up to 1MSPS.

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5

Wen, Ju Hong, Wei Jiang Wang, Wei Gao, and Xiao Nan Fan. "FPGA Implementation of NAND Flash Wear-Levelling Algorithm." Applied Mechanics and Materials 241-244 (December 2012): 1209–12. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1209.

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NAND flash would generate invalid blocks during its manufacturing and using, and the invalid block management is a key point of NAND flash. By studying the structure and storage rules of NAND flash, this paper put forward a wear-levelling algorithm against the invalid blocks of NAND flash based on FPGA. This algorithm use invalid block table and logical-physical address mapping table to manage the invalid blocks and do wear-levelling. The design is implemented by VHDL, and successfully realized the wear-levelling and the reading and writing operations of NAND flash.

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6

Li, Jin Ming, Nan Song, and Qiu Lin Tan. "The Design to Achieve the Data Breakpoint Survivor by Using FPGA." Advanced Materials Research 468-471 (February 2012): 2599–602. http://dx.doi.org/10.4028/www.scientific.net/amr.468-471.2599.

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Recording data for the increasingly diverse needs, the design is using FPGA to achieve the data breakpoint deposit. Choosing NAND Flash K9KAG08U0M as data storage media , the data according to an external command realize erasing ,storage and read-back operation under the control of the FLASH-based FPGA (A3P125). The design of data breakpoints deposit can achieved interruption of data collection, and by reading the data back before the FLASH chip erase operation to comply the repeated use of data acquisition system.

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7

Zhou, Ming Yu, Xuan Zhou, Guang Yu Zheng, and Shu Sheng Peng. "High-Speed Data Acquisition System Based on FPGA in Missile-Borne Test System." Applied Mechanics and Materials 333-335 (July 2013): 452–59. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.452.

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In this paper, a high-speed data acquisition system based on FPGA is introduced, which has three different channels with one 5Msps sampling rate and 3×256Mb NAND FLASH. This system is controlled by a large scale FPGA chip from Xilinx Inc., XC3S500E-4FG320C. The collected data are first stored in nonvolatile flash on this fuse in-orbit and imported into a USB disk after down-falling. The main hardware and software design of each module are introduced in detail. Experiment results are shown in the final chapter.

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8

Xiao-qiang, Guo, Cao Liang-zhi, Chen Wei, Zhao Wen, Zhang Feng-qi, Wang Xun, Ding Li-li, Luo Yin-hong, and Guo Gang. "SET characterization of 130 nm flash-based FPGA device." Microelectronics Reliability 127 (December 2021): 114369. http://dx.doi.org/10.1016/j.microrel.2021.114369.

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9

Vo, Hai Hong, Hung Quoc Nguyen, and Tuyet Kim Tran. "Development of triggering and DAQ systems for radiation detectors using FPGA technology." Science and Technology Development Journal - Natural Sciences 1, T4 (December 31, 2017): 197–204. http://dx.doi.org/10.32508/stdjns.v1it4.481.

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Field-programmable gate array (FPGA) technology has been widely used in setting up triggering systems and DAQ systems for radiation detectors, because it has several advantages such as fast digital processing, compact, programmable and high stability. Since 2010, with we have developed FPGA-based trigger systems and FPGA-based DAQ systems used for radiation detectors. Triggering systems for cosmic ray measurements, readout electronic for environmental radiation monitor in air. We also developed nuclear electronic equipment such as spectrum analyzer MCA (Flash-ADC/FPGA based), the pulse generator, counters, readout electronic for multiple radiation sensors. In this paper, we present two experiments, on the cosmic-ray induced response on the NaI(Tl) detector and environmental radiation monitoring system. For those experiments, trigger system are built by FPGA-based technology.

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10

Zhu, Juan Hua, Ang Wu, and Juan Fang Zhu. "Research and Design of Digital Clock Based on FPGA." Advanced Materials Research 187 (February 2011): 741–45. http://dx.doi.org/10.4028/www.scientific.net/amr.187.741.

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A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.

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11

Li, Sheng Kun, Cheng Qun Chu, Hai Liang Chen, and Fang Ma. "Design of a Small-Sized High-Speed Data Storage Module Based on FPGA." Advanced Materials Research 912-914 (April 2014): 1556–60. http://dx.doi.org/10.4028/www.scientific.net/amr.912-914.1556.

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The large-capacity, high-speed and low power consumption become the new requirements for the data storage systems. In this paper, a high-performance storage module based on multiple NAND flash memory chips is presented to real-time massive data acquisition system. In order to achieve the miniaturization dimension and the high-speed data storage design requirements, the paper presents a small size and high-speed storage unit based on NAND flash, where the dimensions of the module can reach 33mm×33mm and the maximum rate is up to 60MB/s. Ensuring continuous and reliable operation requires a dedicated buffering for the data transmission. We analyze the elements and peculiarities of the flash memory chip and propose a multi-way architecture to speed up data access. The design of a multilevel high-speed buffer structure based on the field programmable gate array (FPGA) technology is introduced in the paper. The proposed system can be applicable to some portable digital equipment.

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12

Qin, Xi, Chang Qing Feng, De Liang Zhang, Lei Zhao, Shu Bin Liu, and Qi An. "Multi-Time Averaging TDCs Implemented in an Actel Flash-Based FPGA." Applied Mechanics and Materials 336-338 (July 2013): 9–18. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.9.

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Theoretical analysis and performance of multi-time averaging TDCs are presented in this paper. The TDCs are implemented in an Actel flash-based FPGA A3PE1500 using delay lines for time interpolating and utilizing CMOS buffers as the delay elements.Wave-unionandMulti parallel delay chainsmethod are employed for multi-time averaging to improve timing performance. The 17 timesWave-unionTDC can achieve a best resolution of 32 ps RMS, while the 20 timesMulti delay chainsTDC can achieve a minimum resolution of 23 ps RMS. Without the multi-time scheme, the TDC resolution is 127 ps RMS and 427 ps averaged bin size.

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13

Wei, Debao, Zhelong Piao, Hua Feng, Liyan Qiao, and Xiyuan Peng. "FPGA-based reliability testing and analysis for 3D NAND flash memory." Microelectronics Reliability 114 (November 2020): 113846. http://dx.doi.org/10.1016/j.microrel.2020.113846.

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14

Al-Hashimi, Ahmed, Anis Nurashikin Nordin, and Amelia Wong Azman. "Design of a Reconfigurable, Modular and Multi-Channel Bioimpedance Spectroscopy System." Indonesian Journal of Electrical Engineering and Computer Science 8, no. 2 (November 1, 2017): 428. http://dx.doi.org/10.11591/ijeecs.v8.i2.pp428-440.

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This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.

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15

Liu, Hai Ke, Shun Wang, Xin Gna Kang, and Jin Liang Wang. "Realization of NAND FLASH Control Glueless Interface Circuit." Advanced Materials Research 1008-1009 (August 2014): 659–62. http://dx.doi.org/10.4028/www.scientific.net/amr.1008-1009.659.

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The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

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16

Aoki, T. "Complete design of maximally-automated self-driven control mechanism for a large scale electronics system and its application to the ATLAS Phase-II TGC system." Journal of Instrumentation 18, no. 02 (February 1, 2023): C02054. http://dx.doi.org/10.1088/1748-0221/18/02/c02054.

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Abstract Establishing a reliable and efficient method to control electronics system consisting of many circuit boards is critical in the system design. Among unique requirements for the control in high energy physics experiments, we propose a maximally-automated and self-driven scheme for a system that exploits FPGAs, flash memory devices, and high-speed optical links. We have demonstrated our ideas in the ATLAS Phase-II Thin Gap Chamber system as the prototype for this new automated scheme. The method is widely applicable and knowledge and experience can be shared with other experiments using an FPGA-based large-scale electronics system.

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17

Chu, Cheng Qun, Yong Feng Ren, and Fang Ma. "Design of a High-Speed Image Data Real-Time Storage and Display Circuit." Advanced Materials Research 912-914 (April 2014): 1222–27. http://dx.doi.org/10.4028/www.scientific.net/amr.912-914.1222.

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The needs of large-capacity storage in high-speed image acquisition systems require the design of reliable and efficient storage instruments. The paper presents a FPGA-based high-speed storage instrument for high speed Camera Link image acquisition system. The FPGA processes the input data and stores the results into the storage array. Multi-chip large-capacity SLC NAND Flash chips constitute a storage array, with up to 100MByte/s storage rate, is used for the digitization image signals. A multilevel high-speed buffer structure based on abundant internal block RAM resources in FPGA is used for speeding up data access. At the same time, it can take advantage of FPGA constructing the corresponding VGA timing signals to control the video conversion chip ADV7123 to realize the function of real-time display. After a description of the proposed hardware and solutions, an experimental was built to test the performance. The results have shown that the FPGA-based acquisition system is a compact and flexible solution for high-speed image acquisition applications.

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18

Li, Cong Bing, and Haruo Kobayashi. "A Residue Number System Based Time-to-Digital Converter Architecture and its FPGA Implementation." Key Engineering Materials 698 (July 2016): 127–32. http://dx.doi.org/10.4028/www.scientific.net/kem.698.127.

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A time-to-digital converter (TDC) based on residue number system is presented. This architecture can reduce hardware and chip area as well as power significantly compared to a flash-type TDC while keeping comparable performance. Its proof-of-concept prototype was implemented on FPGA, and the measurement results validate the effectiveness of the proposed architecture

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19

Wang, Hong Liang, Hai Rui Wang, and Hai Fei Ding. "Design of Data Acquisition and Storage System for Digital and Analog Signal Based on FPGA." Advanced Materials Research 605-607 (December 2012): 955–59. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.955.

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This paper mainly introduces a FPGA-based data acquisition system which is designed to acquire multi-channel analog signal and one channel digital signal. Analog data and digital data are stored into a FLASH memory in a mixed frame format. When the acquisition finished, the data in the FLASH was read out via the LVDS communication interface to a data-read device, and the host computer receives the data through the USB bus, so the subsequent data processing and analysis can be accomplished and the information we needed can be got. The design is applied successfully to a remote measurement system, and the data acquired is reliable and precise.

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20

Fafara, Przemyslaw, Wojciech Jalmuzna, Waldemar Koprek, Krzysztof Pozniak, Ryszard Romaniuk, Jaroslaw Szewinski, and Wojciech Cichalewski. "FPGA-based implementation of a cavity field controller for FLASH and X-FEL." Measurement Science and Technology 18, no. 8 (July 6, 2007): 2365–71. http://dx.doi.org/10.1088/0957-0233/18/8/010.

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21

Zhang, Qiutao, Sarah Azimi, Germano La Vaccara, Luca Sterpone, and Boyang Du. "A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA." Microelectronics Reliability 76-77 (September 2017): 58–63. http://dx.doi.org/10.1016/j.microrel.2017.07.066.

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22

Ocaya, R. O. "A Linear CCD Spectrometer Based on FPGA for Light-Source Characterization." Applied Mechanics and Materials 763 (May 2015): 120–25. http://dx.doi.org/10.4028/www.scientific.net/amm.763.120.

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We report on the implementation of a FPGA-based ultra-violet (UV), infra-red (IR) visible (Vis) CCD spectrometer using a linear CCD detector operating at room temperature. The host interface is high-speed USB for data exchange with high-level environments such as Visual Basic, MATLAB and LABVIEW. The high-resolution intensity versus wavelength output is 8-bit digitized for secondary processing using a semi-flash analogue-to-digital converter (ADC) capable of sustained sampling rates of 20Mb/s.

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23

Zhao, Zhi Peng, Jun Wang, Chao Yun Mai, and Yu Xi Zhang. "A Multi-Channel Large-Capacity Acquisition and Storage System." Applied Mechanics and Materials 687-691 (November 2014): 3427–32. http://dx.doi.org/10.4028/www.scientific.net/amm.687-691.3427.

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In this paper, a multi-channel large-capacity acquisition and storage system is prototyped to meet the urgent need of multi-channel analog signals’ acquisition and analysis. Composed of an acquisition board and storage board based on FPGA, the system could acquire 4 channel signals and store them in 512GB flash array. Gigabit Ethernet is used to connect the system and PC, which ensures high throughout between them. Ping-pong operation and pipeline technology are applied to cover the programming time of flash to improve the access speed. The system is portable, stable, and expansible, and could be used in various areas.

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24

Li, Jia Ying, Yun Chen Jiang, and Lei Ren. "Real-Time Infrared Image Non-Uniformity Correction Based on FPGA." Advanced Materials Research 971-973 (June 2014): 1696–99. http://dx.doi.org/10.4028/www.scientific.net/amr.971-973.1696.

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IRFPA is the main direction of infrared imaging technology at present. It has high sensitivity and detection capability, but it also has disadvantages such as bad non-uniformity. Non-uniformity correction is a key technology in the application of IRFPA. As an applicable and real time non-uniformity correction method, the two-point correction algorithmic and single-point correction algorithmic are used widely. Their flow is simple and fixed. They are also suitable to be implemented by FPGA. In this paper, the two-point and single-point method of non-uniformity correction based on FPGA are introduced. And whether the two-point correction or the single-point correction is taken is determined by external control signal. After the completion of the correction coefficients calculation, the coefficients are written into FLASH so that the data will not be lost when the system is powered off.

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25

Evans, Adrian, Carlos Urbina Ortega, Kostas Marinis, Enrico Costenaro, Houssem Laroussi, Kay-Voss Obbe, Giorgio Magistrati, and Veronique Ferlet-Cavrois. "Heavy-Ion Micro Beam and Simulation Study of a Flash-Based FPGA Microcontroller Implementation." IEEE Transactions on Nuclear Science 64, no. 1 (January 2017): 504–11. http://dx.doi.org/10.1109/tns.2016.2633401.

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26

Hai, V. H., N. Q. Dao, and M. Nomachi. "Cosmic ray angular distribution employing plastic scintillation detectors and flash-ADC/FPGA-based readout systems." Kerntechnik 77, no. 6 (December 2012): 462–64. http://dx.doi.org/10.3139/124.110204.

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27

Tarrillo, Jimmy, José Rodrigo Azambuja, Fernanda Lima Kastensmidt, Evaldo Carlos Pereira Fonseca, Rafael Galhardo, and Odair Goncalez. "Analyzing the Effects of TID in an Embedded System Running in a Flash-Based FPGA." IEEE Transactions on Nuclear Science 58, no. 6 (December 2011): 2855–62. http://dx.doi.org/10.1109/tns.2011.2170855.

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28

Gupta, Ashima, Anil Singh, and Alpana Agarwal. "Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC." Journal of Circuits, Systems and Computers 29, no. 05 (July 16, 2019): 2050073. http://dx.doi.org/10.1142/s0218126620500735.

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A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180[Formula: see text]nm CMOS technology with 1.8[Formula: see text]V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43[Formula: see text]dB, 25.2[Formula: see text]dB and 30.1[Formula: see text]dB, respectively at 33.20[Formula: see text]MHz input frequency and 200[Formula: see text]MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14[Formula: see text]mW. The calculated value of DNL and INL is [Formula: see text] LSB and [Formula: see text] LSB respectively.

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29

Zhang, Hui Xin, Zheng Guo, and Yong Ye. "Design of High-Speed Remote Image Data Storage Memory Based on LVDS." Advanced Materials Research 605-607 (December 2012): 1989–93. http://dx.doi.org/10.4028/www.scientific.net/amr.605-607.1989.

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Due to the characteristics of the large amount of data and the high rate of transmission in the system of remote image acquisition, introduces a remote image storage memory based on the LVDS. The FPGA design as the core, and adopting the LVDS interface solution string and the drive chip combined, ensure the effective of receiving remote data. Meanwhile the system adopted the flash programming technology of alternative two-plane to storage the image data. It realized the speed of 28.95 MB/s high-speed real-time image data storage requirements in system. The application shows that the data memory stable and reliable, meets the practical requirements

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30

Rezzak, Nadia, Jih-Jong Wang, Michael Traas, Amal Zerrouki, Gregory Bakker, Fengliang Xue, Alex Cai, Frank Hawley, John McCollum, and Esmat Hamdy. "Investigation of TID and Dynamic Burn-In-Induced $V_{{T}}$ Shift on RTG4 Flash-Based FPGA." IEEE Transactions on Nuclear Science 65, no. 1 (January 2018): 64–70. http://dx.doi.org/10.1109/tns.2017.2768038.

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31

Wang, Jih-Jong, Nadia Rezzak, Durwyn Dsilva, Fengliang Xue, Salim Samiee, Pavan Singaraju, James Jia, Victor Nguyen, Frank Hawley, and Esmat Hamdy. "Combine Flash-Based FPGA TID and Long-Term Retention Reliabilities Through ${{\rm V}_{\rm T}}$ Shift." IEEE Transactions on Nuclear Science 63, no. 4 (August 2016): 2129–36. http://dx.doi.org/10.1109/tns.2016.2524692.

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32

Chu, Kai-Chun, Kuo-Chi Chang, Hsiao-Chuan Wang, Yuh-Chung Lin, and Tsui-Lien Hsu. "Field-Programmable Gate Array-Based Hardware Design of Optical Fiber Transducer Integrated Platform." Journal of Nanoelectronics and Optoelectronics 15, no. 5 (May 1, 2020): 663–71. http://dx.doi.org/10.1166/jno.2020.2835.

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This study focuses on the hardware architecture of a Raman scattering distributed optical fiber transducer platform, the principles of Raman scattering are analyzed, and the output 2 analog electrical signals are converted to digital signals at a 16-bit sampling rate by an Analog-to-Digital Converter (ADC). The system is implemented based on the FPGA. The integrated circuit is responsible for controlling the data acquisition process. The differential amplifier circuit, FPGA peripheral circuit, and CPU subsystem circuit, which takes ARM as the core, are separately designed. The composition of software includes a DDR2 (Double Data Rate 2) driver and central control logic. In this study, the optical fiber transducer platform has been tested. The CPU DDR2 is read/written by the test program respectively. According to the results, the program passes the read/write test. The NAND FLASH is tested. The results show that this program returns all operations successfully. The timing tests of the DDR2 interface and data latching are conducted. The results show that the read/write operations ensure that the clock and data curves are aligned. Therefore, the optical fiber transducer integrated platform designed in this study is effective.

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33

Sha, Yun Dong, Jia Han, and Feng Tong Zhao. "The Design of Embedded AeroEngine Measurement and Test System Based on ARM and FPGA." Advanced Engineering Forum 2-3 (December 2011): 458–62. http://dx.doi.org/10.4028/www.scientific.net/aef.2-3.458.

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Present Measurement and test system for aeroengine rig testing is primarily based on DSP and PC104 industrial computer, which have the disadvantages of large volume, high power consumption, single function and less-generic. So it is a valuable job to promote the performance of the system employing the latest methods of collaborative design and embedded hardware and software technology. For designing of the new type improved aeroengine test system, a hardware and software co-design strategy is employed. After a thorough trade-off analysis and comparison among different hardware and software systems, an embedded aeroengine test system based on ARM and FPGA is designed, by using S3C2440A CPU with ARM920T core and FPGA from Xilinx as fundamental hardware data acquisition and process platform, using Linux as real time operating system. The data transmission between ARM and FPGA take the path of dual-port RAM, during which the read-write operation is coordinated by means of interruption. The system uses U-Boot to initialize hardware and load operating system. FPGA is used as foreside of data acquisition system, which sampling parameter setting is loaded by reading configuration file during start-up and read into inner register by SPI bus. Data is exported from flash-chip of test system by means of U-disk or network, and analyzed in PC equipped with specialized software. Strong post-proceeding capacity for multi parameters of aeroengine rig testing can be realized, especially for dynamic signal analysis in time domain, frequency domain. Because of the use of the new platform, a big promotion has been achieved. I) the capacity of data processing increases by 15%. II) The new system allows numbers of the sampling channels to double. III) Abundant functions of software can realize more professional, intelligent and generic tests. IV) Sampling frequencies increases by 20%, meeting the demand of monitoring dynamic random signals such as noise and vibration, on fluctuating pressure with wide frequency band. The embedded aeroengine test system based on ARM and FPGA is successful and the prototype is manufactured and tested. It is found that the performance of the new system is promoted significantly, which shows the effectiveness and reliability of the method employed.

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Salamat, Sahand, Hui Zhang, Yang Seok Ki, and Tajana Rosing. "NASCENT2: Generic Near-Storage Sort Accelerator for Data Analytics on SmartSSD." ACM Transactions on Reconfigurable Technology and Systems 15, no. 2 (June 30, 2022): 1–29. http://dx.doi.org/10.1145/3472769.

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As the size of data generated every day grows dramatically, the computational bottleneck of computer systems has shifted toward storage devices. The interface between the storage and the computational platforms has become the main limitation due to its limited bandwidth, which does not scale when the number of storage devices increases. Interconnect networks do not provide simultaneous access to all storage devices and thus limit the performance of the system when executing independent operations on different storage devices. Offloading the computations to the storage devices eliminates the burden of data transfer from the interconnects. Near-storage computing offloads a portion of computations to the storage devices to accelerate big data applications. In this article, we propose a generic near-storage sort accelerator for data analytics, NASCENT2, which utilizes Samsung SmartSSD, an NVMe flash drive with an on-board FPGA chip that processes data in situ. NASCENT2 consists of dictionary decoder, sort, and shuffle FPGA-based accelerators to support sorting database tables based on a key column with any arbitrary data type. It exploits data partitioning applied by data processing management systems, such as SparkSQL, to breakdown the sort operations on colossal tables to multiple sort operations on smaller tables. NASCENT2 generic sort provides 2 × speedup and 15.2 × energy efficiency improvement as compared to the CPU baseline. It moreover considers the specifications of the SmartSSD (e.g., the FPGA resources, interconnect network, and solid-state drive bandwidth) to increase the scalability of computer systems as the number of storage devices increases. With 12 SmartSSDs, NASCENT2 is 9.9× (137.2 ×) faster and 7.3 × (119.2 ×) more energy efficient in sorting the largest tables of TPCC and TPCH benchmarks than the FPGA (CPU) baseline.

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Owen Jr., Don, Derek Heeger, Calvin Chan, Wenjie Che, Fareena Saqib, Matt Areno, and Jim Plusquellic. "An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays." Cryptography 2, no. 3 (July 18, 2018): 15. http://dx.doi.org/10.3390/cryptography2030015.

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Secure booting within a field-programmable gate array (FPGA) environment is traditionally implemented using hardwired embedded cryptographic primitives and non-volatile memory (NVM)-based keys, whereby an encrypted bitstream is decrypted as it is loaded from an external storage medium, e.g., Flash memory. A novel technique is proposed in this paper that self-authenticates an unencrypted FPGA configuration bitstream loaded into the FPGA during the start-up. The internal configuration access port (ICAP) interface is accessed to read out configuration information of the unencrypted bitstream, which is then used as input to a secure hash function SHA-3 to generate a digest. In contrast to conventional authentication, where the digest is computed and compared with a second pre-computed value, we use the digest as a challenge to a hardware-embedded delay physical unclonable function (PUF) called HELP. The delays of the paths sensitized by the challenges are used to generate a decryption key using the HELP algorithm. The decryption key is used in the second stage of the boot process to decrypt the operating system (OS) and applications. It follows that any type of malicious tampering with the unencrypted bitstream changes the challenges and the corresponding decryption key, resulting in key regeneration failure. A ring oscillator is used as a clock to make the process autonomous (and unstoppable), and a novel on-chip time-to-digital-converter is used to measure path delays, making the proposed boot process completely self-contained, i.e., implemented entirely within the re-configurable fabric and without utilizing any vendor-specific FPGA features.

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Kastensmidt, Fernanda Lima, Evaldo Carlos Pereira Fonseca, Rafael Galhardo Vaz, Odair Lelis Goncalez, Raul Chipana, and Gilson Inácio Wirth. "TID in Flash-Based FPGA: Power Supply-Current Rise and Logic Function Mapping Effects in Propagation-Delay Degradation." IEEE Transactions on Nuclear Science 58, no. 4 (August 2011): 1927–34. http://dx.doi.org/10.1109/tns.2011.2128881.

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Aras, Emekcan, Stéphane Delbruel, Fan Yang, Wouter Joosen, and Danny Hughes. "Chimera." ACM Transactions on Internet of Things 2, no. 2 (May 2021): 1–25. http://dx.doi.org/10.1145/3440995.

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The Internet of Things (IoT) is being deployed in an ever-growing range of applications, from industrial monitoring to smart buildings to wearable devices. Each of these applications has specific computational requirements arising from their networking, system security, and edge analytics functionality. This diversity in requirements motivates the need for adaptable end-devices, which can be re-configured and re-used throughout their lifetime to handle computation-intensive tasks without sacrificing battery lifetime. To tackle this problem, this article presents Chimera, a low-power platform for research and experimentation with reconfigurable hardware for the IoT end-devices. Chimera achieves flexibility and re-usability through an architecture based on a Flash Field Programmable Gate Array (FPGA) with a reconfigurable software stack that enables over-the-air hardware and software evolution at runtime. This adaptability enables low-cost hardware/software upgrades on the end-devices and an increased ability to handle computationally-intensive tasks. This article describes the design of the Chimera hardware platform and software stack, evaluates it through three application scenarios, and reviews the factors that have thus far prevented FPGAs from being utilized in IoT end-devices.

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Rodriguez-Olivares, N. A., A. Gomez-Hernandez, L. Nava-Balanzar, H. Jimenez-Hernandez, and J. A. Soto-Cajiga. "FPGA-Based Data Storage System on NAND Flash Memory in RAID 6 Architecture for In-Line Pipeline Inspection Gauges." IEEE Transactions on Computers 67, no. 7 (July 1, 2018): 1046–53. http://dx.doi.org/10.1109/tc.2018.2794986.

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39

Rezgui, Sana, Edward P. Wilcox, Poongyeub Lee, Martin A. Carts, Kenneth LaBel, Victor Nguyen, Nicola Telecco, and John McCollum. "Investigation of Low Dose Rate and Bias Conditions on the Total Dose Tolerance of a CMOS Flash-Based FPGA." IEEE Transactions on Nuclear Science 59, no. 1 (February 2012): 134–43. http://dx.doi.org/10.1109/tns.2011.2179316.

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Sun, Yong, Li Zhao, Neng Xu, and Rong Ou. "Research of Visual Stimulation Method and Design of Visual Stimulator Based on Brain-Computer Interface." Applied Mechanics and Materials 734 (February 2015): 375–82. http://dx.doi.org/10.4028/www.scientific.net/amm.734.375.

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Brain Computer Interface (BCI) is a new ways of communicating with outside for the loss of some or all of the muscles controlling function of the patients. And the BCI is to set up a new information communication and control channel though the computer or other electronic device between the human brain and the external environment that does not depend on the peripheral nerve and muscle tissue. Firstly, this paper studies the methods of visual stimulation based on Brain Computer Interface that classified by stimulating form can be divided into flash simulation and figures simulation and classified by stimulating frequency can be divide into transient visual stimulation and steady-state visual stimulation. Then, using FPGA and the VGA interface designed of the visual stimulator that can be used to acquisition of steady-state visual evoked potential. Finally, adopting EEG signal processing platform verify this simulator. After numbers of verification, this simulator obtains a good desired result which achieved over 80% accuracy rate.

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Hai, Vo Hong, Nguyen Quoc Hung, and Bui Tuan Khai. "Development of gamma spectroscopy employing NaI(Tl) detector 3 inch × 3 inch and readout electronic of flash-ADC/FPGA-based technology." Kerntechnik 80, no. 2 (April 28, 2015): 180–83. http://dx.doi.org/10.3139/124.110491.

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Karnati, Sudarsana Reddy, Lakshmi Boppanna, and D. R. Jahagirdar. "A Novel Loss Tolerant Data Transmission Schemes for Airborne Telemetry System of a Long Range Aerospace Vehicle." Defence Science Journal 72, no. 1 (January 5, 2022): 114–21. http://dx.doi.org/10.14429/dsj.72.17024.

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The on-board telemetry system of an aerospace vehicle sends the vehicle performance parameters to the ground receiving station at all instances of its trajectory. During the course of its trajectory, the communication channel of a long range vehicle, experiences various phenomena such as plume attenuation, stage separation, manoeuvring of a vehicle and RF blackout, causing loss of valuable telemetry data. The loss of communication link is inevitable due to these harsh conditions even when using the space diversity of ground receiving systems. Conventional telemetry systems do not provide redundant data for long range aerospace vehicles. This research work proposes an innovative delay data transmission, frame switchover and multiple frames data transmission schemes to improve the availability of telemetry data at ground receiving stations. The proposed innovative schemes are modelled using VHDL and extensive simulations have been performed to validate the results. The functionally simulated net list has been synthesised with 130 nm ACTEL flash based FPGA and verified on telemetry hardware.

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Lv, Hao, Shengbing Zhang, Wei Han, Yongqiang Liu, Shuo Liu, Yaoqin Chu, and Lei Zhang. "Design and Realization of an Aviation Computer Micro System Based on SiP." Electronics 9, no. 5 (May 7, 2020): 766. http://dx.doi.org/10.3390/electronics9050766.

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In recent years, microelectronics technology has entered the era of nanoelectronics/integrated microsystems. System in Package (SiP) and System on Chip (SoC) are two important technical approaches for microsystems. The development of micro-system technology has made it possible to miniaturize airborne and missile-borne electronic equipment. This paper introduces the design and implementation of an aerospace miniaturized computer system. The SiP chip uses Xilinx Zynq® SoC (2ARM® + FPGA), FLASH memory and DDR3 memory as the main components, and integrates with SiP high-density system packaging technology. The chip has the advantages of small size and ultra-low power consumption compared with the traditional PCB circuit design. A pure software-based DDR3 signal eye diagram test method is used to verify the improvement inf the signal integrity of the chip without the need for probe measurement. The method of increasing the thermal conductive silver glue was used to improve the thermal performance after the test and analysis. The SiP chip was tested and analyzed with other mainstream aviation computers using a heading measurement of extended Kalman filter (EKF) algorithm. The paper has certain reference value and research significance in the miniaturization of the aviation computer system, the heat dissipation technology of SiP chip and the test method of signal integrity.

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Hamadaqa, Emad, Ayoub Mars, and Wael Adi. "Physical Security for Fleet Management Systems." Cryptography 4, no. 1 (December 31, 2019): 1. http://dx.doi.org/10.3390/cryptography4010001.

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Fleet Management (FM) deals with the management of transport, distribution, and logistics of national and international goods exchange, in which many operators worldwide are involved. Fleet management involves many security-relevant participating entities, such as vehicles, FM mobile clients, smart trackers with goods, drivers, etc. Existing automated fleet management systems are basically vulnerable to physical replacement attacks when managed by mass-produced electronic identities. Analog Physical Unclonable Functions (PUFs) failed to serve as unclonable electronic identities due to being costly, unstable and inefficient for such mass-usage. We propose in this paper to deploy the Secret Unknown Ciphers (SUCs) techniques introduced a decade ago as digital low-cost clone-resistant identities to be embedded in selected participating electronic Fleet Management System (FMS) units. SUCs, as stable self-created digital modules to be embedded in future smart non-volatile (NV)-FPGA devices, are expected to cover all emerging FMS physical security requirements. Such information-retaining units (when switched-off) are emerging to become widely used as ultra-low-power mass-products in automotive environment. We propose a new FMS security architecture based on embedding SUC modules in each security-relevant entity in the FMS such as vehicles, mobile clients, smart trackers and goods. This paper investigates the expected technical impacts when using SUCs technology as physical security anchors in a standard FMS configuration. Several SUC-related generic security protocols adapted to the FM environment show how to securely-link tracing of goods, tracks routing, and personnel in such FM system. It is also shown how to combine other biometric fingerprints to simplify personal liability and enhance the security management in such globally-operating automated procedures. The presented security analysis of the resulting FMS shows that the major security concerns in existing FMSs can be resolved. One major advantage of SUC technique, is that device-manufacturers can be largely-excluded as security players. The FPGA technology required for the SUC solution is currently not available and is thought for future use. The concept is ultimately applicable if the future electronic mass products would deploy self-reconfiguring non-volatile (flash-based) System on Chip smart units. Such units are expected to dominate future Internet of Things (IoT) ultra-low-energy applications, as power-off does not lose any information. The proposed SUC strategy is highly flexible, scalable, and applicable to cover a large class of globally operating protection mechanisms similar to those of the addressed FMS scenarios.

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Utrilla, Ramiro, Roberto Rodriguez-Zurrunero, Jose Martin, Alba Rozas, and Alvaro Araujo. "MIGOU: A Low-Power Experimental Platform with Programmable Logic Resources and Software-Defined Radio Capabilities." Sensors 19, no. 22 (November 15, 2019): 4983. http://dx.doi.org/10.3390/s19224983.

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The increase in the number of mobile and Internet of Things (IoT) devices, along with the demands of new applications and services, represents an important challenge in terms of spectral coexistence. As a result, these devices are now expected to make an efficient and dynamic use of the spectrum, and to provide processed information instead of simple raw sensor measurements. These communication and processing requirements have direct implications on the architecture of the systems. In this work, we present MIGOU, a wireless experimental platform that has been designed to address these challenges from the perspective of resource-constrained devices, such as wireless sensor nodes or IoT end-devices. At the radio level, the platform can operate both as a software-defined radio and as a traditional highly integrated radio transceiver, which demands less node resources. For the processing tasks, it relies on a system-on-a-chip that integrates an ARM Cortex-M3 processor, and a flash-based FPGA fabric, where high-speed processing tasks can be offloaded. The power consumption of the platform has been measured in the different modes of operation. In addition, these hardware features and power measurements have been compared with those of other representative platforms. The results obtained confirm that a state-of-the-art tradeoff between hardware flexibility and energy efficiency has been achieved. These characteristics will allow for the development of appropriate solutions to current end-devices’ challenges and to test them in real scenarios.

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Azimi, S., B. Du, and L. Sterpone. "On the prediction of radiation-induced SETs in flash-based FPGAs." Microelectronics Reliability 64 (September 2016): 230–34. http://dx.doi.org/10.1016/j.microrel.2016.07.106.

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Rezgui, Sana, J. J. Wang, Eric Chan Tung, Brian Cronquist, and John McCollum. "New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs." IEEE Transactions on Nuclear Science 54, no. 6 (December 2007): 2512–24. http://dx.doi.org/10.1109/tns.2007.910126.

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Evans, Adrian, Dan Alexandrescu, Veronique Ferlet-Cavrois, and Michael Nicolaidis. "New Techniques for SET Sensitivity and Propagation Measurement in Flash-Based FPGAs." IEEE Transactions on Nuclear Science 61, no. 6 (December 2014): 3171–77. http://dx.doi.org/10.1109/tns.2014.2365410.

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Rezgui, Sana, J. J. Wang, Yinming Sun, Brian Cronquist, and John McCollum. "Configuration and Routing Effects on the SET Propagation in Flash-Based FPGAs." IEEE Transactions on Nuclear Science 55, no. 6 (December 2008): 3328–35. http://dx.doi.org/10.1109/tns.2008.2007726.

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Wei, Wang, and Zhang Zhijie. "The Intelligent Storage Recording System Based On Cluster Bombs Testing and The Data Analysis." Open Electrical & Electronic Engineering Journal 9, no. 1 (October 28, 2015): 530–33. http://dx.doi.org/10.2174/1874129001509010530.

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According to the bullet of cluster bombs in the separated Rotate- speed, dispensing overload, parachuteopening overload, landing overload and other parameters testing background, this paper designs a intelligent storage recording system which selects a the thin film geomagnetic sensor and photoelectric accelerometer as the sensitive unit, the intelligent storage recording system is mainly composed of the FPGA controller, FLASH memory, 12 bit high speed analog to digital converter. After live-fire test and numerical analysis, intelligent storage recording system can accurately obtain the whole process of flight parameter data from scatters to fall to the ground.

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