Relevant bibliographies by topics / Flash-based FPGA

Academic literature on the topic 'Flash-based FPGA'

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Published: 14 March 2023

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Journal articles on the topic "Flash-based FPGA"

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Shan, Yueer, Zhengzhou Cao, and Guozhu Liu. "Research on eigenstate current control technology of Flash-based FPGA." Journal of Semiconductors 43, no. 12 (December 1, 2022): 122401. http://dx.doi.org/10.1088/1674-4926/43/12/122401.

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Abstract To solve the Flash-based FPGA in the manufacturing process, the ion implantation process will bring electrons into the floating gate of the P-channel Flash cell so that the Flash switch is in a weak conduction state, resulting in the Flash-based FPGA eigenstate current problem. In this paper, the mechanism of its generation is analyzed, and four methods are used including ultraviolet light erasing, high-temperature baking, X-ray irradiation, and circuit logic control. A comparison of these four methods can identify the circuit design by using circuit logic to control the path of the power supply that is the most suitable and reliable method to solve the Flash-based FPGA eigenstate current problem. By this method, the power-on current of 3.5 million Flash-based FPGA can be reduced to less than 0.3 A, and the chip can start normally. The function and performance of the chip can then be further tested and evaluated, which is one of the key technologies for developing Flash-based FPGA.
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Zhang, Zhi Xian, and Yuan Yao. "Platform Flash XCFP PROMs Updating Using JTAG Boundary-Scan." Advanced Materials Research 433-440 (January 2012): 4423–27. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4423.

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This paper demonstrates a method to update design revisions in the Platform Flash XCFP PROMs for configuration of Xilinx® FPGAs. The Platform Flash XCFP PROMs contain boundary-scan(JTAG) facilities that are compatible with IEEE Std 1149.1. Combining the FPGA configuration data (FPGA bitstream) into a PROM from GPIO ports of an embedded microcontroller through JTAG TAP interface of the PROM. The JTAG download method based on the GPIO ports of an embedded microcontroller can be implemented to erase, program, and verify the Platform Flash XCFP PROMs using IEEE Std 1149.1[1]
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Arias, Ricardo, Hernán Mediote, and Hernán Tacca. "Flash FPGA-Based Numerical Pulse-Width Modulator." Advances in Power Electronics 2011 (April 4, 2011): 1–6. http://dx.doi.org/10.1155/2011/215376.

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A pulse-width modulator to drive three-phase AC motors is described. It performs a numerical modulation technique, also known as optimum or calculated modulation, but, in order to reduce hardware resources, a hybrid approach merging that calculated modulation with proportional modulation is proposed. The modulator is tested in a flash-based field programmable gate array (FPGA) implementation.
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Zhang, Hui Xin, Xiang Jiao Meng, Xiang Hong Li, and Bin Li. "The Design of 12-Channels Acquisition and Storage System Based on FPGA and AD7492." Advanced Materials Research 655-657 (January 2013): 1604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.655-657.1604.

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This paper introduces the principle and realization process of multi-channel data acquisition and storage system based on FPGA, A/D converter, FLASH and USB microcontroller. The system’s controlling core is FPGA. FPGA finished the switch of the multi-channel analog switch、A/D conversion、data compilation and storaging in the FLASH and uploading the data to PC by USB microcontroller. Test result can indicate that the system is simply and practical .The system can finish the real-time acquisition and processing for 12 input signals, sampling rate up to 1MSPS.
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Wen, Ju Hong, Wei Jiang Wang, Wei Gao, and Xiao Nan Fan. "FPGA Implementation of NAND Flash Wear-Levelling Algorithm." Applied Mechanics and Materials 241-244 (December 2012): 1209–12. http://dx.doi.org/10.4028/www.scientific.net/amm.241-244.1209.

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NAND flash would generate invalid blocks during its manufacturing and using, and the invalid block management is a key point of NAND flash. By studying the structure and storage rules of NAND flash, this paper put forward a wear-levelling algorithm against the invalid blocks of NAND flash based on FPGA. This algorithm use invalid block table and logical-physical address mapping table to manage the invalid blocks and do wear-levelling. The design is implemented by VHDL, and successfully realized the wear-levelling and the reading and writing operations of NAND flash.
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Li, Jin Ming, Nan Song, and Qiu Lin Tan. "The Design to Achieve the Data Breakpoint Survivor by Using FPGA." Advanced Materials Research 468-471 (February 2012): 2599–602. http://dx.doi.org/10.4028/www.scientific.net/amr.468-471.2599.

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Recording data for the increasingly diverse needs, the design is using FPGA to achieve the data breakpoint deposit. Choosing NAND Flash K9KAG08U0M as data storage media , the data according to an external command realize erasing ,storage and read-back operation under the control of the FLASH-based FPGA (A3P125). The design of data breakpoints deposit can achieved interruption of data collection, and by reading the data back before the FLASH chip erase operation to comply the repeated use of data acquisition system.
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Zhou, Ming Yu, Xuan Zhou, Guang Yu Zheng, and Shu Sheng Peng. "High-Speed Data Acquisition System Based on FPGA in Missile-Borne Test System." Applied Mechanics and Materials 333-335 (July 2013): 452–59. http://dx.doi.org/10.4028/www.scientific.net/amm.333-335.452.

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In this paper, a high-speed data acquisition system based on FPGA is introduced, which has three different channels with one 5Msps sampling rate and 3×256Mb NAND FLASH. This system is controlled by a large scale FPGA chip from Xilinx Inc., XC3S500E-4FG320C. The collected data are first stored in nonvolatile flash on this fuse in-orbit and imported into a USB disk after down-falling. The main hardware and software design of each module are introduced in detail. Experiment results are shown in the final chapter.
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Xiao-qiang, Guo, Cao Liang-zhi, Chen Wei, Zhao Wen, Zhang Feng-qi, Wang Xun, Ding Li-li, Luo Yin-hong, and Guo Gang. "SET characterization of 130 nm flash-based FPGA device." Microelectronics Reliability 127 (December 2021): 114369. http://dx.doi.org/10.1016/j.microrel.2021.114369.

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Vo, Hai Hong, Hung Quoc Nguyen, and Tuyet Kim Tran. "Development of triggering and DAQ systems for radiation detectors using FPGA technology." Science and Technology Development Journal - Natural Sciences 1, T4 (December 31, 2017): 197–204. http://dx.doi.org/10.32508/stdjns.v1it4.481.

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Field-programmable gate array (FPGA) technology has been widely used in setting up triggering systems and DAQ systems for radiation detectors, because it has several advantages such as fast digital processing, compact, programmable and high stability. Since 2010, with we have developed FPGA-based trigger systems and FPGA-based DAQ systems used for radiation detectors. Triggering systems for cosmic ray measurements, readout electronic for environmental radiation monitor in air. We also developed nuclear electronic equipment such as spectrum analyzer MCA (Flash-ADC/FPGA based), the pulse generator, counters, readout electronic for multiple radiation sensors. In this paper, we present two experiments, on the cosmic-ray induced response on the NaI(Tl) detector and environmental radiation monitoring system. For those experiments, trigger system are built by FPGA-based technology.
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Zhu, Juan Hua, Ang Wu, and Juan Fang Zhu. "Research and Design of Digital Clock Based on FPGA." Advanced Materials Research 187 (February 2011): 741–45. http://dx.doi.org/10.4028/www.scientific.net/amr.187.741.

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A digital clock system designed by using VHDL hardware description language is presented in this paper. The proposed architecture fully utilizes the digital clock system available on FPGA chips based top-down design method in the Quartus II development environment. The Clock system is divided into four design modules: core module, frequency_division module, display module and tune module. It not only can time accurately and display time, but also can reset and adjust time. The LED lights will flash and the loudspeaker will tell time on the hour. The architecture is implemented and verified experimentally on a FPGA board. Because of the universality of digital clock and the portability of VHDL language, it can be applied directly in various designs based on FPGA chip.
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Dissertations / Theses on the topic "Flash-based FPGA"

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DU, BOYANG. "Fault Tolerant Electronic System Design." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2644047.

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Due to technology scaling, which means reduced transistor size, higher density, lower voltage and more aggressive clock frequency, VLSI devices may become more sensitive against soft errors. Especially for those devices used in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g., aging and wear-out effects) also have negative impacts on reliability of modern circuits. Recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems. On one hand, processor-based system are commonly used in a wide variety of applications, including safety-critical and high availability missions, e.g., in the automotive, biomedical and aerospace domains. In these fields, an error may produce catastrophic consequences. Thus, dependability is a primary target that must be achieved taking into account tight constraints in terms of cost, performance, power and time to market. With standards and regulations (e.g., ISO-26262, DO-254, IEC-61508) clearly specify the targets to be achieved and the methods to prove their achievement, techniques working at system level are particularly attracting. On the other hand, Field Programmable Gate Array (FPGA) devices are becoming more and more attractive, also in safety- and mission-critical applications due to the high performance, low power consumption and the flexibility for reconfiguration they provide. Two types of FPGAs are commonly used, based on their configuration memory cell technology, i.e., SRAM-based and Flash-based FPGA. For SRAM-based FPGAs, the SRAM cells of the configuration memory highly susceptible to radiation induced effects which can leads to system failure; and for Flash-based FPGAs, even though their non-volatile configuration memory cells are almost immune to Single Event Upsets induced by energetic particles, the floating gate switches and the logic cells in the configuration tiles can still suffer from Single Event Effects when hit by an highly charged particle. So analysis and mitigation techniques for Single Event Effects on FPGAs are becoming increasingly important in the design flow especially when reliability is one of the main requirements.
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Book chapters on the topic "Flash-based FPGA"

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Tambara, Lucas A., Marcelo S. Lubaszewski, Tiago R. Balen, Paolo Rech, Fernanda L. Kastensmidt, and Christopher Frost. "Neutron-Induced Single Event Effect in Mixed-Signal Flash-Based FPGA." In FPGAs and Parallel Architectures for Aerospace Applications, 201–16. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14352-1_14.

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Baofeng, Zhang, Zhang Suhao, Zhu Junchao, and Li Xinzhi. "Study for System Bootloader Based on DSP and FPGA Shared Flash." In Proceedings of the 2012 International Conference on Communication, Electronics and Automation Engineering, 1263–68. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31698-2_178.

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Wang, Jih-Jong, Nadia Rezzak, Durwyn DSilva, Chang-Kai Huang, Stephen Varela, Victor Nguyen, Gregory Bakker, John McCollum, Frank Hawley, and Esmat Hamdy. "Radiation Effects in 65 nm Flash-Based Field Programmable Gate Array." In FPGAs and Parallel Architectures for Aerospace Applications, 155–74. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14352-1_11.

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Sterpone, Luca, and Boyang Du. "SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs." In Lecture Notes in Computer Science, 129–40. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-16214-0_11.

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"Design and implementation of SPI flash controller based on Xilinx FPGA." In Electronic Engineering and Information Science, 43–46. CRC Press, 2015. http://dx.doi.org/10.1201/b18471-10.

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Rajagopalan, Sundararaman, Siva Janakiraman, and Amirtharajan Rengarajan. "Medical Image Encryption." In Medical Data Security for Bioengineers, 278–304. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7952-6.ch014.

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The healthcare industry has been facing a lot of challenges in securing electronic health records (EHR). Medical images have found a noteworthy position for diagnosis leading to therapeutic requirements. Millions of medical images of various modalities are generally safeguarded through software-based encryption. DICOM format is a widely used medical image type. In this chapter, DICOM image encryption implemented on cyclone FPGA and ARM microcontroller platforms is discussed. The methodology includes logistic map, DNA coding, and LFSR towards a balanced confusion – diffusion processes for encrypting 8-bit depth 256 × 256 resolution of DICOM images. For FPGA realization of this algorithm, the concurrency feature has been utilized by simultaneous processing of 128 × 128 pixel blocks which yielded a throughput of 79.4375 Mbps. Noticeably, the ARM controller which replicated this approach through sequential embedded “C” code took 1248 bytes in flash code memory and Cyclone IV FPGA consumed 21,870 logic elements for implementing the proposed encryption scheme with 50 MHz operating clock.
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Rajagopalan, Sundararaman, Siva Janakiraman, and Amirtharajan Rengarajan. "Medical Image Encryption." In Research Anthology on Artificial Intelligence Applications in Security, 269–93. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-7705-9.ch013.

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The healthcare industry has been facing a lot of challenges in securing electronic health records (EHR). Medical images have found a noteworthy position for diagnosis leading to therapeutic requirements. Millions of medical images of various modalities are generally safeguarded through software-based encryption. DICOM format is a widely used medical image type. In this chapter, DICOM image encryption implemented on cyclone FPGA and ARM microcontroller platforms is discussed. The methodology includes logistic map, DNA coding, and LFSR towards a balanced confusion – diffusion processes for encrypting 8-bit depth 256 × 256 resolution of DICOM images. For FPGA realization of this algorithm, the concurrency feature has been utilized by simultaneous processing of 128 × 128 pixel blocks which yielded a throughput of 79.4375 Mbps. Noticeably, the ARM controller which replicated this approach through sequential embedded “C” code took 1248 bytes in flash code memory and Cyclone IV FPGA consumed 21,870 logic elements for implementing the proposed encryption scheme with 50 MHz operating clock.
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Rajagopalan, Sundararaman, Siva Janakiraman, and Amirtharajan Rengarajan. "Medical Image Encryption." In Research Anthology on Artificial Intelligence Applications in Security, 269–93. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-7705-9.ch013.

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The healthcare industry has been facing a lot of challenges in securing electronic health records (EHR). Medical images have found a noteworthy position for diagnosis leading to therapeutic requirements. Millions of medical images of various modalities are generally safeguarded through software-based encryption. DICOM format is a widely used medical image type. In this chapter, DICOM image encryption implemented on cyclone FPGA and ARM microcontroller platforms is discussed. The methodology includes logistic map, DNA coding, and LFSR towards a balanced confusion – diffusion processes for encrypting 8-bit depth 256 × 256 resolution of DICOM images. For FPGA realization of this algorithm, the concurrency feature has been utilized by simultaneous processing of 128 × 128 pixel blocks which yielded a throughput of 79.4375 Mbps. Noticeably, the ARM controller which replicated this approach through sequential embedded “C” code took 1248 bytes in flash code memory and Cyclone IV FPGA consumed 21,870 logic elements for implementing the proposed encryption scheme with 50 MHz operating clock.
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Conference papers on the topic "Flash-based FPGA"

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Zhou, Guoqing, Jinlong Chen, Pengyun Chen, Xiang Zhou, Wei Huang, Lieping Zhang, and Jiandong Wei. "FPGA-Based Image Storage in Flash Lidar." In 2018 5th International Conference on Information Science and Control Engineering (ICISCE). IEEE, 2018. http://dx.doi.org/10.1109/icisce.2018.00057.

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Qin, Qin, Bing Lu, and Xin Wang. "NOR Flash test system based on FPGA." In DSIT 2021: 2021 4th International Conference on Data Science and Information Technology. New York, NY, USA: ACM, 2021. http://dx.doi.org/10.1145/3478905.3478961.

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Yu, Xiuli, and Bingqi Li. "Simulation SPI+FLASH system based on FPGA." In 2019 6th International Conference on Systems and Informatics (ICSAI). IEEE, 2019. http://dx.doi.org/10.1109/icsai48974.2019.9010251.

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Mubing Li, Min Xie, Guoman Liu, and Xiaochao Liu. "A SPI FLASH-based FPGA dynamic reconfiguration method." In 2013 IEEE International Conference on Microwave Technology & Computational Electromagnetics (ICMTCE). IEEE, 2013. http://dx.doi.org/10.1109/icmtce.2013.6812490.

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Wu, Guohui, Yongjie Hu, and Jian Wu. "NAND Flash Bad Block Management Research Based On FPGA." In 2015 International conference on Applied Science and Engineering Innovation. Paris, France: Atlantis Press, 2015. http://dx.doi.org/10.2991/asei-15.2015.33.

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Abusultan, Monther, and Sunil P. Khatri. "Exploring static and dynamic flash-based FPGA design topologies." In 2016 IEEE 34th International Conference on Computer Design (ICCD). IEEE, 2016. http://dx.doi.org/10.1109/iccd.2016.7753317.

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Jia, James Yingbo, Pavan Singaraju, Fethi Dhaoui, Rich Newell, Patty Liu, Habtom Micael, Michael Traas, et al. "Performance and reliability of a 65nm Flash based FPGA." In 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2012. http://dx.doi.org/10.1109/icsict.2012.6466679.

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Szewinski, Jaroslaw, Piotr Pucyk, Wojciech Jalmuzna, Przemyslaw Fafara, Marcin Pieciukiewicz, Ryszard Romaniuk, and Krzysztof T. Pozniak. "Embedded system in FPGA-based LLRF controller for FLASH." In SPIE Proceedings, edited by Ryszard S. Romaniuk. SPIE, 2006. http://dx.doi.org/10.1117/12.714521.

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Lavenier, Dominique, Liu Xinchun, and Gilles Georges. "Seed-based genomic sequence comparison using a FPGA/FLASH accelerator." In 2006 IEEE International Conference on Field Programmable Technology. IEEE, 2006. http://dx.doi.org/10.1109/fpt.2006.270389.

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Han, Kyung Joon, Martin Stiftinger, Ronald Kakoschke, Nigel Chan, Sungrae Kim, Ben Leung, Volker Hecht, et al. "A Novel Flash-based FPGA Technology with Deep Trench Isolation." In 2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop. IEEE, 2007. http://dx.doi.org/10.1109/nvsmw.2007.4290569.

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