Academic literature on the topic 'Filtri analogici'

Parameters of integrated analog filters can vary due to temperatu-re change, IC process variation and therefore they should have dedicated tuning circuits that compensate these imperfections. A method is proposed that speeds up switched resistor bank design while taking into account the required tuning range and step size. A novel counter structure is used in the tuning circuit that is ba-sed on successive approximation approach. The proposed swit-ched resistor design method and tuning circuit are designed in 0.18 μm CMOS technology and verified. Results are compared to existing tuning circuit designs. Integrinių analoginių filtrų parametrai gali kisti dėl temperatūros, senėjimo ar integrinių grandynų gamybos procesų netolydumo. Todėl jiems būtina numatyti papildomus grandynus, kurie kompensuotų filtrų komponentų pokyčius. Darbe siūlomas naujas integrinių aktyviųjų RC filtrų perjungiamų rezistorių matricų projektavimo metodas, kuris leidžia kompensuoti pasyvių komponentų nuokrypius ir užtikrina filtro praleidžiamų dažnių juostos derinimą reikiamu žingsniu. Savaiminio derinimo sistemoje remiamasi nauja skaitiklio architektūra, kuri naudoja nuosekliosios aproksimacijos paieškos algoritmą. Darbe pasiūlytas projektavimo metodas tikrinamas projektuojant filtro derinimo sistemą, naudojant 0,18 μm KMOP integrinių grandynų gamybos technologiją ir Cadence Virtuoso programinę įrangą. Gauti rezultatai palyginami su literatūroje pateiktais derinimo sistemų skaičiavimų rezultatais.

Multistandard transceivers usually have high order low pass filters in their receiver chains. Different filter topologies may have various component variation tolerances and different output noise. In this work, three 6th order filter with different topologies are analyzed for use in multistandard transceivers. Filters are designed in 0.18 µm and 65 nm CMOS technologies and simu-lated using Cadence software. The results show, that the filter frequency response variation in integrated circuits does not de-pend on the filter topology. Simulation results also show that the Leapfrog filter topology has the smallest integrated output noise in the filter bandwidth and is most suited for low noise applications. Daugiaustandarčiuose siųstuvuose-imtuvuose naudojami aukštesnės eilės žemųjų dažnių filtrai. Skirtingos filtrų struktūros gali būti nevienodai jautrios jas sudarančių elementų nuokrypiams ir daryti skirtingą įtaką daugiastandarčių siųstuvų-imtuvų triukšmams. Darbe pateikti trijų šeštosios eilės skirtingų struktūrų aktyviųjų RC filtrų, skirtų daugiaustandarčiams siųstuvams-imtuvams, tyrimo rezultatai. Filtrų struktūros modeliuojamos naudojant 0,18 μm ir 65 nm KMOP integrinių grandynų gamybos technologijas ir Cadence Virtuoso programinę įrangą. Iš imitacijos rezultatų matyti, kad moderniose integrinių grandynų technologijose filtrų dažninių amplitudės charakteristikų (DACh) parametrų nuokrypis beveik nepriklauso nuo filtro struktūros. Tarp analizuotų filtrų struktūrų mažiausia praleidžiamųjų dažnių juostoje integruota išėjimo triukšmo vidutinė kvadratinė vertė gaunama naudojant šuolinių grįžtamųjų ryšių struktūros filtrus.

An analysis of modern automated integrated analog circuits design methods and their use in integrated filter design is done. Current modern analog circuits automated tools are based on optimization algorithms and/or new circuit generation methods. Most automated integrated filter design methods are only suited to gmC and switched current filter topologies. Here, an algorithm for an active RC integrated filter design is proposed, that can be used in automated filter designs. The algorithm is tested by designing an integrated active RC filter in a 65 nm CMOS technology. Atlikta naujausių integrinių analoginių grandynų automatizuotojo projektavimo metodų ir jų taikymo projektuojant integrinius filtrus analizė. Modernios analoginių grandynų automatizavimo priemonės yra grindžiamos esamos topologijos optimizacijos algoritmais ir/arba naujų elektroninių principinių schemų generavimo būdais. Didžioji dauguma literatūroje aprašytų automatizuotojo integrinių filtrų projektavimo metodų yra skirti tik gm-C arba perjungiamos srovės/talpos topologijos filtrams. Darbe siūlomas naujas integrinių aktyviųjų RC filtrų projektavimo algoritmas, įvertinantis integrinių technologijų elementų nuokrypius. Jis patikrintas suprojektavus integrinį aktyvųjį RC filtrą taikant 65 nm KMOP technologiją ir Cadence programinį paketą.

Negli ultimi 30 anni, l’elettronica per le Telecomunicazioni Wireless si è dimostrata una delle forze trainanti nello sviluppo delle nuove tecnologie Complementary Metal-OxideSemiconductor (CMOS). Questa piccola branca del vasto mondo dell’elettronica è infatti in grado di smuovere, in tutto il mondo, miliardi di dollari, molti dei quali inevitabilmente finiscono per finanziare gli avanzati progetti di ricerca in grado di rispondere alle domande del Mercato. In tutto il mondo, le persone chiedono nuovi dispositivi portatili, più performanti, più veloci, più affidabili, che consumino poca potenza e che abbiano una maggiore capacità di immagazzinare dati. Per rispondere a queste richieste, fisici e ingegneri hanno sviluppato nuovi e incredibili nodi tecnologici ultra-scalati, che soddisfano i requisiti di velocità e bassi consumi, garantendo un’impressionante densità circuitale. Al giorno d’oggi, le fonderie come TSMC e Samsung sono in grado di realizzare transistor estremamente piccoli, con lunghezze di canale di soli 7 nm e frequenze di transizione nell’ordine delle centinaia di GHz. Questo sviluppo si rivela estremamente favorevole per lo sviluppo di dispositivi digitali ad alte prestazioni, che raggiungono performance di velocità e di memoria prima inimmaginabili. Non di meno, anche i blocchi analogici devono essere integrati in questi nodi estremamente scalati, in modo da potersi adattare ai circuiti integrati (IC) digitali. Primo obiettivo di questo lavoro di tesi è, quindi, lo sviluppo di IC analogici in nodi tecnologici deep-submicron, come il 28 nm bulk-CMOS e il 16 nm FinFET (Fin Field Effect Transistor). Questo obiettivo è stato raggiunto affrontando diverse difficoltà date dalle scarse performance analogiche di queste tecnologie avanzate, tra cui un basso guadagno intrinseco e una limitata tensione di alimentazione. Il secondo obiettivo di questo lavoro è stato sviluppare questi stessi IC in modo che fossero compatibili con i più moderni standard per telecomunicazioni come LTE e 5G. L’aumento del numero dei dispositivi portatili in tutto il mondo ha, infatti, fatto sì che fosse necessario introdurre nuovi standard, in modo da poter gestire il numero maggiore di dispositivi connessi. Questo lavoro presenta 4 blocchi fondamentali che possono essere impiegati in qualsiasi transceiver di nuova generazione. In particolare, questo lavoro analizza, attraverso estensive simulazioni e misure, 3 filtri analogici in Banda-Base e un amplificatore a guadagno variabile compatibili con applicazioni 5G. Questi design sono stati sviluppati in tecnologia 28 nm CMOS e 16 nm FinFET. Per ogni design vengono mostrate le più importanti difficoltà incontrate e vengono riportate le performance di ogni prototipo in modo da essere confrontate con lo stato dell’arte. Il primo dispositivo e un filtro analogico del sesto ordine basato su una cella Rauch che sfrutta un amplificatore a banda larga per raggiungere alte performance di linearità e una bassa sensitivity del fattore di qualità. Il secondo è un amplificatore a guadagno variabile del terzo ordine, a basso rumore e alta linearità, studiato per essere integrato nella sezione in Banda Base di un dispositivo transceiver Full Duplex compatibile con il 5G. Il terzo e il quarto sono filtri analogici del quarto ordine basati sulla struttura del source-follower, a basso rumore e bassi consumi. Il primo sfrutta la topologia del Flipped-Source-Follower, mentre il secondo integra un innovativo Fully-Differential Super-Source-Follower. Quest’ultimo design inoltre sfrutta la tecnologia FinFET in modo da mantenere alte performance di linearità, nonostante la struttura completamente differenziale, grazie al più grande guadagno intrinseco dei transistor in questo nodo tecnologico.<br>In the last 30 years, Mobile Telecommunication (TLC) electronics proved to be one of the major driving motors in the development of new Complementary Metal-OxideSemiconductor (CMOS) technologies. This limited branch of the electronics world managed to move billions of dollars worldwide, some of which unavoidably ended up in financing advanced research projects to answer market demands. People all around the world ask for extremely performing portable devices, faster, more reliable, low power consuming and with impressive memory capability. To answer all these requests, physics and engineers developed new and incredibly down-scaled technology nodes, which met the high speed and low power consumption requirement, granting an impressive circuital density. Nowadays foundries such as TSMC or Samsung are able to manufacture incredibly small transistor devices, with channel length in the order of only 7 nm and transition frequency in the order of several hundreds of GHz. This situation has become extremely favorable for the development of high-performance digital devices, which are able to reach speed and memory capability previously unbelievable. Nonetheless, also analog building blocks must be integrated in deeply down-scaled node, in order to adapt with digital ICs. First task of this thesis work is to develop analog ICs in deep sub-micron technology nodes, such as 28 nm bulk-CMOS and 16 nm FinFET (Fin Field Effect Transistor). This has been accomplished facing several difficulties given by the very poor analog behavior of such advanced technologies, especially in terms of low transistor intrinsic gain and limited signal headroom, caused by the low supply voltage. The second task of this work is to develop these same analog ICs in order that they meet requirements of the most advanced TLC standards, such as LTE and 5G. The increased number of portable devices worldwide made in fact unavoidable the introduction of new communication standards, in order to face the huge number of connected devices. This work presents 4 building blocks that can be exploited in every next generation transceiver device. In detail, this work analyzes though extended simulations and measurements 3 Base-Band analog filters and 1 variable gain amplifier, suitable for 5G applications. These designs have been developed in 28nm CMOS and 16 nm FinFET. Each design shows the most important difficult that was faced for its realization and highlight the most important performances of every prototype device, with an extensive confrontation with the State-of-the Art. The first device is a 6th Order Rauch based analog filter, which exploit a large bandwidth amplifier to achieve low quality factor sensitivity and high linearity performances. The second is a 3rd order variable gain amplifier, with low noise and high linearity performances, suitable to be integrated in a Full-Duplex 5G transceiver Base-Band section. The third and fourth devices are Source-Follower-based 4th order filters with very low noise and low power performances. One exploit the Flipped-Source-Follower architecture, while the second integrates an innovative Fully-Differential Super-Source-Follower topology. This last design also exploits the advanced FinFET technology, which shows better intrinsic gain, in order to maintain high linearity performances, despite the Fully-Differential configuration.

Le but de cette thèse est de fournir des outils permettant à la déduction automatique de réutiliser les résultats déjà obtenus. En effet, la preuve par analogie consiste à construire de nouvelles preuves à partir de preuves existantes. Il faut dans un premier temps reconnaître que le problème à résoudre est semblable à un problème déjà résolu, puis, transformer la solution existante, pour obtenir une solution du nouveau problème. L'approche adoptée consiste à définir formellement des relations liant deux formules logiques du premier ordre - celle dont nous possédons une preuve est appelée référence - pour en déduire une méthode automatique de transformation de la preuve de référence en une preuve de la nouvelle formule. Le concept d'analogie est très puissant, mais aussi très intuitif. Ainsi, pour le formaliser, nous l'avons réduit à des concepts plus simples afin de les automatiser. Nous avons défini quatre relations liant les formules, que nous appelons similitudes. Ces similitudes considèrent les propriétés de la logique propositionnelle, les propriétés des quantificateurs, le renommage des fonctions et prédicats et les propriétés associatives-commutatives des connecteurs logiques. Un outil fondamental pour la reconnaissance de ces similitudes est un algorithme de filtrage du second ordre modulo AC. La complétude et la terminaison de cet algorithme montrent la décidabilité du problème de filtrage AC du second ordre. Les transformations de preuves correspondant à ces similitudes sont données pour les preuves par expansion introduites par Miller et Pfenning. Cette représentation possède des propriétés très intéressantes pour l'analogie. Pour dépasser le stade des similitudes, nous utilisons le calcul de différence, qui utilise les échecs du filtrage. Nous montrons que lorsque la différence entre les deux formules considérées est simple, nous pouvons espérer une méthode complète d'analogie. Enfin, nous montrons, dans le cas général, et à partir d'exemples, comment l'analogie peut être envisagée par l'étude de la différence.

Cette thèse de doctorat se subdivise en deux parties. La première partie est focalisée sur l'analyse et la compensation des ondes de réflexion qui apparaissent lorsque, dans le domaine électrique autant que dans le domaine mécanique, l'interconnexion entre deux sous systèmes se comporte comme une ligne de transmission et dégrade les prestations nominales du système. Dans cette optique, on propose un cadre alternatif à la compensation par filtres passifs qui se base sur la technologie des filtres actifs et qui garantit une atténuation du phénomène des ondes de réflexion. Bien que cette nouvelle approche à la compensation soit orientée aux systèmes électriques, une parfaite dualité avec le bien connu problème de la téléopération prouve la généralité de notre analyse qui peut donc être naturellement étendue au domaine mécanique et électromécanique. La seconde, et moins développée, partie du manuscrit est dédiée à l'extension de l'analogie "masse-inducteur" "ressort-condensateur" entre les systèmes mécaniques et électriques. Une fois définies les limites d'une telle analogie, on introduit le nouvel élément électrique qu'on appelle "pseudo-inducteur" et qui est physiquement interprétable comme un inducteur standard contrôlé en courant avec un coefficient de couplage magnétique régulé en voltage. Ainsi, on peut étendre la formulation donnée par les équations de Brayton-Moser aux systèmes mécaniques décris à travers la formulation Lagrangienne, potentiellement non-linéaires, et leurs associer une contrepartie électrique. Puis, en exploitant la description en puissance de cette classe de systèmes mécaniques on propose une nouvelle propriété de passivité formulée en puissance<br>This PhD work consists of two parts. The first one is focused on the analysis and compensation of the wave reflection phenomenon that occurs whenever, in the electrical as in the mechanical domain, the mutual interconnection among the constituent subsystems behaves as a transmission line and degrades the expected performances of the whole system. In this respect, we propose an novel compensation framework based on active filters technology that guarantees an attenuation of the wave reflections phenomenon. Although this new compensation approach is electrical systems oriented, a perfect duality with the well-known robotic teleoperation problem shows the generality of our analysis that could be naturally extended to the mechanical and electromechanical domain. The second, and less extensive, part of the manuscript is devoted to extend the well-known mass--inductor spring--capacitor analogy between mechanical and electrical systems. Once defined the limits of such standard analogy, we introduce a new electrical element,“the pseudo-inductor”, physically interpretable as a normal current-controlled inductor with coupling coefficient voltage-controlled. Hence,we give rise to an extension of the Brayton-Moser framework enlarging to possibly non-linear mechanical (Euleur-Lagrangian) systems an electrical counterpart. Furthermore, exploiting the power-based description of such a class of mechanical systems we provide a novel passivity property that open the doors to recent Passivity-Based Control strategies, already and successfully applied in RLC networks, that cope with the supplied power, e. G. , Power Shaping, instead of the internal energy of a system,e. G. ,Energy Shaping

Wong Chun Kit.<br>Thesis submitted in: October 2006.<br>Thesis (M.Phil.)--Chinese University of Hong Kong, 2007.<br>Includes bibliographical references (leaves 73-76).<br>Abstracts in English and Chinese.<br>Chapter 1 --- Introduction --- p.1<br>Chapter 1.1 --- Background and Motivation --- p.1<br>Chapter 1.2 --- Objectives --- p.4<br>Chapter 1.3 --- Contributions --- p.4<br>Chapter 1.4 --- Thesis Outline --- p.5<br>Chapter 2 --- Digital Signal Processing --- p.6<br>Chapter 2.1 --- Introduction --- p.6<br>Chapter 2.2 --- Discrete-time Signals and Systems --- p.7<br>Chapter 2.2.1 --- Discrete-time Signals --- p.7<br>Chapter 2.2.2 --- Discrete-time Signal Processing Systems --- p.9<br>Chapter 2.2.3 --- Linear Time-Invariant (LTI) Systems --- p.10<br>Chapter 2.3 --- Finite Impulse Response (FIR) Filters --- p.13<br>Chapter 2.3.1 --- Introduction --- p.13<br>Chapter 2.3.2 --- Windowing FIR Filter Design Method --- p.15<br>Chapter 2.4 --- Infinite Impulse Response (IIR) Filters --- p.17<br>Chapter 2.4.1 --- Introduction --- p.17<br>Chapter 2.4.2 --- Bilinear Transform IIR Filter Design Method --- p.18<br>Chapter 2.4.3 --- Spectral Transformations of IIR Filters --- p.22<br>Chapter 2.5 --- Comparison on FIR and IIR Filters --- p.25<br>Chapter 2.6 --- Digital Signal Resampling --- p.26<br>Chapter 2.6.1 --- Introduction --- p.26<br>Chapter 2.6.2 --- Resampling by Decimation --- p.26<br>Chapter 2.6.3 --- Resampling by Interpolation --- p.28<br>Chapter 2.6.4 --- Resampling by a Rational Factor --- p.29<br>Chapter 2.7 --- Introduction to Dual Fixed-point (DFX) Representation --- p.30<br>Chapter 2.8 --- Summary --- p.33<br>Chapter 3 --- Lyon and Mead's Cochlea Model --- p.34<br>Chapter 3.1 --- Introduction --- p.34<br>Chapter 3.2 --- Digital Cochlea Model: Cascaded IIR Filters --- p.37<br>Chapter 3.2.1 --- Introduction --- p.37<br>Chapter 3.2.2 --- Bandwidth and Centre frequencies --- p.38<br>Chapter 3.2.3 --- Zeros and Poles --- p.39<br>Chapter 3.3 --- Modifications for Decimated Cochlea Model --- p.41<br>Chapter 3.3.1 --- Introduction --- p.41<br>Chapter 3.3.2 --- Aliasing Avoidance --- p.42<br>Chapter 3.3.3 --- Coefficient Modification after Decimation --- p.43<br>Chapter 3.4 --- Summary --- p.47<br>Chapter 4 --- System Architecture --- p.48<br>Chapter 4.1 --- Introduction --- p.48<br>Chapter 4.2 --- Hardware Platform and CAD Tools --- p.48<br>Chapter 4.3 --- Sequential Processing Electronic Cochlea --- p.51<br>Chapter 4.3.1 --- Pipelining - An Interleaving Scheme --- p.53<br>Chapter 4.3.2 --- Decimation in Sequential Processing Electronic Cochlea . --- p.54<br>Chapter 4.3.3 --- Multiple Sequential Cores --- p.55<br>Chapter 4.3.4 --- Architecture of the DFX Filter Computation Core --- p.55<br>Chapter 4.4 --- Summary --- p.60<br>Chapter 5 --- Experimental Results --- p.61<br>Chapter 5.1 --- Introduction --- p.61<br>Chapter 5.2 --- Testing Environment --- p.61<br>Chapter 5.3 --- Performance of the Sequential Electronic Cochlea --- p.63<br>Chapter 5.3.1 --- Comparisons --- p.63<br>Chapter 5.4 --- Summary --- p.69<br>Chapter 6 --- Conclusions --- p.70<br>Chapter 6.1 --- Future Work --- p.72<br>Bibliography --- p.73

Starting from fundamental principles, the quantitative analogies between electron waves in semiconductors and electromagnetic waves in dielectrics have been developed.1 A voltage-biased semiconductor superlattice structure that can serve simultaneously as an electron filter and a tunable emitter has recently been proposed.2 The current-voltage (I–V) and transmission characteristics of these structures are analyzed by means of a nonself-consistent (NSC) and a self-consistent (SC) calculation. For the NSC calculation, only the Schrodinger equation is solved, but for the SC calculation both the Schrodinger and Poisson equations are solved iteratively.3 The approach of Esaki et al4. is used for the computation of the I–V characteristics. It is shown that for low-to-medium Fermi energies, the effect of the space-charge on the filter/emitteroperation is small and results in a shift of the I–V and transmission characteristics toward higher bias voltages. Examples of Ga1-xAlxAs filter/emitters are presented. Resonant filter/emitters with a current peak-to-valley ratio of ~50, as well as nonresonant devices, are analyzed. Charge-density distributions are presented. Superlattice electron filters/emitters can be used as high-speed switches and oscillators and as monoenergetic emitters in electroluminescent devices and photodetectors.

Starting from fundamental principles, quantitative analogies between quantum electron waves in semiconductors and electromagnetic optical waves in dielectrics have been developed.1 Due to those analogies optical design techniques can be adapted for the design of narrowband superlattice electron filter/emitters. A voltage-biased semiconductor superlattice structure can serve simultaneously as an electron filter and as a continuously tunable emitter. The thickness of each superlattice layer is restricted to be an integer multiple of the monolayer thickness. Furthermore, for practical materials (Ga1− x Al x As), there is a usable composition range and a range of usable electron energies to avoid intervalley and phonon scattering that degrade the electron coherence. Under these constraints, an optimum design procedure has been developed that specifies the layer compositions and thicknesses for a given bias voltage and input kinetic energy. Examples of Ga1− x Al x As filter/emitters are presented. Sensitivity of the device to fabrication variations is investigated. These superlattice electron filter/emitters can exhibit very narrow electron kinetic energy passbands and can be integrated into solid state devices for potential use as monoenergetic emitters for electroluminescent devices, photodetectors, and fast ballistic transistors.

Starting from fundamental principles, quantitative analogies between electron waves in semiconductor materials and electromagnetic waves in dielectrics are presented. This in turn suggests a new class of electron wave optical devices such as narrowband superlattice interference filters. Phase effects associated with an electron wave are incorporated using the electron wave vector, which is proportional to the square root of the product of the effective mass and the electron kinetic energy. It is shown that the amplitude of a free electron wave is analogous to the electric field of a TE polarized electromagnetic wave in a dielectric. Amplitude effects associated with an electron wave are incorporated, using an effective amplitude refractive index that is proportional to the square root of the ratio of the kinetic energy to the effective mass. A simple expression for the critical angle for total internal reflection of an electron wave is developed. By analogy to the electromagnetic optical case, the overall electron transmissivity and reflectivity of a semiconductor superlattice are determined.

Abstract After two years of development, the GAIA Explorer is now ready to assist Geoscientists at Total! This knowledge platform works like a little Google, but with a focus solely on Geosciences - for the time being. The main goal of the GAIA Explorer is to save time finding the right information. Therefore, it is particularly useful for datarooms or after business acquisitions to quickly digest the knowledge, but also for feeding databases, exploration syntheses, reservoir studies, or even staff onboarding specially when remote working. With this additional time, Geoscientists can focus on tasks with added value, such as to synthesize, find analogies or propose alternative scenarios. This new companion automatically organizes and extracts knowledge from a large number of unstructured technical documents by using Machine Learning (ML). All the models relie on Google Cloud Platform (GCP) and have been trained on our own datasets, which cover main petroleum domains such as geosciences and operations. First, the layout of more than 75,000 document pages were analyzed for training a segmentation model, which extracts three types of content (text, images and tables). Secondly, the text content extracted from about 6,500 documents labelled amongst 30 classes was used to train a model for document classification. Thirdly, more than 55,000 images were categorized amongst 45 classes to customize a model of image classification covering a large panel of figures such as maps, logs, seismic sections, or core pictures. Finally, all the terms (n-grams) extracted from objects are compared with an inhouse thesaurus to automatically tag related topics such as basin, field, geological formation, acquisition, measure. All these elementary bricks are connected and used for feeding a knowledge database that can be quickly and exhaustively searched. Today, the GAIA Explorer searches within texts, images and tables from a corpus (document collection), which can be made up of both technical and operational reports, meeting presentations and academic publications. By combining queries (keywords or natural language) with a large array of filters (by classes and topics), the outcomes are easily refined and exploitable. Since the release of a production version in February 2021 at Total, about 180 users for 30 projects regularly use the tool for exploration and development purposes. This first version is following a continuous training cycle including active learning and, preliminary user feedback is good and admits that some information would have been difficult to locate without the GAIA Explorer. In the future, the GAIA Explorer could be significantly improved by implementing knowledge graph based on an ontology dedicated specific to petroleum domains. Along with the help of Specialists in related activities such as drilling, project or contract, the tool could cover the complete range of upstream topics and be useful for other business with time.