Dissertations / Theses on the topic 'Filtre Gm-C'

The present manuscript studies the limitations and the opportunities resulting in using fully-active circuits as an alternative to classical passive solutions for the realization of an RF filtering for TV tuners. This RF filtering has to be frequency tunable, selective and high performances in terms of noise and linearity. After the study of the state-of-the-art, two structures of filter are studied in details and simulated on a second order bandpass topology which best fulfills the required specifications. Proposed Gm-C filters have interesting performances but are limited by the gyrator which is the main source of degradation of the RF signal in this structure. A Rauch filter is also proposed with the purpose of designing a highly linear filter to increase the dynamic range. An original feedback allows using this filter with a good selectivity – gain trade-off, as well as high RF performances. This filter has been integrated on silicon and measured in laboratory, leading to perfect agreement with simulations. Proposed Gm-C and Rauch structures are compared to state-of-the-art results from the literature by means of an innovative figure-of-merit. An interesting perspective to this work is proposed though the study of N-path filters which exhibit encouraging results but may require important changes in the TV tuner architecture to be used at full potential
La présente thèse étudie les limitations et les opportunités résultant de l’utilisation de circuits purement actifs comme alternative aux circuits passifs classiques pour la réalisation d’un filtrage RF pour récepteur TV. Ce filtrage RF doit être accordable en fréquence, sélectif et à hautes performances en termes de bruit et de linéarité. Après étude de l’état de l’art, deux structures de filtres ont été étudiées plus en détails et simulées, sur une topologie passe bande du second ordre qui est celle qui répond le mieux à nos spécifications. Les filtres Gm-C propose��s ont des performances intéressantes mais limitées car le gyrateur dégrade le signal RF. Un filtre de Rauch est proposé par ailleurs avec le but de créer un filtre hautement linéaire pour augmenter la dynamique. Une rétroaction originale permet l’utilisation de ce filtre avec un bon compromis sélectivité – amplification, ainsi que de très bonnes performances RF. Ce filtre a été réalisé sur silicium et mesuré en laboratoire, menant à une très bonne corrélation des résultats. Enfin, les deux structures proposées ont été comparées à l’état de l’art de la littérature grâce à une figure de mérite. Une perspective intéressante à ce travail est également introduite à travers les filtres N-path, qui fournissent des résultats encourageants mais qui nécessitent un remaniement de l’architecture du récepteur TV

This work analyzes tuning capabilities of different fully integrated active filter topologies. Work only deals with continuous time active filters. Topologies described in this work differ in type of active element and in method of frequency tuning. Techniques of tunning are proved on second order low pass filter. Filter topologies are compared from tunning capabilities and from point of total harmonic distortion. The main building block of all filters is integrator.

This master thesis deals with the problematics of CT filters and focuses on Gm – C filter. Three linearisation techniques are listed and compared in terms of linear input range, distortion and retuning. In the practical part – second - order low – pass filter is designed and its tuning capabilities are examined.

This master’s thesis deals with the design of tuneable frequency second order filter in CMOS technology. The thesis describes the design of a transconductor and its utilization for tunable gm-C filter. The design and all simulations were made in Cadence Spectre and Virtuoso software. Limitedly Orcad Pspice and SNAP were also used.

L'objectif est d'étudier un bloc de terminal RF pour lequel la demande de reconfigurabilité est parmi les plus prononcées, dans le cadre des télécommunications mobiles des générations futures et dans l'optique de l'évolution des terminaux vers des systèmes multi-standards. Il s'agit du filtre actif analogique passe-bas en bande de base dans une chaîne de réception homodyne, qui doit s'adapter aux besoins du standard, au moins en terme d'ordre, de fréquence de coupure, de rapport signal à bruit et de linéarité. La philosophie de cette étude vise à obtenir un bloc de filtrage analogique reconfigurable à volonté. Après une description du contexte et un état de l'art extensif, nous proposons l'introduction d'une nouvelle figure de mérite qui permet de tenir compte du caractère singulier du contexte des radiocommunications mobiles multinormes, notamment en terme de flexibilité des structures et de l'appréciation du compromis bruit/linéarité au sein de ces systèmes. La configurabilité de systèmes de filtrages est ici abordée selon une approche double: - une première approche consiste à relâcher les contraintes d'accordabilité en utilisant la commutation d'éléments actifs, permettant alors de segmenter un large domaine en plusieurs sousdomaines plus accessibles en terme de spécifications électriques. La faisabilité d'un tel système est démontrée dans une technologie BiCMOS 0. 25µm - nous proposons ensuite une technique de construction de structures de filtres Gm-C configurable en topologie (type et ordre du filtre). Une architecture de contrôle numérique de la fréquence de coupure est par ailleurs proposée. Le démonstrateur du système est développé dans une technologie CMOS 0. 13 µm.

This thesis deals with the design, layout, fabrication, testing and characterization of a second-order filter (biquad) using the transconductance-C (gm-C) technique. The biquad was designed to realize the four filter functions - lowpass, highpass, bandpass and notch - by appropriate choice of input and output terminals and element values. The tunable range of frequencies for the biquad was designed to be 18-59MHz. The quality factor of the biquad was designed to be tunable from approximately 1/3 to 3. The filter was designed in LEVEL2 SPICE, laid out using MAGIC, and the circuit was fabricated using MOSIS's 2μm CMOS analog (n-well) process. The circuit board for testing the chip was designed using the PCB design system -PADS-PCB. The chip was tested using the Network Analyzer HP 4195A. The performance of the filter was then compared with the design objectives and simulation results. Both the pole frequency and the quality factor were found to be tunable by the same factor as the design. Noise analysis showed the output noise to be less than -65dB. The notch function could not be experimentally verified due to high sensitivity of this function to component tolerances and process variations. Power dissipation of the filter was found to be 6m W.

Orientadores: Jacobus Willibrordus Swart, Jader Alves de Lima Filho
Dissertação (mestrado) - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação
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Resumo: Este trabalho envolve o estudo de uma nova arquitetura para filtros integrados com freqüência de corte em sub-hertz, orientado para aplicações na área biomédica, possuindo requisitos como baixo consumo e baixa tensão de operação. Devido a sua aplicação também em sistemas implantáveis, o circuito deve operar com tensão de alimentação variando de 0,9V até 1,6V. Para as aplicações envolvendo circuitos implantáveis, as variações de temperatura não são críticas, embora o circuito tenha sido projetado para uma variação de 0°C até 100°C. Este estudo engloba análise, projeto, simulação, fabricação e caracterização experimental do filtro, sendo também testado com um modelo de sinal de eletrocardiograma (ECG). O filtro proposto é do tipo gm-C e se utiliza do controle da impedância vista pela fonte de um transistor NMOS para o ajuste da freqüência de corte. Comparativamente a outras topologias, possui vantagens como o simples controle da freqüência de corte, além da facilidade de imposição de uma tensão de modo-comum. Em termos de desvantagens, uma das principais está no fato de haver distorções significativas para sinais de alta amplitude (tipicamente acima de algumas dezenas de mili-volts). Na maioria das aplicações biomédicas, ou mesmo, por exemplo, sinais de origem sísmica, onde ambos possuem componentes de freqüência bem baixas, as amplitudes são de baixa magnitude. O principal parâmetro testado no circuito foi a freqüência de corte e seu ajuste com a corrente de polarização. Ainda, de forma a testar a capacidade do circuito de processar um sinal sem distorção, impondo um modo comum ao mesmo, foi utilizado o padrão adotado pela norma européia CENELEC (European Committee for Electrotechnical Standardization) para o sinal de ECG. No desenvolvimento foram utilizadas técnicas de projeto para circuitos de baixa potência, assim como utilização do modelo compacto ACM (Advanced Compact Model) para dimensionamento e cálculos manuais, obtendo-se expressões simples para a freqüência de corte. Fatores importantes para este tipo de projeto como correntes de fuga e nível de inversão do canal foram considerados, assim como as influências das capacitâncias parasitas. As correntes de fuga possuem um modelamento muitas vezes questionável e impreciso. Deste modo, de forma a obter uma idéia clara das fugas envolvidas, duzentos transistores NMOS unitários (0,8?m/10?m) foram colocados em paralelo para medir a fuga nas junções em função da temperatura e tensão reversa de polarização. Os dados obtidos de dez amostras de um mesmo lote mostraram um comportamento dentro do esperado. A média medida das correntes de fuga de um transistor unitário para as temperaturas de 27°C e 85°C foram respectivamente 46fA e 3,4pA. Dois filtros foram projetados para obter uma maior flexibilidade nos testes. Ambos os filtros se utilizam de uma fonte de corrente proporcional à temperatura (PTAT) única de valor típico medido igual a 5,65nA como polarização. Cada filtro se utiliza de um OP-AMP para impor o modo-comum e um divisor de corrente de Bult, obtendo-se uma corrente da ordem de pA para polarizar o filtro propriamente dito. O primeiro filtro usa a própria corrente de PTAT para polarização do nó de entrada que define a freqüência de corte. Com isto, é possível uma compensação de primeira ordem para sua variação com temperatura. O segundo filtro possui uma entrada de corrente independente, de forma que a mesma pode ser alterada externamente, possibilitando verificar a variação da freqüência de corte em função da polarização. A verificação funcional dos sub-circuitos que constituem o filtro, assim como todo o sistema, foi realizada utilizando-se simuladores SMASH/PSPICE/Cadence com modelos Bsim3v3, considerando-se a variação dos parâmetros de processo e intervalo de temperatura de 0ºC à 100ºC. O layout do circuito foi realizado através do programa Cadence, e possui uma área efetiva de 0,263mm2 para os dois filtros. A fabricação foi feita na foundry da AMS, usando-se tecnologia CMOS 0,35?m. A caracterização experimental envolveu análise da freqüência de corte, fugas em junções, resposta a um sinal de ECG, consumo e, comportamento com relação à tensão de alimentação. Resultados experimentais para a freqüência de corte do primeiro filtro, em dez amostras, resultaram em uma média de 2,38Hz e desvio padrão de 0,32Hz. A corrente de referência PTAT apresentou uma média de 6,90nA e um desvio padrão de 1,04nA. O comportamento PTAT da mesma pôde ser observado experimentalmente (de forma indireta) na faixa de 27°C à 85°C. A freqüência de corte em função da corrente de polarização foi analisada usando-se o segundo filtro, que confirmou a dependência linear por quase uma década de variação da corrente de entrada. Também, as respostas aos padrões de sinal de ECG de baixa e alta amplitude foram analisadas com sucesso no primeiro filtro. O trabalho teve seus objetivos alcançados, realizando etapas de especificação, projeto, layout e caracterização. Os resultados experimentais obtidos estão dentro do esperado, validando a arquitetura proposta de um filtro passa-altas, totalmente integrado, com freqüência de corte em sub-hertz
Abstract: This work aims the study of a new topology for integrated filters with cut-off frequencies around sub-hertz, oriented to biomedical applications, having requisites as low consumption and low voltage operation. Due to its application also in implantable systems, the circuit must operate with supply voltage varying from 0.9V to 1.6V. For applications involving implantable circuits, temperature variations are not critical, although this circuit was designed for an operation from 0ºC to 100ºC. This study conducts analyses, design, simulation, fabrication and experimental characterization of the filter, being tested with an electrocardiogram signal (ECG). The proposed filter is a gm-C type and uses the control of the impedance seen from the source of a NMOS transistor to adjust the cut-off frequency. Comparatively to other topologies, it has advantages as simple cut-off frequency control and its easiness to impose a common-mode voltage. As drawbacks, one of the most significant is in the fact of having significant distortions with high amplitude signals (tipically above some tens of milli-volts). In most biomedical applications, or even signals with a seismic origin, for example, where both have very low frequency components, their amplitudes are low in magnitude. The main tested parameter in the circuit was the cut-off frequency and its adjustment with the biasing current. Besides, as a test for the circuit capability of processing a signal without distortion, while imposing it a common-mode, it was used a standard from an European norm called CENELEC (European Committee for Electrotechnical Standardization) for the ECG signal. In the development were used design techniques for low power circuits, as well as the use of the compact model ACM (Advanced Compact Model) for dimensioning and hand calculations, getting simple expression for the cut-off frequency. Important factors for this kind of project as leakage current and channel inversion level were considered, also the influence of stray capacitances. The leakage current has a doubtful and imprecise modeling. Herewith, as a way to get a better idea of leakage values involved, two hundred unity NMOS transistors (0,8?m/10?m) were placed in parallel in order to measure the junction leakages as a function of temperature and reverse voltage biasing. The obtained data for ten samples of a single batch showed a behavior as expected. The mean value for the leakage currents of a unity transistor for temperatures between 27ºC and 85ºC were repectivelly, 46fA and 3.4pA. Two filters were designed to obtain a larger flexibility during the tests. Both filters use a unique PTAT current source with measured typical value equal to 5,65nA as biasing. Each filter uses an OP-AMP to impose a common-mode voltage and a Bult current divider, getting a current with a magnitude of pA to bias the filter itself. The first filter uses the proportional to temperature (PTAT) current directly from source to bias the input branch that defines the cut-off frequency. The second filter has and independent input, so that it can be changed externally, allowing to verify the cut-off frequency as a function of biasing current. The functional verification of the sub-circuits that build-up the filter, as the whole system, was performed using simulators SMASH/PSPICE/Cadence with Bsim3v3 models, considering the process parameters variations and temperature interval from 0ºC to 100ºC. The circuit layout was developed through Cadence program, and has an effective area of 0,263mm2 for both filters. The fabrication was done on AMS foundry, using the CMOS 0.35?m technology. The experimental characterization considered cut-off frequency analysis, junction leakages, response to an ECG signal, consumption and, behavior with respect to supply voltage. Experimental results for cut-off frequency of the first filter, on ten samples, resulted in a mean value of 2.38Hz with a standard deviation of 0.32Hz. The PTAT current presented a mean value of 6.90nA with 1.04nA of standard deviaton. The PTAT behavior of this current could be experimentally observed on range of 27ºC to 85ºC. The cut-off frequency as a function of biasing current was analyzed using the second filter, which confirmed the linear dependency for almost a decade of input current variation. Also, the responses to ECG standard signals of low and high amplitudes were analyzed successfully on the first filter. This work has achieved its purpose, making specifications stages, design, layout and characterization. The experimental results obtained are within expected, validating the proposed architecture of a high-pass filter, fully integrated, with cut-off frequency in sub-hertz
Mestrado
Eletrônica, Microeletrônica e Optoeletrônica
Mestre em Engenharia Elétrica

A tendência do mercado da microeletrônica é integrar em um mesmo chip sistemas eletrônicos completos, incluindo simultaneamente circuitos analógicos, digitais e RF. Por causa da complexidade do problema de projeto, a parte analógica e RF desses sistemas é o gargalo do desenvolvimento. Uma alternativa de projeto para circuitos analógicos é formular o projeto como um problema de otimização matemática conhecido como programação geométrica. As vantagens são: o ótimo global é obtido eficientemente, e é possível fazer automatização do projeto. A principal desvantagem é que não todos os parâmetros e equações que modelam um circuito são compatíveis com a forma desse problema de otimização. Os receptores para sistemas de comunicação modernos realizam o processo de downconvertion usando uma freqüência intermediária baixa ou diretamente em banda-base. As topologias de receptor Zero-IF e Low-IF são preferidas por sua alta capacidade de integração e baixo consumo de área e de potência. Os filtros analógicos são blocos de composição básicos nesses sistemas. Neste trabalho é desenvolvida uma metodologia de projeto baseada na aplicação de programação geométrica para projeto de filtros Gm-C. A metodologia de projeto foi usada para projetar filtros analógicos complexos e reais para os padrões de comunicação Bluetooth e Zigbee IEEE/802.15.4. Os resultados obtidos mostram que a metodologia de projeto proposta neste trabalho é uma solução efetiva para reduzir o tempo de projeto e otimizar o desempenho de filtros analógicos.
The tendency of the microelectronic market is to integrate in the same chip complete electronic systems, including digital, analog and RF circuits simultaneously. The analog part of those systems represents the bottleneck in the design process. The complexity of analog design makes this one an intuitive and creative process but time expensive. An alternative methodology for analog integrated circuits design is to represent the design as a mathematical optimization problem known as geometric programming. The advantages are: global optimum achieved efficiently, and the possibility of design automation. The main disadvantage, is that all the parameters or equations that characterize a circuit are not compatible with the form of this optimization problem. Modern receivers perform downconvertion of the signal using very low, or zero intermediate frequency. Zero-IF and Low-IF topologies are preferred because of their high integration capabilities, and low area and power consumption. Analog filters are basic building blocks of such systems. In this work, a design methodology based on geometric programming is developed, for automated and optimal design of Gm-C filters. The design methodology was used to design analog complex and real filters for the digital communications standards Bluetooth and Zigbee IEEE/802.15.4. The results show that the design methodology proposed in this work is an effective solution for fast, automated and optimal analog filter design

Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.
Committee Chair: Allen Phillip; Committee Member: Hasler Paul; Committee Member: Keezer David; Committee Member: Kenny James; Committee Member: Pan Ronghua.

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Sistemas de aquisição e processamento de sinais exigem constante desenvolvimento e pesquisa com o avanço da tecnologia, a fim de diminuir área e consumo de energia dos circuitos. O filtro, elemento essencial em sistemas de aquisição e processamento, deve ser capaz de atenuar sinais indesejados e permitir a passagem livre dos sinais de interesse, com um cuidado ainda maior quando se trata de aplicações médicas. Neste trabalho, é proposto um filtro CMOS notch elíptico G-C de 5ª ordem para rejeição de ruídos provenientes da rede elétrica em aplicações de eletroencefalograma. O circuito é desenvolvido em tecnologia CMOS 130 nm, alimentado por uma fonte de 1,0 V, e possui um circuito de capacitância programável capaz de chavear entre eliminar ruídos de 50 ou 60 Hz. Foram realizadas simulações no ambiente CADENCE (Virtuoso Analog Design Environment L Editing), apresentando atenuação superior a 90 dB para as frequências de interesse, consumo abaixo de 600 nW e área de 879,2 m², mostrando que o circuito é capaz de filtrar os ruídos dos sinais de EEG, além de operar com baixa potência, permitindo utilização em aplicações portáteis.

Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.

A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.

The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.

碩士
國立清華大學
電機工程學系
92
Abstract The third generation wireless communication systems (3G) prevail over the market recently. This is because the 3G systems provide higher data rate than the traditionally 2G ones. The direct conversion receiver is a possible solution due to low-power, low-cost requirement. Channel-select filter is a crucial building block since it has to define the desired signal bandwidth and attenuate the out-band interference to reduce the dynamic range requirement of ADC. The First chapter describes the channel-select filter in different receiver architectures. Basic theories of the WCDMA system and analog filter are introduced in chapter 2. Chapter 3 presents the modified gm-C architecture for CMOS continuous time filter design. It achieves high linearity under low supply voltage operation. The filter is suitable for fully integrated wireless receivers, like WCDMA system 1.92MHz signal bandwidth. The simulation results of Six-order Butterworth channel-select filter based on modified gm-C structure is illustrated. The filter is realized on TSMC 1P6M CMOS process. The filter linearity is simulated under the out-band two tone test condition. spurious free dynamic range is 62 dB under 1.8V supply voltage. i

碩士
國立臺北大學
電機工程研究所
100
This paper proposes a fifth-order Elliptic operational transconductance amplifier-capacitor (OTA-C) low-pass filter using the complex filter techniques to implement a band-pass filter. Integrating the passive components on-chip will result in frequency error due to the effect of process variations. For this reason, a filter circuit with automatic calibration scheme will be independent on process, voltage and temperature variations. In this work, the passive components are integrated on-chip. The center frequency is 450 kHz and the dynamic range is 35dB. The chip is implemented using TSMC 0.18um 1P6M CMOS process with chip area of 0.76x0.97 mm2 and the total power consumption is 0.14mW. Keywords: Fifth-order elliptic filter, OTA-C low-pass filter, Complex filter, Band-pass filter, Automatic calibration scheme circuit

碩士
國立交通大學
電機與控制工程系所
93
The gm-C filter has been popular in high speed analog filter applications. However, to obtain accurate frequency response is not easy due to process variation. Although several tuning circuits are proposed to improve the accuracy, the cost and circuit complexity are usually very large. In this thesis, based on traditional threshold-voltage compensation method, we proposed a current source biasing technique to reduce the current error caused by inevitable threshold-voltage variation and power line IR drop. Finally we apply this technique to third order gm-C analog filter. SPICE simulations show that for 0.35-μm TSMC Mixed Signal 2P4M process with a 3.3 V power supply, filter passband frequency variation is reduced significantly.

碩士
國立成功大學
奈米科技暨微系統工程研究所
98
In this thesis, two kinds of fifth-order differential Gm-C low pass filters are presented. Three operational transconductance amplifiers (OTAs) are employed to realized the filters, namely, the multiple-input-differential-output (MIDO) OTA, the current-mirror-output-differential-input (CMDI) OTA, and the multiple-output-differential-input (MODI) OTA. The fifth-order OTA-C low pass filter was micro-fabricated by using the CMDI and MODI OTA design which required smaller area of die and lower power consumption. The simulated results showed a dynamic range of 51.2dB, while harmonic distortion components were below -50dB for differential input signals up to 100mV peak to peak (Vp-p). The power consumption of this filter was below 320nW, the supply voltage was 1V, and the active area of die was 0.176 mm2. This chip was fabricated with 0.18-μm CMOS process in TSMC. The measured results indicated that this low-voltage and low-power filter possessed the dynamic range of 30.5dB, while total harmonic distortion was less than -40dB for 60mVp-p input. According to the testing results, this filter can be adopted to eliminate the out-of-band interference of the electroencephalography (EEG) whose signal bandwidth is below 100Hz.

碩士
國立交通大學
電機學院碩士在職專班電信組
94
In Chapter 1, there are some descriptions about the role of the IF filter in a communication system. Then, the motivation and the methodology to perform the research of the GM-C filter is presented. In Chapter 2, the fundamental theorem and functional blocks of the GM-C filter are introduced. After that, the possibility to compensate the fixed and variable errors is discussed. In Chapter 3, the author uses one 36MHz IF band-pass filter as reference design to study the corner effects and the temperature effects. Analyses and proves that the two variances of this filter can be compensated by using IC trimming skills and self-compensated bias circuits. In Chapter4, it is concluded that one can use the IC trimming skills to correct the center frequency error of the band-pass filter that is due to the IC process variance, and then use a self-compensation bias circuit to compensate the IC temperature effect. This design methodology is approved in this thesis, but a small error will exist due to the fact that this method is not an auto-feedback system, such as the auto-tuning method. This error will limit the application of the IF filter, but there are still lots of benefits in the low-Q IF filter design. The GM-C filter that is designed by this suggested methodology has a lot of benefits. These benefits are a) simple design method, b) very small IC area, c) low power consumption, d) no interference that exists in the auto-tuning system, and e) no need of an accurate reference frequency source. This method uses the IC trimming technology in the IC test, so the test cost will be increased. The center frequency detection system of band-pass filter will dominate the total test time in the IC tester. To design an excellent center frequency detection system will reduce the IC test cost. The purpose of the GM-C filter design methodology that is presented in this thesis provides another design possibility for GM-C filter mass production. There are some research areas that can be done following this design methodology. The research motivation and the theorems are introduced. The corner effect and temperature effect of the GM-C filter are then analyzed. Finally, this design methodology can be proved to be useful in low-Q IF filter design. The key point of this thesis is to provide an alternative for the mass production of IF band-pass filter design.

碩士
淡江大學
電機工程學系碩士班
93
The analog filter is the primary element of electronic circuit. Nowadays, signal processing system had been forced to design the digital circuit, but we are living in the analog world actually. As the result, the analog filter is necessary as an interface between analog and digital. Because the integrated circuit is growing quickly, the high frequency circuits and SOC (system on a chip) is designed. Based on these two techniques, the high frequency integrated filter is more needed in the future. In the development of integrated filter circuit, which can be differentiated between passive filter technique and active filter technique. Based on the SOC, the integrated active filter would be preferred, because the integrated active filter has small chip size and low active power. In order to achieve high operation frequency, we choose the continuous-time filters which is made by operational transconductance amplifier (OTA) and capacitors. The research of this thesis is to design a new operational transconductance amplifier (OTA) which can achieve a 70MHz band-pass filter. The band-pass filter has simulated by TSMC 181P6M technology model. The property of integrated active-filter is decided by its transconductance value, linearity and linear Range. Those will affect frequency response, total harmonic distortion (THD) and input signal range. In this new operational transconductance amplifier, the fully differential structure is preferred, because it has better noise immunity and distortion properties. We use cross-coupling and unbalanced differential pairs as input stages which can increase and compensate transconductance value, linearity and linear range. In order to solve process variation, the automatic frequency tuning is used. It utilizes the phase characteristic of band-pass filter to product Vtune, the error voltage Vtune can be applied to control the frequency. As the result, the center frequency of fourth order band-pass can operate at 70MHz.

碩士
國立中山大學
資訊工程學系研究所
98
This thesis has described a wide tuning range transconductor combining source degeneration, cross-coupled, translinear loop to achieve high linearity. The transconductance tuning range from 220μs to 1050μs with 1V input range and the total harmonic distortion is -50dB with 0.6Vpp input voltage. And its application to a fifth-order elliptic low-pass Gm-C filter for the front-end RF circuit is presented. In order to transform the passive element circuit into a Gm-C based filter, a GIC flow method has been used. The proposal Gm-C based filter achieve a with performance a low frequency filtering range from 5Mhz to 10Mhz by transconductance tuning.

碩士
淡江大學
電機工程學系碩士班
106
Ultrasound imaging is an imaging method that uses high-frequency sound waves to produce images that led to diagnosis of many diseases. Frequency of ultrasound imaging for medical diagnosis is between 2 to 30 MHz. This thesis presents a design of a 3 order Butterworth Gm-C Low Pass Filter (LPF) for ultrasound System implemented in TSMC 90nm CMOS process. A operational transconductance amplifier (OTA) based on rail-to-rail input pairs is designed and characterized. The LPF achieved a bandwidth of 30 MHz.The total power dissipation is 1.152mW.

This dissertation presents design and implementation of continuous time analog filters for two specific applications: wideband analog systems such as disk drive channel and low-power wireless applications. Specific focus has been techniques that reduce the power requirements of the overall system either through improvement in architecture or efficiency of the analog building blocks. The first problem that this dissertation addresses is the implementation of wideband filters with high equalization gain. An efficient architecture that realizes equalization zeros by combining available transfer functions associated with a biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with 24dB boost is designed using the proposed architecture. The prototype fabricated in standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though at the cost of much larger area. Secondly, a complementary current mirror based building block is proposed, which pushes the limits imposed by conventional transconductors on the powerefficiency of Gm-C filters. Signal processing through complementary devices provides good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly 7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in 1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter realization occupies a relatively small area and is well suited for integration in deep submicron technologies. Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter is designed for a ten bit continuous time sigma delta ADC architecture developed specifically for fine-line CMOS technologies. Inverter based amplification and a common mode feedback for such amplifiers are discussed. The filter consumes 5mW of power and occupies an area of 0.07 mm2.

碩士
國立清華大學
電機工程學系
93
In this thesis, we design an operational transconductance amplifier (OTA) with low distortion and tunable transconductance (Gm). By applying current reusing and gain boosting techniques, the MOS devices in the input stage of the proposed OTA operate in the linear region and the high linear voltage-to-current conversion can be obtained. Using this OTA, a Gm-C filter which is suitable for high frequency operation is constructed. To overcome the process variations, the transconductance of the OTA is tunable so that the cutoff frequency of the Gm-C filter can be set properly. Moreover, an on-chip automatic bandwidth tuning loop is also designed to automatically decide the transconductance of the OTA and compensate most variation effects. To verify the designed circuits, an experimental chip is fabricated in UMC 0.18 mm CMOS process. The realized filter is a 6th-order Butterworth lowpass filter. The power supply voltage is 1.8 V. The measurement results of the filter show that the tuning range of the -3-dB bandwidth is among 5.8 MHz to 7.9 MHz and the DC gain is among –1 dB to –0.12 dB. The total harmonic distortion (THD) is small than –40 dBc when the input signal is 1 MHz sinusoidal waveform with 1.4 Vppd. The input third intercept point (IIP3) is 11 dBV, and the power consumption is 11.75 mW. When activate the on-chip automatic tuning loop, the error of the filter bandwidth is less than 5.3 %.

碩士
國立清華大學
電機工程學系
96
In this thesis, a 4th-order Butterworth Gm-C filter with low power consumption and high linearity performance for wireless communication applications is designed and implemented in two different structures: common lossless-integrator-based structure and novel lossy-integrator-based one. To increase the linearity of the filter, an operational transconductance amplifier (OTA) with high linearity is introduced. Furthermore, the multi-input OTA structure is employed to reduce the power consumption and the active area. Due to the adjustability of the OTA transconductance, an offline frequency tuning system is also added to overcome the bandwidth inaccuracy which is caused by the process variation. In order to evaluate the performances of the designed filters, two test chips are fabricated with TSMC 0.18_μm CMOS process and the supply voltage is 1.8 V. The measurement results of the lossless-integrator-based 4th-order filter show that the filter bandwidth is varied from 10 MHz to 8.8 MHz and the DC gain is about -0.74 dB. The total harmonic distortion (THD) is smaller than -40 dBc when the input signal frequency is 1 MHz and the amplitude is less than 1.5 Vppd. Besides, the power consumption of the filter is about 5.5 mW. According to simulation results, the lossy-integrator-based 4th-order filter has better linearity performance than the lossless-integrator-based one. Its THD is smaller than -40 dBc when the input signal frequency is 1 MHz and the amplitude is less than 1.9 Vppd. Moreover, the power consumption of the lossy-integrator-based 4th-order filter is only 4 mW. By enabling the offline tuning loop, the frequency tuning error is less than 5%.

碩士
國立清華大學
電機工程學系
95
In this thesis, we propose an operational transconductance amplifier (OTA) with low distortion by using some techniques: (a) current reusing (b) gain-boosting (c) MOS triode region operation. Therefore, a high linear relationship between input voltage and output current can be obtained. We use the proposed OTA to implement a sixth-order Gm-C filter for wireless communication applications. Moreover, the bandwidth of the Gm-C filter can be tuned by tuning the transconductance of the OTA. By using this property, we can overcome the bandwidth variation of the filter due to the process variation. An on-chip automatic frequency tuning system is also designed to compensate the bandwidth variation automatically. The power consumption and the active area of the automatic-tuning system are reduced by the lots usage of the digital circuits in the automatic-tuning system. Besides, a low noise fourth-order Butterworth filter implemented with the proposed OTA is also designed for low noise application. In order to verify this design, two test chips are fabricated with TSMC 0.18 μm CMOS process. The power supply is 1.8 V. The measurement results of the first chip show that the -3dB frequency is about 8 MHz and the DC gain is 0.056 dB. The total harmonic distortion (THD) is smaller than -40 dB when the input signal is a 1 MHz sinusoidal waveform with 1.2 Vppd amplitude. The input third intercept point (IIP3) is 10 dBV, and the power consumption of the filter and the automatic-tuning circuit are 8.1 mW and 3.53 mW, respectively. The tuning error of the automatic frequency tuning system is less than 5 %. The measurement results of the second chip show that the -3dB frequency is about 11.5 MHz and the DC gain is -0.61 dB. The THD is 0.96 % with 1.1 Vppd input signal at 1 MHz. The IIP3 is 8 dBV, and the power consumption is 13.3 mW. The noise level is 40.7 nV/rt Hz.

碩士
淡江大學
電機工程學系
90
Because of the process technology has developed rapidly and undergone an incredible development in recent years. Many devices such as microprocessors and communication chips were required to increase their operation frequency. We need a PLL to generate a high frequency reference clock. This thesis is introduced the design and implementation of COMS PLL. This thesis describes a transconductance-C (Gm-C) filter applies on the PLL (Phase-Locked Loop), and implement a fully integrated circuit. This thesis is divided into two parts. The first part is chapter 2, in which the operation mechanisms and related analysis of the phase-locked loop are presented. The second part is chapter 3 and chapter 4, we describe some type of the Gm-C filter and the design of the third-order lowpass Gm-C filter. Finally, chapter 4 presents the third-order lowpass Gm-C filter applied on the PLL, and circuit design of the PLL. In chapter 2 of this thesis, PLL frequency synthesizers will be introduced. And this system contains phase frequency detector, charge pump, voltage controlled oscillator, loop filter and frequency divider.Chapter 3 presents several Gm-C filters, including first-order, second- order and third-order Gm-C lowpass filter. In chapter 4, we employ active element to achieve third-order low-pass filter and apply on the PLL. The PLL was realized in a 0.5μm CMOS technology, operation frequency is 471MHz, and the core circuit dissipates 150mW from a 5-V power supply.

碩士
國立高雄大學
電機工程學系碩士班
96
In this thesis, we design a high-speed and wide-bandwidth continuous-time sigma-delta modulator (CT-SDM) with Gm-C filter. We focus on the design of low power wide-bandwidth (10MHz) CT-SDM for WLAN Std. 802.11b receiver. In the application of wireless receiver, we will prove that continuous-time sigma-delta ADC is more suitable than pipeline or flash ADC. Instead of active-RC filter, we use Gm-C filter in our CT-SDM design because Gm-C filter consumes lower power and requires less limitation on op-amp. The CT-SDM is implemented with TSMC 0.35μm CMOS process. The proposed CT-SDM achieves 43dB peak SNR (signal-to-noise ratio) and 48-dB DR (dynamic range) with 10-MHz bandwidth at 1GHz sampling rate for WLAN Std. 802.11b. The power consumption is 17.3mW with 3.3V power supply.

碩士
國立交通大學
電信工程系所
96
This paper presents a CMOS low-power rail-to-rail transconductor under a supply voltage of 1.8-V. Base on the rail-to-rail transconductor, we build a third-order GM-C filter. Instead of using an n-type and a p-type differential input pairs, we use an n-type and a level-shift n-type differential input pairs to design a rail-to-rail input stage, and both of the differential pairs that work in the weak inversion cost less power than the traditional one. A novel level-shift n-type differential input pair is designed to maintain constant transconductance. The tunable cutoff frequency of the GM-C filter is needed. The total transconductance can be tuning by changing the tail current of the differential pairs. This work designed in TSMC 0.18-μm CMOS technology. Results show that the fluctuation of total transconductance of the proposed transconductor is less than ± 3%. And the cutoff frequency of the GM-C filter is 0.75MHz to 1.5MHz. The power dissipation of the GM-C filter is less than 4mW. The total harmonic distortion of the filter is about -35db.

碩士
國立交通大學
電子工程系所
93
A 5th order CMOS high frequency elliptic low pass filter is designed to achieve narrowest transition band. The filter is composed of Gm blocks and capacitances. The symmetrical & unsymmetrical differential pair increases Gm linearity, and negative impedance increases Gm differential output resistance. The total harmonic distortion (THD) of this filter is -40dB within 0.52Vp-p. Input-referred noise is 211.8uVrms. Dynamic range is 58.4dB for 20MHz input. The power consumption of filters is 32.25mW (include 12.1mW output buffer) from 1.8V supply. The figure-of-merit for the filter is 59.75dB. The filter is implemented in UMC 0.18-μm CMOS technology and has been packaged in SPIL QFN20 which is mounted on PCB board in favor of measurement. The f3db is 226MHz and gain is -4.07 dB with 1.32 dB passband ripple. The power dissipation of this filter is 43.2mW.

碩士
國立成功大學
電機工程學系碩博士班
95
In this thesis, a linearity improved and digitally programmable operational transconductance amplifiers (OTA) for Gm-C filter has been designed and implemented in a 0.35-µm 2P4M CMOS process. In order to improve the linearity of OTA, we used an adaptive biasing technique. In addition, the transconductance of OTA can be controlled by our proposed digitally programmable current mirror technique. A second-order bandpass filter was designed to verify the linearity and transconductance of OTA by using our proposed techniques. The digitally programmable OTA has been simulated by circuit simulator, HSPICE. While the sampling frequency and input frequency are 50 MHz and 10 MHz respectively, the signal-to-noise and distortion ratio (SNDR) of the digitally programmable OTA is 61 dB. In our bandpass filter, the specification of 56-dB third-order intermodulation (IM3) was also achieved with input frequency mixed 9 MHz and 10 MHz.

碩士
國立清華大學
電機工程學系
96
In this thesis, a low-power-consumption multi-bandwidth filter is proposed. There are two operational transconductance amplifiers(OTA) to be designed. One is multi-input and the other is multi-output. By using both OTAs, a six-bandwidth fourth-order Gm-C filter is realized. The six bandwidths are 0.875 MHz, 1.75 MHz, 2.75 MHz, 3.5 MHz, 5 MHz, 10 MHz. Moreover, the bandwidth of the Gm-C filter can be tuned by the transconductance of the OTA. An on-chip automatic frequency tuning system is also designed to compensate. To verify this design, a test chip is fabricated with TSMC 0.18 μm CMOS process and the power supply is 1.8 V. According to the simulation results, total harmonic distortion (THD) is small than 1% when input signal is 1Vppd; IIP3 are more than 5 dBV; P1dB are more than -3 dBV; total capacitors are smaller then 15pF; current consumption is small than 15mA; and bandwidth tuning error is small than 5%.

碩士
國立臺灣科技大學
電子工程系
100
Recently, the PLL-based frequency synthesizers are widely used in wireless communication systems; however, many of PLL architectures are created. This thesis is a design of two chips of frequency synthesizer with tunable Gm-C loop filter. The tunable Gm-C loop filter, instead of a conventional passive loop filter, is used to overcome the process variations of resistance (R) and capacitance (C). The first chip, a 21.6 GHz low-power integer-N frequency synthesizer, is implemented in TSMC 90 nm CMOS process. In this proposed circuit, there are two important features. The primary advantage is the use of an all-nMOS cross-coupled Colpitts VCO, which decreases transistor parasitic capacitances and reduces phase noise. Second, an injection-locked frequency divider (ILFD) is inserted in the first divider stage to divide the high frequency signal. At low supply voltage of 1.2-V, the chip’s measured results achieved locked output frequency tunable from 21.54~21.96 GHz and the phase noise is -103.3 dBc/Hz at 1MHz offset at 21.6 GHz. The overall power consumption is 9.54 mW. Including pads, the chip area is 0.925 (0.925 × 1.0) mm2. The second chip, a 5.8 GHz fractional-N frequency synthesizer, is fabricated in TSMC 0.18 mm CMOS process. To improve phase noise, the VCO adopts cross-coupled Colpitts structure and uses average varactor. The CP employs dynamic current-matching circuit to compensate for the channel-length modulation effect. Furthermore, the MASH 1-1-1 ??{??nmodulator, which performs the fractional division number, can improve the phase noise as well. In this chip design, the measured results achieve locked output frequency tunable from 5.56~5.95 GHz and the phase noise is -109.8 dBc/Hz@1M at 5.8 GHz. The overall power consumption is 22.7 mW. Including pads, the chip area is 1.032 (1.2 × 0.86) mm2.

碩士
國立交通大學
電信工程系所
94
This thesis presents a low-voltage CMOS fifth-order elliptic low-pass gm-C filter with large differential input swings and wide common-mode ranges. The Operational Transconductance Amplifier (OTA) is a low-voltage CMOS voltage-to-current (V-I) converter. The basic OTA cell with NMOS-inputs is connected in parallel with its counterpart PMOS-input OTA circuit, in conjunction with NMOS and PMOS output current mirrors, to achieve large input signal and common-mode voltage ranges. For the gm-C filter, additional tuning circuitry is required in order to compensate the process and temperature variation.. In this OTA design, two frequency tuning circuits are utilized, respectively, to adjust the control voltage of NMOS-input and PMOS-input OTAs so as to fix the filter cutoff frequency and also maintain the equivalence between the two transconductance of NMOS-input and PMOS-input OTAs. The gm-C filter operates with supply voltage of 1.8V, has cutoff frequency of 1.6MHz to 2.4MHz, dissipates 0.75mW power, and has large differential input signals and wide common-mode voltage ranges of ±0.7V.

碩士
國立臺北大學
電機工程學系
105
This is the research for IEEE 802.11 and WiFi. Use fives order Elliptic low pass Gm-C filter. Integrating the passive components on-chip will result in frequency error due to the effect of process variations. Using a fully differential OTA and capacitors equivalent passive element resistance or inductance, implement a continuous time filter. This paper combines the advantages and disadvantages of the previous technology. Select the fully differential amplifier, reduce even harmonic. In order to avoid the output signal does not match the resulting voltage is different. Therefore, join the common mode feedback skills. The OTA use the source degradation、the use of unbalanced differential pairs and the auxiliary differential pairs. Increase the linearity of OTA. Research all kinds of capacitive architecture, the final choice of PMOS capacitance. Normal operation in the acceptable cutoff frequency range and the physical area is about 1.5 times smaller than the MIM capacitor. This paper is LPF, cutoff frequency is 20MHz. The chip is implemented using TSMC 0.18um 1P6M CMOS process with chip area of 1298.56 X 697.15 um2 and the total power consumption is 22.4mW of operating frequency is 30MHz.

碩士
國立中山大學
通訊工程研究所
93
The first topic of this thesis is a novel NTSC video sync separator (NSS) with a high-PSR (power supply rejection) bias generation circuitry (BGC) comprising a temperature compensation circuitry. The proposed BGC is composed of step-down regulators and a bandgap-based bias with cascode current control. The clamping voltages required for sync separation from an NTSC signal are generated. The second topic is a temperature-compensated 6th order transconductance-C (Gm-C) anti-aliasing filter (AAF) with digitally tunable bandwidth which can be applied in the analog front-end circuit of DVB-T receivers. The proposed AAF is controlled by digital signals to provide three different baseband bandwidth (6, 7, 8 MHz) selection. A regulator with a bandgap circuitry supplies a stable voltage to suppress the variations of power and temperature. Moreover, a temperature -compensated circuitry is used to neutralize bandwidth drifting caused by the temperature variation. The bandwidth accuracy of the proposed design verified by HSPICE post-layout simulations is better than 3.28% at every PVT (process, supply voltage, temperature) corner. It is adequate for the DVB-T receivers’ baseband processing.

High linearity transmitters and receivers should be used to efficiently utilize the available channel bandwidth. Power consumption is also a critical factor that determines the battery life of portable devices and wireless sensors. Three base-band and RF building blocks are designed with the focus of high linearity and low power consumption. An architectural attenuation-predistortion linearization scheme for a wide range of operational transconductance amplifiers (OTAs) is proposed and demonstrated with a transconductance-capacitor (Gm-C) filter. The linearization technique utilizes two matched OTAs to cancel output harmonics, creating a robust architecture. Compensation for process variations and frequency-dependent distortion based on Volterra series analysis is achieved by employing a delay equalization scheme with on-chip programmable resistors. The distortion-cancellation technique enables an IM3 improvement of up to 22dB compared to a commensurate OTA without linearization. A proof-of-concept lowpass filter with the linearized OTAs has a measured IM3 < -70dB and 54.5dB dynamic range over its 195MHz bandwidth. Design methodology for high efficiency class D power amplifier is presented. The high efficiency is achieved by using higher current harmonic to achieve zero voltage switching (ZVS) in class D power amplifier. The matching network is used as a part of the output filter to remove the high order harmonics. Optimum values for passive circuit elements and transistor sizes have been derived in order to achieve the highest possible efficiency. The proposed power amplifier achieves efficiency close to 60 percent at 400 MHz for -2dBm of output power. High efficiency class A power amplifier using dynamic biasing technique is presented. The power consumption of the power amplifier changes dynamically according to the output signal level. Effect of dynamic bias on class A power amplifier linearity is analyzed and the results were verified using simulations. The linearity of the dynamically biased amplifier is improved by adjusting the preamplifier gain to guarantee constant overall gain for different input signal levels.

Three main analog circuit building blocks that are important for a mixed-signal system are investigated in this work. New building blocks with emphasis on power efficiency and compatibility with deep-submicron technology are proposed and experimental results from prototype integrated circuits are presented. Firstly, a 1.1GHz, 5th order, active-LC, Butterworth wideband equalizer that controls inter-symbol interference and provides anti-alias filtering for the subsequent analog to digital converter is presented. The equalizer design is based on a new series LC resonator biquad whose power efficiency is analytically shown to be better than a conventional Gm-C biquad. A prototype equalizer is fabricated in a standard 0.18μm CMOS technology. It is experimentally verified to achieve an equalization gain programmable over a 0-23dB range, 47dB SNR and -48dB IM3 while consuming 72mW of power. This corresponds to more than 7 times improvement in power efficiency over conventional Gm-C equalizers. Secondly, a load capacitance aware compensation for 3-stage amplifiers is presented. A class-AB 16W headphone driver designed using this scheme in 130nm technology is experimentally shown to handle 1pF to 22nF capacitive load while consuming as low as 1.2mW of quiescent power. It can deliver a maximum RMS power of 20mW to the load with -84.8dB THD and 92dB peak SNR, and it occupies a small area of 0.1mm2. The power consumption is reduced by about 10 times compared to drivers that can support such a wide range of capacitive loads. Thirdly, a novel approach to design of ADC in deep-submicron technology is described. The presented technique enables the usage of time-to-digital converter (TDC) in a delta-sigma modulator in a manner that takes advantage of its high timing precision while noise-shaping the error due to its limited time resolution. A prototype ADC designed based on this deep-submicron technology friendly architecture was fabricated in a 65nm digital CMOS technology. The ADC is experimentally shown to achieve 68dB dynamic range in 20MHz signal bandwidth while consuming 10.5mW of power. It is projected to reduce power and improve speed with technology scaling.

This dissertation presents a low-power high-resolution delta-sigma ADC. Two new architectural design techniques are proposed to reduce the power dissipation of the ADC. Compared to the conventional active adder, the direct charge transfer (DCT) adder greatly saves power by keeping the feedback factor of the active adder unity. However, the inherent delay originated from the DCT adder will cause instability to the modulator and complex additional branches are usually needed to stabilize the loop. A simple and power-efficient technique is proposed to absorb the delay from the DCT adder and the instability issue is therefore solved. Another proposed low-power design technique is to feed differentiated inverted quantization noise to the input of the last integrator. The modulator noise-shaping order with this proposed technique is effectively increased from two to three without adding additional active elements. The delta-sigma ADC with the proposed architectural design techniques has been implemented in transistor-level and fabricated in 0.18 µm CMOS technology. Measurement results showed a SNDR of 99.3 dB, a DR of 101.3 dB and a SFDR of 112 dB over 20 kHz signal bandwidth, resulting in a very low figure-of-merit (FoM) in its application category. Finally, two new circuit ideas, low-power parasitic-insensitive switched-capacitor integrator for delta-sigma ADCs and switched-resistor tuning technique for highly linear Gm-C filter design are presented.
Graduation date: 2012
Access restricted to the OSU Community at author's request from June 9, 2012 - June 9, 2014