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Journal articles on the topic 'Field Programmable Counter Arrays'

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Published: 30 May 2022

Last updated: 31 May 2022

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1

Li, Xu, Xing Guang Qi, Qing Hua Li, Ning Wang, and Li Peng Wang. "Photon Counter Implemented by Field Programmable Gate Array." Advanced Materials Research 591-593 (November 2012): 1396–99. http://dx.doi.org/10.4028/www.scientific.net/amr.591-593.1396.

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Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This tenchnology has a good prospect and commerical value. Photon counter is used in photon correlation spectroscopy experiment to gain the intensity of photon. In order to obtain the accurate values of the photon correlation, efficient and accurate photon counter must be designed. This paper presents two kinds of photon counters implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in the integration circumstance of ISE. Experiments show that our work is effective. They all have a simple circuit design, and easy to be upgraded. The accurate photon counters can meet the different requirements of photon correlation.

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2

Szymanowski, Rafal, and Józef Kalisz. "Field programmable gate array time counter with two-stage interpolation." Review of Scientific Instruments 76, no. 4 (April 2005): 045104. http://dx.doi.org/10.1063/1.1878212.

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3

Ahmad, Nabihah, Lim Mei Wei, and M. Hairol Jabbar. "Advanced Encryption Standard with Galois Counter Mode using Field Programmable Gate Array." Journal of Physics: Conference Series 1019 (June 2018): 012008. http://dx.doi.org/10.1088/1742-6596/1019/1/012008.

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4

Chaberski, Dariusz, Robert Frankowski, Maciej Gurski, and Marek Zieliński. "Comparison of Interpolators Used for Time-Interval Measurement Systems Based on Multiple-Tapped Delay Line." Metrology and Measurement Systems 24, no. 2 (June 27, 2017): 401–12. http://dx.doi.org/10.1515/mms-2017-0033.

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AbstractThe paper describes the construction, operation and test results of three most popular interpolators from a viewpoint of time-interval (TI) measurement systems consisting of many tapped-delay lines (TDLs) and registering pulses of a wide-range changeable intensity. The comparison criteria include the maximum intensity of registered time stamps (TSs), the dependency of interpolator characteristic on the registered TSs’ intensity, the need of using either two counters or a mutually-complementing pair counter-register for extending a measurement range, the need of calculating offsets between TDL inputs and the dependency of a resolution increase on the number of used TDL segments. This work also contains conclusions about a range of applications, usefulness and methods of employing each described TI interpolator. The presented experimental results bring new facts that can be used by the designers who implement precise time delays in the field-programmable gate arrays (FPGA).

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5

Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (January 1, 2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.

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In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.

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6

Durani, Fahim, Mainuddin Mainuddin, Upendra Mittal, Jitender Kumar, Devendra Barlewar, and A. T. Nimal. "Field Programmable Gate Array based Readout for Surface Acoustic Wave Portable Gas Detector." Defence Science Journal 70, no. 5 (October 8, 2020): 498–504. http://dx.doi.org/10.14429/dsj.70.16343.

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Surface acoustic wave (SAW) is one of the most promising technology in the field of gas sensing at low concentrations. Field deployable portable SAW detectors are, however, prone to noise, there by limiting the detection at low concentrations. To meet the current requirements of gas detection at low concentrations, the readout methodology needs to be based on minimal hardware and better noise management. In this paper we describe a readout scheme for portable SAW gas detectors incorporating a field programmable gate array (FPGA). The developed readout system includes a modified reciprocal frequency counter for differential SAW sensor, median noise filtering and moving averages smoothing for noise management, peak detection and interfacing with external display, all implemented in FPGA. The developed readout was tested against VOCs using a lab developed vapour generator and the results have been presented in the paper. The readout system is compact, low power consuming and expandable through software thus ideal for portable handheld applications.

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7

Gong, Yanping, Fengyu Qian, and Lei Wang. "Masked FPGA Bitstream Encryption via Partial Reconfiguration." International Journal of High Speed Electronics and Systems 28, no. 03n04 (September 2019): 1940022. http://dx.doi.org/10.1142/s0129156419400226.

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Field Programmable Gate Arrays (FPGA), as one of the popular circuit implementation platforms, provide the flexible and powerful way for different applications. IC designs are configured to FPGA through bitstream files. However, the configuration process can be hacked by side channel attacks (SCA) to acquire the critical design information, even under the protection of encryptions. Reports have shown many successful attacks against the FPGA cryptographic systems during the bitstream loading process to acquire the entire design. Current countermeasures, mostly random masking methods, are effective but also introduce large hardware complexity. They are not suitable for resource-constrained scenarios such as Internet of Things (IoT) applications. In this paper, we propose a new secure FPGA masking scheme to counter the SCA. By utilizing the FPGA partial reconfiguration feature, the proposed technique provides a light-weight and flexible solution for the FPGA decryption masking.

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8

Tian, Haiting, Shakith Fernando, Hock Wei Soon, Zhang Qiang, Chunxi Zhang, Yajun Ha, and Nanguang Chen. "Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array." IEEE Transactions on Biomedical Circuits and Systems 4, no. 1 (February 2010): 1–10. http://dx.doi.org/10.1109/tbcas.2009.2027026.

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9

Zhu, Hao, Mu Lan Wang, Wei Su, and Hua Jun Liu. "Design of Servo System Intelligent Control Chip Based on FPGA." Advanced Materials Research 542-543 (June 2012): 949–52. http://dx.doi.org/10.4028/www.scientific.net/amr.542-543.949.

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According to the required functions of speed control and position control in Computer Numerical Control (CNC) system, the hardware control modules of speed and position are designed based on Field Programmable Gates Array (FPGA) of CYCLONE II family. The software hardening technology is used for speed control and position control. The servo intelligent control chip consists of reset unit, frequency division unit, speed processing unit, subdivision unit, phase discrimination unit, counter unit, compare unit, etc. Through analysis of waveform simulation, the correctness of design and the enhancement of transportability and reliability are achieved.

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10

Frankowski, Robert, Dariusz Chaberski, Marcin Kowalski, and Marek Zieliński. "A High-Speed Fully Digital Phase-Synchronizer Implemented in a Field Programmable Gate Array Device." Metrology and Measurement Systems 24, no. 3 (September 1, 2017): 537–50. http://dx.doi.org/10.1515/mms-2017-0037.

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AbstractMost systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.

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11

Tang, Sheng, Jing Ke, Tianxiang Wang, and Zhouhu Deng. "Development of a Miniaturized Frequency Standard Comparator Based on FPGA." Electronics 8, no. 2 (January 23, 2019): 123. http://dx.doi.org/10.3390/electronics8020123.

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Frequency standard comparison measurement has important practical significance for the rational use of frequency standard in engineering. This paper was devoted to the study of frequency standard comparison measurement based on classical dual mixing time difference method. However, in the actual system design and implementation, the commonly used counter was discarded and the phase difference was measured by a digital signal processing method based on Field Programmable Gate Array (FPGA). A miniaturized 10 MHz frequency standard comparator with good noise floor was successfully developed. The size of the prototype circuit board is only about 292.1 cm2. The experimental results showed that the noise floor of the frequency standard comparator was typically better than 7.50 × 10-12/s, and its relative error of phase difference measurement was less than 1.70 × 10-5.

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12

Gordon, David, Christian Wouters, Maximilian Wick, Bastian Lehrheuer, Jakob Andert, Charles Koch, and Stefan Pischinger. "Development and experimental validation of a field programmable gate array–based in-cycle direct water injection control strategy for homogeneous charge compression ignition combustion stability." International Journal of Engine Research 20, no. 10 (April 8, 2019): 1101–13. http://dx.doi.org/10.1177/1468087419841744.

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Homogeneous charge compression ignition is a part-load combustion method, which can significantly reduce oxides of nitrogen (NO x) emissions compared to current lean-burn spark ignition engines. The challenge with homogeneous charge compression ignition combustion is the high cyclic variation due to the lack of direct ignition control. A fully variable electromagnetic valve train provides the internal exhaust gas recirculation through negative valve overlap which is required to obtain the necessary thermal energy to enable homogeneous charge compression ignition. This also increases the cyclic coupling as residual gas and unburnt fuel is transferred between cycles through exhaust gas recirculation. To improve combustion stability, an experimentally validated feed-forward water injection controller is presented. Utilizing the low latency and rapid calculation rate of a field programmable gate array, a real-time calculation of residual fuel mass is implemented on a prototyping engine controller. Using this field programmable gate array–based calculation, it is possible to calculate the amount of fuel and the required control interaction during an engine cycle. This controller prevents early rapid combustion following a late combustion cycle using direct water injection to cool the cylinder charge and counter the additional thermal energy from any residual fuel that is transferred between cycles. By cooling the trapped cylinder mass, the upcoming combustion phasing can be delayed to the desired setpoint. The controller was tested at several operating points and showed an improvement in the combustion stability as shown by a reduction in the standard deviation of combustion phasing and indicated mean effective pressure.

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13

Shaker, Manar N., Ahmed Hussien, Gehad I. Alkady, Hassanein H. Amer, and Ihab Adly. "FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors." Electronics 9, no. 12 (December 4, 2020): 2064. http://dx.doi.org/10.3390/electronics9122064.

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Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

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14

Khurshid, Burhan. "Improved Synthesis of Generalized Parallel Counters on FPGAs Using Only LUTs." Journal of Circuits, Systems and Computers 27, no. 01 (August 23, 2017): 1850002. http://dx.doi.org/10.1142/s0218126618500020.

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Generalized parallel counters (GPCs) are frequently used to construct high speed compressor trees on field programmable gate arrays (FPGAs). The introduction of fast carry-chain in FPGAs has greatly improved the performance of these elements. Evidently, a large number of GPCs have been proposed in literature that use a combination of look-up tables (LUTs) and carry-chains. In this paper, we take an alternate approach and try to eliminate the carry-chain from the GPC structure. We present a heuristic that aims at synthesizing GPCs on FPGAS using only the general LUT fabric. The resultant GPCs are then easily pipelined by placing registers at the output node of each LUT. We have used our heuristic on various GPCs reported in prior work. Our heuristic successfully eliminates the carry-chain from the GPC structure with an increase in LUT count in some GPCs. Experimentation using Xilinx FPGAs shows that filter systems constructed using our GPCs show an improvement in speed and power performance and a comparable area performance.

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15

Tung, Dam Minh, Nguyen Van Toan, and Jeong-Gun Lee. "A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA." Electronics 9, no. 4 (April 10, 2020): 633. http://dx.doi.org/10.3390/electronics9040633.

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Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

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16

Zhang, Zhun, Xiang Wang, Qiang Hao, Dongdong Xu, Jinlei Zhang, Jiakang Liu, and Jinhui Ma. "High-Efficiency Parallel Cryptographic Accelerator for Real-Time Guaranteeing Dynamic Data Security in Embedded Systems." Micromachines 12, no. 5 (May 15, 2021): 560. http://dx.doi.org/10.3390/mi12050560.

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Dynamic data security in embedded systems is raising more and more concerns in numerous safety-critical applications. In particular, the data exchanges in embedded Systems-on-Chip (SoCs) using main memory are exposing many security vulnerabilities to external attacks, which will cause confidential information leakages and program execution failures for SoCs at key points. Therefore, this paper presents a security SoC architecture with integrating a four-parallel Advanced Encryption Standard-Galois/Counter Mode (AES-GCM) cryptographic accelerator for achieving high-efficiency data processing to guarantee data exchange security between the SoC and main memory against bus monitoring, off-line analysis, and data tampering attacks. The architecture design has been implemented and verified on a Xilinx Virtex-5 Field Programmable Gate Array (FPGA) platform. Based on evaluation of the cryptographic accelerator in terms of performance overhead, security capability, processing efficiency, and resource consumption, experimental results show that the parallel cryptographic accelerator does not incur significant performance overhead on providing confidentiality and integrity protections for exchanged data; its average performance overhead reduces to as low as 2.65% on typical 8-KB I/D-Caches, and its data processing efficiency is around 3 times that of the pipelined AES-GCM construction. The reinforced SoC under the data tampering attacks and benchmark tests confirms the effectiveness against external physical attacks and satisfies a good trade-off between high-efficiency and hardware overhead.

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17

Guillén-Fernández, Omar, María Fernanda Moreno-López, and Esteban Tlelo-Cuautle. "Issues on Applying One- and Multi-Step Numerical Methods to Chaotic Oscillators for FPGA Implementation." Mathematics 9, no. 2 (January 12, 2021): 151. http://dx.doi.org/10.3390/math9020151.

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Chaotic oscillators have been designed with embedded systems like field-programmable gate arrays (FPGAs), and applied in different engineering areas. However, the majority of works do not detail the issues when choosing a numerical method and the associated electronic implementation. In this manner, we show the FPGA implementation of chaotic and hyper-chaotic oscillators from the selection of a one-step or multi-step numerical method. We highlight that one challenge is the selection of the time-step h to increase the frequency of operation. The case studies include the application of three one-step and three multi-step numerical methods to simulate three chaotic and two hyper-chaotic oscillators. The numerical methods provide similar chaotic time-series, which are used within a time-series analyzer (TISEAN) to evaluate the Lyapunov exponents and Kaplan–Yorke dimension (DKY) of the (hyper-)chaotic oscillators. The oscillators providing higher exponents and DKY are chosen because higher values mean that the chaotic time series may be more random to find applications in chaotic secure communications. In addition, we choose representative numerical methods to perform their FPGA implementation, which hardware resources are described and counted. It is highlighted that the Forward Euler method requires the lowest hardware resources, but it has lower stability and exactness compared to other one-step and multi-step methods.

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18

Lombardi, F. "Field Programmable Gate-Arrays." IEEE Design & Test of Computers 15, no. 1 (January 1998): 8–9. http://dx.doi.org/10.1109/mdt.1998.655176.

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19

Verma, H. "Field programmable gate arrays." IEEE Potentials 18, no. 4 (1999): 34–36. http://dx.doi.org/10.1109/45.796099.

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20

Hurst, S. L. "Field programmable gate arrays." Microelectronics Journal 28, no. 1 (January 1997): 102. http://dx.doi.org/10.1016/s0026-2692(97)87854-8.

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21

Pérez, Daniel, Ivana Gasulla, and Jose Capmany. "Field-programmable photonic arrays." Optics Express 26, no. 21 (October 3, 2018): 27265. http://dx.doi.org/10.1364/oe.26.027265.

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22

Bhatia, Dinesh. "Field-Programmable Gate Arrays." VLSI Design 4, no. 4 (January 1, 1996): i—ii. http://dx.doi.org/10.1155/1996/87608.

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23

Marchal, Pierre. "Field-programmable gate arrays." Communications of the ACM 42, no. 4 (April 1999): 57–59. http://dx.doi.org/10.1145/299157.299594.

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24

Jay, Christopher. "Field programmable gate arrays." Microprocessors and Microsystems 17, no. 7 (September 1993): 370. http://dx.doi.org/10.1016/0141-9331(93)90058-f.

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25

Hurst, S. L. "Field-programmable gate arrays." Microelectronics Journal 25, no. 1 (February 1994): 77–78. http://dx.doi.org/10.1016/0026-2692(94)90166-x.

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26

Noorsal, Emilia, Asyraf Rongi, Intan Rahayu Ibrahim, Rosheila Darus, Daniel Kho, and Samsul Setumin. "Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model." Micromachines 13, no. 2 (January 25, 2022): 179. http://dx.doi.org/10.3390/mi13020179.

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Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

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27

Greene, J., E. Hamdy, and S. Beal. "Antifuse field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (July 1993): 1042–56. http://dx.doi.org/10.1109/5.231343.

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28

Hasler, Jennifer. "Large-Scale Field-Programmable Analog Arrays." Proceedings of the IEEE 108, no. 8 (August 2020): 1283–302. http://dx.doi.org/10.1109/jproc.2019.2950173.

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29

Rose, J., A. El Gamal, and A. Sangiovanni-Vincentelli. "Architecture of field-programmable gate arrays." Proceedings of the IEEE 81, no. 7 (July 1993): 1013–29. http://dx.doi.org/10.1109/5.231340.

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Leon, A. F. "Field programmable gate arrays in space." IEEE Instrumentation & Measurement Magazine 6, no. 4 (December 2003): 42–48. http://dx.doi.org/10.1109/mim.2003.1251482.

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Zemmouri, A., R. Elgouri, M. Alareqi, M. Benbrahim, and L. Hlou. "Design and Implementation of Pulse Width Modulation Using Hardware/Software MicroBlaze Soft-Core." International Journal of Power Electronics and Drive Systems (IJPEDS) 8, no. 1 (March 1, 2017): 167. http://dx.doi.org/10.11591/ijpeds.v8.i1.pp167-175.

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This paper presents an embedded control application of clock frequency to control the pulse width of the output signals, implemented on field programmable get array. This control allows the creation of lines of Pulse-width modulation depending on the numbers of card outputs, without using the specific "Timers /Counters" blocks; this method is effective to adjust the amount of power supplied to an electrical charge. The purpose of this work is to achieve a real time hardware implementation with higher performance in both size and speed. Performance of these design implemented in field programmable get array virtex5 card, and Signals displayed on an oscilloscope.

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32

Ting-Ting Hwang, R. M. Owens, M. J. Irwin, and Kuo Hua Wang. "Logic synthesis for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, no. 10 (1994): 1280–87. http://dx.doi.org/10.1109/43.317471.

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33

PALUSINSKI, O. A., D. M. GETTMAN, D. ANDERSON, H. ANDERSON, and C. MARCJAN. "FILTERING APPLICATIONS OF FIELD PROGRAMMABLE ANALOG ARRAYS." Journal of Circuits, Systems and Computers 08, no. 03 (June 1998): 337–53. http://dx.doi.org/10.1142/s021812669800016x.

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A Field Programmable Analog Array (FPAA), built in CMOS technology, contains uncommitted operational amplifiers, switches, and capacitors. A FPAA containing banks of programmable switched capacitors (SC) can be used to build filters for analog signals as well as a large number of diverse analog applications. The parameters of a given application, such as a filter, are functions of the capacitor values. Manufacturing and quantization errors may result in capacitor values in the FPAA other than those required by the application. For an FPAA to be a viable substitute for dedicated devices we must examine the error performance of the implementation. Such performance analysis can be built into the software to provide circuit designers with additional information. A methodology is described for determining a bound for the filter error as a function of capacitor errors and capacitor sizes. An example of detailed analysis for a low pass filter is included. Measurements of a low-pass filter implemented using Motorola's prototype FPAA compared favorably with the model predictions.

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34

Dettmer, R. "Onwards and upwards [field programmable gate arrays]." IEE Review 51, no. 12 (December 1, 2005): 40–43. http://dx.doi.org/10.1049/ir:20051204.

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35

Dasgupta, S., and D. Cussans. "Field Programmable Gate Arrays—Detecting Cosmic Rays." Journal of Instrumentation 10, no. 07 (July 9, 2015): C07006. http://dx.doi.org/10.1088/1748-0221/10/07/c07006.

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36

Erbagci, Burak, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, and Ken Mai. "Secure hardware-entangled field programmable gate arrays." Journal of Parallel and Distributed Computing 131 (September 2019): 81–96. http://dx.doi.org/10.1016/j.jpdc.2019.04.002.

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37

Sangiovanni-Vincentelli, A., A. El Gamal, and J. Rose. "Synthesis method for field programmable gate arrays." Proceedings of the IEEE 81, no. 7 (July 1993): 1057–83. http://dx.doi.org/10.1109/5.231344.

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38

Leeser, Miriam, Scott Hauck, and Russell Tessier. "Field-Programmable Gate Arrays in Embedded Systems." EURASIP Journal on Embedded Systems 2006 (2006): 1–2. http://dx.doi.org/10.1155/es/2006/51312.

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39

Leeser, Miriam, Scott Hauck, and Russell Tessier. "Field-Programmable Gate Arrays in Embedded Systems." EURASIP Journal on Embedded Systems 2006, no. 1 (2006): 051312. http://dx.doi.org/10.1186/1687-3963-2006-051312.

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AHUJA, SUMIT, and S. K. BALASUBRAMANIAN. "Field Programmable Gate Arrays Based Overcurrent Relays." Electric Power Components and Systems 32, no. 3 (March 2004): 247–55. http://dx.doi.org/10.1080/15325000490207769.

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41

Hurst, S. L. "Logic synthesis for field-programmable gate arrays." Microelectronics Journal 27, no. 8 (November 1996): 803–4. http://dx.doi.org/10.1016/0026-2692(96)82780-7.

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Mintzer, Les. "FIR filters with field-programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 6, no. 2 (August 1993): 119–27. http://dx.doi.org/10.1007/bf01607876.

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Louie, Marianne E., and Milos D. Ercegovac. "Implementing division with field programmable gate arrays." Journal of VLSI signal processing systems for signal, image and video technology 7, no. 3 (October 1994): 271–85. http://dx.doi.org/10.1007/bf02409403.

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GAUDET, VINCENT C., and P. GLENN GULAK. "IMPLEMENTATION ISSUES FOR HIGH-BANDWIDTH FIELD-PROGRAMMABLE ANALOG ARRAYS." Journal of Circuits, Systems and Computers 08, no. 05n06 (October 1998): 541–58. http://dx.doi.org/10.1142/s0218126698000341.

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Abstract:

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10 MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5 mm× 3.5 mm in a 0.8 μm CMOS technology.

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Ogurtsov, A. A. "Conducting functional control of field-programmable gate arrays." VESTNIK of Samara University. Aerospace and Mechanical Engineering 16, no. 4 (January 22, 2018): 137. http://dx.doi.org/10.18287/2541-7533-2017-16-4-137-146.

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Joginipelly, Arjun Kumar, and Dimitrios Charalampidis. "Efficient separable convolution using field programmable gate arrays." Microprocessors and Microsystems 71 (November 2019): 102852. http://dx.doi.org/10.1016/j.micpro.2019.102852.

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Brown, S., J. Rose, and Z. G. Vranesic. "A detailed router for field-programmable gate arrays." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 11, no. 5 (May 1992): 620–28. http://dx.doi.org/10.1109/43.127623.

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Bogdan, IstvÁn A., Daniel Coca, and Rob J. Beynon. "Peptide Mass Fingerprinting Using Field-Programmable Gate Arrays." IEEE Transactions on Biomedical Circuits and Systems 3, no. 3 (June 2009): 142–49. http://dx.doi.org/10.1109/tbcas.2008.2010945.

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Yazdanshenas, Sadegh, and Vaughn Betz. "Interconnect Solutions for Virtualized Field-Programmable Gate Arrays." IEEE Access 6 (2018): 10497–507. http://dx.doi.org/10.1109/access.2018.2806618.

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Reiss, G., and D. Meyners. "Reliability of field programmable magnetic logic gate arrays." Applied Physics Letters 88, no. 4 (January 23, 2006): 043505. http://dx.doi.org/10.1063/1.2167609.

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