Dissertations / Theses on the topic 'Field Programmable Counter Arrays'
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Карнаушенко, В. П., and А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.
Full textAttarzadeh, Niaki Seyed Hosein. "Design Space Exploration Of Field Programmable Counter Arrays And Their Integration With FPGAs." Thesis, KTH, Elektronik- och datorsystem, ECS, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-46479.
Full textSven, Engström. "A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction." Thesis, Linköpings universitet, Datorteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171111.
Full textHoward, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.
Full textMessa, Norman C. "Design implementation into field programmable gate arrays." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.
Full textNiu, Jianyong. "Digital control using field programmable gate arrays." Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.
Full textLu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.
Full textLeong, David Chin Kuang. "Incremental placement for field-programmable gate arrays." Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.
Full textApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.
Full textCamus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.
Full textHall, Tyson Stuart. "Field-Programmable Analog Arrays: A Floating-Gate Approach." Diss., Available online, Georgia Institute of Technology, 2004:, 2004. http://etd.gatech.edu/theses/available/etd-07122004-124607/unrestricted/hall%5Ftyson%5Fs%5F200407%5Fphd.pdf.
Full textPrvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.
James, Calvin L. "COMPLEX WAVEFORM GENERATION UTILIZING FIELD PROGRAMMABLE GATE ARRAYS." International Foundation for Telemetering, 1997. http://hdl.handle.net/10150/609692.
Full textThe basic building blocks for implementing complex waveform generators using a look-up table approach are random access memory (RAM) and read only memory (ROM) devices. Due to technological advancements in field programmable gate array (FPGA) development, these devices have the ability to allocate large amounts of memory elements within the same structure. The self containment property makes the FPGA a suitable topology for complex waveform generation applications. In addition, this self containment property significantly reduces implementation costs by reducing the number of external components required to support many applications. This paper examines the use of FPGA’s in various complex waveform generation applications. In particular, a discussion will ensue examining possible mappings of the time domain response of the complex waveform into memory elements of the FPGA. The analyses and examples contained in the sequel are from existing waveform generation applications, developed for Gauissian Minimum Shift Keying (GMSK) and Unbalanced Quadriphase Shift Keying (UQPSK) modulation formats.
Newalkar, Aditya. "Alternative techniques for Built-In Self-Test of Field Programmable Gate Arrays." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Summer/master's/NEWALKAR_ADITYA_6.pdf.
Full textDixon, Bobby Earl Stroud Charles E. "Built-in self-test of the programmable interconnect in field programmable gate arrays." Auburn, Ala, 2008. http://repo.lib.auburn.edu/EtdRoot/2008/FALL/Electrical_and_Computer_Engineering/Thesis/Dixon_Bobby_16.pdf.
Full textMutlu, Baris Ragip. "Real-time Motion Control Using Field Programmable Gate Arrays." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612049/index.pdf.
Full textand finally an assembled solution is developed to test the overall design. Tests of the overall design are realized via hardware-in-the-loop simulation of a real-world control problem, selected as a CNC machining center. The developed methods are discussed in terms of their success, resource consumptions and attainable sampling rates.
Luo, Ji. "Circuit design and routing for field programmable analog arrays." College Park, Md. : University of Maryland, 2005. http://hdl.handle.net/1903/3167.
Full textThesis research directed by: Electrical Engineering. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
Källström, Petter. "Direct Digital Frequency Synthesis in Field-Programmable Gate Arrays." Thesis, Linköping University, Department of Electrical Engineering, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56550.
Full textThis thesis is about creation of a Matlab program that suggests and automatically generates a Phase to Sine Amplitude Converter (PSAC) in the hardware language VHDL, suitable for Direct Digital Frequency Synthesis (DDFS). Main hardware target is Field Programmable Gate Arrays (FPGAs).
Focus in this report is how an FPGA works, different methods for sine amplitude generation and their signal qualities vs the hardware resources they use.
Detta exjobb handlar om att skapa ett Matlab-program som föreslår och implementerar en sinusgenerator i hårdvaruspråket VHDL, avsedd för digital frekvenssyntes (DDFS). Ämnad hårdvara för implementeringen är en fältprogrammerbar grindmatris (FPGA).
Fokus i denna rapport ligger på hur en FPGA är uppbyggd, olika metoder för sinusgenerering och vilka kvaliteter på sinusvågen de ger och vilka resurser i hårdvaran de använder.
Raina, Baljit Singh. "Delay-optimized placement in symmetrical field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31862.pdf.
Full textTickle, Andrew Jason. "Applications of Morphological Operators on Field Programmable Gate Arrays." Thesis, University of Liverpool, 2009. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.507628.
Full textAmbat, Shadab Gopinath. "SINGLE EVENT UPSET DETECTION IN FIELD PROGRAMMABLE GATE ARRAYS." UKnowledge, 2008. http://uknowledge.uky.edu/gradschool_theses/511.
Full textSelf, R. P. "Software-orientated system design for field programmable gate arrays." Thesis, University of Essex, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.397736.
Full textGray, Jordan D. "Application of Floating-Gate Transistors in Field Programmable Analog Arrays." Thesis, Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7540.
Full textBaskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.
Full textCommittee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Shen, Ying. "Compiling a synchronous programming language into field programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1999. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape8/PQDD_0029/MQ47476.pdf.
Full textMacQueen, Daniel Montgomery. "Total ionizing dose effects on Xilinx field-programmable gate arrays." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ59840.pdf.
Full textSareen, Aman. "Reconfigurable design for pattern recognition using field programmable gate arrays." Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1175625525.
Full textRoyal, Andrew Peter. "Globally asynchronous locally synchronous interconnect for field programmable gate arrays." Thesis, Imperial College London, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.415717.
Full textGundam, Madhuri. "Implementation of Directional Median Filtering using Field Programmable Gate Arrays." ScholarWorks@UNO, 2010. http://scholarworks.uno.edu/td/111.
Full textDavis, James. "Low-overhead fault-tolerant logic for field-programmable gate arrays." Thesis, Imperial College London, 2015. http://hdl.handle.net/10044/1/44382.
Full textPereira, Gustavo Vieira. "Teste da rede de interconexões de field programmable analog arrays." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2005. http://hdl.handle.net/10183/6305.
Full textPapadonikolakis, Markos. "Mapping of support vector machines on field programmable gate arrays." Thesis, Imperial College London, 2012. http://hdl.handle.net/10044/1/10004.
Full textBrown, Simon James. "Fault-tolerance of field-programmable gate arrays subjected to radiation." Thesis, University of Salford, 2010. http://usir.salford.ac.uk/26592/.
Full textLee, Kok Kiong. "CAD algorithms for field programmable logic devices /." Digital version:, 2000. http://wwwlib.umi.com/cr/utexas/fullcit?p9992847.
Full textKumar, Akhilesh. "Leakage Power Modeling and Reduction Techniques for Field Programmable Gate Arrays." Thesis, University of Waterloo, 2006. http://hdl.handle.net/10012/766.
Full textIn this work an analytical state dependent leakage power model for FPGAs is developed, followed by dual-Vt based designs of the FPGA architecture for reducing leakage power.
The leakage power model computes subthreshold and gate leakage in FPGAs, since these are the two dominant components of total leakage power in the scaled nanometer technologies. The leakage power model takes into account the dependency of gate and subthreshold leakage on the state of the circuit inputs. The leakage power model has two main components, one which computes the probability of a state for a particular FPGA circuit element, and the other which computes the leakage of the FPGA circuit element for a given input using analytical equations. This FPGA power model is particularly important for rapidly analyzing various FPGA architectures across different technology nodes.
Dual-Vt based designs of the FPGA architecture are proposed, developed, and evaluated, for reducing the leakage power using a CAD framework. The logic and the routing resources of the FPGA are considered for dual-Vt assignment. The number of the logic elements that can be assigned high-Vt in the ideal case by using a dual-Vt assignment algorithm in the CAD framework is estimated. Based upon this estimate two kinds of architectures are developed and evaluated, homogeneous and heterogeneous architectures. Results indicate that leakage power savings of up to 50% can be obtained from these architectures. The analytical state dependent leakage power model developed has been used for estimating the leakage power savings from the dual-Vt FPGA architectures. The CAD framework that has been developed can also be used for developing and evaluating different dual-Vt FPGA architectures, other than the ones proposed in this work.
Lamoureux, Julien. "Modeling and reduction of dynamic power in field-programmable gate arrays." Thesis, University of British Columbia, 2007. http://hdl.handle.net/2429/414.
Full textWilton, Steven J. E. "Architectures and algorithms for field-programmable gate arrays with embedded memory." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1997. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp03/NQ28082.pdf.
Full textLi, Wei. "Routability prediction for field programmable gate arrays with hierarchical interconnection structures." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk2/ftp01/MQ31846.pdf.
Full textDai, Zhibin. "Routability prediction for Field Programmable Gate Arrays with a routing hierarchy." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ56315.pdf.
Full textCampregher, Nicola. "Interconnect yield analysis and fault tolerance for field programmable gate arrays." Thesis, Imperial College London, 2007. http://hdl.handle.net/10044/1/11966.
Full textInuani, Maurice Kilavuka. "Technology mapping of heterogeneous lookup table based field programmable gate arrays." Thesis, University of Oxford, 1998. http://ora.ox.ac.uk/objects/uuid:8ec8745f-c0b2-43c0-994f-bd949d9fdefa.
Full textKeeley, Jared Matthew. "An Incremental Trace-Based Debug System for Field-Programmable Gate-Arrays." BYU ScholarsArchive, 2013. https://scholarsarchive.byu.edu/etd/3880.
Full textLovell, Jack James. "Development of smart, compact fusion diagnostics using field-programmable gate arrays." Thesis, Durham University, 2017. http://etheses.dur.ac.uk/12401/.
Full textMoeller, Tyler J. (Tyler John) 1975. "Field programmable gate arrays for radar front-end digital signal processing." Thesis, Massachusetts Institute of Technology, 1999. http://hdl.handle.net/1721.1/80555.
Full textIncludes bibliographical references (p. 113-116).
by Tyler J. Moeller.
S.B.and M.Eng.
Honoré, Francis. "Energy-aware architectures, circuits and CAD for field programmable gate arrays." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/37911.
Full textIncludes bibliographical references (p. 113-117).
Field Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of fine grain configurable power domains. By introducing fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the analysis and implementation of these configurable power domains. A test chip using dual core voltages fabricated in a 0.18 /m CMOS process features these power reduction techniques. The test chip includes an 8x8 array of logic tiles and a 9x9 switch matrix grid. The chip design flow utilizes a mix of synthesized logic and custom cells. 'The layout required a customized approach to overcome some of the challenges of implementing a fine granularity multiple voltage design.
(cont.) A set of benchmark circuits shows a measured average energy-delay improvement of nearly 2X. Additionally, enhancements for the implementation of finite impulse response filters provide a 2.5x improvement in the energy-delay product relative to standard FPGA architectures. This thesis also addresses static: power consumption by reducing sub-threshold leakage through the use of distributed multi-threshold CMOS. A separate test chip using a 0.13 m dual VT process demonstrates the advantages of distributed power gating for sub-threshold leakage reduction by achieving over 10X reduction in static power.
by Francis A. Honoré.
Ph.D.
Potgieter, Juan-Pierre. "Single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12520.
Full textOrtiz, Gual Fernando Enrique. "Novel reconfigurable computing architectures for embedded high performance signal processing and numerical applications." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file 1.73 Mb., 102 p, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:3221141.
Full textMilton, Daniel. "Built-in self test of configurable memory resources in field programmable gate arrays." Auburn, Ala., 2007. http://repo.lib.auburn.edu/07M%20Theses/MILTON_DANIEL_9.pdf.
Full textLin, Yu Colin, and 林郁. "ArchSyn: an energy-efficient FPGA high-level synthesizer." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2012. http://hub.hku.hk/bib/B49799599.
Full textpublished_or_final_version
Electrical and Electronic Engineering
Doctoral
Doctor of Philosophy
Johnson, Steven A. "Implementation of a configurable fault tolerant processor (CFTP)." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 2003. http://library.nps.navy.mil/uhtbin/hyperion-image/03Mar%5FJohnson.pdf.
Full textThesis advisor(s): Herschel H. Loomis, Alan A. Ross. Includes bibliographical references (p. 117). Also available online.
Hauck, Scott. "Multi-FPGA systems /." Thesis, Connect to this title online; UW restricted, 1995. http://hdl.handle.net/1773/7008.
Full text