Relevant bibliographies by topics / Field Programmable Counter Arrays

Academic literature on the topic 'Field Programmable Counter Arrays'

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Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "Field Programmable Counter Arrays"

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Li, Xu, Xing Guang Qi, Qing Hua Li, Ning Wang, and Li Peng Wang. "Photon Counter Implemented by Field Programmable Gate Array." Advanced Materials Research 591-593 (November 2012): 1396–99. http://dx.doi.org/10.4028/www.scientific.net/amr.591-593.1396.

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Photon correlation technique is an effective method for measuring the particle size of sub-micron particles and nanoparticles. This tenchnology has a good prospect and commerical value. Photon counter is used in photon correlation spectroscopy experiment to gain the intensity of photon. In order to obtain the accurate values of the photon correlation, efficient and accurate photon counter must be designed. This paper presents two kinds of photon counters implemented by FPGA. The programming language used is Verilog HDL. The software design and system simulation are completed in the integration circumstance of ISE. Experiments show that our work is effective. They all have a simple circuit design, and easy to be upgraded. The accurate photon counters can meet the different requirements of photon correlation.
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Szymanowski, Rafal, and Józef Kalisz. "Field programmable gate array time counter with two-stage interpolation." Review of Scientific Instruments 76, no. 4 (April 2005): 045104. http://dx.doi.org/10.1063/1.1878212.

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Ahmad, Nabihah, Lim Mei Wei, and M. Hairol Jabbar. "Advanced Encryption Standard with Galois Counter Mode using Field Programmable Gate Array." Journal of Physics: Conference Series 1019 (June 2018): 012008. http://dx.doi.org/10.1088/1742-6596/1019/1/012008.

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Chaberski, Dariusz, Robert Frankowski, Maciej Gurski, and Marek Zieliński. "Comparison of Interpolators Used for Time-Interval Measurement Systems Based on Multiple-Tapped Delay Line." Metrology and Measurement Systems 24, no. 2 (June 27, 2017): 401–12. http://dx.doi.org/10.1515/mms-2017-0033.

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AbstractThe paper describes the construction, operation and test results of three most popular interpolators from a viewpoint of time-interval (TI) measurement systems consisting of many tapped-delay lines (TDLs) and registering pulses of a wide-range changeable intensity. The comparison criteria include the maximum intensity of registered time stamps (TSs), the dependency of interpolator characteristic on the registered TSs’ intensity, the need of using either two counters or a mutually-complementing pair counter-register for extending a measurement range, the need of calculating offsets between TDL inputs and the dependency of a resolution increase on the number of used TDL segments. This work also contains conclusions about a range of applications, usefulness and methods of employing each described TI interpolator. The presented experimental results bring new facts that can be used by the designers who implement precise time delays in the field-programmable gate arrays (FPGA).
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Lu, Shyue-Kung, Fu-Min Yeh, and Jen-Sheng Shih. "Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs." VLSI Design 15, no. 1 (January 1, 2002): 397–406. http://dx.doi.org/10.1080/1065514021000012011.

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In this paper, we present a novel fault detection and fault diagnosis technique for Field Programmable Gate Arrays (FPGAs). The cell is configured to implement a bijective function to simplify the testing of the whole cell array. The whole chip is partitioned into disjoint one-dimensional arrays of cells. For the lookup table (LUT), a fault may occur at the memory matrix, decoder, input or output lines. The input patterns can be easily generated with a k-bit binary counter, where k denotes the number of input lines of a configurable logic block (CLB). Theoretical proofs show that the resulting fault coverage is 100%. According to the characteristics of the bijective cell function, a novel built-in self-test structure is also proposed. Our BIST approaches have the advantages of requiring less hardware resources for test pattern generation and output response analysis. To locate a faulty CLB, two diagnosis sessions are required. However, the maximum number of configurations is k + 4 for diagnosing a faulty CLB. The diagnosis complexity of our approach is also analyzed. Our results show that the time complexity is independent of the array size of the FPGA. In other words, we can make the FPGA array C-diagnosable.
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Durani, Fahim, Mainuddin Mainuddin, Upendra Mittal, Jitender Kumar, Devendra Barlewar, and A. T. Nimal. "Field Programmable Gate Array based Readout for Surface Acoustic Wave Portable Gas Detector." Defence Science Journal 70, no. 5 (October 8, 2020): 498–504. http://dx.doi.org/10.14429/dsj.70.16343.

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Surface acoustic wave (SAW) is one of the most promising technology in the field of gas sensing at low concentrations. Field deployable portable SAW detectors are, however, prone to noise, there by limiting the detection at low concentrations. To meet the current requirements of gas detection at low concentrations, the readout methodology needs to be based on minimal hardware and better noise management. In this paper we describe a readout scheme for portable SAW gas detectors incorporating a field programmable gate array (FPGA). The developed readout system includes a modified reciprocal frequency counter for differential SAW sensor, median noise filtering and moving averages smoothing for noise management, peak detection and interfacing with external display, all implemented in FPGA. The developed readout was tested against VOCs using a lab developed vapour generator and the results have been presented in the paper. The readout system is compact, low power consuming and expandable through software thus ideal for portable handheld applications.
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Gong, Yanping, Fengyu Qian, and Lei Wang. "Masked FPGA Bitstream Encryption via Partial Reconfiguration." International Journal of High Speed Electronics and Systems 28, no. 03n04 (September 2019): 1940022. http://dx.doi.org/10.1142/s0129156419400226.

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Field Programmable Gate Arrays (FPGA), as one of the popular circuit implementation platforms, provide the flexible and powerful way for different applications. IC designs are configured to FPGA through bitstream files. However, the configuration process can be hacked by side channel attacks (SCA) to acquire the critical design information, even under the protection of encryptions. Reports have shown many successful attacks against the FPGA cryptographic systems during the bitstream loading process to acquire the entire design. Current countermeasures, mostly random masking methods, are effective but also introduce large hardware complexity. They are not suitable for resource-constrained scenarios such as Internet of Things (IoT) applications. In this paper, we propose a new secure FPGA masking scheme to counter the SCA. By utilizing the FPGA partial reconfiguration feature, the proposed technique provides a light-weight and flexible solution for the FPGA decryption masking.
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Tian, Haiting, Shakith Fernando, Hock Wei Soon, Zhang Qiang, Chunxi Zhang, Yajun Ha, and Nanguang Chen. "Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array." IEEE Transactions on Biomedical Circuits and Systems 4, no. 1 (February 2010): 1–10. http://dx.doi.org/10.1109/tbcas.2009.2027026.

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Zhu, Hao, Mu Lan Wang, Wei Su, and Hua Jun Liu. "Design of Servo System Intelligent Control Chip Based on FPGA." Advanced Materials Research 542-543 (June 2012): 949–52. http://dx.doi.org/10.4028/www.scientific.net/amr.542-543.949.

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According to the required functions of speed control and position control in Computer Numerical Control (CNC) system, the hardware control modules of speed and position are designed based on Field Programmable Gates Array (FPGA) of CYCLONE II family. The software hardening technology is used for speed control and position control. The servo intelligent control chip consists of reset unit, frequency division unit, speed processing unit, subdivision unit, phase discrimination unit, counter unit, compare unit, etc. Through analysis of waveform simulation, the correctness of design and the enhancement of transportability and reliability are achieved.
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Frankowski, Robert, Dariusz Chaberski, Marcin Kowalski, and Marek Zieliński. "A High-Speed Fully Digital Phase-Synchronizer Implemented in a Field Programmable Gate Array Device." Metrology and Measurement Systems 24, no. 3 (September 1, 2017): 537–50. http://dx.doi.org/10.1515/mms-2017-0037.

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AbstractMost systems used in quantum physics experiments require the efficient and simultaneous recording different multi-photon coincidence detection events. In such experiments, the single-photon gated counting systems can be applicable. The main sources of errors in these systems are both instability of the clock source and their imperfect synchronization with the excitation source. Below, we propose a solution for improvement of the metrological parameters of such measuring systems. Thus, we designed a novel integrated circuit dedicated to registration of signals from a photon number resolving detectors including a phase synchronizer module. This paper presents the architecture of a high-resolution (~60 ps) digital phase synchronizer module cooperating with a multi-channel coincidence counter. The main characteristic feature of the presented system is its ability to fast synchronization (requiring only one clock period) with the measuring process. Therefore, it is designed to work with various excitation sources of a very wide frequency range. Implementation of the phase synchronizer module in an FPGA device enabled to reduce the synchronization error value from 2.857 ns to 214.8 ps.
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Dissertations / Theses on the topic "Field Programmable Counter Arrays"

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Карнаушенко, В. П., and А. В. Бородин. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays." Thesis, NURE, MC&FPGA, 2019. https://mcfpga.nure.ua/conf/2019-mcfpga/10-35598-mcfpga-2019-004.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between Field Programmable Gates Arrays (FPGA) and Application Specified Integrated Circuits (ASICs) for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions.
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Attarzadeh, Niaki Seyed Hosein. "Design Space Exploration Of Field Programmable Counter Arrays And Their Integration With FPGAs." Thesis, KTH, Elektronik- och datorsystem, ECS, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-46479.

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Field Programmable Counter Arrays (FPCAs) have been recently introduced to close the gap between FPGA and ASICs for arithmetic dominated applications. FPCAs are reconfigurable lattices that can be embedded into FPGAs to efficiently compute the result of multi-operand additions. The first contribution of this work is a Design Space Exploration (DSE) of the FPCAs and the identification of trade-offs between different parameters which describe them. Methods for analyzing and pruning the design space are proposed to enable a smart exploration. Finally, a set of best performing architectures in terms of area and delay is determined. Secondly, a study of possible integration schemes to build a hybrid FPGA/FPCA chip is performed. The goal is to find a solution with optimal usage of on-chip silicon area. The advantages and disadvantages of each solution are studied and a new integration solution based on properties of FPCAs is suggested. A VLSI implementation proves the applicability of the proposed solutions.
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Sven, Engström. "A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction." Thesis, Linköpings universitet, Datorteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-171111.

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This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps.
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Howard, Neil John. "Defect-tolerant Field-Programmable Gate Arrays." Thesis, University of York, 1994. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.359290.

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Messa, Norman C. "Design implementation into field programmable gate arrays." Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26451.

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Niu, Jianyong. "Digital control using field programmable gate arrays." Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434507.

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Lu, Aiguo. "Logic synthesis for field programmable gate arrays." Thesis, University of Bristol, 1995. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.295061.

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Leong, David Chin Kuang. "Incremental placement for field-programmable gate arrays." Thesis, University of British Columbia, 2006. http://hdl.handle.net/2429/31671.

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As the logic capacity of FPGAs continues to increase with deep submicron technology, performing a full recompilation for small iterative changes in a large design is an extremely time-consuming and costly process. To address this issue, this thesis presents a new incremental placement algorithm for FPGAs named "iPlace" that significantly reduces the time required for recompilation. The iPlace algorithm is based on shifting, compaction, and annealing. Key ideas from the algorithm include a placement super-grid that is larger than the physical size of the FPGA. The super-grid allows insertion of additional CLBs into areas with no free locations by CPU-efficient shifting. This is followed by a compaction scheme to re-legalize CLBs that are shifted to illegal locations outside of the physical size of the FPGA. The algorithm ends with a low-temperature anneal to improve quality. This algorithm is capable of handling multiple design changes across large regions of a FPGA. This is especially useful for hierarchical designs where sub-circuits are re-used multiple times. If one such sub-circuit is modified, iPlace can quickly produce a high quality incremental placement solution. For a single region of design change, we found that iPlace is 34 to 260 times faster than the academic tool Versatile Place and Route (VPR) in default mode. Compared to VPR's reduced-quality "-fast" placement option, iPlace is 3 to 28 times faster with equivalent quality. For multiple regions of design changes, iPlace is still 50-70 times faster compared to VPR in default mode when up to 2/3 of the CLBs are modified; Compared to the "-fast" placement option, iPlace is still 5-8 times faster. We believe that iPlace is the first academically available incremental placement algorithm capable of handling significant changes to a netlist for very large circuits.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Vachranukunkiet, Petya Nagvajara Prawat Johnson Jeremy. "Power flow computation using field programmable gate arrays /." Philadelphia, Pa. : Drexel University, 2007. http://hdl.handle.net/1860/1789.

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Camus, Dominic Roger. "Improved logic optimisation for field programmable gate arrays." Thesis, University of Oxford, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.301840.

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Books on the topic "Field Programmable Counter Arrays"

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Brown, Stephen D. Field-Programmable Gate Arrays. Boston, MA: Springer US, 1992.

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Pierzchala, Edmund, Glenn Gulak, Leon O. Chua, and Angel Rodríguez-Vázquez, eds. Field-Programmable Analog Arrays. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3.

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Brown, Stephen D., Robert J. Francis, Jonathan Rose, and Zvonko G. Vranesic. Field-Programmable Gate Arrays. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3572-0.

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Vuillamy, Jean-Michel. Performance enhancement in field-programmable Gate Arrays. Ottawa: National Library of Canada, 1991.

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Murgai, Rajeev. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995.

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Samiha, Mourad, ed. Digital design using field programmable gate arrays. Englewood Cliffs, N.J: PTR Prentice Hall, 1994.

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Murgai, Rajeev. Logic synthesis for field-programmable gate arrays. Boston: Kluwer Academic Publishers, 1995.

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Murgai, Rajeev, Robert K. Brayton, and Alberto Sangiovanni-Vincentelli. Logic Synthesis for Field-Programmable Gate Arrays. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-1-4615-2345-1.

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Ukeiley, Richard Larry. Field programmable gate arrays (FPGAs): The 3000 series. Englewood Cliffs, N.J: PTR Prentice Hall, 1993.

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Digital signal processing with field programmable gate arrays. 2nd ed. Berlin: Springer-Verlag, 2004.

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Book chapters on the topic "Field Programmable Counter Arrays"

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Nussbaum, Pascal, Bernard Girau, and Arnaud Tisserand. "Field programmable processor arrays." In Evolvable Systems: From Biology to Hardware, 311–22. Berlin, Heidelberg: Springer Berlin Heidelberg, 1998. http://dx.doi.org/10.1007/bfb0057633.

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Gu, Changyi. "Field-Programmable Gate Arrays." In Building Embedded Systems, 191–231. Berkeley, CA: Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-1919-5_9.

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Barkalov, Alexander, Larysa Titarenko, and Małgorzata Mazurkiewicz. "Field Programmable Gate Arrays." In Foundations of Embedded Systems, 81–106. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-11961-4_4.

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Teife, John, and Rajit Manohar. "Programmable Asynchronous Pipeline Arrays." In Field Programmable Logic and Application, 345–54. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_34.

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D’Mello, Dean R., and P. Glenn Gulak. "Design Approaches to Field-Programmable Analog Integrated Circuits." In Field-Programmable Analog Arrays, 7–34. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_1.

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Lee, Edward K. F., and Wai L. Hui. "A Novel Switched-Capacitor Based Field-Programmable Analog Array Architecture." In Field-Programmable Analog Arrays, 35–50. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_2.

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Kutuk, Haydar, and Sung-Mo Steve Kang. "A Switched Capacitor Approach to Field-Programmable Analog Array (FPAA) Design." In Field-Programmable Analog Arrays, 51–65. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_3.

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Bratt, Adrian, and Ian Macbeth. "DPAD2—A Field Programmable Analog Array." In Field-Programmable Analog Arrays, 67–89. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_4.

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Klein, Hans W. "The EPAC Architecture: An Expert Cell Approach to Field Programmable Analog Devices." In Field-Programmable Analog Arrays, 91–103. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_5.

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Premont, Christophe, Richard Grisel, Nacer Abouchi, and Jean-Pierre Chante. "A Current Conveyor based Field Programmable Analog Array." In Field-Programmable Analog Arrays, 105–24. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_6.

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Conference papers on the topic "Field Programmable Counter Arrays"

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Karnaushenko, Vladimir, and Alexander Borodin. "Field Programmable Counter Arrays Integration with Field Programmable Gates Arrays." In Theoretical and Applied Aspects of Device Development on Microcontrollers and FPGAs. Kharkiv National University of Radio Electronics, 2019. http://dx.doi.org/10.35598/mcfpga.2019.004.

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Cevrero, Alessandro, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gurkaynak, Yusuf Leblebici, and Paolo Ienne. "Architectural improvements for field programmable counter arrays." In the 16th international ACM/SIGDA symposium. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1344671.1344699.

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Williams, Stephen M., and Mingjie Line. "Reactive Signal Obfuscation with Time-Fracturing to Counter Information Leakage in FPGAs." In FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3373087.3375353.

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Barkalov, A., L. Titarenko, I. Zeleneva, and S. Hrushko. "Implementing on the field programmable gate array of combined finite state machine with counter." In 2018 IEEE 9th International Conference on Dependable Systems, Services and Technologies (DESSERT). IEEE, 2018. http://dx.doi.org/10.1109/dessert.2018.8409135.

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Sood, Vindhyali, and MPR Prasad. "Simulation of Counter Based DPWM for Implementation on FPGA." In International Conference on Women Researchers in Electronics and Computing. AIJR Publisher, 2021. http://dx.doi.org/10.21467/proceedings.114.60.

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A Digital Pulse Width Modulation technique based on the counter has been considered for analysis and simulation. It utilizes one of the many functions due to the advanced characteristics already present on the field-programmable gate array (FPGA) which is a huge advantage. Delay Locked Loop (DLL) is one of those features on the FPGA that is used. This architecture merged a counter-comparator-based synchronous block with an asynchronous block that uses the Delay Locked Loop (DLL). This action helps to achieve a better or higher resolution. The architecture proposed is to be executed on an inexpensive but lower-speed FPGA. This FPGA is given a 32 MHz clock externally that helps us to get a time resolution under 2ns. To use the DLL on FPGA, the Digital Clock Manager (DCM) block is used.
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Chen, Shili, Guangde Song, Shijiu Jin, and Xianglin Zhan. "The Design of an Ultrasonic Phased Array System on Pipelines’ Weld Inspection." In 2004 International Pipeline Conference. ASMEDC, 2004. http://dx.doi.org/10.1115/ipc2004-0719.

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Phased arrays generate ultrasonic waves by using recisely-defined time delays for each element in an ultrasonic array group, this permits constructive and destructive interference of the wavefronts to form the pre-defined beam. So, ultrasonic phased arrays are well suited to weld inspections. First, beams can be multiplexed across the array, in what is called “electronic scanning”. This permits very rapid inspections of components, typically an order of magnitude faster than a single transducer raster scan. Second, the beam can be swept through a range of angles without moving the array; this is called “beam steering”, and the inspections are typically called “azimuthal” scans or “sectorial” scans. Before weld inspecting, the time delays between elements were computed using a specific model and compared to experimental delays obtained using through transmission tests. This paper describes the application of phased array on pipelines’ weld inspection. The detail hardware designs of linear phased arrays system and the summary of system performance are presented. This inspection system includes eight ultrasonic signal transmitting and receiving circuit units, which are used to control time sequence of ultrasonic beam and select channel used for waves construction, and amplify the received ultrasonic signal. Each unit is connected with 16 probe elements (total 128 elements in this system), and can receive 4-way ultrasonic signals (channel selection is done by RF switching). Additional performance is gained by intensively using FPGA (Field Programmable Gate Arrays) technology for memory and delay counters. Since the working frequency or FPGA is 100MHz, the delay time less than 10 ns is realized by analogue delay line. This system not only has the functions of conventional ultrasonic inspector, but also can display the defect shape and its size on the screen.
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Jyothi, Vinayaka, Ashik Poojari, Richard Stern, and Ramesh Karri. "Fingerprinting Field Programmable Gate Arrays." In 2017 IEEE 35th International Conference on Computer Design (ICCD). IEEE, 2017. http://dx.doi.org/10.1109/iccd.2017.58.

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Arnold, Mark G. "Configuring Field-Programmable Robot Arrays." In 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011). IEEE, 2011. http://dx.doi.org/10.1109/reconfig.2011.21.

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Gulak, Glen, and Dean R. D'Mello. "Review of field-programmable analog arrays." In Photonics East '96, edited by John Schewel, Peter M. Athanas, V. Michael Bove, Jr., and John Watson. SPIE, 1996. http://dx.doi.org/10.1117/12.255812.

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Pérez López, Daniel, Aitor López Hernández, Andrés Macho Ortiz, Prometheus DasMahapatra, and José Capmany Francoy. "Towards field-programmable photonic gate arrays." In Smart Photonic and Optoelectronic Integrated Circuits XXII, edited by Sailing He and Laurent Vivien. SPIE, 2020. http://dx.doi.org/10.1117/12.2551289.

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Reports on the topic "Field Programmable Counter Arrays"

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Mumbru, Jose, George Panotopoulos, and Demetri Psaltis. Optically Programmable Field Programmable Gate Arrays (FPGA) Systems. Fort Belvoir, VA: Defense Technical Information Center, January 2004. http://dx.doi.org/10.21236/ada421336.

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Tyler, Stephen C. The Design of a Frequency Domain Interference Excision Processor Using Field Programmable Gate Arrays. Fort Belvoir, VA: Defense Technical Information Center, January 2005. http://dx.doi.org/10.21236/ada432369.

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