Dissertations / Theses on the topic 'Fault-tolerant multiprocessor systems'

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1

Kao, Ming-lai. "A reconfigurable fault-tolerant multiprocessor system for real-time control /." The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487266011223248.

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2

Somani, Arun K. (Arun Kumar). "A unified theory of system-level diagnosis and its application to regular interconnected structures /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=72037.

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System-level diagnosis is considered to be a viable alternative to circuit-level testing in complex multiprocessor systems. The characterization problem, the diagnosability problem, and the diagnosis problem in this framework have been widely studied in the literature with respect to a special fault class, called t-fault class, in which all fault sets of size up to t are considered. Various models for the interpretation of test outcomes have been proposed and analyzed. Among these, four most known models are: symmetric invalidation model, asymmetric invalidation model, symmetric invalidation model with intermittent faults, and asymmetric invalidation model with intermittent faults.
In this thesis, a completely new generalization of the characterization problem in system-level diagnosis area is developed. This generalized characterization theorem provides necessary and sufficient conditions for any fault-pattern of any size to be uniquely diagnosable under all the four models. Moreover, the following three results are obtained for the t-fault class: (1) the characterization theorem for t-diagnosable systems under the asymmetric invalidation model with intermittent faults is developed for the first time; (2) a unified t-characterization theorem covering all the four models is presented; and finally (3) it is proven that the classical t-characterization theorems under the first three models and the new result for the fourth model, as mentioned in (1) above, are special cases of the generalized characterization theorem.
The general diagnosability problem is also studied. It is shown that the single fault diagnosability problem, under the asymmetric invalidation model is Co-NP-complete.
As regards the diagnosis problem, most of the diagnosis algorithms developed thus far are global algorithms in which a complete syndrome is analyzed by a single supervisory processor. In this thesis, distributed diagnosis algorithms for regular interconnected structures are developed which take advantage of the interconnection architecture of a multiprocessor system.
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3

Gagnon, Nicolas. "Développement et étude d'un système d'exploitation tolérant aux défaillances pour système un multiprocesseur /." Thèse, Chicoutimi : Université du Québec à Chicoutimi, 1997. http://theses.uqac.ca.

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4

Морозов, Костянтин В’ячеславович. "Методи і засоби побудови моделей поведінки небазових відмовостійких багатопроцесорних систем." Doctoral thesis, Київ, 2021. https://ela.kpi.ua/handle/123456789/40485.

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Дисертація присвячена проблемі побудови графо-логічних моделей (GL-моделей) небазових відмовостійких багатопроцесорних систем (ВБС) з метою розрахунку їх параметрів надійності шляхом проведення статистичних експериментів із вищезгаданими моделями. Запропоновано метод перетворення GL-моделей за рахунок модифікації виразу будь-якої реберної функції так званої МВР-моделі. Метод базуються на зміні як однієї, так і обох частин виразу реберної функції та дозволяє модифікувати модель так, що на деяких векторах стану системи вона, на відміну від оригінальної, починає показувати роботозданий і/або нероботоздатний стан. Проаналізовано межі впливу для загального випадку модифікації як однієї, так і кількох реберних функцій на зміну поведінки моделі. Вперше запропоновано аналітичний апарат, що дозволяє визначати вектор стану t-діагностованої ВБС на основі результатів взаємного тестування процесорів, згідно із моделлю Препарати-Метца-Чена (ПМЧ-модель), для довільної топології зв’язків між ними. Вперше запропоновано метод побудови GL-моделей так званих зважених систем, в яких кожний компонент має деяку вагу, що характеризує його вклад в роботоздатність системи в цілому, а також узагальнення методу побудови GL-моделей, що базується на використанні в якості реберних функцій багатозначної логіки та дозволяє використовувати їх для побудови моделей систем, для яких, як і їх компонентів характерні більше двох станів роботоздатності. Запропоновано метод побудови GL-моделей ієрархічних систем шляхом композиції декількох МВР-моделей, а також моделей систем, що складаються з кількох підсистем та мають ковзний резерв.
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5

張明鈿. "A Fault-Tolerant Dynamic Scheduling Algorithm for Real-Time Systems on Heterogeneous Multiprocessor." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/25509613819048563444.

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碩士
國立交通大學
資訊工程系所
92
Real-time systems are being increasingly used in several applications which are time critical. Tasks corresponding to these applications have deadlines to be met. Fault-tolerance is an important requirement of such systems, due to the catastrophic consequences of not tolerating faults. In this thesis, we propose an algorithm do dynamically schedule arriving real-time tasks with PB fault-tolerant requirement on to a set of heterogeneous multiprocessor. Our algorithm, named density first with minimum non-overlap scheduling algorithm (DNA), proposes two performance improving techniques. First, a new heuristic function, called density, takes account of the needed computation time and schedulable time of a task. The task with the maximum density value will be given the highest priority. Second, the MNO strategy for backup scheduling will minimize the time reserved for backups. In the result of dynamic simulation, we can find that our algorithm has fewer rejected tasks and more general and suitable for any kind of environment.
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6

Wu, Cheng-Kwang, and 吳建寬. "Design and Simulation of Fault-Tolerant Crossbar Switches for Multiprocessor Systems with VHDL." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/87331911686192482042.

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碩士
國立交通大學
資訊科學學系
82
In this thesis, we propose two general crossbar switch models, the modified one-sided crossbar switch and the ripple k one- sided crossbar switch, which both balance between cost and fault tolerance degree. The two-sided crossbar switch and the one-sided crossbar switch are just two special cases of the above two new structures. These two structures provide choices for compromising structures between the two-sided crossbar siwtch and the one-sided crossbar switch in terms of cost and fault tolerance degree. We have derive a mathematical model to simulate the effective bandwidth of each crossbar switch. Simulation with VHDL has been performed to verify the functionality of each crossbar system. Synthesis has also been conducted to evaluate delay and area for each crossbar design.
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7

Feng-Chen, Chang, and 張鳳真. "Reliability Analysis and FPGA Realization of Fault-Tolerant One- Sided Crossbar Switches for Multiprocessor Systems." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/16059103760654056015.

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Abstract:
碩士
國立交通大學
資訊科學學系
83
In this thesis, we analyse the reliability of three crossbar switches for shared memory multiprocessor systems: the one- sided crossbar switch}, the modified one-sided crossbar switch, and the ripple K one-sided crossbar switch. We also use FPGA tools to implement these three fault-tolerant one-sided crossbar switches. In a traditional two-sided crossbar switch, there is a unique-path between a processor and a memory module. It results in no fault-tolerance in the two-sided crossbar switch. The one-sided crossbar switch enhances the fault tolerance ability by providing multiple paths between a processor and a memory module. However, the cost of the one- sided crossbar switch is almost twice than that of the traditional two-sided crossbar switch. The drawback prevents the one-sided crossbar switch from applying in multiprocessor systems widespreadly. The two new switches can provide a trade- off between fault tolerance ability and cost. However, their reliabilities should be further verified. Results indicate reliability (R(t)) of either of these two switches remains 1 for first ten hours of operation as failure rate = 0.01. This prompts them to be applied to multiprocessors systems to enhance performance and reliability as well. In addition, we use the Synopsys FPGA (Field Programmable Gate Array) Compiler and the Xilinx tools to realize the three fault-tolerant one- sided crossbar switches using FPGAs. The main contribution of this thesis is promoting to adopt the two novel fault-tolerant one-sided crossbar switches in multiprocessor systems by further demonstrating their cost-effectiveness via reliability/ cost analysis and FPGA prototyping.
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8

KE, KAI-WEI, and 柯開維. "Fault tolerant memory in a multiprocessor system." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/78231428916735979532.

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9

吳輝銘. "The fault-tolerant multiprocessor system design:fault diagnosis." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/62905986558635690496.

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10

簡明春. "The fault-tolerant multiprocessor system design:fault recovery." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/58206618821016576148.

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11

張正榮. "The fault-tolerant multiprocessor system design:hardware organization." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/09392911310959699686.

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12

王錫川. "The fault-tolerant multiprocessor system design:disk file system." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/59322795939688939246.

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13

JIANG, HUI-LIANG, and 姜惠良. "The design of a fault-tolerant operating system for multiprocessor system." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/07873494302191360619.

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14

蔣介文. "The fault-tolerant multiprocessor system design-input and output server." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/71070611919200646593.

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15

徐明發. "The fault tolerant multiprocessor system design-porting of the MINIX operating system." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/72483150040449862270.

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