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Relevant bibliographies by topics / Fault-tolerant multiprocessor systems

Academic literature on the topic 'Fault-tolerant multiprocessor systems'

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Published: 30 May 2022

Last updated: 31 May 2022

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Journal articles on the topic "Fault-tolerant multiprocessor systems"

1

Tafesse, Bisrat, and Venkatesan Muthukumar. "Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration." VLSI Design 2013 (July 11, 2013): 1–16. http://dx.doi.org/10.1155/2013/936181.

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Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of design choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to be addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC (MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques for MpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore there exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This work proposes a modular framework for the exploration and evaluation of various design algorithms for MpSoC system. This work also proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using the developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm for robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The framework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations were implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for various design scenarios.

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Feseniuk, A. P. "Software SERC for Monte Carlo Error analysis of fault-tolerant multiprocessor systems reliability estimation." PROBLEMS IN PROGRAMMING, no. 4 (December 2016): 048–57. http://dx.doi.org/10.15407/pp2016.04.048.

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The article devoted to reliability estimation of fault-tolerant reconfigurable multiprocessor systems. The paper briefly describes implementation of software SERC (Statistical Experiments for Reliability Calculation) which contains known and proposed by author statistical methods for fault tolerant reconfigurable multiprocessor systems reliability estimation and tools for Monte Carlo Error analysis of the estimation.

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3

Alam, M. S., and R. G. Melhem. "Routing in modular fault-tolerant multiprocessor systems." IEEE Transactions on Parallel and Distributed Systems 6, no. 11 (1995): 1206–20. http://dx.doi.org/10.1109/71.476192.

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4

Bruno, John, and E. G. Coffman Jr. "Optimal fault-tolerant computing on multiprocessor systems." Acta Informatica 34, no. 12 (November 1, 1997): 881–904. http://dx.doi.org/10.1007/s002360050110.

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5

ZHU, LINJIE, TONGQUAN WEI, XIAODAO CHEN, YONGHE GUO, and SHIYAN HU. "ADAPTIVE FAULT-TOLERANT TASK SCHEDULING FOR REAL-TIME ENERGY HARVESTING SYSTEMS." Journal of Circuits, Systems and Computers 21, no. 01 (February 2012): 1250004. http://dx.doi.org/10.1142/s0218126612500041.

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Fault tolerance and energy have become important design issues in multiprocessor system-on-chips (SoCs) with the technology scaling and the proliferation of battery-powered multiprocessor SoCs. This paper proposed an energy-efficient fault tolerance task allocation scheme for multiprocessor SoCs in real-time energy harvesting systems. The proposed fault-tolerance scheme is based on the principle of the primiary/backup task scheduling, and can tolerate at most one single transient fault. Extensive simulated experiment shows that the proposed scheme can save up to 30% energy consumption and reduce the miss ratio to about 8% in the presence of faults.

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Bertossi, Alan A., and Luigi Mancini. "Fault-tolerant LPT task scheduling in multiprocessor systems." Microprocessors and Microsystems 16, no. 2 (January 1992): 91–99. http://dx.doi.org/10.1016/0141-9331(92)90076-6.

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7

Karavay, M. F. "Methodology of Designing the Fault-Tolerant Distributed Multiprocessor systems." IFAC Proceedings Volumes 21, no. 19 (June 1988): 107–14. http://dx.doi.org/10.1016/s1474-6670(17)54478-x.

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8

Blough, D. M., and H. Y. Wang. "Cooperative Diagnosis and Routing in Fault-Tolerant Multiprocessor Systems." Journal of Parallel and Distributed Computing 27, no. 2 (June 1995): 205–11. http://dx.doi.org/10.1006/jpdc.1995.1083.

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9

Yajnik, S., and N. K. Jha. "Graceful degradation in algorithm-based fault tolerant multiprocessor systems." IEEE Transactions on Parallel and Distributed Systems 8, no. 2 (1997): 137–53. http://dx.doi.org/10.1109/71.577256.

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10

Tabba, Nabil, Reza Entezari-Maleki, and Ali Movaghar. "Reduced Communications Fault Tolerant Task Scheduling Algorithm for Multiprocessor Systems." Procedia Engineering 29 (2012): 3820–25. http://dx.doi.org/10.1016/j.proeng.2012.01.577.

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Dissertations / Theses on the topic "Fault-tolerant multiprocessor systems"

1

Kao, Ming-lai. "A reconfigurable fault-tolerant multiprocessor system for real-time control /." The Ohio State University, 1986. http://rave.ohiolink.edu/etdc/view?acc_num=osu1487266011223248.

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2

Somani, Arun K. (Arun Kumar). "A unified theory of system-level diagnosis and its application to regular interconnected structures /." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=72037.

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System-level diagnosis is considered to be a viable alternative to circuit-level testing in complex multiprocessor systems. The characterization problem, the diagnosability problem, and the diagnosis problem in this framework have been widely studied in the literature with respect to a special fault class, called t-fault class, in which all fault sets of size up to t are considered. Various models for the interpretation of test outcomes have been proposed and analyzed. Among these, four most known models are: symmetric invalidation model, asymmetric invalidation model, symmetric invalidation model with intermittent faults, and asymmetric invalidation model with intermittent faults.
In this thesis, a completely new generalization of the characterization problem in system-level diagnosis area is developed. This generalized characterization theorem provides necessary and sufficient conditions for any fault-pattern of any size to be uniquely diagnosable under all the four models. Moreover, the following three results are obtained for the t-fault class: (1) the characterization theorem for t-diagnosable systems under the asymmetric invalidation model with intermittent faults is developed for the first time; (2) a unified t-characterization theorem covering all the four models is presented; and finally (3) it is proven that the classical t-characterization theorems under the first three models and the new result for the fourth model, as mentioned in (1) above, are special cases of the generalized characterization theorem.
The general diagnosability problem is also studied. It is shown that the single fault diagnosability problem, under the asymmetric invalidation model is Co-NP-complete.
As regards the diagnosis problem, most of the diagnosis algorithms developed thus far are global algorithms in which a complete syndrome is analyzed by a single supervisory processor. In this thesis, distributed diagnosis algorithms for regular interconnected structures are developed which take advantage of the interconnection architecture of a multiprocessor system.

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3

Gagnon, Nicolas. "Développement et étude d'un système d'exploitation tolérant aux défaillances pour système un multiprocesseur /." Thèse, Chicoutimi : Université du Québec à Chicoutimi, 1997. http://theses.uqac.ca.

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Морозов, Костянтин В’ячеславович. "Методи і засоби побудови моделей поведінки небазових відмовостійких багатопроцесорних систем." Doctoral thesis, Київ, 2021. https://ela.kpi.ua/handle/123456789/40485.

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Дисертація присвячена проблемі побудови графо-логічних моделей (GL-моделей) небазових відмовостійких багатопроцесорних систем (ВБС) з метою розрахунку їх параметрів надійності шляхом проведення статистичних експериментів із вищезгаданими моделями. Запропоновано метод перетворення GL-моделей за рахунок модифікації виразу будь-якої реберної функції так званої МВР-моделі. Метод базуються на зміні як однієї, так і обох частин виразу реберної функції та дозволяє модифікувати модель так, що на деяких векторах стану системи вона, на відміну від оригінальної, починає показувати роботозданий і/або нероботоздатний стан. Проаналізовано межі впливу для загального випадку модифікації як однієї, так і кількох реберних функцій на зміну поведінки моделі. Вперше запропоновано аналітичний апарат, що дозволяє визначати вектор стану t-діагностованої ВБС на основі результатів взаємного тестування процесорів, згідно із моделлю Препарати-Метца-Чена (ПМЧ-модель), для довільної топології зв’язків між ними. Вперше запропоновано метод побудови GL-моделей так званих зважених систем, в яких кожний компонент має деяку вагу, що характеризує його вклад в роботоздатність системи в цілому, а також узагальнення методу побудови GL-моделей, що базується на використанні в якості реберних функцій багатозначної логіки та дозволяє використовувати їх для побудови моделей систем, для яких, як і їх компонентів характерні більше двох станів роботоздатності. Запропоновано метод побудови GL-моделей ієрархічних систем шляхом композиції декількох МВР-моделей, а також моделей систем, що складаються з кількох підсистем та мають ковзний резерв.

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5

張明鈿. "A Fault-Tolerant Dynamic Scheduling Algorithm for Real-Time Systems on Heterogeneous Multiprocessor." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/25509613819048563444.

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碩士
國立交通大學
資訊工程系所
92
Real-time systems are being increasingly used in several applications which are time critical. Tasks corresponding to these applications have deadlines to be met. Fault-tolerance is an important requirement of such systems, due to the catastrophic consequences of not tolerating faults. In this thesis, we propose an algorithm do dynamically schedule arriving real-time tasks with PB fault-tolerant requirement on to a set of heterogeneous multiprocessor. Our algorithm, named density first with minimum non-overlap scheduling algorithm (DNA), proposes two performance improving techniques. First, a new heuristic function, called density, takes account of the needed computation time and schedulable time of a task. The task with the maximum density value will be given the highest priority. Second, the MNO strategy for backup scheduling will minimize the time reserved for backups. In the result of dynamic simulation, we can find that our algorithm has fewer rejected tasks and more general and suitable for any kind of environment.

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6

Wu, Cheng-Kwang, and 吳建寬. "Design and Simulation of Fault-Tolerant Crossbar Switches for Multiprocessor Systems with VHDL." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/87331911686192482042.

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碩士
國立交通大學
資訊科學學系
82
In this thesis, we propose two general crossbar switch models, the modified one-sided crossbar switch and the ripple k one- sided crossbar switch, which both balance between cost and fault tolerance degree. The two-sided crossbar switch and the one-sided crossbar switch are just two special cases of the above two new structures. These two structures provide choices for compromising structures between the two-sided crossbar siwtch and the one-sided crossbar switch in terms of cost and fault tolerance degree. We have derive a mathematical model to simulate the effective bandwidth of each crossbar switch. Simulation with VHDL has been performed to verify the functionality of each crossbar system. Synthesis has also been conducted to evaluate delay and area for each crossbar design.

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7

Feng-Chen, Chang, and 張鳳真. "Reliability Analysis and FPGA Realization of Fault-Tolerant One- Sided Crossbar Switches for Multiprocessor Systems." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/16059103760654056015.

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碩士
國立交通大學
資訊科學學系
83
In this thesis, we analyse the reliability of three crossbar switches for shared memory multiprocessor systems: the one- sided crossbar switch}, the modified one-sided crossbar switch, and the ripple K one-sided crossbar switch. We also use FPGA tools to implement these three fault-tolerant one-sided crossbar switches. In a traditional two-sided crossbar switch, there is a unique-path between a processor and a memory module. It results in no fault-tolerance in the two-sided crossbar switch. The one-sided crossbar switch enhances the fault tolerance ability by providing multiple paths between a processor and a memory module. However, the cost of the one- sided crossbar switch is almost twice than that of the traditional two-sided crossbar switch. The drawback prevents the one-sided crossbar switch from applying in multiprocessor systems widespreadly. The two new switches can provide a trade- off between fault tolerance ability and cost. However, their reliabilities should be further verified. Results indicate reliability (R(t)) of either of these two switches remains 1 for first ten hours of operation as failure rate = 0.01. This prompts them to be applied to multiprocessors systems to enhance performance and reliability as well. In addition, we use the Synopsys FPGA (Field Programmable Gate Array) Compiler and the Xilinx tools to realize the three fault-tolerant one- sided crossbar switches using FPGAs. The main contribution of this thesis is promoting to adopt the two novel fault-tolerant one-sided crossbar switches in multiprocessor systems by further demonstrating their cost-effectiveness via reliability/ cost analysis and FPGA prototyping.

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8

KE, KAI-WEI, and 柯開維. "Fault tolerant memory in a multiprocessor system." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/78231428916735979532.

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9

吳輝銘. "The fault-tolerant multiprocessor system design:fault diagnosis." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/62905986558635690496.

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10

簡明春. "The fault-tolerant multiprocessor system design:fault recovery." Thesis, 1987. http://ndltd.ncl.edu.tw/handle/58206618821016576148.

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Books on the topic "Fault-tolerant multiprocessor systems"

1

Padilla, Peter A. Abnormal fault-recovery characteristics of the fault-tolerant multiprocessor uncovered using a new fault-injection methodology. Hampton, Va: Langley Research Center, 1991.

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2

Padilla, Peter A. Abnormal fault-recovery characteristics of the fault-tolerant multiprocessor uncovered using a new fault-injection methodology. [Washington, D.C.]: National Aeronautics and Space Administration, Office of Management, Scientific and Technical Information Division, 1991.

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3

Coghlan, B. The case for TransparentStable memory. Dublin: Trinity College, Department of Computer Science, 1991.

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4

Zary, Segall, Siewiorek Daniel P, and Langley Research Center, eds. Fault-free behavior of reliable multiprocessor systems: FTMP experiments in airlab. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1985.

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Fault-free behavior of reliable multiprocessor systems: FTMP experiments in airlab. Hampton, Va: National Aeronautics and Space Administration, Langley Research Center, 1985.

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Center, Langley Research, and United States. National Aeronautics and Space Administration. Scientific and Technical Information Division., eds. Abnormal fault-recovery characteristics of the fault-tolerant multiprocessor uncovered using a new fault-injection methodology. [Washington, D.C.]: National Aeronautics and Space Administration, Office of Management, Scientific and Technical Information Division, 1991.

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Abnormal fault-recovery characteristics of the fault-tolerant multiprocessor uncovered using a new fault-injection methodology. [Washington, D.C.]: National Aeronautics and Space Administration, Office of Management, Scientific and Technical Information Division, 1991.

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Abnormal fault-recovery characteristics of the fault-tolerant multiprocessor uncovered using a new fault-injection methodology. [Washington, D.C.]: National Aeronautics and Space Administration, Office of Management, Scientific and Technical Information Division, 1991.

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Book chapters on the topic "Fault-tolerant multiprocessor systems"

1

Hildebrand, U. "A Fault Tolerant Interconnection Network for Memory-Coupled Multiprocessor Systems." In Fault-Tolerant Computing Systems, 360–71. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76930-6_30.

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Michel, Edgar, and Wolfgang Hohl. "Concurrent Error Detection Using Watchdog Processors in the Multiprocessor System MEMSY." In Fault-Tolerant Computing Systems, 54–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76930-6_5.

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Yao, Wenbin, Dongsheng Wang, and Weimin Zheng. "A Fault-Tolerant Single-Chip Multiprocessor." In Advances in Computer Systems Architecture, 137–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-30102-8_12.

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Bauch, Andreas, and Erik Maehle. "Self-Diagnosis, Reconfiguration and Recovery in the Dynamical Reconfigurable Multiprocessor System DAMP." In Fault-Tolerant Computing Systems, 18–29. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76930-6_2.

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Lepold, Roland. "Performability Evaluation of a Fault-Tolerant Multiprocessor Architecture Using Stochastic Petri Nets." In Fault-Tolerant Computing Systems, 253–65. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76930-6_22.

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Lehmann, L., and J. Brehm. "Rollback Recovery in Multiprocessor Ring Configurations." In Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, 213–23. Berlin, Heidelberg: Springer Berlin Heidelberg, 1987. http://dx.doi.org/10.1007/978-3-642-45628-2_19.

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Sitaraman, Ramesh, and Niraj K. Jha. "Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessor Systems." In Fault-Tolerant Computing Systems, 396–406. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76930-6_33.

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Turski, Władysław M. "On Doubly Guarded Multiprocessor Control System Design." In Dependable Computing and Fault-Tolerant Systems, 3–13. Vienna: Springer Vienna, 1995. http://dx.doi.org/10.1007/978-3-7091-9396-9_1.

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Li, Qiang, Edward Hong, and Alex Tsukerman. "Fault-Tolerance Issues of Local Area Multiprocessor (LAMP) Storage Subsystem." In Fault-Tolerant Parallel and Distributed Systems, 139–53. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5449-3_8.

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Kumar, V. P., and S. M. Reddy. "Fault-Tolerant Multistage Interconnection Networks for Multiprocessor Systems." In Concurrent Computations, 495–523. Boston, MA: Springer US, 1988. http://dx.doi.org/10.1007/978-1-4684-5511-3_25.

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Conference papers on the topic "Fault-tolerant multiprocessor systems"

1

Istomin, D. R., and D. B. Borzov. "Placement of tasks in fault tolerant cubic multiprocessor systems." In Scientific dialogue: Young scientist. ЦНК МОАН, 2019. http://dx.doi.org/10.18411/spc-22-11-2019-03.

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Hvasshovd, S. O., T. Saeter, and O. Torbjornsen. "Critical issues in the design of a fault-tolerant multiprocessor database server." In Proceedings Pacific Rim International Symposium on Fault Tolerant Systems. IEEE, 1991. http://dx.doi.org/10.1109/rfts.1991.212941.

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Strollo, Elio, and Alessandro Trifiletti. "A fault-tolerant real-time microcontroller with multiprocessor architecture." In 2016 MIXDES - 23rd International Conference "Mixed Design of Integrated Circuits and Systems". IEEE, 2016. http://dx.doi.org/10.1109/mixdes.2016.7529781.

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Beitollahi, Hakem, and Geert Deconinck. "Fault-Tolerant Partitioning Scheduling Algorithms in Real-Time Multiprocessor Systems." In 2006 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06). IEEE, 2006. http://dx.doi.org/10.1109/prdc.2006.34.

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Peng, Hao, and Fan Yang. "Fault Tolerant Global Scheduling for Multiprocessor Hard Real Time Systems." In First International Conference on Information Sciences, Machinery, Materials and Energy. Paris, France: Atlantis Press, 2015. http://dx.doi.org/10.2991/icismme-15.2015.332.

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Yingfeng Oh and Sang H. Son. "An algorithm for real-time fault-tolerant scheduling in multiprocessor systems." In Fourth Euromicro workshop on Real-Time Systems. IEEE, 1992. http://dx.doi.org/10.1109/emwrt.1992.637492.

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Junsung Kim, Karthik Lakshmanan, and Ragunathan Rajkumar. "R-BATCH: Task Partitioning for Fault-tolerant Multiprocessor Real-Time Systems." In 2010 IEEE 10th International Conference on Computer and Information Technology (CIT). IEEE, 2010. http://dx.doi.org/10.1109/cit.2010.321.

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Jing Wei-peng, Liu Ya-qiu, and Wu Qu. "Fault-tolerant task scheduling in multiprocessor systems based on primary-backup scheme." In 2010 3rd International Symposium on Systems and Control in Aeronautics and Astronautics (ISSCAA 2010). IEEE, 2010. http://dx.doi.org/10.1109/isscaa.2010.5633237.

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Huang, Jia, Jan Olaf Blech, Andreas Raabe, Christian Buckl, and Alois Knoll. "Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems." In the seventh IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2039370.2039409.

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Romankevich, Alexei, Andrii Feseniuk, Vitaliy Romankevich, and Tetiana Sapsai. "About a fault-tolerant multiprocessor control system in a pre-dangerous state." In 2018 IEEE 9th International Conference on Dependable Systems, Services and Technologies (DESSERT). IEEE, 2018. http://dx.doi.org/10.1109/dessert.2018.8409129.

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Reports on the topic "Fault-tolerant multiprocessor systems"

1

Pradhan, Dhiraj K. Fault-Tolerant Multiprocessor and VLSI-Based Systems. Fort Belvoir, VA: Defense Technical Information Center, January 1986. http://dx.doi.org/10.21236/ada183344.

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2

Trivedi, K. S. Reliability Evaluation of Fault-Tolerant Multiprocessor Systems. Fort Belvoir, VA: Defense Technical Information Center, May 1985. http://dx.doi.org/10.21236/ada160234.

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Pradhan, Dhiraj K. Fault-Tolerant Architectures for Multiprocessor and VLSI-Based Systems. Fort Belvoir, VA: Defense Technical Information Center, September 1992. http://dx.doi.org/10.21236/ada267370.

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4

Lee, Sing H. Design and Packaging of Fault Tolerant Optoelectronic Multiprocessor Computing Systems. Fort Belvoir, VA: Defense Technical Information Center, October 1991. http://dx.doi.org/10.21236/ada253465.

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Lee, Sing H. Design and Packaging of Fault Tolerant Optoelectronic Multiprocessor Computing Systems. Fort Belvoir, VA: Defense Technical Information Center, January 1992. http://dx.doi.org/10.21236/ada253466.

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Pradhan, Dhiraj. Fault Tolerant Multiprocessors and VLSI-Based Systems. Fort Belvoir, VA: Defense Technical Information Center, March 1988. http://dx.doi.org/10.21236/ada209579.

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Pradhan, Dhiraj K. Fault Tolerant Architectures for Multiprocessors and VLSI-Based Systems. Fort Belvoir, VA: Defense Technical Information Center, September 1991. http://dx.doi.org/10.21236/ada244034.

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Lee, Sing H. Design and Packaging of Fault Tolerant Optoelectronic Multiprocessor Computing System. Fort Belvoir, VA: Defense Technical Information Center, April 1992. http://dx.doi.org/10.21236/ada260051.

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