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1
Sagoo, Girish Kumar. "Pilot in loop assessment of fault tolerant flight control schemes in a motion flight simulator." Morgantown, W. Va. : [West Virginia University Libraries], 2008. https://eidr.wvu.edu/etd/documentdata.eTD?documentid=5800.
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Thesis (M.S.)--West Virginia University, 2008.Title from document title page. Document formatted into pages; contains xiv, 121 p. : ill. (some col.), col. map. Includes abstract. Includes bibliographical references (p. 116-121).
2
Moncayo, Hever Y. "Immunity-based detection, identification, and evaluation of aircraft sub-system failures." Morgantown, W. Va. : [West Virginia University Libraries], 2009. http://hdl.handle.net/10450/10678.
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Thesis (Ph. D.)--West Virginia University, 2009.Title from document title page. Document formatted into pages; contains xiv, 118 p. : ill. (some col.). Includes abstract. Includes bibliographical references (p. 109-118).
3
Eklöf, Martin. "Fault-tolerance in HLA-based distributed simulations." Licentiate thesis, KTH, Electronic, Computer and Software Systems, ECS, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-4063.
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Successful integration of simulations within the Network-Based Defence (NBD), specifically use of simulations within Command and Control (C2) environments, enforces a number of requirements. Simulations must be reliable and be able to respond in a timely manner. Otherwise the commander will have no confidence in using simulation as a tool. An important aspect of these requirements is the provision of fault-tolerant simulations in which failures are detected and resolved in a consistent manner. Given the distributed nature of many military simulations systems, services for fault-tolerance in distributed simulations are desirable. The main architecture for distributed simulations within the military domain, the High Level Architecture (HLA), does not provide support for development of fault-tolerant simulations.
A common approach for fault-tolerance in distributed systems is check-pointing. In this approach, states of the system are persistently stored through-out its operation. In case a failure occurs, the system is restored using a previously saved state. Given the abovementioned shortcomings of the HLA standard this thesis explores development of fault-tolerant mechanisms in the context of the HLA. More specifically, the design, implementation and evaluation of fault-tolerance mechanisms, based on check-pointing, are described and discussed.
4
Su, Yuan-Liang David. "Modeling fault diagnosis performance on a marine powerplant simulator." Diss., Georgia Institute of Technology, 1985. http://hdl.handle.net/1853/24170.
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Sjökvist, Stefan. "Demagnetization and Fault Simulations of Permanent Magnet Generators." Doctoral thesis, Uppsala universitet, Elektricitetslära, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-303517.
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Permanent magnets are today widely used in electrical machines of all sorts. With their increase in popularity, the amount of research has increased as well. In the wind power project at Uppsala University permanent magnet synchronous generators have been studied for over a decade. However, a tool for studying demagnetization has not been available. This Ph.D. thesis covers the development of a simulation model in a commercial finite element method software capable of studying demagnetization. Further, the model is also capable of simulating the connected electrical circuit of the generator. The simulation model has continuously been developed throughout the project. The simulation model showed good agreement compared to experiment, see paper IV, and has in paper III and V successfully been utilized in case studies. The main focus of these case studies has been different types of short-circuit faults in the electrical system of the generator, at normal or at an elevated temperature. Paper I includes a case study with the latest version of the model capable of handling multiple short-circuits events, which was not possible in earlier versions of the simulation model. The influence of the electrical system on the working point ripple of the permanent magnets was evaluated in paper II. In paper III and VI, an evaluation study of the possibility of creating a generator with an interchangeable rotor is presented. A Neodymium-Iron-Boron (Nd-Fe-B) rotor was exchanged for a ferrite rotor with the electrical properties almost maintained.
6
Walker, Ryan. "Localising imbalance faults in rotating machinery." Thesis, Cranfield University, 2013. http://dspace.lib.cranfield.ac.uk/handle/1826/8606.
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This thesis presents a novel method of locating imbalance faults in rotating machinery through the study of bearing nonlinearities. Localisation in this work is presented as determining which discs/segments of a complex machine are affected with an imbalance fault. The novel method enables accurate localisation to be achieved using a single accelerometer, and is valid for both sub and super-critical machine operations in the presence of misalignment and rub faults. The development of the novel system for imbalance localisation has been driven by the desire for improved maintenance procedures, along with the increased requirement for Integrated Vehicle Health Management (IVHM) systems for rotating machinery in industry. Imbalance faults are of particular interest to aircraft engine manufacturers such as Rolls Royce plc, where such faults still result in undesired downtime of machinery. Existing methods of imbalance localisation have yet to see widespread implementation in IVHM and Engine Health Monitoring (EHM) systems, providing the motivation for undertaking this project. The imbalance localisation system described has been developed primarily for a lab-based Machine Fault Simulator (MFS), with validation and verification performed on two additional test rigs. Physics based simulations have been used in order to develop and validate the system. An Artificial Neural Network (ANN) has been applied for the purposes of reasoning, using nonlinear features in the frequency domain originating from bearing nonlinearities. The system has been widely tested in a range of situations, including in the presence of misalignment and rub faults and on a full scale aircraft engine model. The novel system for imbalance localisation has been used as the basis for a methodology aimed at localising common faults in future IVHM systems, with the aim of communicating the results and findings of this research for the benefit of future research. The works contained herein therefore contribute to scientific knowledge in the field of IVHM for rotating machinery.
7
Coan, Brian A. (Brian Anthony). "Achieving consensus in fault-tolerant distributed computer systems : protocols, lower bounds, and simulations." Thesis, Massachusetts Institute of Technology, 1987. http://hdl.handle.net/1721.1/80450.
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Pelo, Herbert Leburu. "Evaluation of an advanced fault detection system using Koeberg nuclear power plant data / H.L. Pelo." Thesis, North-West University, 2013. http://hdl.handle.net/10394/9686.
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The control and protection system of early nuclear power plants (Generation II) have been designed and built on the then reliable analog system. Technology has evolved in recent times and digital system has replaced most analog technology in most industries. Due to safety precautions and robust licensing requirements in the nuclear industry, the analog and digital system works concurrent to each other in most control and protection systems of nuclear power plants. Due to the ageing, regular maintenance and intermittent operation, the analog plant system often gives faulty signals. The objective of this thesis is to simulate a transient using a simulator to reduce the effects of system faults on the nuclear plant control and protection system, by detecting the faults early. The following steps will be performed:
• validating the simulator measurements by simulating a normal operation,
• detecting faults early on in the system
These can be performed by resorting to a model that generates estimates of the correct sensors signal values based on actual readings and correlations among them. The next step can be performed by a fault detection module which determines early whether or not the plant systems are behaving normally and detects the fault. (Baraldi P. et al, 2010.)Thesis (MSc (Engineering Sciences in Nuclear Engineering))--North-West University, Potchefstroom Campus, 2013.
9
Macpherson, Kenneth A. "Long-period ground motions in the upper Mississippi embayment from finite-fault, finite-difference simulations." Lexington, Ky. : [University of Kentucky Libraries], 2009. http://hdl.handle.net/10225/1097.
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Thesis (Ph. D.)--University of Kentucky, 2009.Title from document title page (viewed on October 29, 2009). Document formatted into pages; contains: x, 197 p. : ill. (some col.), col. maps. Includes abstract and vita. Includes bibliographical references (p. 191-196).
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Glaude, Robin Francoise. "Applicability of Uncertainty analysis to groundwater environmental risks through Fault Tree Analysis and Monte Carlo simulations." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2020.
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The Anthropocene epoch initiated by human in
uence on its Earth system (biosphere,
hydrosphere, ...) leads to an irreversible change: Global warming. Climate
change alters all existing natural processes, including the ones related to groundwater.
The present paper aims to study the occurrence's probability of two particular
groundwater risks: the generation of thermokarst lakes in permafrost environment
and its subsequent thermal consequences in the surroundings as well as seawater
intrusion inducing saltwater contamination in pumping wells. These processes are
dependent of physical parameters to which is attached uncertainty. Consequently,
two uncertainty analysis methods have been applied to determine the probability
of occurence of these undesired events: Fault Tree Analysis and Monte Carlo Simulation.
Beside the rough approximation performed to evaluate the probability of
thermokarst lake occurence (48%) and of talik development under these latter (73%)
by means of fault tree analysis, these high failure probabilities translate the urge to
slow down global warming due to the irreversible effect on permafrost environment,
meaning its thawing and releasing of trapped methane in the atmosphere. On the
other hand, Monte Carlo simulations have been performed to compare dfferent scenarii
related to seawater intrusion in Akrotiri aquifer in Cyprus. The results once
again translate the disastrous effect of climate change regarding the probability of
occurence of these unwanted events. Indeed, a failure probability around 6 times
greater (43%) is observed in the climate change scenario with respect to the reference
scenario (7%).
Uncertainty analysis is good methodology to apply to environmental concerns
to quantify the occurence's probability of these undesired events. This would urge
public authorities to perform decision making in order to avoid or reduce the failure's
probability of these groundwater issues that have irreversible consequences.
11
Ugurhan, Beliz. "Stochastic Strong Ground Motion Simulations On North Anatolian Fault Zone And Central Italy: Validation, Limitation And Sensitivity Analyses." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612413/index.pdf.
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Assessment of potential ground motions in seismically active regions is essential for purposes of seismic design and analysis. Peak ground motion intensity values and frequency content of seismic excitations are required for reliable seismic design, analysis and retrofitting of structures. In regions of sparse or no strong ground motion records, ground motion simulations provide physics-based synthetic records. These simulations provide not only the earthquake engineering parameters but also give insight into the mechanisms of the earthquakes. This thesis presents strong ground motion simulations in three regions of intense seismic activity. Stochastic finite-fault simulation methodology with a dynamic corner frequency approach is applied to three case studies performed in Düzce, L&rsquo
Aquila and Erzincan regions. In Dü
zce study, regional seismic source, propagation and site parameters are determined through validation of the simulations against the records. In L&rsquo
Aquila case study, in addition to study of the regional parameters, the limitations of the method in terms of simulating the directivity effects are also investigated. In Erzincan case study, where there are very few records, the optimum model parameters are determined using a large set of simulations with an error-minimization scheme. Later, a parametric sensitivity study is performed to observe the variations in simulation results to small perturbations in input parameters. Results of this study confirm that stochastic finite-fault simulation method is an effective technique for generating realistic physics-based synthetic records of large earthquakes in near field regions.
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Vailhé, Christophe N. P. "Deformation mechanisms in B2 aluminides: shear faults and dislocation core structures in FeAl, NiAl, CoAl and FeNiAl." Diss., Virginia Tech, 1996. http://hdl.handle.net/10919/38075.
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Monaro, Renato Machado. "Lógica fuzzy aplicada na melhoria da proteção digital de geradores síncronos." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/18/18154/tde-15032013-151305/.
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Este trabalho propõe um novo método de proteção de geradores síncronos baseado em inteligência artificial, mais especificamente lógica fuzzy, com o propósito de melhorar a proteção destes componentes vitais aos sistema elétricos de potência. Um sistema elétrico de potência completo composto por geradores, linhas de transmissão e cargas foi simulado através do Real Time Digital Simulator para fornecer dados para realização de testes e validação do algoritmo de proteção inteligente. Adicionalmente, foram desenvolvidos dois esquemas experimentais que proporcionaram a obtenção de um conjunto extensivo de ensaios de faltas internas em dois geradores síncronos reais, com o objetivo de fornecer dados para comprovar a eficácia da proteção proposta. Um sistema integrado de software e hardware cujo objetivo é servir de plataforma para desenvolver e executar em tempo real algoritmos de proteção aplicados foi desenvolvido. Esse sistema integrado foi utilizado nos testes embarcados em tempo-real do algoritmo de proteção desenvolvido. Apresenta-se também um arranjo composto por funções de proteção tradicionais mais utilizadas em campo, as quais serviram como base de comparação de desempenho para o esquema de proteção inteligente desenvolvido. Os resultados apresentados mostram que o método de proteção inteligente proposto é mais sensível para detectar instantaneamente faltas fase-terra em geradores síncronos com aterramento de alta-impedância, além de ser capaz de identificar faltas entre-espiras e entre-caminhosThis work presents the development of a synchronous generator protective technique based on artificial intelligence, specifically fuzzy logic, in order to improve the protection of these vital components of the electric power system. A complete electric power system composed of generators, transmission lines and loads was simulated using the Real Time Digital Simulator to provide data for testing and validating the intelligent protection algorithm. Additionally, an extensive set of internal fault experiments conducted on two actual synchronous generators provided oscillograms to demostrate the proposed protection effectiveness. An integrated hardware and software system whose purpose is to serve as a platform for developing and executing real-time protection algorithms is presented. This integrated system was used for real-time embedded testing of the protection algorithm developed. An arrangement composed of traditional protection functions most used in the field is also presented, this arrangement served as a comparison basis for the intelligent protection scheme performance. The results show that the intelligent protection is more sensitive to detect instantly ground faults in synchronous generators with high-impedance grounding, it is also shown that the proposed scheme is able to identify inter-turns and inter-circuits faults
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COSTA, Cecília Alves Buriti da. "Modelagem de um relé de distância em um simulador digital em tempo real." Universidade Federal de Campina Grande, 2016. http://dspace.sti.ufcg.edu.br:8080/jspui/handle/riufcg/580.
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Capes
Este trabalho apresenta o processo de modelagem de um relé de distância em um simulador digital em tempo real. O modelo inclui: i) as principais funcionalidades da arquitetura de um relé digital, incluindo filtro anti-aliasing e estimação fasorial; ii) as características de operação do tipo mho e quadrilateral, ambas com duas zonas de atuação; iii) a etapa de diagnóstico de falta, que informa as principais características do distúrbio. Para o diagnóstico da falta, foram avaliados métodos de detecção, classificação e localização por meio de simulação em massa de diferentes cenários de falta em uma linha de transmissão. Dos resultados obtidos, os melhores métodos de cada etapa foram escolhidos para compor o relé. Ao final, a atuação e o diagnóstico do relé modelado foram comparados com os resultados fornecidos pelo relé de distância disponível no próprio simulador e por um relé digital real.
This work presents the modeling process of a distance relay in a real-time digital simulator. The model contains: i) the main features of a digital relay architecture, including anti-aliasing filter and phasor estimation; ii) mho and quadrilateral operating characteristics, with two protection zones; iii) fault diagnosis, which informs the main features of the disturbance. For the fault diagnosis, detection, classification and location methods were evaluated using batch mode simulation of different fault scenarios in a transmission line. From the obtained results, the best methods were selected to be part of the modeled relay. At the end, the operation and diagnosis of the modeled relay were compared with the results presented by the distance relay model provided by the simulator manufacturer and by a digital relay.
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Domke, Jens. "Routing on the Channel Dependency Graph:." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2017. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-225902.
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In the pursuit for ever-increasing compute power, and with Moore's law slowly coming to an end, high-performance computing started to scale-out to larger systems. Alongside the increasing system size, the interconnection network is growing to accommodate and connect tens of thousands of compute nodes. These networks have a large influence on total cost, application performance, energy consumption, and overall system efficiency of the supercomputer. Unfortunately, state-of-the-art routing algorithms, which define the packet paths through the network, do not utilize this important resource efficiently. Topology-aware routing algorithms become increasingly inapplicable, due to irregular topologies, which either are irregular by design, or most often a result of hardware failures. Exchanging faulty network components potentially requires whole system downtime further increasing the cost of the failure. This management approach becomes more and more impractical due to the scale of today's networks and the accompanying steady decrease of the mean time between failures. Alternative methods of operating and maintaining these high-performance interconnects, both in terms of hardware- and software-management, are necessary to mitigate negative effects experienced by scientific applications executed on the supercomputer. However, existing topology-agnostic routing algorithms either suffer from poor load balancing or are not bounded in the number of virtual channels needed to resolve deadlocks in the routing tables.
Using the fail-in-place strategy, a well-established method for storage systems to repair only critical component failures, is a feasible solution for current and future HPC interconnects as well as other large-scale installations such as data center networks. Although, an appropriate combination of topology and routing algorithm is required to minimize the throughput degradation for the entire system. This thesis contributes a network simulation toolchain to facilitate the process of finding a suitable combination, either during system design or while it is in operation. On top of this foundation, a key contribution is a novel scheduling-aware routing, which reduces fault-induced throughput degradation while improving overall network utilization. The scheduling-aware routing performs frequent property preserving routing updates to optimize the path balancing for simultaneously running batch jobs. The increased deployment of lossless interconnection networks, in conjunction with fail-in-place modes of operation and topology-agnostic, scheduling-aware routing algorithms, necessitates new solutions to solve the routing-deadlock problem. Therefore, this thesis further advances the state-of-the-art by introducing a novel concept of routing on the channel dependency graph, which allows the design of an universally applicable destination-based routing capable of optimizing the path balancing without exceeding a given number of virtual channels, which are a common hardware limitation. This disruptive innovation enables implicit deadlock-avoidance during path calculation, instead of solving both problems separately as all previous solutions.
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Velásquez, Omar Chayña Chayña. "Ajuste e ensaio de sistemas de proteção de geradores síncronos." Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/3/3143/tde-13062016-090911/.
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Os sistemas de proteção dos elementos da rede elétrica desempenham um papel de fundamental importância na segurança e confiabilidade dos sistemas de potência. A não atuação ou a atuação incorreta dos relés de proteção durante uma falta localizada em um componente da rede pode transformar-se em um evento sistêmico de grandes proporções (blecaute). Esses eventos trazem riscos e elevados prejuízos econômicos à sociedade. A proteção dos geradores síncronos, apesar do alto custo e complexidade deste tipo de equipamento, não recebe a mesma atenção na literatura que a dedicada à proteção de outros elementos da rede, como, por exemplo, a das linhas de transmissão. Isso decorre do menor número de geradores existentes na rede e também da ideia que as faltas neste tipo de equipamento são menos frequentes. Este trabalho aborda os principais aspectos envolvidos com o projeto de um sistema de proteção para geradores síncronos de grande porte. Incialmente, discutese os principais conceitos associados com os geradores, de interesse para a tarefa de proteção. Particular atenção é dedicada às formas de aterramento e aos critérios adotados para projeto do resistor de aterramento utilizado nesse equipamento. Em seguida, apresentam-se as principais funções de proteção aplicáveis aos geradores, particularmente aquelas voltadas para a detecção de faltas nos enrolamentos do estator. Discute-se também os critérios de ajustes dos parâmetros dessas funções. Descreve-se o uso de uma plataforma laboratorial, baseada em simulador de tempo real (RTDS), para ensaio e análise do sistema de proteção visando validar seu correto desempenho frente às possíveis condições operativas que podem ser encontradas em campo. Finalmente, utilizando os conceitos desenvolvidos ao longo do trabalho, desenvolve-se um estudo de caso, onde é realizado o projeto e implementação do sistema de proteção dos geradores de uma usina hidrelétrica hipotética. Para avaliar e analisar o desempenho do sistema de proteção dessa rede exemplo, parametrizou-se o IED G60 (GE) e realizou-se inúmeras simulações na plataforma de testes proposta.Protection systems play a critical role in the safety and reliability of electric power systems. The non-operation or wrong operation of protective relays during a fault in a network element can evolve to a systemic event in large scale (blackout). These events bring risks and high economic losses to society. Despite the high cost and complexity, the protection of synchronous generators has not received much attention in the literature devoted to protection of other network elements, such as transmission lines. This stems from the smaller number of generators in the network and also the idea that the faults in this type of equipment are less frequent. This research discusses the main aspects involved in the design of a protection system for large synchronous generators. Initially, it discusses the key concepts of interest to the generation protection. Particular attention is given to grounding techniques and the criteria adopted for the design of grounding resistors used in those equipment. Then the main protection functions applicable to generators are presented, particularly those related to fault detection in the stator windings. The criteria for setting the parameters of these functions are also discussed. After that, the use of a laboratory shelf, based on Real-Time Digital Simulator (RTDS) for testing and analysis of the protection system, is described in order to validate the correct performance in face of possible operating conditions in the field. Finally, a study case is developed using the concepts developed throughout the research. Then, the design and implementation of the protection system of generators of a hypothetical hydroelectric plant are carried out. To evaluate and analyze the performance of this example network protection system, parameterized up IED G60 (GE) and held numerous simulations in the proposed test platform.
17
Eriksson, Niklas, and Patrik Lifvendahl. "Utbildningssimulator av funktioner i spårfordon : Hårdvarusimulator med felsökning på dörrsystem." Thesis, KTH, Data- och elektroteknik, 2015. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-168951.
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I denna rapport beskrivs en utvecklad utbildningssimulator över spårfordon och dess del- komponenter på järnvägen. Simulatorn är en hårdvarubaserad prototyp över ett dörrsystem på spårfordon. Prototypen ska användas av systemspecialister och tekniker inom järnvägs- branschen. Simulatorn ger användare en teknisk demonstration av hur komponenter funge- rar i ett dörrsystem. Prototypen innehåller motor, brytare, reläer och givare. Komponenterna används för att illustrerar funktioner i ett dörrsystem på ett spårfordon. Utbildningssimula- torn kontrolleras med en styrenhet och genom tryckknappar för manuell styrning. För de- monstration av säkerheten vid av och ombordstigning används en optisk givare som symbo- liserar hinderdetektering. Utbildningssimulatorn har två vanliga fel inbyggda: kabelfel och jordfel. En instruktions- manual bestående av ett kretsschema används för felsökning. Kretsschemat över dörrsyste- met används för hitta felen och åtgärda dem. I felanalysen ingår de faktorer som är orsaken till att de vanligaste felen inträffar på ett spårfordon. Dörrsystem tar emot diagnostiska ko- der från en dörrdator som styr prioriteringen på vilka åtgärder som ska göras.This report is a description of a developed educational simulator over rail vehicles and its components. The simulator is a hardware-based prototype over a door system on rail vehi- cles. System specialists and technicians will use the prototype. The Simulator should give the user a technical demonstration on how components work in a door system. The proto- type consists of motor, switch, relay and sensor. The components are used for illustration of the functions in a door system on a rail vehicle. The educational simulator is controlled with a control unit and with pushbuttons for manual control. For demonstration of the boarding security an optical sensor is used as symbolize for the obstacle detection. The educational simulation has two embedded common faults: cable fault and ground fault. The instruction manual consists of a circuit diagram and is used for troubleshooting. The circuit diagram over the door system is used to find the faults and to correct them. The fault analysis includes the factors, which is the reason for the most common faults to occur in a rail vehicle. Door system receives diagnostic code from a door computer that control priori- tizing for arrangements that will be made.
18
Araújo, José. "Design, Implementation and Validation of Resource-Aware and Resilient Wireless Networked Control Systems." Doctoral thesis, KTH, Reglerteknik, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-152535.
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Networked control over wireless networks is of growing importance in many application domains such as industrial control, building automation and transportation systems. Wide deployment however, requires systematic design tools to enable efficient resource usage while guaranteeing close-loop control performance. The control system may be greatly affected by the inherent imperfections and limitations of the wireless medium and malfunction of system components. In this thesis, we make five important contributions that address these issues. In the first contribution, we consider event- and self-triggered control and investigate how to efficiently tune and execute these paradigms for appropriate control performance. Communication strategies for aperiodic control are devised, where we jointly address the selection of medium-access control and scheduling policies. Experimental results show that the best trade-off is obtained by a hybrid scheme, combining event- and self-triggered control together with contention-based and contention-free medium access control. The second contribution proposes an event-based method to select between fast and slow periodic sampling rates. The approach is based on linear quadratic control and the event condition is a quadratic function of the system state. Numerical and experimental results show that this hybrid controller is able to reduce the average sampling rate in comparison to a traditional periodic controller, while achieving the same closed-loop control performance. In the third contribution, we develop compensation methods for out-of-order communications and time-varying delays using a game-theoretic minimax control framework. We devise a linear temporal coding strategy where the sensor combines the current and previous measurements into a single packet to be transmitted. An experimental evaluation is performed in a multi-hop networked control scenario with a routing layer vulnerability exploited by a malicious application. The experimental and numerical results show the advantages of the proposed compensation schemes. The fourth contribution proposes a distributed reconfiguration method for sensor and actuator networks. We consider systems where sensors and actuators cooperate to recover from faults. Reconfiguration is performed to achieve model-matching, while minimizing the steady-state estimation error covariance and a linear quadratic control cost. The reconfiguration scheme is implemented in a room heating testbed, and experimental results demonstrate the method's ability to automatically reconfigure the faulty system in a distributed and fast manner. The final contribution is a co-simulator, which combines the control system simulator Simulink with the wireless network simulator COOJA. The co-simulator integrates physical plant dynamics with realistic wireless network models and the actual embedded software running on the networked devices. Hence, it allows for the validation of the complete wireless networked control system, including the study of the interactions between software and hardware components.QC 20140929
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Zounon, Mawussi. "On numerical resilience in linear algebra." Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0038/document.
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Comme la puissance de calcul des systèmes de calcul haute performance continue de croître, en utilisant un grand nombre de cœurs CPU ou d’unités de calcul spécialisées, les applications hautes performances destinées à la résolution des problèmes de très grande échelle sont de plus en plus sujettes à des pannes. En conséquence, la communauté de calcul haute performance a proposé de nombreuses contributions pour concevoir des applications tolérantes aux pannes. Cette étude porte sur une nouvelle classe d’algorithmes numériques de tolérance aux pannes au niveau de l’application qui ne nécessite pas de ressources supplémentaires, à savoir, des unités de calcul ou du temps de calcul additionnel, en l’absence de pannes. En supposant qu’un mécanisme distinct assure la détection des pannes, nous proposons des algorithmes numériques pour extraire des informations pertinentes à partir des données disponibles après une pannes. Après l’extraction de données, les données critiques manquantes sont régénérées grâce à des stratégies d’interpolation pour constituer des informations pertinentes pour redémarrer numériquement l’algorithme. Nous avons conçu ces méthodes appelées techniques d’Interpolation-restart pour des problèmes d’algèbre linéaire numérique tels que la résolution de systèmes linéaires ou des problèmes aux valeurs propres qui sont indispensables dans de nombreux noyaux scientifiques et applications d’ingénierie. La résolution de ces problèmes est souvent la partie dominante; en termes de temps de calcul, des applications scientifiques. Dans le cadre solveurs linéaires du sous-espace de Krylov, les entrées perdues de l’itération sont interpolées en utilisant les entrées disponibles sur les nœuds encore disponibles pour définir une nouvelle estimation de la solution initiale avant de redémarrer la méthode de Krylov. En particulier, nous considérons deux politiques d’interpolation qui préservent les propriétés numériques clés de solveurs linéaires bien connus, à savoir la décroissance monotone de la norme-A de l’erreur du gradient conjugué ou la décroissance monotone de la norme résiduelle de GMRES. Nous avons évalué l’impact du taux de pannes et l’impact de la quantité de données perdues sur la robustesse des stratégies de résilience conçues. Les expériences ont montré que nos stratégies numériques sont robustes même en présence de grandes fréquences de pannes, et de perte de grand volume de données. Dans le but de concevoir des solveurs résilients de résolution de problèmes aux valeurs propres, nous avons modifié les stratégies d’interpolation conçues pour les systèmes linéaires. Nous avons revisité les méthodes itératives de l’état de l’art pour la résolution des problèmes de valeurs propres creux à la lumière des stratégies d’Interpolation-restart. Pour chaque méthode considérée, nous avons adapté les stratégies d’Interpolation-restart pour régénérer autant d’informations spectrale que possible. Afin d’évaluer la performance de nos stratégies numériques, nous avons considéré un solveur parallèle hybride (direct/itérative) pleinement fonctionnel nommé MaPHyS pour la résolution des systèmes linéaires creux, et nous proposons des solutions numériques pour concevoir une version tolérante aux pannes du solveur. Le solveur étant hybride, nous nous concentrons dans cette étude sur l’étape de résolution itérative, qui est souvent l’étape dominante dans la pratique. Les solutions numériques proposées comportent deux volets. A chaque fois que cela est possible, nous exploitons la redondance de données entre les processus du solveur pour effectuer une régénération exacte des données en faisant des copies astucieuses dans les processus. D’autre part, les données perdues qui ne sont plus disponibles sur aucun processus sont régénérées grâce à un mécanisme d’interpolationAs the computational power of high performance computing (HPC) systems continues to increase by using huge number of cores or specialized processing units, HPC applications are increasingly prone to faults. This study covers a new class of numerical fault tolerance algorithms at application level that does not require extra resources, i.e., computational unit or computing time, when no fault occurs. Assuming that a separate mechanism ensures fault detection, we propose numerical algorithms to extract relevant information from available data after a fault. After data extraction, well chosen part of missing data is regenerated through interpolation strategies to constitute meaningful inputs to numerically restart the algorithm. We have designed these methods called Interpolation-restart techniques for numerical linear algebra problems such as the solution of linear systems or eigen-problems that are the inner most numerical kernels in many scientific and engineering applications and also often ones of the most time consuming parts. In the framework of Krylov subspace linear solvers the lost entries of the iterate are interpolated using the available entries on the still alive nodes to define a new initial guess before restarting the Krylov method. In particular, we consider two interpolation policies that preserve key numerical properties of well-known linear solvers, namely the monotony decrease of the A-norm of the error of the conjugate gradient or the residual norm decrease of GMRES. We assess the impact of the fault rate and the amount of lost data on the robustness of the resulting linear solvers.For eigensolvers, we revisited state-of-the-art methods for solving large sparse eigenvalue problems namely the Arnoldi methods, subspace iteration methods and the Jacobi-Davidson method, in the light of Interpolation-restart strategies. For each considered eigensolver, we adapted the Interpolation-restart strategies to regenerate as much spectral information as possible. Through intensive experiments, we illustrate the qualitative numerical behavior of the resulting schemes when the number of faults and the amount of lost data are varied; and we demonstrate that they exhibit a numerical robustness close to that of fault-free calculations. In order to assess the efficiency of our numerical strategies, we have consideredan actual fully-featured parallel sparse hybrid (direct/iterative) linear solver, MaPHyS, and we proposed numerical remedies to design a resilient version of the solver. The solver being hybrid, we focus in this study on the iterative solution step, which is often the dominant step in practice. The numerical remedies we propose are twofold. Whenever possible, we exploit the natural data redundancy between processes from the solver toperform an exact recovery through clever copies over processes. Otherwise, data that has been lost and is not available anymore on any process is recovered through Interpolationrestart strategies. These numerical remedies have been implemented in the MaPHyS parallel solver so that we can assess their efficiency on a large number of processing units (up to 12; 288 CPU cores) for solving large-scale real-life problems
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Wu, Jing Ping, and 吳敬平. "Fault simulators of digital system." Thesis, 1994. http://ndltd.ncl.edu.tw/handle/96824811501793333927.
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Wu, Song-Guang, and 巫松洸. "RAMSES-D: DRAM Fault Simulator Supporting Delay Fault and Weighted Coupling Fault." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/04107792806765637030.
Full textAbstract:
碩士國立清華大學
電機工程學系
95
Memory fault simulator is an important tool for memory test sequence optimization. Traditional sequential fault simulation algorithm has time complexity O(N3) (N: number of cells in memory), which may be too slow to simulate a large number of memory words. Therefore, we had developed a fault simulator called Random Access Memory Simulator for Error Screening (RAMSES). RAMSES uses fault descriptors to describe fault models' behaviors, which can reduce the time complexity to O(N2) and support new fault models. Delay fault plays a more and more important role in memory testing. In this thesis, we adopt new delay fault models targeting DRAM timing parameters and modify RAMSES that is now called RAMSES-D. Finally, the concept of weighted coupling fault is proposed. Fault count itself cannot accurately represent the real coupling fault distribution. Even if the same fault model is concerned, cells in diRerent positions will have diRerent fault occurrence probability. We propose a weight function and assign a weight to each coupling fault, and modify the fault coverage calculation method. The weighted fault coverage shows the effectiveness of the weight function, and that different coupling fault ratio varies with diRerent memory configuraitons. We propose a 23N March test pattern for delay fault models, which reduces 23.3% test length from originally proposed delay fault test patterns. With the weight function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between diRerent memory configurations.
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Chen, Shung-Chih, and 陳順智. "Fault and Diagnostic Fault Simulations for Digital Circuits." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/90187797144483833882.
Full textAbstract:
博士國立成功大學
電機工程學系
85
Several efficient fault and diagnostic fault simulation algorithms forcombin ational and synchronous sequential circuits have been developed inthis dissert ation. For combinational circuits, the advantages of critical path tracing an dparallel simulation techniques have been adopted to form a new fault simulato r,which is 2.4 times, in average, faster than the original critical path traci ngfault simulator. Applying the algorithm to diagnostic fault simulation alsoo btains remarkable improvement over the previous algorithms. The speedup factor s range from tens to hundreds times for benchmark circuits. For synchronous sequential circuits, in addition to adopting the above twotechniques, a dynam ic fault ordering technique, which puts the multiple eventfaults with the same faulty effects into the same packet to reduce the numberof events being proce ssed, has been introduced to form a new fault simulator.Its performance is com parable with the current most efficient fault simulators,such as HOPE and HyHO PE. By extending the fault simulation techniques andcombining a two-level opti mization technique, an efficient diagnostic faultsimulator has been developed. It minimizes the number of comparisons betweenfault-pair output responses by using an indistinguishability fault list in eachfault to store the faults that are indistinguishable from the fault.Experimental results show that it is fas ter than the previous one; even though,it still needs a very long period of ti me to deal with a very large benchmarkcircuit. To overcome the problem, a new distributed diagnostic fault simulatoris therefore developed. The major idea i n it is that the indistinguishabilityfault lists of all the detectable faults are obtained from the computers in thenetwork system. This way not only reduce s the number of faults being simulatedin fault simulation but also reduces the number of comparisons of outputresponse. That is the reason why for a very la rge circuit it can obtain a remarkable speedup.
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Sheu, Meng-Lieh, and 許孟烈. "A switch-level fault simulator (fmossim)." Thesis, 1986. http://ndltd.ncl.edu.tw/handle/91604516779377825040.
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HUANG, SHUN-DA, and 黃順達. "Ppdfsim: a parallel pattern delay fault simulator." Thesis, 1990. http://ndltd.ncl.edu.tw/handle/34154974230798536351.
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GIU, SHU-HUI, and 邱淑慧. "FMOTA:an MOS timing simulator with fault information." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/67745205844425463219.
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Liu, Jing-jia, and 劉靖家. "EFSIM: Enhanced Synchronous Sequential Circuit Fault Simulator." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/23899317188861909384.
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Chou, Tzung-Ping, and 周宗平. "A Fault Simulator Based on Software Emulation." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/98234692667115648923.
Full textAbstract:
碩士國立交通大學
電子研究所
83
In this thesis, a new fault simulation technique is presented. The technique uses software emulation to speed up the fault simulator. The keyword "Software Emulation" means that a module, which should be a netlist which describes connections for each gate at the gate level representation, is replaced by a set of software instructions. Hence fault effects can be propagated by symbolic operation. In this way, the fault effects can pass through a complex module quickly and a large amount of gate level evaluations is saved. Some traditional fault simulation techniques are modified in this work to fit the high level circuits and to speed up this fault simulator. In this way , We can take the advantage of high simulation speed of hierarchical level circuit and reverse the accuracy of the gate level circuit simulation at the same time. And the memory usage is also small in this method.
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HUANG, ZHI-SONG, and 黃志松. "A parallel pattern mixed-level fault simulator." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/93649544133439722866.
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QIAN, MEI-XING, and 錢美星. "A fault-simulator for synchronous sequential circuits." Thesis, 1989. http://ndltd.ncl.edu.tw/handle/30798342405567396445.
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Wang, Jia-Zhong, and 王家忠. "An Event-Stop Compiled-Code Parallel Fault Simulator." Thesis, 1996. http://ndltd.ncl.edu.tw/handle/56444268771093696056.
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CHEN, MING-DE, and 陳明德. "ACCEPT:a fault simulater for VLSI digital circuits." Thesis, 1988. http://ndltd.ncl.edu.tw/handle/64873595656132070957.
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Wu, Hsiang-Huang, and 吳祥煌. "CAMEL: An Efficient Fault Simulator for Content Addressable Memories." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/17160713307814954751.
Full textAbstract:
碩士國立清華大學
電機工程學系
91
Content Addressable Memory (CAM) is popular with networking industries so the testing of CAM plays an important role for the sake of the yield. There are various CAM for different applications. It means that developing efficient test algorithms are more difficulty when the functional outputs of CAM are different form each other. In this paper we provide an efficient fault simulator of CAM called the Content Addressable Memory EvaLuation tool (CAMEL) to help us. As a result of various CAM, we implement six common functional outputs, read, hit, multi-hit, empty, up priority address and low priority address. All combinations of these five functional outputs are supported. Besides, we also provide a method of detecting the coupling fault and the scaling method to reduce the memory usage and speed up the simulation time. The complexity of the memory usage and the simulation time all increase in proportion as the square of the word length. For diagnosis, CAMEL can output the signatures. It is convenient to develop test algorithms for most CAM.
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LIN, QI-XIANG, and 林祺祥. "Simulations on the fault operation of dc drives." Thesis, 1992. http://ndltd.ncl.edu.tw/handle/89027785429100384593.
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呂伍峰. "TRANS-DNR: A Dependent Non-Robust Path Delay Fault Simulator." Thesis, 1997. http://ndltd.ncl.edu.tw/handle/02872615557243297342.
Full textAbstract:
碩士中華大學
電機工程學系
85
This thesis presents a path delay fault simulator─TRANS-DNR, which is based on dependent non-robust path delay tests to improve the detection of path delay faults for multilevel circuits. The motivation results from one reason, in which the definition of a hazard-free robust or robust path delay test is too strict and the definition of a non-robust path delay test is too loose to make a fault simulator not to be accurate (either too strict or too loose). According to the definition of a dependent non-robust test, there are three types, DNR-I, DNR-II and DNR-III, of TRANS-DNR to evaluate the fault coverage of path delay faults under a set of test pattern pairs. Furthermore, we also propose a confident coefficient called "CoC" to measure the validity of path delay testing. By the experimental results, for DNR-I, DNR-II and DNR-III, the average fault coverage and CoC are 41.31% and 66.78, 46.22% and 47.34, and 46.67% and 45.85, respectively. Comparing the results with pessimistic robust fault coverage, 31.15%, TRANS-DNR is less stringent, and with optimistic non-robust fault coverage, 50.75%, TRANS-DNR is more stringent. Therefore, TRANS-DNR is better than either a robust or a non-robust path delay fault simulator in identifying the detection of path delay faults. For this reason, TRANS-DNR can be used to improve the accuracy of the identification of path delay faults of multilevel circuits.
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Li, Ting-Hui, and 李亭慧. "A Flexible Hybrid Fault Simulator for Software-Based Self-Test." Thesis, 2017. http://ndltd.ncl.edu.tw/handle/e67d34.
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碩士國立臺灣大學
電子工程學研究所
105
The use of software-based self-test technology can compensate for the shortages of conventional structural test and enhance the hardware in-field reliability. We have developed a flexible hybrid fault simulator which utilizes both logic gate level and register transfer level simulation to retain the accuracy and reduce the fault simulation time. Furthermore, we provide users the flexibility to set the fault model to be simulated. The proposed fault simulator aims to detect the possible hardware faults during the execution of test programs or applications. Evaluating the fault coverage of the generated test programs/applications can help develop fault tolerance techniques to improve the reliability of the system. The target fault model is the hardware fault caused by aging defects. We model the fault behavior as the path delay fault and transition delay fault models for aging fault simulation.
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Thomas, Marion Y. "Frictional Properties of Fault: From Observations on the Longitudinal Valley Fault, Taiwan, to Dynamic Simulations." Thesis, 2014. https://thesis.library.caltech.edu/7953/13/CH1_PhD_thesis_thomas_marion.pdf.
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Faults can slip either aseismically or through episodic seismic ruptures, but we still do not understand the factors which determine the partitioning between these two modes of slip. This challenge can now be addressed thanks to the dense set of geodetic and seismological networks that have been deployed in various areas with active tectonics. The data from such networks, as well as modern remote sensing techniques, indeed allow documenting of the spatial and temporal variability of slip mode and give some insight. This is the approach taken in this study, which is focused on the Longitudinal Valley Fault (LVF) in Eastern Taiwan. This fault is particularly appropriate since the very fast slip rate (about 5 cm/yr) is accommodated by both seismic and aseismic slip. Deformation of anthropogenic features shows that aseismic creep accounts for a significant fraction of fault slip near the surface, but this fault also released energy seismically, since it has produced five M_w>6.8 earthquakes in 1951 and 2003. Moreover, owing to the thrust component of slip, the fault zone is exhumed which allows investigation of deformation mechanisms. In order to put constraint on the factors that control the mode of slip, we apply a multidisciplinary approach that combines modeling of geodetic observations, structural analysis and numerical simulation of the "seismic cycle". Analyzing a dense set of geodetic and seismological data across the Longitudinal Valley, including campaign-mode GPS, continuous GPS (cGPS), leveling, accelerometric, and InSAR data, we document the partitioning between seismic and aseismic slip on the fault. For the time period 1992 to 2011, we found that about 80-90% of slip on the LVF in the 0-26 km seismogenic depth range is actually aseismic. The clay-rich Lichi M\'elange is identified as the key factor promoting creep at shallow depth. Microstructural investigations show that deformation within the fault zone must have resulted from a combination of frictional sliding at grain boundaries, cataclasis and pressure solution creep. Numerical modeling of earthquake sequences have been performed to investigate the possibility of reproducing the results from the kinematic inversion of geodetic and seismological data on the LVF. We first investigate the different modeling strategy that was developed to explore the role and relative importance of different factors on the manner in which slip accumulates on faults. We compare the results of quasi dynamic simulations and fully dynamic ones, and we conclude that ignoring the transient wave-mediated stress transfers would be inappropriate. We therefore carry on fully dynamic simulations and succeed in qualitatively reproducing the wide range of observations for the southern segment of the LVF. We conclude that the spatio-temporal evolution of fault slip on the Longitudinal Valley Fault over 1997-2011 is consistent to first order with prediction from a simple model in which a velocity-weakening patch is embedded in a velocity-strengthening area.
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Jiang, Jung Wu. "A Test Program Fault Simulator for Microprocessor Software-Based Self-Testing." 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2801200505453900.
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Wu, Jiang Jung, and 吳佳龍. "A Test Program Fault Simulator for Microprocessor Software-Based Self-Testing." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80033768228251602258.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
93
Abstract Software self-testing for embedded processor cores based on their instruction sets is a topic of increasing interest. Since it provides an excellent test resource partitioning technique for sharing the testing task of complex System-on-Chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. Although BIST or scan chain can provide higher fault coverage for complex SoC, higher power consumption and area overhead are two issues that should be solved. Software self-testing concept is to utilize the instruction sets provided by microprocessors or microcontrollers. The users can establish test program candidates by combining the instructions. Users can perform logic simulation and detect structural faults with test program candidates, record the signals in every clock cycle at the same time. The signals which were recorded in every clock cycle are called test vectors. The purpose of proposed fault simulator is to transfer test vectors into test file like STIL (standard test interface language) which can be accepted by fault simulator, and evaluate fault coverage, fault dictionary with circuit files. In the thesis, we present a high accuracy fault simulator for user defined test program candidates to evaluate fault coverage by performing fault simulation without modifying the original design. We acquire some useful information like fault coverage, fault dictionary through fault simulation. Users can compare the quality of these test program candidates and find out which candidate can detect the most faults. In addition, higher fault coverage could be achieved by combining test program candidates or finding some specific ordering. Some experiments are established to validate the proposed fault simulator. The Parwan and 8051 IP cores are taken for experiments. Some test programs come from public literature and others are from public websites. Before performing fault simulation, the correctness of function was validated in the beginning. Simulation results are shown to validate the proposed technique.
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Wu, Jiang-Jung, and 吳佳龍. "A Test Program Fault Simulator for Microprocessor Software-Based Self-Testing." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/93626535914953767835.
Full textAbstract:
碩士國立臺灣大學
電子工程學研究所
93
Software self-testing for embedded processor cores based on their instruction sets is a topic of increasing interest. Since it provides an excellent test resource partitioning technique for sharing the testing task of complex System-on-Chip (SoC) between slow, inexpensive testers and embedded code stored in memory cores of the SoC. Although BIST or scan chain can provide higher fault coverage for complex SoC, higher power consumption and area overhead are two issues that should be solved. Software self-testing concept is to utilize the instruction sets provided by microprocessors or microcontrollers. The users can establish test program candidates by combining the instructions. Users can perform logic simulation and detect structural faults with test program candidates, record the signals in every clock cycle at the same time. The signals which were recorded in every clock cycle are called test vectors. The purpose of proposed fault simulator is to transfer test vectors into test file like STIL (standard test interface language) which can be accepted by fault simulator, and evaluate fault coverage, fault dictionary with circuit files. In the thesis, we present a high accuracy fault simulator for user defined test program candidates to evaluate fault coverage by performing fault simulation without modifying the original design. We acquire some useful information like fault coverage, fault dictionary through fault simulation. Users can compare the quality of these test program candidates and find out which candidate can detect the most faults. In addition, higher fault coverage could be achieved by combining test program candidates or finding some specific ordering. Some experiments are established to validate the proposed fault simulator. The Parwan and 8051 IP cores are taken for experiments. Some test programs come from public literature and others are from public websites. Before performing fault simulation, the correctness of function was validated in the beginning. Simulation results are shown to validate the proposed technique.
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Chyi, Lin Meng, and 林孟祺. "TRANS: A Fast Path Delay Fault Simulator Based on Path Identification Technique." Thesis, 1993. http://ndltd.ncl.edu.tw/handle/58431372130769792074.
Full textAbstract:
碩士中華大學
電機工程研究所
81
This thesis presents a path delay fault simulator -- TRANS, which adopts a path identification technique, for both robust and nonrobust test pattern simulations. TRANS can evaluate the fault coverage of the path delay fault for a set of test pattern pairs. It is shown that TRANS exhibits a fast time performance and requires very little memory. To record a detected path delay fault, on average, only 2.5 bytes and 0.7 byte are needed for robust and nonrobust tests, respectively. Therefore, TRANS can very efficiently handle the enormous number of paths in a VLSI circuit. Comparing the experimental results with DAC'89, TRANS gets 85 times the gain of memory- speed product.
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Zhang, Chuan. "Modifying Instruction Sets In The Gem5 Simulator To Support Fault Tolerant Designs." 2015. https://scholarworks.umass.edu/masters_theses_2/310.
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Traditional fault tolerant techniques such as hardware or time redundancy incur high overhead and are inefficient for checking arithmetic operations. Our objective is to study an alternative approach of adding new instructions to check arithmetic operations. These checking instructions either rely on error detecting code or calculate approximate results and consequently, consume much less execution time. To evaluate the effectiveness of such an approach we wish to modify several benchmarks to use checking instructions and run simulation experiments to find out their execution time and memory usage. However, the checking instructions are not included in the instruction set and as a result, are not supported by current architecture simulators. Therefore, another objective of this thesis is to develop a method for inserting new instructions in the Gem5 simulator and cross compiler. The insertion process is integrated into a software tool called Gtool. Gtool can add an error checking capability to C programs by using the new instructions.
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Chen, Hui-Tzuen, and 陳匯尊. "A Fast and Accurate Multilevel Delay Fault Simulator for Software-based Self-Testing." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/8uwtyr.
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碩士國立臺灣大學
電子工程學研究所
106
Due to technology scaling, the reliability issue in modern CPU is increasingly important and is widely discussed since aging effect can affect transistor performance after decades. In order to detect aging-induced delay faults, at-speed software-based self-testing (SBST) is needed. Simulation-based schemes for SBST at different abstraction levels have been proposed, and these works entailed different tradeoff between speed and accuracy. In this thesis, we propose a functional delay fault simulator that supports SBST infrastructure. The proposed simulator mainly runs micro-architectural simulation and conditionally switches to gate level simulation to accurately simulate delay faults with high speed. To evaluate the proposed simulator, we extract paths in ALU module of ARM instruction set CPU, and we discuss fault activation behavior and report fault coverage of test programs.
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Wang, Jung-Hong, and 汪俊宏. "Simulations and Analysis of DC Motor Fault-SignalForewarning of a Steel Plant." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/86538260661456497695.
Full textAbstract:
碩士國立成功大學
電機工程學系碩博士班
95
In this thesis, simulations and measurements of DC motors of a steel plant have been carried out in order to develop a forewarning system such that the predictive maintenance can be better realized. In the method, each component of the steel devices was first individually formulated. Then, after connecting each model through a one-line diagram, the integrated scheme was validated through different scenarios, including load variations, low power-quality, bearing bias and shorting of a stator phase winding. It was expected that the fault probability can be prudently evaluated through the scenarios investigated. In the mean time, for each acquired data, they were presented by a feature value in order to facilitate the neural network training, hence anticipating the fault forewarning performance can be also significantly upgraded. Furthermore, test results of this proposed approach have been compared with the measurement data so as to better confirm the feasibility of the method applied for the motor-fault monitoring study.
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Hsu, Chia-Hsiang, and 徐家祥. "Evolution of fault-induced fold at Chushan excavation site, central Taiwan, derived from numerical analysis of PFC simulations." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/32696453744322240209.
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碩士國立中央大學
應用地質研究所
104
Exposures in the Chushan trench were 40 m long and 10 m deep, excavated across a 1999 earthquake-induced escarpment of 2 m high. There were two main structure profiles, called north wall and south wall. On south wall the fold was truncated through along the axial trace of its anticline by a fault branch with a dip angle of 32 degrees and a maximum separation of 4.2 m while on the north wall the steep limb of the fold was displaced up to 3.0 m along the axial trace of its syncline by another fault branch with a dip angle of 24 degrees. The distance between two walls was only 14 m. This study intends to explore the geometerail condition of the site when the site fromed the pure monocline which is before the heterogeneous structure and explore how this heterogeneous structure might form using distinct element simulation of basement faulting. This study uses Particle Flow Code (PFC) based on discrete element method, regarding material as assembled rigid particles. The rigid particles can be connected by two types of bond models. Because the PFC parameters are different from geomaterial mechanic properties, we cannot directly use the values of geomaterial mechanic properties. In order to attain the values of PFC parameters equailvent to the mechanic properties. PFC simulations of direct shear test and bilateral test are perfomed. All our models consist of two mechanical layers, including an upper clayey layer of 7 meters thick and a lower gravelly layer of 8-15 meters thick, as revealed by the excavation, a borehole nearby and soil tests. At the vertical displacement of 3.6 meters, Our results show that the monocline fold can be simulated by a low-angle reverse faulting similar to a subsurface dominant fault with a dip angle of 24 degrees derived from the trench site at the ground surface and in a borehole in the hanging wall, and the monocline structure can only generate when the cohesion of the clay layer is 11~12 kPa. Furthermore, the different structures on the two exposures were mainly controlled by the dip-angle variation of the upper part of the subsurface dominant fault. The simulation of reverse faulting with a dip angle of 24 degrees shows a monocline forms in the clayey layer, and then a gravelly wedge starts to protrude into the clayey layer and displace it along the axial trace of the syncline similar to the structure on the north wall, and the simulation of reverse faulting with a dip angle of 32 degrees shows a monocline forms in the clayey layer, and then this monoclinal clayey layer starts to be displaced along the axial trace of the anticline similar to the structure on the southern exposure.
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Arsénio, Pedro Miguel Lucas. "Contribution for the Study of Inductive Fault Current Limiters in Electrical Distribution Grids." Doctoral thesis, 2017. http://hdl.handle.net/10362/26673.
Full textAbstract:
Inductive type fault current limiters with superconducting tapes are emerging devices that provide technology for the advent of modern electrical grids, helping to mitigate operational problems that such grids can experience as well as preventing the often-costly upgrade of power equipment, namely protections. The development of such limiters leads to several design challenges regarding the constitutive parts of those devices, namely the magnetic core, primary winding and superconducting secondary.
Fault current limiters are required to operate at overcurrents during a certain amount of time. The operation at such currents can lead to harmful effects due to mechanical, electromagnetic and thermal stresses, especially in the superconducting tape. Since the operation principle of fault current limiters envisaged in this thesis is based on the superconducting-normal transition of superconducting materials, the study of its transient behaviour is an important research subject.
In this work, an electromagnetic methodology based on the characteristics of the constitutive parts of the limiters, previously developed and compared to finite element modelling simulations with very similar results, is simulated and validated with experimental results. Furthermore, the current in the superconducting tape is modelled from experimental results with the purpose of predicting the temperature of the material during normal and fault operation conditions, by employing a thermal-electrical analogy. These results are also compared to experimental measurements. A fast simulation tool, with computation times in the order of minutes, is also developed in Simulink, from Matlab environment.
With the developed simulation tool, it is possible to quickly predict the transient electromagnetic-thermal behaviour of an inductive type fault current limiter operating in electrical grids, namely the line current and primary linked flux, as well as current and temperature in the superconducting tape.
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Κασερίδης, Δημήτριος. "Ανάπτυξη εξομοιωτή σφαλμάτων για σφάλματα μετάβασης σε ψηφιακά ολοκληρωμένα κυκλώματα." Thesis, 2006. http://nemertes.lis.upatras.gr/jspui/handle/10889/536.
Full textAbstract:
Η μεταπτυχιακή αυτή εργασία μπορεί να χωριστεί σε δύο λογικά μέρη (Μέρος Α’ και Μέρος Β’). Το πρώτο μέρος αφορά τον έλεγχο ορθής λειτουργίας ψηφιακών κυκλωμάτων χρησιμοποιώντας το μοντέλο των Μεταβατικών (Transient) σφαλμάτων και πιο συγκεκριμένα περιλαμβάνει την μελέτη για το μοντέλο, τρόπο λειτουργίας και την υλοποίηση ενός Εξομοιωτή Μεταβατικών Σφαλμάτων (Transition Faults Simulator). Ο εξομοιωτής σφαλμάτων αποτελεί το πιο σημαντικό μέρος της αλυσίδας εργαλείων που απαιτούνται για τον σχεδιασμό και εφαρμογή τεχνικών ελέγχου ορθής λειτουργίας και η ύπαρξη ενός τέτοιου εργαλείου επιτρέπει την μελέτη νέων τεχνικών ελέγχου κάνοντας χρήση του Μεταβατικού μοντέλου σφαλμάτων.
Το δεύτερο μέρος της εργασίας συνοψίζει την μελέτη που πραγματοποιήθηκε για την δημιουργία ενός νέου αλγόριθμου επιλογής διανυσμάτων ελέγχου στην περίπτωση των Test Set Embedding τεχνικών ελέγχου. Ο αλγόριθμος επιτυγχάνει σημαντικές μειώσεις τόσο στον όγκο των απαιτούμενων δεδομένων που είναι απαραίτητο να αποθηκευτούν για την αναπαραγωγή του ελέγχου, σε σχέση με τις κλασικές προσεγγίσεις ελέγχου, όσο και στο μήκος των απαιτούμενων ακολουθιών ελέγχου που εφαρμόζονται στο υπό-έλεγχο κύκλωμα σε σχέση με προγενέστερους Test Set Embedding αλγορίθμους. Στο τέλος του μέρους Β’ προτείνεται μία αρχιτεκτονική για την υλοποίηση του αλγόριθμου σε Built-In Self-Test περιβάλλον ελέγχου ορθής λειτουργίας ακολουθούμενη από την εκτίμηση της απόδοσης αυτής και σύγκριση της με την καλύτερη ως τώρα προτεινόμενη αρχιτεκτονική που υπάρχει στην βιβλιογραφία (Βλέπε Παράρτημα Α).The thesis consists of two basic parts that apply in the field of VLSI testing of integrated circuits. The first one concludes the work that has been done in the field of VLSI testing using the Transient Fault model and more specifically, analyzes the model and the implementation of a Transition Fault Simulator. The transient fault model moves beyond the scope of the simple stuck-at fault model that is mainly used in the literature, by introducing the concept of time and therefore enables the testing techniques to be more precise and closer to reality. Furthermore, a fault simulator is probably the most important part of the tool chain that is required for the design, implementation and study of vlsi testing techniques and therefore having such a tool available, enables the study of new testing techniques using the transient fault model. The second part of the thesis summaries the study that took place for a new technique that reduces the test sequences of reseeding-based schemes in the case of Test Set Embedding testing techniques. The proposed algorithm features significant reductions in both the volumes of test data that are required to be stored for the precise regeneration of the test sequences, and the length of test vector sequences that are applied on the circuit under test, in comparison to the classical proposed test techniques that are available in the literature. In addition to the algorithm, a low hardware overhead architecture for implementing the algorithm in Built-in Self-Test environment is presented for which the imposed hardware overhead is confined to just one extra bit per seed, plus one, very small, extra counter in the scheme’s control logic. In the end of the second part, the proposed architecture is compared with the best so far proposed architecture available in the literature (see Appendix A)
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Mao, Vincent Chi Ann. "The Thermo-Mechanical Dynamics of DNA Self-Assembled Nanostructures." Diss., 2010. http://hdl.handle.net/10161/2435.
Full textAbstract:
The manufacturing of molecular-scale computing systems requires a scalable, reliable, and economic approach to create highly interconnected, dense arrays of devices. As a candidate substrate for nanoscale logic circuits, DNA self-assembled nanostructures have the potential to fulfill these requirements. However, a number of open challenges remain, including the scalability of DNA self-assembly, long-range signal propagation, and precise patterning of functionalized components. These challenges motivate the development of theory and experimental techniques to illuminate the connections among the physical, optical, and thermodynamic properties of DNA self-assembled nanostructures.
In this thesis, three tools are developed, validated, and applied to study the thermo-mechanical properties of DNA nanostructures: 1) a method to quantitatively measure the quality of DNA grid self-assembly, 2) a spectrofluorometer capable of capturing fluorescence and absorbance data under simultaneous multi-wavelength excitation, and 3) a Monte Carlo simulator that models the ensemble response of DNA nanostructures as simple harmonic oscillators.
The broad contributions of this dissertation are as follows: 1) insight into the thermo-mechanical properties of DNA grid nanostructures, and 2) a categorization of self-assembly defects and their impact on proposed logic circuits.
The results of the work presented in this dissertation show that: 1) the quality of self-assembly of DNA grid nanostructures can be quantitatively calculated to demonstrate the impact of changes in temperature or structure, 2) the optical absorbance of complex DNA nanostructures can be modeled to capture their thermo-mechanical properties (i.e., worst case within 10% of experimental melting temperatures and 70% of experimental thermodynamic parameters), 3) the structural resilience of DNA nanostructures can be quantifiably improved by chemical cross-linking with up to 60% retaining their original structure, and 4) DNA self-assembly introduces structural defects which create new fault models with respect to conventional technologies for logic circuits.
Dissertation
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Yuan, Yi. "A microprocessor performance and reliability simulation framework using the speculative functional-first methodology." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4848.
Full textAbstract:
With the high complexity of modern day microprocessors and the slow speed of cycle-accurate simulations, architects are often unable to adequately evaluate their designs during the architectural exploration phases of chip design. This thesis presents the design and implementation of the timing partition of the cycle-accurate, microarchitecture-level SFFSim-Bear simulator. SFFSim-Bear is an implementation of the speculative functional-first (SFF) methodology, and utilizes a hybrid software-FPGA platform to accelerate simulation throughput. The timing partition, implemented in FPGA, features throughput-oriented, latency-tolerant designs to cope with the challenges of the hybrid platform. Furthermore, a fault injection framework is added to this implementation that allows designers to study the reliability aspects of their processors. The result is a simulator that is fast, accurate, flexible, and extensible.text
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Ravishankar, Kurre. "Transient Analysis of EHV/UHV Transmission Systems for Improved Protection Schemes." Thesis, 2012. http://hdl.handle.net/2005/3248.
Full textAbstract:
Ever increasing demand for electricity, exploitation of large hydro and nuclear power at remote location has led to power evacuation by long EHV/UHV transmission systems. This thesis concentrates on transient analysis of EHV/UHV transmission systems for improved planning and protection.
In this thesis, the uncontrolled and controlled switching methods to limit the switching surges during energization of 765kV and 1200k VUHV transmission lines are studied. The switching surge over voltages during the energization of series compensated line are compared with uncompensated line. A Generalized Electromagnetic Transients Program has been developed. The program incorporates specific models for studying the effectiveness of various means for control of switching surge over voltages during UHV transmission line energization and also simulation of various types of faults. Since power grids may adopt next higher UHV transmission level 1200kV, these studies are necessary for insulation coordination as well as transmission line protection relay settings.
A new fault detection/location technique is presented for transmission line using synchronized fundamental voltage and current phasors obtained by PMUs at both ends of line. It is adaptive to fault resistance, source impedance variation, line loading and fault incidence angle. An improved Discrete Fourier Transform (DFT) algorithm to estimate and eliminate the decaying dc component in a fault current signal is proposed for computing the phasors.
The settings for digital distance relays under different operating conditions are obtained. The relay should operate faster and be more sensitive to various faults under different conditions without loosing selectivity. An accurate faulted transmission line model which considers distributed shunt capacitance has been presented. The relay trip boundaries are obtained considering transmission line model under realistic fault conditions. For different loading conditions ideal relay characteristic has been developed. The obtained trip boundaries can be used for proper settings of practical relay.
An adaptive relaying scheme is proposed for EHV/UHV transmission line using unsynchronized/synchronized fundamental voltage and current phasors at both ends of line. For fault location, the redundancy in equations is achieved by using two kinds of Clarke’s components which makes the calculations non-iterative and accurate. An operator for synchronization of the unsynchronized measurements is obtained by considering the distributed parameter line model. The distance to fault is calculated as per the synchronized measurements.
Support Vector Machine(SVM) is used for high speed protection of UHV line. The proposed relaying scheme detects the fault and faulted phase effectively within few milli seconds. The current and voltage signals of all phases at the substation are fed to SVM directly at a sampling frequency of 1.0kHZi.e20 samples/cycle . It is possible to detect faulted phase with in 3msec, using the data window of 1/4th cycle. The performance of relaying scheme has been checked with a typical 765kV Indian transmission System which is simulated using the developed EMTP.