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Palesko, Chet, and Amy Lujan. "Cost Comparison of Fan-out Wafer-Level Packaging to Fan-out Panel-Based Packaging." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000180–84. http://dx.doi.org/10.4071/isom-2016-wa32.
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Abstract Fan-out wafer-level packaging (FOWLP) offers many significant benefits over other packaging technologies. It is one of the smallest packaging options, but unlike fan-in wafer-level packaging, the IO count of FOWLP is not limited to the area of the die. Given these advantages, FOWLP continues to grow in popularity. While the cost of FOWLP is usually reasonable, there are still opportunities for future cost reduction. Many FOWLP suppliers are exploring panel-based manufacturing instead of the current wafer-based approach. Since many more packages can fit on a large panel than on a wafer, the cost per package can be reduced. The surface area of a 370mm × 470mm panel is 1,739 sq.cm. compared to 706 sq.cm. for a 300mm wafer. This means more than twice as many packages can be manufactured on a single panel. However, this does not mean that the cost per package will be cut in half. Many of the costly manufacturing activities do not depend on the surface area of the panel or wafer and they will not be affected by a larger panel. This paper analyzes the current cost of FOWLP activities and highlights which activities will benefit from a move to panels. An analysis of each manufacturing activity is presented comparing the cost impact of panel versus wafer. The total potential cost savings is also presented.
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Li, Ming, Qingqian Li, John Lau, Nelson Fan, Eric Kuah, Wu Kai, Ken Cheung, et al. "Characterizations of Fan-out Wafer-Level Packaging." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000557–62. http://dx.doi.org/10.4071/isom-2017-tha31_057.
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Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.
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Becker, Karl-Friedrich, Tanja Braun, S. Raatz, M. Minkus, V. Bader, J. Bauer, R. Aschenbrenner, et al. "On the Way from Fan-out Wafer to Fan-out Panel Level Packaging." International Symposium on Microelectronics 2016, S2 (October 1, 2016): S1—S23. http://dx.doi.org/10.4071/isom-2016-slide-4.
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Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.
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Shelton, Doug. "Advanced Manufacturing Technology for Fan-Out Wafer Level Packaging." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000251–55. http://dx.doi.org/10.4071/isom-2015-wa34.
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Advanced process technology is required to develop and enable mass production of Fan-Out Wafer-Level Packaging (FOWLP) solutions for high-density 3D and 2.5D packaging. Canon has identified key challenges that must be solved for successful implementation of high-density integration technologies and has developed key technology for Canon Litho Systems to support the most challenging processes. In this paper, Canon will present process optimization results for high-resolution patterning of wafers across large topography as well as solutions that enable litho systems to compensate for FOWLP grid error due to die placement errors.
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GOTO, Yoshio, Kosuke URUSHIHARA, Bunsuke TAKESHITA, and Ken-Ichiro MORI. "A study of Sub-micron Fan-out Wafer Level Packaging solutions." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000488–93. http://dx.doi.org/10.4071/2380-4505-2018.1.000488.
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Abstract In Fan-out Wafer Level Packaging (FOWLP) processes, redistribution layer (RDL) line width reduction is a key challenge to expand the FOWLP market to multi-chip interconnections, including interconnections between SoC and DRAM, split-die connection of FPGA, and interconnections between image sensors and SoC. Next generation FOWLP requires 1.0 μm RDL and future FOWLP is targeting 0.8 μm RDL. To meet these requirements, Canon has developed new projection optics with a high NA and wide-field that is best suited for sub-micron FOWLP. These projection optics are a new option for FPA-5520iV steppers, offering NA 0.24 imaging and a 52 × 34 mm exposure field. FPA-5520iV steppers with NA 0.24 provide excellent 0.8 μm resolution performance throughout all imaging fields thanks to Canon's wave-front aberration based projection optics manufacturing methods and on-axis optical tilt focus sensor.
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Palesko, Chet, and Amy Lujan. "Cost Comparison of Fan-out Wafer-Level Packaging to Embedded Die Packaging." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000721–26. http://dx.doi.org/10.4071/isom-2017-thp32_050.
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Abstract Fan-out wafer-level packaging (FOWLP) and embedded die packaging offer similar advantages over traditional packaging technologies. For example, both packages can be quite thin since the die is placed early in the manufacturing process and the package is fabricated around the die. This is in contrast to traditional packaging technologies, in which the package is fabricated first, and then the die is placed on top of the package. This results in a thicker package compared to fabricating the package around the die. Due to the ongoing miniaturization market requirements, thinner packages are becoming increasingly important. Both FOWLP and embedded die packaging also provide the capability of placing multiple die and passives in a single package. This capability can have both size and performance benefits since the interconnect distance between the embedded components is shorter. In this paper, the cost and cost drivers of FOWLP and embedded die packaging technologies will be compared. Activity based modeling will be used to characterize the cost of each activity in the two manufacturing flows.
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Ray, Urmi. "Chip Package Interaction Considerations in Fan-out Wafer Level Packaging." International Symposium on Microelectronics 2016, S2 (October 1, 2016): S1—S13. http://dx.doi.org/10.4071/isom-2016-slide-7.
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With the advent of thinner die/packages, new materials and more complex packages Chip Package Interaction has become a larger concern for the industry. Wafer Level Packages and variants such as Fan Out Wafer Level Packages (FOWLP) have an additional risk which we refer to as Chip Board Interaction. This talk will discuss some of the basics of the CPI and CBI risks to FOWLP which include both mechanical and electrical risks to products. These mechanisms span the Design, Process and Package domains and as such requires a collaborative efforts to manage the risks and trade-offs.
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Braun, Tanja, Karl-Friedrich Becker, Ole Hoelck, Steve Voges, Ruben Kahle, Marc Dreissigacker, and Martin Schneider-Ramelow. "Fan-Out Wafer and Panel Level Packaging as Packaging Platform for Heterogeneous Integration." Micromachines 10, no. 5 (May 23, 2019): 342. http://dx.doi.org/10.3390/mi10050342.
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Fan-out wafer level packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration, including multiple die packaging, passive component integration in packages and redistribution layers or package-on-package approaches, larger substrate formats are also targeted. Manufacturing is currently done on a wafer level of up to 12”/300 mm and 330 mm respectively. For a higher productivity and, consequently, lower costs, larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging (PLP) might be the next big step. Both technology approaches offer a lot of opportunities as high miniaturization and are well suited for heterogeneous integration. Hence, FOWLP and PLP are well suited for the packaging of a highly miniaturized energy harvester system consisting of a piezo-based harvester, a power management unit and a supercapacitor for energy storage. In this study, the FOWLP and PLP approaches have been chosen for an application-specific integrated circuit (ASIC) package development with integrated SMD (surface mount device) capacitors. The process developments and the successful overall proof of concept for the packaging approach have been done on a 200 mm wafer size. In a second step, the technology was scaled up to a 457 × 305 mm2 panel size using the same materials, equipment and process flow, demonstrating the low cost and large area capabilities of the approach.
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Bluck, Terry, Chris Smith, and Paul Werbaneth. "Productivity Comparison of Wafer Transport Architectures in PVD Tools Used for Fan-Out Packaging RDL Barrier/Seed Formation." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000748–53. http://dx.doi.org/10.4071/2380-4505-2018.1.000748.
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Abstract Physical Vapor Deposition (PVD) systems are widely used in the semiconductor fabrication industry, both for front-end applications in the wafer fab and for back-end applications at device packaging houses. In fan-out wafer level packaging (FOWLP), and in fan-out panel level packaging (FOPLP), sputter deposited Ti and Cu are the base on which electroplated copper Redistribution Layers (RDLs) are built. For these RDL barrier/seed layers, PVD cluster tools, wafer transport architectures that have been widely used since the mid-1980s, are the current Process of Record (POR) in advanced packaging; however, these tools typically operate in a regime where wafer transport is robot-limited to approximately 50 wafers per hour, which limits overall throughput and greatly influences Cost of Ownership (COO) for the sputter deposition step(s), because the central handling robot occupied with a transfer from the Ti PVD module to the Cu PVD module, for example, has no opportunity to be doing anything other than that specific transfer. Other wafer transport architectures are more efficient from a wafer handling perspective. In linear transport carrier-based PVD tools, wafers or panels passing through the system benefit from a mechanical transfer time budget that is considerably less than for a cluster tool. Transport time overhead per wafer on linear transport systems is quite low, and scheduler software optimization becomes less onerous too, as a result of the simpler wafer transport architecture. We analyzed the relative throughput of cluster and linear transport PVD tools for a typical FOWLP barrier/seed layer (1000Å Ti / 2000Å Cu) sputter deposition process, and present details here of how the time spent moving wafers to various processing chambers affects overall system productivity. In the case of the cluster tool architecture, with its central wafer handling robot, wafer throughputs are approximately 50 wafers per hour, while on the linear transport system wafer throughputs as high as 240 wafers per hour are possible. The significant difference in system throughputs greatly affects the relative Cost of Ownership (COO) per wafer processed, with the linear transport system returning COO results that are less than half those of the typical cluster PVD tool.
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Chen, Scott, Simon Wang, Coltrane Lee, Adren Hsieh, John Hunt, and William Chen. "Chip Last Fan Out as an Alternative to Chip First." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000245–50. http://dx.doi.org/10.4071/isom-2015-wa33.
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Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, and they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), and system in package (SIP) being widely used in these smart phones & mobile devices.. Fan out WLCSP (FOWLP) has great potential to be the next new package for the smart phone mobility application. Two factors have driven fan out WLCSP (FOWLP) package technology in the last few years. The first is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solder ball interconnects. The second and potentially more important factor relates to the demand of the market for more functions. Not all silicon functionality benefits from these advanced nodes, and merely adds to the cost of the die. This has driven the designers to partitioning of desired functionality into multiple die, which in turn requires effective interconnection of these separate die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). Up to date FOWLP used chip first processing, in which the bare die was molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a new alternative to chip first FOWLP, an alternative which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package has been in production in ASE for over a year, and uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented. We have designated this package structure “Fan Out Chip Last Package (FOCLP)” For higher end applications we will show the ability to use a high density substrate process for use in more demanding chip last fan out packages
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Roshanghias, Ali, Marc Dreissigacker, Christina Scherf, Christian Bretthauer, Lukas Rauter, Johanna Zikulnig, Tanja Braun, Karl-F. Becker, Sven Rzepka, and Martin Schneider-Ramelow. "On the Feasibility of Fan-Out Wafer-Level Packaging of Capacitive Micromachined Ultrasound Transducers (CMUT) by Using Inkjet-Printed Redistribution Layers." Micromachines 11, no. 6 (May 31, 2020): 564. http://dx.doi.org/10.3390/mi11060564.
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Fan-out wafer-level packaging (FOWLP) is an interesting platform for Microelectromechanical systems (MEMS) sensor packaging. Employing FOWLP for MEMS sensor packaging has some unique challenges, while some originate merely from the fabrication of redistribution layers (RDL). For instance, it is crucial to protect the delicate structures and fragile membranes during RDL formation. Thus, additive manufacturing (AM) for RDL formation seems to be an auspicious approach, as those challenges are conquered by principle. In this study, by exploiting the benefits of AM, RDLs for fan-out packaging of capacitive micromachined ultrasound transducers (CMUT) were realized via drop-on-demand inkjet printing technology. The long-term reliability of the printed tracks was assessed via temperature cycling tests. The effects of multilayering and implementation of an insulating ramp on the reliability of the conductive tracks were identified. Packaging-induced stresses on CMUT dies were further investigated via laser-Doppler vibrometry (LDV) measurements and the corresponding resonance frequency shift. Conclusively, the bottlenecks of the inkjet-printed RDLs for FOWLP were discussed in detail.
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Coudrain, Perceval, Arnaud Garnier, Laetitia Castagné, Aurélia Plihon, Rémi Vélard, Rémi Franiatte, Jean-Charles Souriau, Jeanne Pignol, Célia Darrambide, and Emmanuel Ollier. "(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems." ECS Transactions 109, no. 2 (September 30, 2022): 3–14. http://dx.doi.org/10.1149/10902.0003ecst.
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This article describes opportunities and challenges towards heterogeneous systems integration by the so-called fan-out wafer-level packaging (FOWLP) technology. An introduction on the technology is given, before we describe specific developments built up at CEA-Leti. Recent assessments of a multi-chip SiP for 5G applications and scalable three-dimensional interconnects are presented.
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Dreissigacker, Marc, Ole Hoelck, Joerg Bauer, Tanja Braun, Karl-Friedrich Becker, Martin Schneider-Ramelow, and Klaus-Dieter Lang. "A numerical study on mitigation of flying dies in compression molding of microelectronic packages." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000355–60. http://dx.doi.org/10.4071/2380-4505-2018.1.000355.
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Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dies during encapsulation in Fan-Out Wafer Level Packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemo-rheology, as well as to extract forces exerted on individual dies. It offers separate evaluation of pressure and shear-contributions for two cases, 0 ° and 45 ° between the dies' frontal area and the melt front. Process parameters, such as compression speed and process temperature, are determined to minimize flying dies and thereby maximize yield. The approach is easily scalable and is therefore well suited to face the challenges that come with the current efforts towards the transition from FOWLP to FOPLP (Fan-Out Panel Level Packaging).
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Kang, Lewis(In Soo). "FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–41. http://dx.doi.org/10.4071/2017dpc-ta2_presentation2.
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The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.
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Lim, Jacinta Aman, and Vinayak Pandey. "Innovative Integration Solutions for SiP Packages Using Fan-Out Wafer Level eWLB Technology." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000263–69. http://dx.doi.org/10.4071/isom-2017-wa42_039.
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Abstract Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effectiveness. The increasing complexities in achieving a higher degree of performance, bandwidth and better power efficiency in various markets are pushing the boundaries of emerging packaging technologies to smaller form factor packaging designs with finer line/width spacing as well as improved thermal/electrical performance and the integration of System-in-Package (SiP) or 3D capabilities. SiP technology has been evolving through utilization of various package technology building blocks to serve the market needs with respect to miniaturization, higher integration, and smaller form factor as cited above, with the added benefits of lower cost and faster time to market as compared to silicon (Si) level integration, which is commonly called system-on-chip or SoC. As such, SiP incorporates flip chip (FC), wire bond (WB), and fan-out wafer-level packaging (FOWLP) as its technology building blocks and serves various end applications ranging from radio frequency (RF), power amplifiers (PA), Micro-Electro-Mechanical-Systems (MEMS) and Sensors, and connectivity, to more advanced application processors (AP), and other logic devices such as graphics processing units (GPUs)/central processing units (CPUs). FOWLP, also referred to as advanced embedded Wafer Level Ball Grid Array (eWLB) technology, provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D SiP configurations. This paper presents developments in SiP applications with eWLB/Fan-out WLP technology, integration of various functional blocks such as wire bonding, Package-on-Package (PoP), 2.5D, 3D, smaller form factor, embedded passives, multiple redistribution layer routing and z-height reduction. Test vehicles have been designed and fabricated to demonstrate and characterize these low profile and integrated packaging solutions for mobile products including Internet of Things (IoT)/wearable electronics (WE), MEMS and sensors. Finer line/width spacing of 2/2mm with multiple redistribution layers (RDL) are fabricated and implemented on the eWLB platform to enable higher interconnect density and signal routing. Assembly process details, component level reliability, board level reliability and characterization results for eWLB SiP will be discussed.
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Kroehnert, Steffen, André Cardoso, Steffen Kroehnert, Raquel Pinto, Elisabete Fernandes, and Isabel Barros. "Integration of MEMS in Fan-Out Wafer-Level Packaging Technology based System-in-Package (WLSiP)." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–23. http://dx.doi.org/10.4071/2017dpc-tp2_presentation6.
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The Internet of Things/ Everything (IoT/E) will require billions of single or multiple MEMS/Sensors integrated in modules together with other functional building blocks like processor, memory, connectivity, built-in security, power management, energy harvesting, and battery charging. The success of IoT/E will also depend on the selection of the right Packaging Technology. The winner will be the one achieving the following key targets: best electrical and thermal system performance, miniaturization by dense system integration, effective MEMS/Sensors fusion into the systems, manufacturability in high volume at low cost. MEMS/Sensors packaging in low cost molded packages on large manufacturing formats has always been a challenge, whether because of the parameter drift of the sensors caused by the packaging itself or, as in many cases, the molded packaging technology is not compatible to the way MEMS/Sensors are working. Wafer-Level Packaging (WLP), namely Fan-Out WLP (FOWLP) technologies such as eWLB, WLFO, RCP, M-Series and InFO are showing good potential to meet those requirements and offer the envisioned system solutions. FOWLP will grow with CAGR between 50–80% until 2020, forecasted by the leading market research companies in this field. System integration solutions (WLSiP and WL3D) will dominate FOWLP volumes in the future compared to current single die FOWLP packages for mobile communication. The base technology is available and has proven maturity in high volume production, but for dense system integration of MEMS/Sensors, additional advanced building blocks need to be developed and qualified to extend the technology platform. The status and most recent developments on NANIUM's WLFO technology, which is based on Infineon's/Intel's eWLB technology, aiming to overcome the current limits for MEMS/Sensors integration, will be presented in this paper. This will cover the processing of Keep-Out Zones (KOZ) for MEMS/Sensors access to environment in molded wafer-level packages, mold stress relief on dies for MEMS/Sensors die decoupling from internal package stress, thin-film shielding using PVD seed layer as functional layer, and heterogeneous dielectrics stacking, in which different dielectric materials fulfill different functions in the package, including the ability to integrate Microfluidic.
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Coudrain, Perceval, Arnaud Garnier, Laetitia Castagné, Aurélia Plihon, Rémi Vélard, Rémi Franiatte, Jean-Charles Souriau, Jeanne Pignol, Célia Darrambide, and Emmanuel Ollier. "(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems." ECS Meeting Abstracts MA2022-02, no. 17 (October 9, 2022): 849. http://dx.doi.org/10.1149/ma2022-0217849mtgabs.
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Fan-out wafer-level packaging has become during the last decade an iconic part of the More Than Moore trend. Emerging in the mid-2000s and early declined in embedded wafer level ball grid array (eWLB), it has since gained popularity for the realization of high-potential systems-in-package (SiP). The basic technology is based on the reconstruction of wafers from individual chips. After embedding chips with an epoxy mold compound (EMC), electrical connections are processed in the form of redistribution layers (RDL) to fan-out signals from chip I/Os to solder balls, whose dimensions are compatible with direct soldering to a printed circuit board. Eliminating the need for intermediate laminated substrates, it has enabled the integration of systems with high performance at reduced cost and footprint. It has also paved the way for applications that would have been difficult to address with conventional packaging. In a resolutely heterogeneous declination of this technology, the co-integration of several chips in a single and dense package has allowed processing multi-chip SiPs including CMOS circuits, memories, radio-frequency (RF) chips and passive components with reduced interconnect length. It is indeed possible to combine in the same package different materials such as Si, SiC, GaN, AsGa. This property gives FOWLP technology unique advantages in terms of cost and versatility that make it attractive in many application areas. Two trends seem to take advantage of this technology. On one hand, the realization of high performance SiPs integrating miniaturized CMOS processors and dense, high bandwidth memories with aggressive interconnects design rules. On the other hand, highly heterogeneous systems mixing semiconductors, especially in the field of wireless telecommunications. For over a decade, RF devices have been taking advantage of FOWLP to build advanced packages with shorter interconnects. Mass production has been reached since 2009 for automotive radars, baseband processors, RF transceivers and power management circuits. More recently, the millimeter wave market has gained interest with the development of 5G at high frequencies (>6 GHz), where the fan-out area becomes an opportunity to embed high quality passives and antennas. CEA-Leti has been studying this technology from its inception, with pioneering work since 2005 outlining wafer reconstruction for heterogeneous integration. At the heart of integration, the epoxy mold compound (EMC) is the way to reconstruct the wafer. By becoming the mechanical link between the different chips, it plays a crucial role during the entire process. On another level, the interconnects constitute the final purpose of the FOWLP integration: RDL layers create the link between chips in heterogeneous SiPs, as well as the link between the SiP and the outside world. These two components must be mastered to ensure functionality and performance of final SiPs. Among various available configurations, the die first scheme consists in positioning chips before molding and processing the interconnects. In RDL 1st scheme the interconnections are, conversely, made before chips are placed. Although these approaches sometimes compete, they generally meet different specifications. Nevertheless, all the configurations share integration issues related to the materials and processes involved. Some of the classic issues met in FOWLP include wafer deformation due to CTE mismatches, die shift during the process and the difficult task of heat dissipation in dense SiPs with increased power densities. We will show how useful the characterization techniques are to develop and improve the overall process, in order to reach the targeted specifications. To illustrate these elements, a detailed description of the technology built up for the realization of heterogeneous systems will be given, such as 5G base stations transceiver operating at 28 GHz including GaN and AsGa chips. We will also present original options implemented to meet the needs of other application fields, and develop our strategy regarding thermal dissipation for future SiPs. In a FOWLP approach, three-dimensional integration is also possible thanks to a technological toolbox that includes, in addition to RDL and solder balls, vertical connections such as Through-Mold Via (TMV). We will describe an original approach developed at CEA-Leti for the fabrication of high aspect ratio TMVs, with a demonstration of 225 µm high and 100 µm pitch TMV for the realization of 3D SiP with high interconnection density. Figure 1
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Bishop, Craig, Suresh Jayaraman, Boyd Rogers, Chris Scanlan, and Tim Olson. "M-Series with Adaptive Patterning for High-Yield Fan-Out SIP." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 000751–73. http://dx.doi.org/10.4071/2016dpc-tp22.
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Fan-Out Wafer Level Packaging (FOWLP) holds immediate promise for packaging semiconductor chips with higher interconnect density than the incumbent Wafer Level Chip Scale Packaging (WLCSP). FOWLP enables size and performance capabilities similar to WLCSP, while extending capabilities to include multi-device system-in-packages. FOWLP can support applications that integrate multiple heterogeneously processed die at lower cost than 2.5D silicon interposer technologies. Current industry challenges with die position yield after die placement and molding result in low-density design rules and the high-cost of accurate die placement. Efficiently handling die shift is essential for making FOWLP cost-competitive with other technologies such as FCCSP and QFN. This presentation will provide an overview of Adaptive Patterning, a new technology for overcoming variability of die positions after placement and molding. In this process, an optical scanner is used to measure the true XY position and rotation of each die after panelization. The die measurements are then fed into a proprietary software engine that generates a unique pattern for each package. The resulting patterns are dispatched to a lithography system, which dynamically implements the unique patterns for all packages within a panel. For system-in-packages, this process offers a unique advantage over a fixed pattern: each die shift can be handled independently. With a fixed pattern, the design tolerances need to be large enough for all die to shift in opposing directions, otherwise yield loss in incurred. With Adaptive Patterning, vias and RDL features remain at minimum size and are matched to the measured die shift. The die-to-die interconnects are dynamically generated and account for the unique position of each die. Thus, Adaptive Patterning retains the same high-density design rules regardless of how many die are in a package. Adaptive Patterning provides the capability to use high-throughput die placement to drive down cost, while enabling higher-density system-in-package interconnect. With this technology the industry can finally realize the cost, flexibility, and form factor benefits of FOWLP.
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Lau, John, Ming Li, Yang Lei, Margie Li, Iris Xu, Tony Chen, Qing Xiang Yong, et al. "Reliability of Fan-Out Wafer-Level Heterogeneous Integration." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000224–32. http://dx.doi.org/10.4071/2380-4505-2018.1.000224.
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Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.
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Silveira, Elvino Da, Keith Best, Gurvinder Singh, and Roger McCleary. "Advanced Packaging Lithography and Inspection Solutions for Next Generation FOWLP-FOPLP Processing." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–36. http://dx.doi.org/10.4071/2017dpc-wp2_presentation2.
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For more than 50 years the semiconductor industry has pursued Moore's law, continuously improving device performance, reducing cost, and scaling transistor geometries down to where advanced CMOS has reached beyond the 10nm technology node. The commensurate increase in I/O count has created many challenges for device packaging which hitherto was considered low cost with simple solutions. It was once thought that old backend foundry lithography steppers could be used to address the new packaging requirements; which was true whilst the substrates remained in the traditional 300mm Silicon format. The recent unprecedented rapid growth in Fan Out Wafer Level Packaging (FOWLP) applications has introduced a more complicated landscape of process challenges, with no restriction on substrate format, where cost is the main driver and high yields are mandatory. This paper discusses the lithography process challenges that have ensued from disruptive FOWLP, and more recently the paradigm shift to Panel fan out Packaging. The work reports on lithography solutions for CD control over topography and high aspect ratio imaging of 2μm line/space RDL. In addition, the introduction of new inspection capabilities for defects and metrology is reported for both wafers and panels. The increase in lithography productivity and cost reduction provided by FOPLP is also discussed with production examples.
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Chen, Chuan, Meiying Su, Rui Ma, Yunyan Zhou, Jun Li, and Liqiang Cao. "Investigation of Warpage for Multi-Die Fan-Out Wafer-Level Packaging Process." Materials 15, no. 5 (February 23, 2022): 1683. http://dx.doi.org/10.3390/ma15051683.
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This paper focuses on characterizing the evolution of warpage, effects of epoxy molding compound (EMC), and effects of carrier 2 (the second carrier in the process) of 12 inch RDL-first multi-die fan-out wafer-level packaging (FOWLP) during the manufacturing process. The linear viscoelasticity properties of EMC and polyimide (PI) were characterized using dynamic mechanical analysis (DMA) in the frequency domain at different temperatures., The elastic and viscoelastic model were used for PI and EMC, the finite element analyses (FEA) of the cured structure were carried out and the results were compared with the test results. The viscoelastic properties of the EMC in the FEA could predict the wafer warpage more accurately. The FEA and experiments were used to investigate the evolution of warpage. The molding had a great influence on the warpage. The effects of the EMC and carrier 2 were also investigated with FEA. The wafer warpage could be reduced by lowering the thickness of the EMC, increasing the thickness of carrier 2, and selecting EMC and carrier 2 with a matched coefficient of thermal expansion (CTE).
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Lau, John, Ming Li, Nelson Fan, Eric Kuah, Zhang Li, Kim Hwee Tan, Tony Chen, et al. "Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000576–83. http://dx.doi.org/10.4071/isom-2017-tha35_056.
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Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).
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Lau, John, Ming Li, Nelson Fan, Eric Kuah, Zhang Li, Kim Hwee Tan, Tony Chen, et al. "Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)." Journal of Microelectronics and Electronic Packaging 14, no. 4 (October 1, 2017): 123–31. http://dx.doi.org/10.4071/imaps.522798.
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This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).
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Xie, Hong, Daquan Yu, Zhenrui Huang, Zhiyi Xiao, Li Yang, and Min Xiang. "Embedded Si Fan Out: A Low Cost Wafer Level Packaging Technology Without Molding and De-bonding Processes." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–15. http://dx.doi.org/10.4071/2017dpc-tp2_presentation2.
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The growing and diversifying system requirements have continued to drive the development of a variety of new package technologies and configurations: small form factor, low weight, low profile, high pin count and high speed and low cost. Embedded chip in EMC, also called fan-out wafer-level packaging (FOWLP), has been used in various products such as baseband, RF (radio frequency) transceiver, and PMICs (power management ICs). Currently, INFO technology developed by TSMC®, NANIUM® were in mass production for 3D integration for processor and memory, which inspires other packaging foundries to develop their own embedded FOWLP for the forecasted explosive growth of this market in the next few years. There are a number of challenges for FOWLP. For process point of view, temporary bonding and de-bonding are required. EMC wafers are difficult to handle due to its large warpage driven by the big CTE difference between the Si and molding material. In addition, the manufacturing of fine pitch RDL on EMC surface is also difficult. In this paper, the concept of wafer level embedded Si Fan-Out (eSiFO) technology was introduced and the development progress was reported. For eSiFO, cavities with certain depth were formed by Si dry etch. Then device dies were thinned to designed thickness. The dice were then placed into the cavities and bonded by the attached film on the bottom of the dice. A reconstructed wafer was formed. The micro gap between the chip and sidewall of the cavity as well as the surface of the reconstructed wafer were filled by dry film using vacuum process. Next, the pads were opened, followed RDL fabrication, repassivation, BGA, wafer thinning and dicing. Finally, an eSiFO package was fabricated. There are a number of advantages for eSiFO technology. There is nearly no warpage since the Si was used as reconstruct substrate. The process is relatively simple since no molding, temporary bonding and de-bonding are required. RDL manufacturing is easier on Si wafer vs with molding compounds and can achieve high density routing. Furthermore, it can provide small form factor since the thinning of wafer is the last step. To prove the concept of eSiFO, a 3.3 x 3.3mm package with 50 BGA bumps at 400μm pitch was fabricated. The device wafer was thinned to 100μm. The die size is 1.96 × 2.36mm with pad pitch at about 90μm. The depth of the cavities on 8 in. wafer formed by Bosch process on bare Si wafer was 107μm with 8μm variation. The length and width of Si cavities is 20μm larger than die size. In the package, there is one layer Cu RDL with thickness of 3μm, minimum line width of 13.72μm. The BGA ball diameter is 280μm. All the processes were evaluated and the results showed such packages can be produced. Reliability tests including THS, T/C, HTS and HAST were carried out and no failure issue was observed. Mechanical simulation was used to analyze the stress distribution during TC test and the results showed the maximum stress was located at the RDL near the UBM. In summary, a low cost wafer level fan out technology using reconstructed Si wafer was developed. The process is simple without molding, temporary bonding and de-bonding. The reliability tests of test vehicles proved that such package is reliable. The newly developed eSiFO technology can be widely used for chips requiring fan-Out, small form factor and high density interconnects.
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Lee, Alvin, Jay Su, Baron Huang, Ram Trichur, Dongshun Bai, Xiao Liu, Wen-Wei Shen, et al. "Optimization of laser release layer, glass carrier, and organic build-up layer to enable RDL-first fan-out wafer-level packaging." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000190–95. http://dx.doi.org/10.4071/isom-2016-wa34.
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Abstract With increasing demand for mobile devices to be lighter and thinner and consume less power while operating at high speed and high bandwidth, many equipment suppliers and assembly participants have invested great efforts to achieve fine-line fan-out wafer-level packaging (FOWLP). However, the inherent warp of reconstituted wafers, which can contribute to poor die placement accuracy and/or delamination at the interface of the build-up layer and carrier, remains a major challenge. In this study, the interactions among laser release layer, glass carrier, and build-up layer were evaluated for optimization of redistribution layer (RDL)–first FOWLP as a foundation to move toward fine-line FOWLP. In this study, a series of experiments incorporating glass carrier, laser release layer, and build-up layers were carried out to determine the optimal setup for RDL-first FOWLP. First, glass carriers (300 mm × 300 mm × 0.7 mm) with coefficients of thermal expansion of 3 and 8 ppm/°C were treated with 150-nm laser release layers. After deposition of 0.1 μm of sacrificial material on the glass carrier, 8-μm build-up layers were coated and patterned by lithography to electroplate Cu interconnections with a density of approximately 10% of the surface area. Subsequent to die attachment, molding compound was applied on top to form a 200-μm protective overcoat. The reconstituted wafer was then separated from the glass carrier through a laser ablation process using a 308-nm laser to complete the design of experiments (DOE). An experiment to study the correlation of glass carrier, laser release layer, build-up layers, and molding compound in RDL-first FOWLP processes is discussed to address full process integration on 300-mm glass substrates. The combination of glass carrier, laser release layer, build-up layer, and molding compound will pave the way for realizing cost-effective RDL-first FOWLP on panel-size substrates.
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Chen, Scott, Simon Wang, Coltrane Lee, and John Hunt. "Low Cost Chip Last Fanout Package using Coreless Substrate." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2015, DPC (January 1, 2015): 000272–300. http://dx.doi.org/10.4071/2015dpc-ta24.
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Smart phones & other portable devices have dominated Semiconductor growth, and drive IC packages smaller, lighter & thinner, but at the same time they continue to integrate more functions in that smaller volume. Besides SOC solutions driven by design houses or system companies, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) being widely used in these smart phones & mobile devices. Two factors have driven a new package technology within the last 10 years. One is the advancing technology nodes which allow the shrinkage of die, allowing more die per wafer. However this comes at the cost of reduced package area for I/Os such as solderball interconnects. The second factor also relates to the advancing technology nodes. Not all silicon functionality benefits from there advanced nodes, and merely adds to the cost of the die. This has driven the partitioning of device functionality into multiple die, which in turn requires effective interconnection of these partitioned die. The packaging technology that has evolved to solve these two situations has been Fan Out Wafer Level Packaging (FOWLP). The typical FOWLP uses chip first processing, in which the bare die is molded into a wafer shaped carrier with die pads exposed. Typically sputtering is used to provide interconnects to the die pad followed by patterned electroplating of redistribution lines (RDL) to “Fan Out” the next level interconnect pads to regions that can extend on to the molded material beyond the die perimeter. These processes require the use of relatively expensive semiconductor front end classes of equipment and are tailored to handle the reconstituted molded plastic wafers. We will describe a relatively low cost alternative to FOWLP, which meets the needs of a large percentage of the applications requiring a packaging technology such as FOWLP. This new package uses a “Chip Last” approach to the problem of increasing useable interconnect pad area. Die which have been bumped with Copper(Cu) Pillars are mass reflowed onto a low cost coreless substrate, followed by over molding which also serves as the die underfill. The Cu pillars allow direct connection to die pads at 50 μm pitch or below, negating the requirement for RDL formation on the die. The use of embedded traces allows for fine lines and spaces down to 15μm or less, and bonding directly on to the bare Copper. The Cu Pillars are bonded to one side of the Copper trace, and the solderballs or LGA pads are directly on the opposite side of the Copper. This makes the substrate to be effectively only as thick as the Copper used in the traces, and allows the final package to be as thin as 400μm. All previous FOWLP designs at ASE were able to be routed in a single layer using this new packaging technology . Since this uses existing high volume packaging infrastructures, more complex assemblies including multiple die, inclusion of passive components, and 3D structures can be easily implemented.
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Hanna, Amir, Arsalan Alam, G. Ezhilarasu, and Subramanian S. Iyer. "Fine Pitch(40μm) Integration Platform for Flexible Hybrid Electronics using Fan-Out Wafer-level Packaging." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000064–68. http://dx.doi.org/10.4071/2380-4505-2018.1.000064.
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Abstract A flexible fan-out wafer-level packaging (FOWLP) process for heterogeneous integration of high performance dies in a flexible and biocompatible elastomeric package (FlexTrateTM) was used to assemble 625 dies with co-planarity and tilt <1μm, average die-shift of 3.28 μm with σ < 2.23 μm. Fine pitch interconnects (40μm pitch) were defined using a novel corrugated topography to mitigate the buckling phenomenon of metal films deposited on elastomeric substrates. Corrugated interconnects were then used to interconnect 200 dies, and then tested for cyclic mechanical bending reliability and have shown less than 7% change in resistance after bending down to 1 mm radius for 1,000 cycles.
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Song, Kay, Zia Karim, Xinxuan Tan, Abhishek Bhat, Kenneth Sautter, A. Mingardi, and D. Vangoidsenhoven. "(Invited) Improvements in Thermal Budget and Film Properties Using Low Pressure Cure Technology for Advanced 3D Integration Packaging." ECS Meeting Abstracts MA2023-01, no. 29 (August 28, 2023): 1788. http://dx.doi.org/10.1149/ma2023-01291788mtgabs.
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3D advanced integration with Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP) offers multiple benefits: heterogenous chip design and stacking, increased interconnect density, and improved performance. However, it also brings new requirements for more compact form factors, low thermal budget materials and processing, and lower cost. The materials, process, and fabrication of heterogenous integration on redistribution layers (RDLs) consisting of metal and polymer dielectrics have become important enablers of the move to advanced packaging applications. To achieve the low-stress and low-cost benefits required by advanced integrated devices, thermal budgets must be reduced throughout the heterogenous integration flow -- including the dielectric curing step, which demands the use of low temperature processing and reduced cure times. In this presentation, the low temperature and low pressure thermal polymerization of dielectric polyimides used for redistribution layers (RDLs) is reviewed. Specifically, this presentation illustrates the significant impact of the low pressure cure process in reducing temperature (20° to 50° lower) and cure times (up to a 50% reduction) while providing better mechanical (elongation%, tensile strength, Young’s modulus), thermal (TG, Td 1%, Td 5%), and electrical (Dk, Df, dielectric breakdown strength - DBS) properties for different types of dielectric polyimides, including the Fujifilm LTC-9300 series, the Asahi BL-300 series, and the Toray LT-8300 and PW-1500 series. The post-curing polymerization ratio (FT-IR) and film stress were studied and are described. Finally, a proposed mechanism for the described dielectric polyimides’ polymerization under reduced pressure is discussed. Ongoing developments in design, materials, process and fabrication for FOWLP and FOPLP devices continue to drive progress in 3D heterogenous integration. This study of thermal processing of dielectric polyimides at low pressure and shorter time demonstrates a promising technique to improve overall process flow by reducing thermal budget, stress, and cost.
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Roshanghias, Ali, Ying Ma, Marc Dreissigacker, Tanja Braun, Christian Bretthauer, Karl-F. Becker, and Martin Schneider-Ramelow. "The Realization of Redistribution Layers for FOWLP by Inkjet Printing." Proceedings 2, no. 13 (December 13, 2018): 703. http://dx.doi.org/10.3390/proceedings2130703.
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The implementation of additive manufacturing technology (e.g., digital printing) to the electronic packaging segment has recently received increasing attention. In almost all types of Fan-out wafer level packaging (FOWLP), redistribution layers (RDLs) are formed by a combination of photolithography, sputtering and plating process. Alternatively, in this study, inkjet-printed RDLs were introduced for FOWLP. In contrast to a subtractive method (e.g., photolithography), additive manufacturing techniques allow depositing the material only where it is desired. In the current study, RDL structures for different embedded modules were realized by inkjet printing and further characterized by electrical examinations. It was proposed that a digital printing process can be a more efficient and lower-cost solution especially for rapid prototyping of RDLs, since several production steps will be skipped, less material will be wasted and the supply chain will be shortened.
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Hichri, Habib, William Vis, and Markus Arendt. "Optical Run-Out Correction for Improved Lithography Overlay Accuracy for FOWLP Applications." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000217–23. http://dx.doi.org/10.4071/2380-4505-2018.1.000217.
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Abstract Finer features sizes in advanced Wafer-level-packaging (WLP) processes create increasing demands to improve lithography equipment overlay control. The improvement goes beyond the inherent overlay capability of the equipment (“tool-to-itself”), but requires ways to compensate for mismatches in actual feature size and position on the wafer with respect to the photomask pattern. In Fan-Out wafer level packaging (FOWLP), error contributions from the die placement robot, and especially errors from expanding and shrinking mold compound in which the dies are embedded (magnification error), lead to undesirable errors in layer to layer overlay. Mask-less laser direct imaging (LDI) technologies or die-by-die alignment strategies on steppers can deal with these error contributions, but they cannot provide adequate throughput and have a high cost-of-ownership, and therefore offer a limited solution for the industry. An Active Optical Magnification Correction and Beam-Steering technology option has been developed, available on a full-field UV projection scanner tool. This option allows compensating any type of run-out or run-in up to +/− 200 ppm, or die shifts of +/− 30 μm on a 300 mm wafer, which corresponds to the amount of magnification error caused by the embedding of dies in mold compound nowadays. In addition, an additional optical asymmetrical correction function has been developed to compensate shifts of up to 50ppm in either X or Y. This paper will detail the principle and realization of this optical magnification correction technology. Performance data results for magnification error mitigation will be presented, and its effects on overlay, patterning performance, resolution, and throughput will be studied.
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Fowler, Michelle, John P. Massey, Matthew Koch, Kevin Edwards, Tanja Braun, Steve Voges, Robert Gernhardt, and Markus Wohrmann. "Advances in Temporary Bonding and Debonding Technologies for use with Wafer-Level System-in-Package (WLSiP) and Fan-Out Wafer-Level Packaging (FOWLP) Processes." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000051–56. http://dx.doi.org/10.4071/2380-4505-2018.1.000051.
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Abstract Today's complex fan-out wafer-level packaging (FOWLP) processes include the use of redistribution layers (RDL) and reconstituted wafers with epoxy mold compound (EMC) for use in heterogeneous integration [1]. Wafer-level system-in-package (WLSiP) uses fan-out wafer-level packaging (FOWLP) to build the system-in-package (SiP) by attaching know-good die (KGD) in a chip-first process to a tape laminated temporary carrier. If the dies are attached in a die-up configuration (active area facing up) and then over-molded with EMC, contact pads on the embedded die are exposed during the backside grind process. During the RDL build, the temporary carrier supplies mechanical support for the thinned substrate. In a die-down configuration with the active area facing down (eWLB), the temporary carrier is removed after the molding process thus exposing the contact pads for RDL build and solder ball mount. The ideal chip attachment scheme should minimize lateral movement of the die during over-mold (die shift) and also minimize vertical deformation of the bonding material. Thermal release tape provides a convenient way to attach die to a carrier prior to over-molding with EMC. However, not all bonding materials are suitable for presentation in tape form, so the material used in the tape may not be the optimal choice. An alternative method is to directly apply temporary bonding material to the carrier substrate. This enables the use of bonding materials with higher melt viscosity and improved thermal stability, resulting in less vertical deformation during die placement, and reduced die shift during over-molding. The bonding material will ideally have high adhesion to the EMC wafer to prevent delamination in the bond line during downstream processing. Stack stress and warpage is a major concern which causes handling and alignment problems during processing. The bonding material and carrier will need to be specifically suited to minimize the effects of stress in the compound wafer. Such material must balance rigidity with warp to prevent lateral die shift and deformation induced by coefficient of thermal expansion (CTE) mismatch between the carrier and EMC material [2]. Bonding materials must also have enough adhesion to the EMC material to overcome such stress without bond failure for an associated debond path (such as laser or mechanical release). In this experiment, we will examine a thermoplastic bonding material in combination with different release materials, addressing die shift, and deformation after EMC processing. Successful pairs will then undergo carrier release using either mechanical release or laser ablation release technology.
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Gongora, Eric, Elie Najjar, Thomas Richardson, Leo Linehan, and John Commander. "Cu Pillar, RDL and Via Fill Challenges facing FOWLP." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–18. http://dx.doi.org/10.4071/2017dpc-wp2_presentation5.
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The mobile market continues to push the limits of performance (electrical, power, thermal) and size. This paralleled with the challenges faced with continued wafer node reductions is driving the need for “More than Moore” through advanced vertical integration. One package form factor that has risen to meet these challenges and is being adopted by several end applications is the Fan Out Wafer Level Package (FO-WLP). This package is a modified version of standard Wafer Level Packages that provides a higher level of integration with an increased amount of I/Os. A variety of FOWLP packaging schemes are offered in the market (eWLB, InFO, SWIFT, etc.), each containing their own set of technical challenges (die first, die last, single RDL, multiple RDL layers, etc..). These challenges drive the need for optimized Cu, Sn, SnAg and Ni plating solutions for each package architecture, end application, die layout, plating tool, pillar construction, etc.. This presentation reviews the progression of Cu Pillars/Bumps, Redistribution Layers, and via fill requirements and how performance chemistry is being developed to meet these individualized needs.
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Yang, Jiajie, Lixin Xu, and Ke Yang. "Design and Optimization of a Fan-Out Wafer-Level Packaging- Based Integrated Passive Device Structure for FMCW Radar Applications." Micromachines 15, no. 11 (October 29, 2024): 1311. http://dx.doi.org/10.3390/mi15111311.
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This paper presents an integrated passive device (IPD) structure based on fan-out wafer-level packaging (FOWLP) for the front end of frequency-modulated continuous wave (FMCW) radar systems, focusing on enhancing the integration efficiency and performance of large passive components like antennas. Additionally, a new metric is introduced to assess this structure’s effect on the average noise figure in FMCW systems. Using this metric as a loss function, we apply the support vector machine (SVM) for electromagnetic simulation and the genetic algorithm (GA) for optimization. The sample fitting variance is 2.42 dB, reducing computation time from 12 min to under 1 millisecond, with the entire optimization completed in less than 100 s. The optimized IPD structure is 0.7 × 0.9 × 0.014 λ03 in size and achieves over 35 dB isolation between the transmitter and receiver. Compared to the IPD model calculated by empirical formulas, the optimized device lowers the average noise figure by 15.2 dB and increases maximum gain by 4.19 dB.
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Dreissigacker, Marc, Ole Hoelck, Joerg Bauer, Tanja Braun, Karl-Friedrich Becker, Martin Schneider-Ramelow, and Klaus-Dieter Lang. "A Numerical Study on Mitigation of Flying Dies in Compression Molding of Microelectronic Packages." Journal of Microelectronics and Electronic Packaging 16, no. 1 (January 1, 2019): 39–44. http://dx.doi.org/10.4071/imaps.763387.
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Abstract Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds depend on process conditions in a complex manner, such as shear-thinning behavior, which is superimposed by a time- and temperature-dependent conversion rate, both strongly affecting viscosity. The focus is set on forces exerted on individual dice during encapsulation in fan-out wafer-level packaging (FOWLP). The presented framework consists of an analytical approach to calculate the melt front velocity and simulations carried out to capture the nonlinear kinematics, chemorheology, and to extract forces exerted on individual dice. It offers separate evaluation of pressure and shear contributions for two cases, 0° and 45° between the dice' frontal area and the melt front. Process parameters, such as compression speed, thus cycle time, and process temperature, are determined to keep the forces on the dice below the critical level, where drag forces exceed adhesive forces. As a result, process parameters are determined to minimize flying dice and thereby maximize yield. The approach is easily transferable to arbitrary geometries and is therefore well suited to face the challenges that come with the current efforts toward the transition from FOWLP to larger substrates.
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Park, John. "The bifurcation of advanced packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000834–55. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_005.
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Following a similar trend from the 1990's, IC package design is experiencing a sea change. As a refresher, the 1990's is when the ball grid array (BGA) came along, introducing a whole new set of design tool requirements. The mechanical design tools used for the previous generation of lead frame styled packages were no longer capable of supporting the new design requirements of the BGA. In short, the BGA introduced multi-layer routable organic and ceramic substrates and new possibilities for stacking (and embedding) multi-die, requiring designers to abandon their mechanical design tools and look at new solutions for doing package design. On top of that, IO's were switching faster than ever, requiring engineers to look at new ways of electrically characterizing these designs. As a result, a couple of EDA companies stepped up and adapted their printed circuit board (PCB) layout and analysis tools for that generation of BGA-based advanced packaging. Problem (more or less) solved! Fast forward to today and we see a very similar trend. Now being introduced at a rapid pace, are new advanced IC packaging solutions that have a lot more silicon content, wafer stacking and, in some cases, chips being packaged directly at the wafer-level at traditional IC foundries, skipping the traditional OSAT model of the past. Make no mistake, this is a significant change to the status quo of BGA package design tools of the past. The PCB-like flows that were established for BGA design are likely not the path forward for technologies like, 2.5D/3D IC and fan-out wafer-level packaging (FOWLP). Instead, in all likelihood IC design tools and flows will need to be slightly adapted to support the next generation of package designs. Let's start with foundry-based FOWLP. In this case, induvial dice are placed on a chip-carrier with additional spacing between them. Molding is poured in the empty space and then an array of bumps (UBM) and the connectivity (RDL) are added. In foundry-based flows, these UBM and RDL layers require IC-styled routing/metal fill and mask generation from the layout tool. In addition, these masks must be verified with traditional IC DRC/LVS tools. It's clear that some kind of hybrid advanced packaging flow using some traditional IC tools in the flow is required to support this type of design. And in fact, if you look at the largest semiconductor foundries reference flow tools, you will find this to be true. This presentation further examines the design tool/flow requirement for FOWLP, 2.5D/3D IC and future multi-die packaging technologies.
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Ali, Burhan, and Mike Marshall. "Automated Optical Inspection (AOI) for FOPLP with Simultaneous Die Placement Metrology." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000203–10. http://dx.doi.org/10.4071/2380-4505-2019.1.000203.
Full textAbstract:
Abstract As the final step of IC fabrication, packaging is the process to encapsulate the chip and provide the interconnections for the I/O of the final form factor. The demand for increasingly higher I/O density, shrinking device size and lower cost that drive wafer processing also apply to the packaging process. Various technologies have been developed in order to achieve these goals with most of them being wafer-level packaging (WLP). Unlike traditional packaging process, most I/O interconnections are done at the wafer-level with redistribution layers (RDLs). RDLs are the layer where copper lines and vias form the electrical connections. Depending on the applications' market such as mobile, memory or the Internet of Things (IoT), fan-out wafer level packaging (FOWLP) provides the most promising method to support the I/O density requirements and fine RDL line/space. Moreover, fan-out panel level packaging (FOPLP) was also developed in order to capitalize on economies of scale and optimize substrate utilization. In this technology, a rectangular substrate is used in the process instead of a round-shape substrate like a wafer. Processes and equipment have long been developed for the wafer substrate market, but the previous developments cannot be directly applied to panel substrates. For instance, in the wafer line, spin on processes are very prevalent but these are not at all practical for a panel line. Some capital equipment manufacturers have been reluctant to embrace panel-level manufacturing due to the uncertainty as to whether it will prevail. Struggles with yield have been very common; some of which are due to die placement and others due to the lack of process control capabilities. With the explosion and adoption of FOWLP to enhance package shrinkage and performance the panel market becomes more and more viable. The companies that have embraced panel level manufacturing from the beginning have a distinct advantage due to their intimate knowledge and experience with the substrates as well as the relationship developed with capital equipment suppliers to develop the necessary technology in order to process the panels. However, there is still a great need to ensure the product mix deployed in panel form can have an acceptable yield; automated optical inspection and die placement metrology bridge that gap. Automated optical inspection allows for defect detection with traditional bright field (BF) or dark field (DF) illumination and also a new novel illumination technique that enables the detection of organic particles and/or residues that are often used in panel-level packaging processes. A system capable of macro defect detection with sub-micron capabilities allows for multi-purpose panel inspections. The system is also equipped with metrology capabilities for critical dimension and die placement measurements which meet the process node dimensional requirements. These features allow for process control of pick and place, overlay as well as feed-forward capabilities for die placement corrections. In a FOWLP/FOPLP process, chip first and chip last can be concluded among all available methods in the market. Die placement either start from the initial phase of the process or in the final phase of the process. In the chip first scenario, the chips are placed on a carrier by a pick-and-place system and then followed by an encapsulating molding process to reconstitute a substrate (reconstituted wafer or reconstituted panel). At this point a semi-additive process (SAP) is typically followed which includes a photo resist layer being coated, exposed and developed following copper (Cu) plating in order to form the redistribution layer. In this workflow, the die position are dominated by the accuracy of the pick-and-place tool and coefficient of thermal expansion (CTE) mismatch of the molding material and carrier. The trade-off between throughputs, placement accuracy and a feedback mechanism is the main impact from the pick-and-place tool in this process step. This affects both the chip first and chip last scenarios. The thermal expansion of the molding process not only adds additional die shift but also causes warpage of the reconstituted substrate that becomes an issue for automated handling systems and local process variation. Therefore, to know the actual die position and orientation after the die placement and molding process is crucial for matching with the following redistribution layers development. In one scenario it is possible to utilize the lithography system to perform die position metrology, however, this is time consuming and impacts the cost of ownership and overall throughput for the lithography process. A solution to this problem is provided by implementation of an optical metrology system. Since this information needs to be passed to the lithography tool in a usable manner for variable exposure positioning, the alignment of the stage coordinate system between the die metrology tool and lithography tool is a key point to ensure the correctness of the feed forward loop. For RDL development overlay between die and RDL via directly impact yield and are just as critical to the process as defect inspection and critical dimension measurements. Based on the corrections for each die, a yield prediction can be made and provides different strategies for the lithography tool's exposure field in order to balance throughput and exposure yield rate. In this paper, we demonstrate a solution using an automatic optical inspection (AOI) system to perform the die metrology for chip placement and RDL development in FOPLP and FOWLP. This includes die shift, die rotation, RDL inspection as well as the overlap between a reconstituted substrate and RDLs. This solution provides comprehensive coverage for packaging process control and significantly impacts yield optimization and throughput enhancement. With a multifunctional AOI system, it also reduces the cost of ownership for packaging processes.
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Chylak, Bob, Horst Clauberg, and Tom Strothmann. "Assembly Equipment Requirements for Next Generation Advanced Packaging." International Symposium on Microelectronics 2016, no. 1 (October 1, 2016): 000321–25. http://dx.doi.org/10.4071/isom-2016-wp35.
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Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.
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Mauer, Laura, John Taddei, and Scott Kroeger. "Wafer Thinning for Advanced Packaging Applications." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–26. http://dx.doi.org/10.4071/2017dpc-wp2_presentation1.
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Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.
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Barbara, Bruce J. "The Package Becomes the System." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–36. http://dx.doi.org/10.4071/2017dpc-wp1_presentation1.
Full textAbstract:
The benefits of system miniaturization lower-cost, higher electrical performance and better thermal mechanical reliability, than the current approach of discrete component packaging have been discussed at length. Several technologies have been used to address these benefits. SOC, SiP, Fan-In and Fan Out and wafer level packages. Recently there has been much discussion about Fan Out Wafer Level packaging (FOWLP) to integrate the entire system in package. However, actual implementations fall short of a complete system in a package in that only few of the chips and some passives are currently integrated into the FOWLP. But what about the rest of the system? A true system also requires additional components not traditionally considered integrate-able into a package. These include antennas, batteries, thermal structures, RF, Optical, micro-electromechanical systems (MEMs), and micro sensor functions. The current FOWLP package technology as discussed by the media falls short of this type of system integration due to limitations in the number of chips that can be integrated and the lack of sufficient interconnect layers to support these functions in a system. 3D stacking has also been employed to improve the SiP by adding memory components. These implementations are limited to stacking of identical chips with through hole silicon vias (TSV) located remotely from any circuitry. Aurora Semiconductor will introduce a packaging technology where the package becomes the system. We call this technology 4DHSiP™ or 4D Heterogeneous System in package. 4DHSiP™ is a system miniaturization technology in contrast to system on chip (SOC) at the integrated circuit level and system in package stacked ICs and packages (SIP) at the module level. 4DHSiP™ is considered an inclusive system technology in which, SIP, thermal structures and batteries are considered as substantive technologies. 3D stacking is no longer limited by the location of the TSV within the stacked components. Heterogeneous multi-chip sub module layers can be stacked to accommodate additional system components. These layers, when interconnected, form the entire system. By stacking sub module layers, specific component types can be located on the top most layer as needed by specific function (e.g. Bio functions, Optical functions, Antennas). An example of this type of module stacking used to create an optical based system will be shown.4DHSiP™ is a new, emerging system concept where the device, package, and system board are miniaturized into a single system package including all the needed system functions. Such a single system package with multiple heterogeneous ICs provides all the system functions by co-design and fabrication of digital, radiofrequency (RF), optical, micro-electromechanical systems (MEMS) in either the IC or the system package. 4DHSiP™ combines the best on chip and off chip integration technologies to develop ultra-miniaturized, high-performance, multifunctional products. A significant benefit of this miniaturization is the elimination of multiple sockets and connectors currently used to connect sub-systems together. This ultra-miniaturization of multiple to mega functions, ultrahigh performance, low cost and high reliability will be the way systems are designed in the future to achieve More than Moore.
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Beyer, Gerald, Kenneth Rebibis, Arnita Podpod, Francisco Cadacio, Teng Wang, Andy Miller, and Eric Beyne. "Packaging and Assembly Challenges for 2.5D/3D Devices." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2016, DPC (January 1, 2016): 001161–91. http://dx.doi.org/10.4071/2016dpc-wp11.
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The continuous development of 2.5D/3D packaging and stack assembly technologies has enabled different ways of producing advanced packages for the said devices. Advancement in D2D, D2W and W2W bonding have allowed these devices to be a step closer to being fully manufactured in volume. Thermo-compression bonding (TCB) process in combination with a pre-applied underfill material (WLUF/NUF) have been developed and investigated for assembling 2.5D and 3D devices with fine pitch (10μm - 40 μm) μbumps. This assembly step though developed, is not without challenges. There is a need to select the right underfill material based on its mechanical and chemical properties which could contribute to issues such as die warping, voiding and non-wetting of μbumps. These materials should also be able to withstand several thermal steps within the entire stack assembly process and is able to pass reliability testing. During the TCB process, bonding forces have a profound impact on the joint formation behavior on the μbumps. A low bonding force could produce a joint formation with a lot of underfill filler entrapment and an incomplete reaction of the solder. A higher bonding force leads to more solder squeezing-out, leaving a thin and completely reacted intermetallic compound (IMC) layer in the joints. The D2D, D2W and W2W assembled chips can then be packaged into a standard flip chip component using laminate BGA substrates. But even with this volume manufacturing process, the introduction of 2.5D/3D stack devices brings another set of challenges to an existing assembly infrastructure. Challenges such as the handling of the stacked devices, the CTE mismatches of an entirely new set of materials and the constant scaling in FC bump (Cu Pillar or C4) pitches in an existing infrastructure remain. The limitations of organic BGA packages in terms of CTE mismatches and costs gave rise to Fan-out Wafer Level Packages (FOWLP) or a technique also known as wafer reconstruction. However, there are certain tradeoffs particularly in the molding process step of fully D2W stacked or reconstructed 300 mm wafers. Molding such a large area of stacked chips with very narrow gaps of around 50μm to 300μm is a major challenge especially in trying to maintain the flatness of the wafer for succeeding wafer level processing steps. The large warpage of over molded (D2W or reconstructed) wafers is due to the coefficient of thermal expansion (CTE) mismatch between silicon and the reconstruction material. Therefore careful selection of materials and design of reconstructed structures is needed. Other techniques to keep the D2W or reconstructed assemblies are being developed and evaluated. Also by selecting an FOWLP or reconstructed wafer type of package, the integration of temporary bonding materials (TBMs) in TCB and wafer molding becomes a challenge. In order to produce the reconstructed wafer or the thinned D2W assembly, thermal and mechanical stability is required for such a material. In summary, the combination of advance stacking techniques and materials within certain 2.5D/3D integration flows could produce a low-cost and reliable 3D package. But these combinations will pose a number of challenges that needs to be addressed. This paper will discuss the different integration flows, stacking and packaging assembly techniques (and their challenges) that could make volume manufacturing possible for 2.5D/3D devices in the future.
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Hübner, Henning, Christian Ohde, and Dirk Ruess. "Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost." International Symposium on Microelectronics 2018, no. 1 (October 1, 2018): 000037–42. http://dx.doi.org/10.4071/2380-4505-2018.1.000037.
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Abstract Electrolytic metal deposition is a key process step in the manufacturing of vertical and horizontal interconnections used in today's PCBs and IC substrates on one hand and advanced packaging applications on the other hand. Historically both application areas were clearly defined and separated by different requirements in feature sizes and substrate formats. PCBs and IC substrates were based on organic large scale substrates with rather large features while advanced packaging technology is wafer based with the capability to incorporate fine features down to a few microns. The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. As a consequence both areas are currently merging while creating a new application segment. This segment combines the request of small feature sizes with the manufacturability on large scale substrates. Obviously many of the traditional process technologies like plating and available equipment cannot be easily adopted and need certain developments, adaptions and improvements. In this respect, a key challenge in the area of electrolytic metal deposition is the combination of various challenging requirements: creation of feature sizes down to 2μm L/S with heterogeneous feature density on large substrates up to 600mm at excellent metal thickness uniformity and high plating speed. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes. Finally latest test results of optimized process conditions will be discussed in detail with different feature sizes providing data of within die and within substrate uniformity. All tests are done on panel level, both organic and glass substrates. The latest findings and achievements of the discussed panel based plating process technology will support the industry to develop panel based packaging processes that meet both technical and commercial requirements.
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Pinto, Raquel, André Cardoso, Sara Ribeiro, Carlos Brandão, João Gaspar, Rizwan Gill, Helder Fonseca, and Margaret Costa. "Application of SU-8 photoresist as a multi-functional structural dielectric layer in FOWLP." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–19. http://dx.doi.org/10.4071/2017dpc-tp2_presentation3.
Full textAbstract:
Microelectromechanical Systems (MEMS) are a fast growing technology for sensor and actuator miniaturization finding more and more commercial opportunities by having an important role in the field of Internet of Things (IoT). On the same note, Fan-out Wafer Level Packaging (FOWLP), namely WLFO technology of NANIUM, which is based on Infineon/ Intel eWLB technology, is also finding further applications, not only due to its high performance, low cost, high flexibility, but also due to its versatility to allow the integration of different types of components in the same small form-factor package. Despite its great potential it is still off limits to the more sensitive components as micro-mechanical devices and some type of sensors, which are vulnerable to temperature and pressure. In the interest of increasing FOWLP versatility and enabling the integration of MEMS, new methods of assembling and processing are continuously searched for. Dielectrics currently used for redistribution layer construction need to be cured at temperatures above 200°C, making it one of the major boundary for low temperature processing. In addition, in order to accomplish a wide range of dielectric thicknesses in the same package it is often necessary to stack very different types of dielectrics with impact on bill of materials complexity and cost. In this work, done in cooperation with the International Iberian Nanotechnology Laboratory (INL), we describe the implementation of commercially available SU-8 photoresist as a structural material in FOWLP, allowing lower processing temperature and reduced internal package stress, thus enabling the integration of components such as MEMS/MOEMS, magneto-resistive devices and micro-batteries. While SU-8 photoresist was first designed for the microelectronics industry, it is currently highly used in the fabrication of microfluidics as well as microelectromechanical systems (MEMS) and BIO-MEMS due to its high biocompatibility and wide range of available thicknesses in the same product family. Its good thermal and chemical resistance and also mechanical and rheological properties, make it suitable to be used as a structural material, and moreover it cures at 150°C, which is key for the applications targeted. Unprecedentedly, SU-8 photoresist is tested in this work as a structural dielectric for the redistribution layers on 300mm fan-out wafers. Main concerns during the evaluation of the new WLFO dielectric focused on processability quality; adhesion to multi-material substrate and metals (copper, aluminium, gold, ¦); between layers of very different thicknesses; and overall reliability. During preliminary runs, processability on 300 mm fan-out wafers was evaluated by testing different coating and soft bake conditions, exposure settings, post-exposure parameters, up to developing setup. The outputs are not only on process conditions and results but also on WLFO design rules. For the first time, a set of conditions has been defined that allows processing SU-8 on WLFO, with thickness values ranging from 1 um to 150 um. The introduction of SU-8 in WLFO is a breakthrough in this fast-growing advanced packaging technology platform as it opens vast opportunities for sensor integration in WLP technology.
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Hichri, Habib, Shohei Fujishima, Seongkuk Lee, Markus Arendt, and Shigeo Nakamura. "Fine Line Routing and Micro via Patterning in ABF Enabled by Excimer Laser Ablation." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000113–19. http://dx.doi.org/10.4071/isom-2017-tp44_011.
Full textAbstract:
Abstract Fan-Out technologies continue to be the main driver for advanced packaging, be it on wafer level (FOWLP) or panel level (FOPLP). There is a continuing need for higher density routing and heterogeneous integration of different devices, but also for continuous cost reduction. While traditional organic flip-chip substrates using semi-additive processes (SAP) have not been able to scale to ultra-fine RDL pitches and via opening below 10um, photo-sensitive spin-on dielectrics and RDL processes used for wafer level packaging do not sufficiently address the cost reduction need, and also face serious technical challenges. This paper presents the latest results from an innovative package RDL and micro via processes using excimer laser ablation in an especially developed non-photo sensitive material, to meet the market's most stringent requirements. To enable panel and wafer based interposers to reduce RDL cost and scale interconnect pitch to 40um and below, excimer laser ablation is introduced as a direct patterning process that uses proven industrialized excimer laser sources to emit high-energy pulses at short wavelengths to remove polymer materials with high precision and high throughput. The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet-processing. With excimer laser patterning technology the industry gains a much wider choice of dielectric materials (photo and non-photo) to help achieve further reductions in manufacturing costs as well as enhancements in interposer and package performance. In this paper, we propose a novel patterning process that uses excimer laser ablation to integrate via and RDL traces in one patterning step, followed by seed layer deposition, plating and planarization. The capability of this excimer laser patterning process in non-photo materials Ajinomoto Build-up Film, which is abbreviated to “ABF” in this paper, will be discussed, and its technical robustness and commercial advantages are demonstrated. We will present electrical and reliability data of Via and RDL traces patterned by excimer laser in ABF material.
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Prenger, Luke, Xiao Liu, Qi Wu, and Rama Puligadda. "Material Design Advancement Create Multifunctional Materials for Single-Layer Bonding and Debonding." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2019, DPC (January 1, 2019): 000908–31. http://dx.doi.org/10.4071/2380-4491-2019-dpc-presentation_wp1_046.
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Multifunctional materials are a relatively new topic in the semiconductor industry for wafer-level packaging (WLP). With the increase in processing steps and the emergence of more advanced technologies, the use of multifunctional materials will become a more integral part in the future of temporary bonding and debonding (TB/DB) as well as other advanced packaging applications. One approach to multifunctional material design incorporates adhesive and laser release attributes in one material layer. Although this is similar to a thermal release material, it has greater thermal capabilities due to its ability to be cured and undergo laser debond. Many advantages may be obtained by combining a curable adhesive and laser release layer into one material. One of the greatest advantages is the reduction in overall processing time and steps required to bond wafer pairs as well as the reduction of chemical waste, due to the use of one material compared to two or more materials which significantly reduces the cost of ownership. Curable adhesive single layer systems offer access to higher temperatures with less material flow from the curable layer, strong adhesion for high stress applications where wafers can delaminate or spontaneously debond when using multilayer mechanically debonding systems such as Fan-Out Wafer Level Packaging (FOWLP), and offer lower wafer stress and warpage due to fewer material interfaces within the bonded wafer pairs causing less potential mismatch of materials coefficient of thermal expansion(CTE). Some challenges with this concept stem from the concern of the cleanability of a curable layer and potential laser damage to the device. In order to wet clean a curable layer, which is usually very solvent resistant due to the crosslinked nature, requires harsh solvent based solutions (that may contain either strong acid or base, require long cleaning time, and high temperature). This study will address all of the aforementioned challenges and includes the developmental advancements in material designs that resulted in the creation of new multifunctional materials. These multifunctional materials have been designed to be thermally curable, prevent material reflow of the bonding layer at higher temperatures, while still remaining wet cleanable without the use of harsh chemicals and long times. As with any material that utilize laser release methods there are concerns about device damage from laser energy penetrating to the device but multifunctional materials address this in two ways: they offer high absorbance of the laser energy at all commercially available laser tool wavelengths and they can be utilized as a thicker film as they act as the bonding layer as well. By overcoming their challenges, they will minimize the cost of ownership while driving advancement in future materials and processing.
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Xu, Cheng, Z. W. Zhong, and W. K. Choi. "Evaluation of fan-out wafer level package strength." Microelectronics International 36, no. 2 (April 1, 2019): 54–61. http://dx.doi.org/10.1108/mi-06-2018-0040.
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Purpose The fan-out wafer level package (FOWLP) becomes more and more attractive and popular because of its flexibility to integrate diverse devices into a very small form factor. The strength of ultrathin FOWLP is low, and the low package strength often leads to crack issues. This paper aims to study the strength of thin FOWLP because the low package strength may lead to the reliability issue of package crack. Design/methodology/approach This paper uses the experimental method (three-point bending test) and finite element method (ANSYS simulation software) to evaluate the FOWLP strength. Two theoretical models of FOWLP strength are proposed. These two models are based on the location of FOWLP initial fracture point. Findings The results show that the backside protection tape does not have the ability to enhance the FOWLP strength, and the strength of over-molded structure FOWLP is superior to that of other structure FOWLPs with the same thickness level. Originality/value There is ample research about the silicon strength and silicon die strength. However, there is little research about the package level strength and no research about the FOWLP strength. The FOWLP is made up of various materials. The effect of individual component and external environment on the FOWLP strength is uncertain. Therefore, the study of strength behavior of FOWLP is significant.
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Ogura, Nobuo, Siddharth Ravichandran, Tailong Shi, Atom Watanabe, Shuhei Yamada, Mohanalingam Kathaperumal, and Rao Tummala. "First Demonstration of Ultra-Thin Glass Panel Embedded (GPE) Package with Sheet Type Epoxy Molding Compound for 5G/mm-wave Applications." International Symposium on Microelectronics 2019, no. 1 (October 1, 2019): 000202–7. http://dx.doi.org/10.4071/2380-4505-2019.1.000202.
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Abstract With the number of connected-devices increasing tremendously, communication data rates are projected to be at least 10–100X in the 5G/mm-wave (MMW) technology - much higher than the existing 4G LTE connections.[1], [2] To catch up with the trend, novel packaging technology in the MMW frequency range is required, which will address fundamental MMW technical challenges such as high dielectric loss, degradation of quality factors in passives, increased parasitic, dramatically-enhanced electromagnetic interference, and the reduced radiation efficiency of antenna arrays. State-of-the-art approaches being pursued include organic-core substrates that have a low dielectric constant (Dk) and low dissipation factor (Df) such as fluorine based or liquid-crystal polymer (LCP) substrates in order to achieve enhanced antenna performance and low signal dissipations. These organic-based substrate technologies, however, can neither miniaturize packages nor handle precision signal routings that enable high density packages. To address these challenges, attention is focused on Fan-Out Wafer Level Package (FOWLP) technologies, like eWLB, InFO, and SWIFT, where integrated circuits (ICs) are embedded in epoxy molding compound. [3]–[6] Recently, glass-panel embedding (GPE) technology is emerging as an ideal packaging methodology that enables superior performance along with small form factor, ultra-low-loss, high density, ultra-short interconnects, and low cost. [7] These benefits stem from the advantages of using glass which has excellent properties such as ultra-smooth surface for precision redistribution layer (RDL), exceptional dimensional stability for panel-scalability and tailorability of CTE that allow direct board-attach for improved system performance. In addition, utilizing the epoxy molding compounds as encapsulation material allows the GPE package to be thinner and more robust package with small farm factor. Molding of glass cavity panels also helps with the handling of ultra-thin glass which is seen as a bottleneck towards glass based packaging solutions in production. These facilitates enhanced throughput by allowing more cavity cut outs (more coupons) per panel. This paper presents the first demonstration of ultra-thin GPE with sheet type epoxy molding compound (SMC) for 5G/mm-wave applications. First part of this paper discusses the process-flow used in glass-panel embedding with laminated SMC, including chip placement in glass cavities, lamination of SMC, and the reliability of the package architecture. This paper reports on such a demonstration in 60 μm glass substrates with 40 μm thickness SMC. The second part of this paper focuses on low-loss interconnects for 5G/mm-wave applications and presents the process development of signal routings such as transmission lines and microvias in RDLs as well as through-package vias (TPVs) with via-in-via process. The results suggest that the ultra-thin GPE architecture is a promising packaging technology solution for a variety of applications including high-frequency communications and high-performance computing.
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Ishibashi, Daijiro, and Yoshihiro Nakata. "Planar Antenna for Terahertz Application in Fan Out Wafer Level Package." International Symposium on Microelectronics 2017, no. 1 (October 1, 2017): 000599–603. http://dx.doi.org/10.4071/isom-2017-tha43_115.
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Abstract This paper shows the terahertz planar antenna integration module structure using a fan out wafer level package (FOWLP), and the important parameters when that structure is designed. A FOWLP enabled a low-loss connection. Embedding an insulator and reflector into the mold resin improved flexibility of the module design. In this paper, the patch antenna was employed as a planar antenna in a proposed structure, and that antenna was operated at 300 GHz. For the design of this structure, two parameters were noted as the most important factors. One was the thickness of the insulator of the patch antenna. The optimal thickness of between 40 μm and 80 μm allowed the radiation efficiency to remain high. The other factor was the gaps of the vias between the ground of the microstrip line and the reflector. The gaps of a quarter-wavelength or less made the antenna characteristics excellent.
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Lujan, Amy. "Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–37. http://dx.doi.org/10.4071/2017dpc-ta2_presentation3.
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In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.
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Yoon, Hyung Seok, and Insu Jeon. "Verification of Faulty Mechanism for Fan-Out Wafer Level Package Using Numerical Analysis." Applied Mechanics and Materials 789-790 (September 2015): 609–12. http://dx.doi.org/10.4028/www.scientific.net/amm.789-790.609.
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The manufactures of the ultra-thin and smaller semiconductor chip are required over the portable electric devices. The investigation of Fan-out wafer level package (FOWLP) is used widely, among the performance improvement and miniaturization technologies. In this paper, we obtained lots of crack near the passivation (PSV) and redistributed layer (RDL) region of FOWLP during the reliability evaluation of thermal cycling test (TCT). The generated stress and deformational behavior was observed through 2D finite-element analysis. The concentrated stress and deformational behavior are observed around the Solder ball edge and RDL & PSV edges. The crack was observed experimentally as well. The verification of the mechanism for crack generation and the validity of the finite-element analysis were verified by the structural analysis.
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Teixeira, Jorge, Mário Ribeiro, and Nélson Pinho. "Advanced warpage characterization for FOWLP." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000641–46. http://dx.doi.org/10.4071/isom-2013-wp21.
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Current standards for silicon wafers shape characterization use simple metrics. Warpage and bow are computed as the mean surface wafer height range or the mean surface wafer center height, respectively [1]. These metrics are valid for silicon wafers because of their homogenous and linear thermomechanical properties [2]. In fan-out wafer level package (FO-WLP), embedded Wafer Level Ball Grid Array in specific (eWLB), the use of epoxy mold compound that works both as the physical carrier of the dies and as the base of second level connections has a major impact on the overall macroscopic behavior of the wafer, inducing shapes that do not follow a simple bended or bowed wafer, impacting wafer processability [3]. Warped wafers can affect device performance, reliability, and linewidth control in various processing steps [3]. Early detection will minimize cost and processing time. In our research, we present a solution for wafer characterization in FO-WLP by increasing the information vector that one obtains from standard automated non-contact scanning equipment. For this, we defined wafer shape and wafer ratio as the two new metrics besides warpage, creating a three dimensional vector that can be used to compare and evaluate wafers in high volume production or even single wafer analysis. This is a major improvement over previously used approaches, in which only the average warpage is considered. These metrics were determined by the developed numeric algorithm and their validity was demonstrated through the use of different production conditions, wafer constructions and production monitoring. The proposed approach requires no extra processing steps and time, as compared to conventional off-line methods. Experimental results demonstrate its feasibility and repeatability. This methodology was successfully used in the field and proved to be of high value when evaluating wafer geometrical requirements for both product development and process monitoring.