Relevant bibliographies by topics / Execution thread

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Execution thread'

Author: Grafiati
Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "Execution thread"

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Chen, Caisen, Yangxia Xiang, Yuqin DengLiu, and Zeyun Zhou. "Research on Cache Timing Attack Against RSA with Sliding Window Exponentiation Algorithm." International Journal of Interdisciplinary Telecommunications and Networking 8, no. 2 (2016): 88–95. http://dx.doi.org/10.4018/ijitn.2016040108.

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The vulnerabilities of the RSA cryptographic algorithm are analyzed, and it is not securely implemented. As the simultaneous multithreading could enable multiple execution threads to share the execution resources of a superscalar between the chipper process and the spy process, the shared access to memory caches provides an easily used high bandwidth covert channel between threads, allowing that a malicious thread can monitor the execution of another thread. This paper targets at RSA algorithm which is implemented with sliding window exponentiation algorithm via OpenSSL, the attacker can monitor the cryptographic thread by executing a spy thread, recording the timing characteristic during the RSA decryption when reading the Cache. The attacker can recover the original key via analyzing these timing measurements. Finally, the authors provide some countermeasures of how this attack could be mitigated or eliminated entirely.
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Hamidi, Beqir, and Lindita Hamidi. "Synchronization Possibilities and Features in Java." European Journal of Interdisciplinary Studies 1, no. 1 (2015): 75. http://dx.doi.org/10.26417/ejis.v1i1.p75-84.

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In this paper we have discussed one of the greatest features of the general purpose computer programming language –Java. This paper represents concepts of Synchronization possibilities and features in Java. Today's operating systems support concept of "Multitasking". Multitasking achieved by executing more than one task at a same time. Tasks runs on threads. Multitasking runs more than one task at a same time. Multitasking which means doing many things at the same time is one of the most fundamental concepts in computer engineering and computer science because the processor execute given tasks in parallel so it makes me think that are executing simultaneously. Multitasking is related to other fundamental concepts like processes and threads. A process is a computer program that is executing in a processor, while a thread is a part of a process that has a way of execution: it is a thread of execution. Every process has at least one thread of execution. There are two types of multitasking: process – based and thread – based. Process-based multitasking, means that on a given computer there can be more than one program or process that is executing, while thread-based multitasking, which is also known as multithreading, means that within a process, there can be more than one thread of execution, each of them doing a job and so accomplishing the job of their process. When there are many processes or many threads within processes, they may have to cooperate with each other or concurrently try to get access to some shared computer resources like: processor, memory and input/output devices. They may have to, for example: print a file in a printer or write and/or read to the same file. We need a way of setting an order, where processes and/or threads could do their jobs (user jobs) without any problem, we need to synchronize them. Java has built-in support for process and thread synchronization, there are some constructs that we can use when we need to do synchronization.This paper, a first phase discussed the concept of Parall Programming, threads, how to create a thread, using a thread, working with more than one thread. Second phase is about synchronization, what is in general and in the end we disscused the synchronization possibilities and feautures in Java.
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Ramanauskaite, Simona, Asta Slotkiene, Kornelija Tunaityte, Ivan Suzdalev, Andrius Stankevicius, and Saulius Valentinavicius. "Reducing WCET Overestimations in Multi-Thread Loops with Critical Section Usage." Energies 14, no. 6 (2021): 1747. http://dx.doi.org/10.3390/en14061747.

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Worst-case execution time (WCET) is an important metric in real-time systems that helps in energy usage modeling and predefined execution time requirement evaluation. While basic timing analysis relies on execution path identification and its length evaluation, multi-thread code with critical section usage brings additional complications and requires analysis of resource-waiting time estimation. In this paper, we solve a problem of worst-case execution time overestimation reduction in situations when multiple threads are executing loops with the same critical section usage in each iteration. The experiment showed the worst-case execution time does not take into account the proportion between computational and critical sections; therefore, we proposed a new worst-case execution time calculation model to reduce the overestimation. The proposed model results prove to reduce the overestimation on average by half in comparison to the theoretical model. Therefore, this leads to more accurate execution time and energy consumption estimation.
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Karasik, O. N., and A. A. Prihozhy. "ADVANCED SCHEDULER FOR COOPERATIVE EXECUTION OF THREADS ON MULTI-CORE SYSTEM." «System analysis and applied information science», no. 1 (May 4, 2017): 4–11. http://dx.doi.org/10.21122/2309-4923-2017-1-4-11.

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Three architectures of the cooperative thread scheduler in a multithreaded application that is executed on a multi-core system are considered. Architecture A0 is based on the synchronization and scheduling facilities, which are provided by the operating system. Architecture A1 introduces a new synchronization primitive and a single queue of the blocked threads in the scheduler, which reduces the interaction activity between the threads and operating system, and significantly speed up the processes of blocking and unblocking the threads. Architecture A2 replaces the single queue of blocked threads with dedicated queues, one for each of the synchronizing primitives, extends the number of internal states of the primitive, reduces the inter- dependence of the scheduling threads, and further significantly speeds up the processes of blocking and unblocking the threads. All scheduler architectures are implemented on Windows operating systems and based on the User Mode Scheduling. Important experimental results are obtained for multithreaded applications that implement two blocked parallel algorithms of solving the linear algebraic equation systems by the Gaussian elimination. The algorithms differ in the way of the data distribution among threads and by the thread synchronization models. The number of threads varied from 32 to 7936. Architecture A1 shows the acceleration of up to 8.65% and the architecture A2 shows the acceleration of up to 11.98% compared to A0 architecture for the blocked parallel algorithms computing the triangular form and performing the back substitution. On the back substitution stage of the algorithms, architecture A1 gives the acceleration of up to 125%, and architecture A2 gives the acceleration of up to 413% compared to architecture A0. The experiments clearly show that the proposed architectures, A1 and A2 outperform A0 depending on the number of thread blocking and unblocking operations, which happen during the execution of multi-threaded applications. The conducted computational experiments demonstrate the improvement of parameters of multithreaded applications on a heterogeneous multi-core system due the proposed advanced versions of the thread scheduler.
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Metzler, Patrick, Neeraj Suri, and Georg Weissenbacher. "Extracting safe thread schedules from incomplete model checking results." International Journal on Software Tools for Technology Transfer 22, no. 5 (2020): 565–81. http://dx.doi.org/10.1007/s10009-020-00575-y.

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Abstract Model checkers frequently fail to completely verify a concurrent program, even if partial-order reduction is applied. The verification engineer is left in doubt whether the program is safe and the effort toward verifying the program is wasted. We present a technique that uses the results of such incomplete verification attempts to construct a (fair) scheduler that allows the safe execution of the partially verified concurrent program. This scheduler restricts the execution to schedules that have been proven safe (and prevents executions that were found to be erroneous). We evaluate the performance of our technique and show how it can be improved using partial-order reduction. While constraining the scheduler results in a considerable performance penalty in general, we show that in some cases our approach—somewhat surprisingly—even leads to faster executions.
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YONG, XIE, and HSU WEN-JING. "ALIGNED MULTITHREADED COMPUTATIONS AND THEIR SCHEDULING WITH PERFORMANCE GUARANTEES." Parallel Processing Letters 13, no. 03 (2003): 353–64. http://dx.doi.org/10.1142/s0129626403001331.

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This paper considers the problem of scheduling dynamic parallel computations to achieve linear speedup without using significantly more space per processor than that required for a single processor execution. Earlier research in the Cilk project proposed the "strict" computational model, in which every dependency goes from a thread x only to one of x's ancestor threads, and guaranteed both linear speedup and linear expansion of space. However, Cilk threads are stateless, and the task graph that Cilk language expresses is series-parallel graph, which is a proper subset of arbitrary task graph. Moreover, Cilk does not support applications with pipelining. We propose the "aligned" multithreaded computational model, which extends the "strict" computational model in Cilk. In the aligned multithreaded computational model, dependencies can go from arbitrary thread x not only to x's ancestor threads, but also to x's younger brother threads, that are spawned by x's parent thread but after x. We use the same measures of time and space as those used in Cilk: T1 is the time required for executing the computation on 1 processor, T∞ is the time required by an infinite number of processors, and S1 is the space required to execute the computation on 1 processor. We show that for any aligned computation, there exists an execution schedule that achieves both efficient time and efficient space. Specifically, we show that for an execution of any aligned multithreaded computation on P processors, the time required is bounded by O(T1/P + T∞), and the space required can be loosely bounded by O(λ·S1P), where λ is the maximum number of younger brother threads that have the same parent thread and can be blocked during execution. If we assume that λ is a constant, and the space requirements for elder and younger brother threads are the same, then the space required would be bounded by O(S1P). Based on the aligned multithreaded computational model, we show that the aligned multithreaded computational model supports pipelined applications. Furthermore, we propose a multithreaded programming language and show that it can express arbitrary task graph.
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Hirata, Hiroaki, and Atsushi Nunome. "Decoupling Computation and Result Write-Back for Thread-Level Parallelization." International Journal of Software Innovation 8, no. 3 (2020): 19–34. http://dx.doi.org/10.4018/ijsi.2020070102.

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Thread-level speculation (TLS) is an approach to enhance the opportunity of parallelization of programs. A TLS system enables multiple threads to begin the execution of tasks in parallel even if there may be the dependency between tasks. When any dependency violation is detected, the TLS system enforces the violating thread to abort and re-execute the task. So, the frequency of aborts is one of the factors that damage the performance of the speculative execution. This article proposes a new technique named the code shelving, which enables threads not to need to abort. It is available not only for TLS but also as a flexible synchronization technique in conventional and non-speculatively parallel execution. The authors implemented the code shelving on their parallel execution system called Speculative Memory (SM) and verified the effectiveness of the code shelving.
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Tatas, Konstantinos, Costas Kyriacou, Paraskevas Evripidou, Pedro Trancoso, and Stephan Wong. "Rapid Prototyping of the Data-Driven Chip-Multiprocessor (D2-CMP) using FPGAs." Parallel Processing Letters 18, no. 02 (2008): 291–306. http://dx.doi.org/10.1142/s0129626408003399.

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This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that enables thread execution using dataflow-like scheduling policy on a chip multiprocessor. Threads are scheduled for execution based on data availability, i.e., a thread is scheduled for execution only if its input data is available. This model of execution is called the non-blocking Data-Driven Multithreading (DDM) model of execution. The DDM model has been evaluated using an execution driven simulator. To validate the simulation results, a 2-node DDM chip multiprocessor has been implemented on a Xilinx Virtex-II Pro FPGA with two PowerPC processors hardwired on the FPGA. Measurements on the hardware prototype show that the TSU can be implemented with a moderate hardware budget. The 2-node multiprocessor has been implemented with less than half of the reconfigurable hardware available on the Xilinx Virtex-II Pro FPGA (45% slices), which corresponds to an ASIC equivalent gate count of 1.9 million gates. Measurements on the prototype showed that the delays incurred by the operation of the TSU can be tolerated.
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Sinharoy, Balaram. "Compiler Optimization to Improve Data Locality for Processor Multithreading." Scientific Programming 7, no. 1 (1999): 21–37. http://dx.doi.org/10.1155/1999/235625.

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Over the last decade processor speed has increased dramatically, whereas the speed of the memory subsystem improved at a modest rate. Due to the increase in the cache miss latency (in terms of the processor cycle), processors stall on cache misses for a significant portion of its execution time. Multithreaded processors has been proposed in the literature to reduce the processor stall time due to cache misses. Although multithreading improves processor utilization, it may also increase cache miss rates, because in a multithreaded processor multiple threads share the same cache, which effectively reduces the cache size available to each individual thread. Increased processor utilization and the increase in the cache miss rate demands higher memory bandwidth. A novel compiler optimization method has been presented in this paper that improves data locality for each of the threads and enhances data sharing among the threads. The method is based on loop transformation theory and optimizes both spatial and temporal data locality. The created threads exhibit high level of intra‐thread and inter‐thread data locality which effectively reduces both the data cache miss rates and the total execution time of numerically intensive computation running on a multithreaded processor.
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Tian, Zhenzhou, Qing Wang, Cong Gao, Lingwei Chen, and Dinghao Wu. "Plagiarism Detection of Multi-threaded Programs Using Frequent Behavioral Pattern Mining." International Journal of Software Engineering and Knowledge Engineering 30, no. 11n12 (2020): 1667–88. http://dx.doi.org/10.1142/s0218194020400252.

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Software dynamic birthmark techniques construct birthmarks using the captured execution traces from running the programs, which serve as one of the most promising methods for obfuscation-resilient software plagiarism detection. However, due to the perturbation caused by non-deterministic thread scheduling in multi-threaded programs, such dynamic approaches optimized for sequential programs may suffer from the randomness in multi-threaded program plagiarism detection. In this paper, we propose a new dynamic thread-aware birthmark FPBirth to facilitate multi-threaded program plagiarism detection. We first explore dynamic monitoring to capture multiple execution traces with respect to system calls for each multi-threaded program under a specified input, and then leverage the Apriori algorithm to mine frequent patterns to formulate our dynamic birthmark, which can not only depict the program’s behavioral semantics, but also resist the changes and perturbations over execution traces caused by the thread scheduling in multi-threaded programs. Using FPBirth, we design a multi-threaded program plagiarism detection system. The experimental results based on a public software plagiarism sample set demonstrate that the developed system integrating our proposed birthmark FPBirth copes better with multi-threaded plagiarism detection than alternative approaches. Compared against the dynamic birthmark System Call Short Sequence Birthmark (SCSSB), FPBirth achieves 12.4%, 4.1% and 7.9% performance improvements with respect to union of resilience and credibility (URC), F-Measure and matthews correlation coefficient (MCC) metric, respectively.
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Dissertations / Theses on the topic "Execution thread"

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Khan, Salman. "Putting checkpoints to work in thread level speculative execution." Thesis, University of Edinburgh, 2010. http://hdl.handle.net/1842/4676.

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With the advent of Chip Multi Processors (CMPs), improving performance relies on the programmers/compilers to expose thread level parallelism to the underlying hardware. Unfortunately, this is a difficult and error-prone process for the programmers, while state of the art compiler techniques are unable to provide significant benefits for many classes of applications. An interesting alternative is offered by systems that support Thread Level Speculation (TLS), which relieve the programmer and compiler from checking for thread dependencies and instead use the hardware to enforce them. Unfortunately, data misspeculation results in a high cost since all the intermediate results have to be discarded and threads have to roll back to the beginning of the speculative task. For this reason intermediate checkpointing of the state of the TLS threads has been proposed. When the violation does occur, we now have to roll back to a checkpoint before the violating instruction and not to the start of the task. However, previous work omits study of the microarchitectural details and implementation issues that are essential for effective checkpointing. Further, checkpoints have only been proposed and evaluated for a narrow class of benchmarks. This thesis studies checkpoints on a state of the art TLS system running a variety of benchmarks. The mechanisms required for checkpointing and the costs associated are described. Hardware modifications required for making checkpointed execution efficient in time and power are proposed and evaluated. Further, the need for accurately identifying suitable points for placing checkpoints is established. Various techniques for identifying these points are analysed in terms of both effectiveness and viability. This includes an extensive evaluation of data dependence prediction techniques. The results show that checkpointing thread level speculative execution results in consistent power savings, and for many benchmarks leads to speedups as well.
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Martinsen, Jan Kasper. "Evaluating JavaScript Execution Behavior and Improving the Performance of Web Applications with Thread-Level Speculation." Licentiate thesis, Karlskrona : Blekinge Institute of Technology, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-00514.

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This thesis addresses two issues: (i) The execution behavior of JavaScript in established benchmarks and in real-world Web Applications and (ii) whether Thread-Level Speculation is a suitable technique for taking advantage of multicore systems in Web Applications written in JavaScript. The first key result is that JavaScript execution behavior by the benchmarks and the JavaScript execution behavior by the Web Applications differ in several important aspects. For instance Web Applications often use function types such as anonymous and eval functions. Our results also show that just-in-time compilation often increases the execution time of Web Applications, despite that just-in-time compilation decreases the execution time for most of the benchmarks. The second key result is that our implementation of Thread-Level Speculation shows that it can be used to take advantage of multicore systems for Web Applications. We have measured the effect on the execution time for a set of Web Applications, and found that we are able to reduce JavaScript execution time more than 8 times compared to the sequential version on a dual quad core computer. For our use-cases we found that we used between 1.1 and 31.0 MB to store information associated with speculation.
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Cuvillo, Juan del. "Breaking away from the OS shadow a program execution model aware thread virtual machine for multicore architectures /." Access to citation, abstract and download form provided by ProQuest Information and Learning Company; downloadable PDF file, 120 p, 2008. http://proquest.umi.com/pqdweb?did=1601517941&sid=4&Fmt=2&clientId=8331&RQT=309&VName=PQD.

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Souček, Dan. "Možnosti vývoje vícevláknových aplikací na platformě Java 8." Master's thesis, Vysoká škola ekonomická v Praze, 2014. http://www.nusl.cz/ntk/nusl-193899.

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This master thesis is a programmer's guide book of a concurrent programming on the Java 8 platform. Concurrency brings additional issues that cannot occur in single-threaded ap-plications. One of the thesis' objectives is to analyze these issues and introduce several principles that, in case they are properly followed, help to create flawless and well-behaving concurrent applications. Another goal of this thesis is to describe the Java con-currency programming from the theoretical point of view. Firstly, the thesis is focused on basic thread development and synchronization issues. Later, it introduces the features and instruments that are provided by Java 5 and higher versions. The theoretical passages are enriched by practical examples that perform discussed features and help to clarify some specific issues. The thesis is written in Czech language and covers large set of concurrency topics from the very basics through the utility libraries to modern instruments present in Java 8.
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Gustavsson, Andreas. "Static Execution Time Analysis of Parallel Systems." Doctoral thesis, Mälardalens högskola, Inbyggda system, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-31399.

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The past trend of increasing processor throughput by increasing the clock frequency and the instruction level parallelism is no longer feasible due to extensive power consumption and heat dissipation. Therefore, the current trend in computer hardware design is to expose explicit parallelism to the software level. This is most often done using multiple, relatively slow and simple, processing cores situated on a single processor chip. The cores usually share some resources on the chip, such as some level of cache memory (which means that they also share the interconnect, e.g., a bus, to that memory and also all higher levels of memory). To fully exploit this type of parallel processor chip, programs running on it will have to be concurrent. Since multi-core processors are the new standard, even embedded real-time systems will (and some already do) incorporate this kind of processor and concurrent code. A real-time system is any system whose correctness is dependent both on its functional and temporal behavior. For some real-time systems, a failure to meet the temporal requirements can have catastrophic consequences. Therefore, it is crucial that methods to derive safe estimations on the timing properties of parallel computer systems are developed, if at all possible. This thesis presents a method to derive safe (lower and upper) bounds on the execution time of a given parallel system, thus showing that such methods must exist. The interface to the method is a small concurrent programming language, based on communicating and synchronizing threads, that is formally (syntactically and semantically) defined in the thesis. The method is based on abstract execution, which is itself based on abstract interpretation techniques that have been commonly used within the field of timing analysis of single-core computer systems, to derive safe timing bounds in an efficient (although, over-approximative) way. The thesis also proves the soundness of the presented method (i.e., that the estimated timing bounds are indeed safe) and evaluates a prototype implementation of it.<br>Den strategi som historiskt sett använts för att öka processorers prestanda (genom ökad klockfrekvens och ökad instruktionsnivåparallellism) är inte längre hållbar på grund av den ökade energikonsumtion som krävs. Därför är den nuvarande trenden inom processordesign att låta mjukvaran påverka det parallella exekveringsbeteendet. Detta görs vanligtvis genom att placera multipla processorkärnor på ett och samma processorchip. Kärnorna delar vanligtvis på några av processorchipets resurser, såsom cache-minne (och därmed också det nätverk, till exempel en buss, som ansluter kärnorna till detta minne, samt alla minnen på högre nivåer). För att utnyttja all den prestanda som denna typ av processorer erbjuder så måste mjukvaran som körs på dem kunna delas upp över de tillgängliga kärnorna. Eftersom flerkärniga processorer är standard idag så måste även realtidssystem baseras på dessa och den nämnda typen av kod.  Ett realtidssystem är ett datorsystem som måste vara både funktionellt och tidsmässigt korrekt. För vissa typer av realtidssystem kan ett inkorrekt tidsmässigt beteende ha katastrofala följder. Därför är det ytterst viktigt att metoder för att analysera och beräkna säkra gränser för det tidsmässiga beteendet hos parallella datorsystem tas fram. Denna avhandling presenterar en metod för att beräkna säkra gränser för exekveringstiden hos ett givet parallellt system, och visar därmed att sådana metoder existerar. Gränssnittet till metoden är ett litet formellt definierat trådat programmeringsspråk där trådarna tillåts kommunicera och synkronisera med varandra. Metoden baseras på abstrakt exekvering för att effektivt beräkna de säkra (men ofta överskattade) gränserna för exekveringstiden. Abstrakt exekvering baseras i sin tur på abstrakta interpreteringstekniker som vida används inom tidsanalys av sekventiella datorsystem. Avhandlingen bevisar även korrektheten hos den presenterade metoden (det vill säga att de beräknade gränserna för det analyserade systemets exekveringstid är säkra) och utvärderar en prototypimplementation av den.<br>Worst-Case Execution Time Analysis of Parallel Systems<br>RALF3 - Software for Embedded High Performance Architectures
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Shu, Xiaokui. "Threat Detection in Program Execution and Data Movement: Theory and Practice." Diss., Virginia Tech, 2016. http://hdl.handle.net/10919/71463.

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Program attacks are one of the oldest and fundamental cyber threats. They compromise the confidentiality of data, the integrity of program logic, and the availability of services. This threat becomes even severer when followed by other malicious activities such as data exfiltration. The integration of primitive attacks constructs comprehensive attack vectors and forms advanced persistent threats. Along with the rapid development of defense mechanisms, program attacks and data leak threats survive and evolve. Stealthy program attacks can hide in long execution paths to avoid being detected. Sensitive data transformations weaken existing leak detection mechanisms. New adversaries, e.g., semi-honest service provider, emerge and form threats. This thesis presents theoretical analysis and practical detection mechanisms against stealthy program attacks and data leaks. The thesis presents a unified framework for understanding different branches of program anomaly detection and sheds light on possible future program anomaly detection directions. The thesis investigates modern stealthy program attacks hidden in long program executions and develops a program anomaly detection approach with data mining techniques to reveal the attacks. The thesis advances network-based data leak detection mechanisms by relaxing strong requirements in existing methods. The thesis presents practical solutions to outsource data leak detection procedures to semi-honest third parties and identify noisy or transformed data leaks in network traffic.<br>Ph. D.
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Gustavsson, Andreas. "Static Timing Analysis of Parallel Systems Using Abstract Execution." Licentiate thesis, Mälardalens högskola, Inbyggda system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-26125.

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The Power Wall has stopped the past trend of increasing processor throughput by increasing the clock frequency and the instruction level parallelism.Therefore, the current trend in computer hardware design is to expose explicit parallelism to the software level.This is most often done using multiple processing cores situated on a single processor chip.The cores usually share some resources on the chip, such as some level of cache memory (which means that they also share the interconnect, e.g. a bus, to that memory and also all higher levels of memory), and to fully exploit this type of parallel processor chip, programs running on it will have to be concurrent.Since multi-core processors are the new standard, even embedded real-time systems will (and some already do) incorporate this kind of processor and concurrent code. A real-time system is any system whose correctness is dependent both on its functional and temporal output. For some real-time systems, a failure to meet the temporal requirements can have catastrophic consequences. Therefore, it is of utmost importance that methods to analyze and derive safe estimations on the timing properties of parallel computer systems are developed. This thesis presents an analysis that derives safe (lower and upper) bounds on the execution time of a given parallel system.The interface to the analysis is a small concurrent programming language, based on communicating and synchronizing threads, that is formally (syntactically and semantically) defined in the thesis.The analysis is based on abstract execution, which is itself based on abstract interpretation techniques that have been commonly used within the field of timing analysis of single-core computer systems, to derive safe timing bounds in an efficient (although, over-approximative) way.Basically, abstract execution simulates the execution of several real executions of the analyzed program in one go.The thesis also proves the soundness of the presented analysis (i.e. that the estimated timing bounds are indeed safe) and includes some examples, each showing different features or characteristics of the analysis.<br>Worst-Case Execution Time Analysis of Parallel Systems<br>RALF3 - Software for Embedded High Performance Architectures
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Idlan, Rabihah Zakaria B. "Three papers in executive remuneration." Thesis, Lancaster University, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.524721.

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Zhao, Jinsha. "Three essays in executive compensation." Thesis, Lancaster University, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.664460.

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This thesis investigates three theoretical problems in executive compensation literature. They involve extension of a standard principal-agent model, incorporating taxation into the valuation of executive stock options, and the pricing of executive stock options in the presence of managerial effort. Empirical literature has long addressed the endogeneity of capital structure and executive compensation. Yet few models, which optimally determine executive compensation, explicitly introduce capital structure choice. Chapter 2 proposes a principal-agent model in which the capital structure, compensation and managerial actions are simultaneously determined. Based on our numerical results leverage has two effects on managerial actions. One is to discipline the manager and the other is to replace the incentive effect of compensation. Two such effects exist because volatility is chosen by the manager. The basic model is also extended to include debt-like compensation. Our results show that for a given leverage level, rewarding the manager with debt makes her work harder but take less risk. But debt compensation cannot limit risk neutral shareholders' risk appetite; we hence conclude that only a combination of capital and pay regulation, which restricts both risk-taking of shareholders and incentives of the manager, can significantly reduce the firm's risk. Taxation is an important consideration in the design of executive (and employee) compensation. It directly affects the firm's revenue as well as the executive's after tax income. Once the compensation is granted, taxes also affect the early exercise strategy of the components of the compensation. Chapter 3 explores the executive (and employees) compensation with tax. Specifically, we build a tax-inclusive valuation model. The new feature of the model is an addition of a tax decision, which allows the executive (and employees) to optimally sell stock to maximize after-tax terminal utility. The stock selling decision is very similar to an option exercise decision. The valuation 'model essentially has two embedded options: one option is when to exercise the stock option and the other option is when to sell the stock. This new feature allows different exercise policies for executive stock options under different tax schemes. We apply the model to the US and the UK tax system. The findings suggest that restricted stock is the preferred form of compensation in the US. In the UK, restricted stock is only preferred when the executive has low wealth. We also investigate incentives of a special tax scheme - section 83b election - which gives employees a choice to pay income tax at grant date. This voluntary election allows the executive to accelerate ta.x on restricted stock. Our results suggest that 83b election is not optimal for the manager, who would get double-taxed. And it is not optimal for the issuing firm either, as restricted stock without the election can provide higher incentives at lower cost. The value of executive stock options (ESOs) should depend on the manager's ability to influence firm value. ESOs are granted under the assumption that the executive could make the firm value increase. However, ESOs are always valued with no managerial influence. Chapter 4 examines valuation of ESOs, with the assumption that the manager can influence the firm value via her effort choice. The manager influences stock prices by exerting effort, which increases the firm's stock expected return. Effort leads to a disutility (which can be regarded as effort cost) to the risk-averse, utility-maximizing manager. In addition to the effort choice, the market asset. is also introduced to the manager's investment set. Effort increases the manager's subjective valuation as well as the cost of ESO. The standard principal-agent model is not strictly speaking consistent with general equilibrium models like CAP1vI. Managerial effort is generally not priced under these equilibrium models, because all managers are pricetakers. For this reason, we assume that CAPM does not strictly hold when effort is introduced. Our results show that the manager's value and the cost increase with the correlation, because the manager delays a value destroying early exercise. We also show that the manager's subjective value of the ESO is higher than the cost only when the manager has low wealth, low risk-aversion, and the stock has a low volatility. Under these scenarios, the manager's marginal utility is high and effort has a large impact on the manager's valuation. As a result, the value is higher than the cost. These results suggest that managers of large public firms are less likely to value their ESOs higher than the cost; while managers of small non-public firms are likely to value their ESOs far higher than their cost. The result may explain why ESO is so popular in small startup firms, where ESO is most likely to be valued higher than the cost.
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Sharma, Vaibhav. "Three Essays On Executive Compensation." Available to subscribers only, 2009. http://proquest.umi.com/pqdweb?did=1879096991&sid=5&Fmt=2&clientId=1509&RQT=309&VName=PQD.

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Thesis (Ph. D.)--Southern Illinois University Carbondale, 2009.<br>"Department of Finance." Keywords: Agency theory, Executive compensation, Mergers and acquisitions, Spin-offs. Includes bibliographical references (p. 81-86). Also available online.
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Books on the topic "Execution thread"

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Hewitt, Janice. Threads of success: Executive summary. Stationery Office, 2000.

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Frank, N. Magid Associates Inc. Executive Summary of Findings: Prepared for ETVC Limited(Survey Research). Frank N Magid Associates, 1991.

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McCreesh, Jim. The privatisation of the Northern Ireland Water Executive: An opportunity or a threat to staff?. The Author], 1993.

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Office, National Audit. Cabinet Office: The millennium threat, 221 days and counting : report. Stationery Office, 1999.

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Mandell, David B. Why doctors need asset protection: The 10 greatest threats to your financial security. Guardian Pub., 1997.

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Mandell, David B. For doctors only: How to protect your practice, property, and savings from lawsuits and other creditor threats. Guardian Pub., 1997.

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Alex, Tresniowski, ed. An invisible thread: The true story of an 11-year-old panhandler, a busy sales executive, and an unlikely meeting with destiny. Howard Books, 2012.

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Alex, Tresniowski, ed. An invisible thread: The true story of an 11-year-old panhandler, a busy sales executive, and an unlikely meeting with destiny. Howard Books, 2011.

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Alex, Tresniowski, ed. An invisible thread: The true story of an 11-year-old panhandler, a busy sales executive, and an unlikely meeting with destiny. Wheeler Pub., 2012.

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Presidential signing statements under the Bush administration: A threat to checks and balances and the rule of law? : hearing before the Committee on the Judiciary, House of Representatives, One Hundred Tenth Congress, first session, January 31, 2007. U.S. G.P.O., 2007.

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Book chapters on the topic "Execution thread"

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Pfannenstiel, W. "Piecewise Execution of Nested Parallel Programs - A Thread-Based Approach." In Euro-Par’99 Parallel Processing. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/3-540-48311-x_59.

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Zhao, Yue, Kenji Yoshigoe, and Mengjun Xie. "Pre-execution Data Prefetching with Inter-thread I/O Scheduling." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38750-0_30.

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Poetzl, Daniel, and Daniel Kroening. "Formalizing and Checking Thread Refinement for Data-Race-Free Execution Models." In Tools and Algorithms for the Construction and Analysis of Systems. Springer Berlin Heidelberg, 2016. http://dx.doi.org/10.1007/978-3-662-49674-9_30.

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Gan, Ge, and Joseph Manzano. "TL-DAE: Thread-Level Decoupled Access/Execution for OpenMP on the Cyclops-64 Many-Core Processor." In Languages and Compilers for Parallel Computing. Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-13374-9_6.

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Mues, Malte, and Falk Howar. "GDart: An Ensemble of Tools for Dynamic Symbolic Execution on the Java Virtual Machine (Competition Contribution)." In Tools and Algorithms for the Construction and Analysis of Systems. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-030-99527-0_27.

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AbstractGDart is an ensemble of tools allowing dynamic symbolic execution of JVM programs. The dynamic symbolic execution engine is decomposed into three different components: a symbolic decision engine (DSE), a concolic executor (SPouT), and a SMT solver backend allowing meta-strategy solving of SMT problems (JConstraints). The symbolic decision component is loosely coupled with the executor by a newly introduced communication protocol. At SV-COMP 2022, GDart solved 471 of 586 tasks finding more correct false results (302) than correct true results (169). It scored fourth place.
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Voss, Michael, Rafael Asenjo, and James Reinders. "Controlling the Number of Threads Used for Execution." In Pro TBB. Apress, 2019. http://dx.doi.org/10.1007/978-1-4842-4398-5_11.

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Oram, Gerard. "Discipline and Morale in the Three Armies: Case Studies of Three British Infantry Divisions." In Military Executions during World War I. Palgrave Macmillan UK, 2003. http://dx.doi.org/10.1057/9780230287983_6.

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Li, Meirong, Yinliang Zhao, and You Tao. "Dynamically Spawning Speculative Threads to Improve Speculative Path Execution." In Algorithms and Architectures for Parallel Processing. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-11194-0_15.

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Kawamoto, Shin ichi, and Takayasu Ito. "Multi-threaded PaiLisp with granularity adaptive parallel execution." In Theory and Practice of Parallel Programming. Springer Berlin Heidelberg, 1995. http://dx.doi.org/10.1007/bfb0026566.

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Bahrami, Amir Hossein, and Hossein Mohammadi Rouzbahani. "Cyber Security of Smart Manufacturing Execution Systems: A Bibliometric Analysis." In AI-Enabled Threat Detection and Security Analysis for Industrial IoT. Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-76613-9_6.

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Conference papers on the topic "Execution thread"

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Srivastava, Ratnesh Prasad, and G. C. Nandi. "Controlling Multi Thread Execution using Single Thread Event Loop." In 2017 International Conference on Innovations in Control, Communication and Information Systems (ICICCI). IEEE, 2017. http://dx.doi.org/10.1109/iciccis.2017.8660809.

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Xekalakis, Polychronis, Nikolas Ioannou, and Marcelo Cintra. "Combining thread level speculation helper threads and runahead execution." In the 23rd international conference. ACM Press, 2009. http://dx.doi.org/10.1145/1542275.1542333.

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Stecca, Michele, and Massimo Maresca. "Thread management in Mashup execution platforms." In the 12th International Conference. ACM Press, 2010. http://dx.doi.org/10.1145/1967486.1967628.

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Hongbin, Yang, Li Chen, and Wu Yue. "Research in Re-execution of the Thread Granule." In 2010 International Symposium on Parallel and Distributed Processing with Applications (ISPA). IEEE, 2010. http://dx.doi.org/10.1109/ispa.2010.16.

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Dickens, P., M. Haines, P. Mehrotra, and D. Nicol. "Towards a thread-based parallel direct execution simulator." In Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences. IEEE, 1996. http://dx.doi.org/10.1109/hicss.1996.495490.

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Welch, Lawrence, and Stephen Ekwaro-Osire. "Fairness in Agent Based Simulation Frameworks." In ASME 2008 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2008. http://dx.doi.org/10.1115/detc2008-49326.

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An agent based simulation engine should provide a fair playing field for all of its agents. A fundamental design axiom of agent based simulation frameworks is that the simulation engine should not arbitrarily bias its execution towards one agent or another. This fairness is basic to giving the agent modeler confidence that differences in behavior and performance between agents derive legitimately from the simulation modeling, initial conditions or specific agent characteristics, rather than the capriciousness of the underlying framework. One aspect of fairness in a simulation is the relative order of execution of agents over time. This order of execution is affected by techniques employed by frameworks to simulate the concurrent activities of multiple agents. One such technique is multi-threading. Multi-threaded operating systems, or programming languages and environments, such as Java, allow multiple agents, represented by software threads, to share the computer’s execution time by taking turns, thus appearing to act simultaneously. The precise order of execution of peer threads in multi-threaded applications is often out of the hands of the programmer, and may be determined exclusively by the operating system or program execution environment. However, if overlooked by the framework developer, the idiosyncrasies of a particular thread ordering mechanism can pass on to the modeler inherent random behavior that is neither intuitive, nor in line with the modeler’s expectations. To be considered fair, the engine should aim to provide all agents with equal probability of executing first within a time step, or last, or in any position in between. This paper analyzes the sequencing of agent thread execution within a Java framework that implements a multi-threaded, time-stepping, agent based simulation engine. The natural ordering of Java thread execution is demonstrated to be unfair (that is, not uniform) in its treatment of agents. This research shows that the standard mechanism of Java thread scheduling, while appropriate for most applications, is inappropriate on its own for the agent based framework. It is demonstrated that with Java’s standard thread scheduling algorithm, over time certain agents tend to execute ahead of others within each time step, while others tend to execute in the middle or at the back of the pack. This paper then introduces and demonstrates the “Uniform Specific Notification” pattern, a technique that produces a fairer, uniformly distributed random order for the initial execution of Java agent threads at each simulation time step.
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Zhao, Deshuo, and Bin Liu. "Thread-Level Speculation Execution Model Based on LLVM Compiler." In CNIOT2021: 2021 2nd International Conference on Computing, Networks and Internet of Things. ACM, 2021. http://dx.doi.org/10.1145/3468691.3468707.

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Raab, Markus. "Global and Thread-Local Activation of Contextual Program Execution Environments." In 2015 IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops (ISORCW). IEEE, 2015. http://dx.doi.org/10.1109/isorcw.2015.52.

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Rivas, Mario Aldea, and Michael González Harbour. "Operating system support for execution time budgets for thread groups." In the 13th international workshop. ACM Press, 2007. http://dx.doi.org/10.1145/1316003.1316017.

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Wilkinson, Simon, and Ian Watson. "Thread and execution-context specific barriers via dynamic method versioning." In the 4th workshop. ACM Press, 2009. http://dx.doi.org/10.1145/1565824.1565831.

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Reports on the topic "Execution thread"

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CENTER FOR NAVAL ANALYSES ALEXANDRIA VA. The Post-Afghanistan IED Threat Assessment: Executive Summary. Defense Technical Information Center, 2013. http://dx.doi.org/10.21236/ada582113.

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Amela, R., R. Badia, S. Böhm, R. Tosi, C. Soriano, and R. Rossi. D4.2 Profiling report of the partner’s tools, complete with performance suggestions. Scipedia, 2021. http://dx.doi.org/10.23967/exaqute.2021.2.023.

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This deliverable focuses on the proling activities developed in the project with the partner's applications. To perform this proling activities, a couple of benchmarks were dened in collaboration with WP5. The rst benchmark is an embarrassingly parallel benchmark that performs a read and then multiple writes of the same object, with the objective of stressing the memory and storage systems and evaluate the overhead when these reads and writes are performed in parallel. A second benchmark is dened based on the Continuation Multi Level Monte Carlo (C-MLMC) algorithm. While this algorithm is normally executed using multiple levels, for the proling and performance analysis objectives, the execution of a single level was enough since the forthcoming levels have similar performance characteristics. Additionally, while the simulation tasks can be executed as parallel (multi-threaded tasks), in the benchmark, single threaded tasks were executed to increase the number of simulations to be scheduled and stress the scheduling engines. A set of experiments based on these two benchmarks have been executed in the MareNostrum 4 supercomputer and using PyCOMPSs as underlying programming model and dynamic scheduler of the tasks involved in the executions. While the rst benchmark was executed several times in a single iteration, the second benchmark was executed in an iterative manner, with cycles of 1) Execution and trace generation; 2) Performance analysis; 3) Improvements. This had enabled to perform several improvements in the benchmark and in the scheduler of PyCOMPSs. The initial iterations focused on the C-MLMC structure itself, performing re-factors of the code to remove ne grain and sequential tasks and merging them in larger granularity tasks. The next iterations focused on improving the PyCOMPSs scheduler, removing existent bottlenecks and increasing its performance by making the scheduler a multithreaded engine. While the results can still be improved, we are satised with the results since the granularity of the simulations run in this evaluation step are much ner than the one that will be used for the real scenarios. The deliverable nishes with some recommendations that should be followed along the project in order to obtain good performance in the execution of the project codes.
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Álvarez, Carola, Leonardo Corral, Ana Cuesta, José Martínez, César Montiel, and Consuelo Yépez. Project Completion Report Analysis: Factors Behind Project Success and Effectiveness. Inter-American Development Bank, 2021. http://dx.doi.org/10.18235/0003116.

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The goal of development assistance is to deliver measurable results. At the Inter-American Development Bank (IDB), the Development Effectiveness Framework (DEF) was adopted to enhance the likelihood this goal is met. The key objective of this analysis is to enhance our understanding of the role the set of tools and processes adopted at the IDB, from project design to completion, play in the assessment of a projects success and effectiveness. Specifically, we are interested in teasing out the role different dimensions of project design, assessed through the Development Effectiveness Matrix (DEM), and execution performance indicators, as per the Project Monitoring Report (PMR), have on the delivery of effective and successful projects measured through the Project Completion Report (PCR) methodology implemented at the IDB. We also explore the validation process of PCRs and delve into the effectiveness analysis at the level of specific objectives and result indicators, identifying key pitfalls associated with objectives not being met. Overall, our findings provide strong validation for the DEF and its tools. We find robust evidence for the importance of the quality at entry assessment conducted through the DEM. In particular, the quality of the results matrix at approval is a strong determinant of project success and effectiveness at closure, and the quality of the Evaluation Plan is strongly associated with the effectiveness of a project. In terms of execution performance, our analysis finds that, on average, projects that execute a lower share of their approved loan amount, are put on Alert, or are classified as a Problem, in its first three years of execution; and projects that experience a higher share of their outputs discontinued, with respect to their first results matrix, are most likely to be ineffective in achieving their objectives and will likely be rated as unsuccessful.
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Niazi, Fawad. CPT-Based Geotechnical Design Manual, Volume 1: CPT Interpretation—Estimation of Soil Properties. Purdue University, 2022. http://dx.doi.org/10.5703/1288284317346.

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This manual provides guidance on how to use the cone penetration test (CPT) for site investigation and foundation design. The manual has been organized into three volumes. Volume 1 covers the execution of CPT-based site investigations and presents a comprehensive literature review of CPT-based soil behavior type (SBT) charts and estimation of soil variables from CPT results. Volume 2 covers the methods and equations needed for CPT data interpretation and foundation design in different soil types, while Volume 3 includes several example problems (based on instrumented case histories) with detailed, step-by-step calculations to demonstrate the application of the design methods. The methods included in the manual are current, reliable, and demonstrably the best available for Indiana geology based on extensive CPT research carried out during the past two decades. The design of shallow and pile foundations in the manual is based on the load and resistance factor design (LRFD) framework. The manual also indicates areas of low reliability and limited knowledge, which can be used as indicators for future research.
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Sakleshpur, Venkata A., Monica Prezzi, Rodrigo Salgado, and Mir Zaheer. CPT-Based Geotechnical Design Manual, Volume 2: CPT-Based Design of Foundations—Methods. Purdue University, 2022. http://dx.doi.org/10.5703/1288284317347.

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This manual provides guidance on how to use the cone penetration test (CPT) for site investigation and foundation design. The manual has been organized into three volumes. Volume 1 covers the execution of CPT-based site investigations and presents a comprehensive literature review of CPT-based soil behavior type (SBT) charts and estimation of soil variables from CPT results. Volume 2 covers the methods and equations needed for CPT data interpretation and foundation design in different soil types, while Volume 3 includes several example problems (based on instrumented case histories) with detailed, step-by-step calculations to demonstrate the application of the design methods. The methods included in the manual are current, reliable, and demonstrably the best available for Indiana geology based on extensive CPT research carried out during the past two decades. The design of shallow and pile foundations in the manual is based on the load and resistance factor design (LRFD) framework. The manual also indicates areas of low reliability and limited knowledge, which can be used as indicators for future research.
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Sakleshpur, Venkata A., Monica Prezzi, Rodrigo Salgado, and Mir Zaheer. CPT-Based Geotechnical Design Manual, Volume 3: CPT-Based Design of Foundations—Example Problems. Purdue University, 2022. http://dx.doi.org/10.5703/1288284317348.

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This manual provides guidance on how to use the cone penetration test (CPT) for site investigation and foundation design. The manual has been organized into three volumes. Volume 1 covers the execution of CPT-based site investigations and presents a comprehensive literature review of CPT-based soil behavior type (SBT) charts and estimation of soil variables from CPT results. Volume 2 covers the methods and equations needed for CPT data interpretation and foundation design in different soil types, while Volume 3 includes several example problems (based on instrumented case histories) with detailed, step-by-step calculations to demonstrate the application of the design methods. The methods included in the manual are current, reliable, and demonstrably the best available for Indiana geology based on extensive CPT research carried out during the past two decades. The design of shallow and pile foundations in the manual is based on the load and resistance factor design (LRFD) framework. The manual also indicates areas of low reliability and limited knowledge, which can be used as indicators for future research.
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Spoors, F., C. D. B. Leakey, and M. A. James. Coast to ocean: a Fife-eye view: ocean literacy in Fife, Scotland. Scottish Oceans Institute, 2021. http://dx.doi.org/10.15664/10023.23981.

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[Extract from Executive Summary] Ocean Literacy (OL), or Ocean Citizenship, is the basis of a movement to sway positive, lasting change in communities that will benefit the sea, coast and climate. An ocean literate person is understanding of the ocean’s influence on their own lives, as well as the way that their behaviours influence the ocean and is knowledgeable concerning ocean threats. A degree of informed-ness (or ‘literacy’) is thought to inspire effective communication and allow for impactful decision-making regarding personal lifestyle and behaviours, which are subsequently beneficial to the marine and coastal environment. Not only that, a collective OL mindset may be translated into policy, informing marine spatial planning authorities of people’s expectations regarding their marine and coastal spaces.
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Orr, Kyla, Ali McKnight, Kathryn Logan, and Hannah Ladd-Jones. Scottish Inshore Fisheries Integrated Data System (SIFIDS): work package 7 final report engagement with inshore fisheries to promote and inform. Edited by Mark James. Marine Alliance for Science and Technology for Scotland (MASTS), 2020. http://dx.doi.org/10.15664/10023.23453.

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[Extract from Executive Summary] This report documents Work Package 7 of the Scottish Inshore Fisheries Integrated Data Systems (SIFIDS) Project, which was designed to facilitate engagement with the key stakeholders including; inshore fishers, their representative bodies, Regional Inshore Fisheries Groups, Marine Scotland including Policy, Compliance and Science. The SIFIDS Project focused on 12 metre and under inshore fisheries vessels, of which around 1,500 are registered in Scotland including those that work part-time or seasonally. The facilitation team was set various targets for engagement based on the requirements of other work packages. The success of the overall project was dependent to a significant extent on securing voluntary engagement and input from working fishers. Previous experience has shown that having a dedicated project facilitation team is an extremely effective model for establishing the necessary trust to encourage industry-participation in projects such as this. The WP7 facilitation team comprised three individuals who have significant marine and fisheries related experience and wide-ranging skills in communications and stakeholder engagement. They worked together flexibly on a part-time basis, ensuring staffing cover over extended hours where required to match fishers’ availability and geographical coverage over Scotland.
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Ruvinsky, Alicia, Timothy Garton, Daniel Chausse, Rajeev Agrawal, Harland Yu, and Ernest Miller. Accelerating the tactical decision process with High-Performance Computing (HPC) on the edge : motivation, framework, and use cases. Engineer Research and Development Center (U.S.), 2021. http://dx.doi.org/10.21079/11681/42169.

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Managing the ever-growing volume and velocity of data across the battlefield is a critical problem for warfighters. Solving this problem will require a fundamental change in how battlefield analyses are performed. A new approach to making decisions on the battlefield will eliminate data transport delays by moving the analytical capabilities closer to data sources. Decision cycles depend on the speed at which data can be captured and converted to actionable information for decision making. Real-time situational awareness is achieved by locating computational assets at the tactical edge. Accelerating the tactical decision process leverages capabilities in three technology areas: (1) High-Performance Computing (HPC), (2) Machine Learning (ML), and (3) Internet of Things (IoT). Exploiting these areas can reduce network traffic and shorten the time required to transform data into actionable information. Faster decision cycles may revolutionize battlefield operations. Presented is an overview of an artificial intelligence (AI) system design for near-real-time analytics in a tactical operational environment executing on co-located, mobile HPC hardware. The report contains the following sections, (1) an introduction describing motivation, background, and state of technology, (2) descriptions of tactical decision process leveraging HPC problem definition and use case, and (3) HPC tactical data analytics framework design enabling data to decisions.
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Melby, Jeffrey, Thomas Massey, Abigail Stehno, Norberto Nadal-Caraballo, Shubhra Misra, and Victor Gonzalez. Sabine Pass to Galveston Bay, TX Pre-construction, Engineering and Design (PED) : coastal storm surge and wave hazard assessment : report 1 – background and approach. Engineer Research and Development Center (U.S.), 2021. http://dx.doi.org/10.21079/11681/41820.

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The US Army Corps of Engineers, Galveston District, is executing the Sabine Pass to Galveston Bay Coastal Storm Risk Management (CSRM) project for Brazoria, Jefferson, and Orange Counties regions. The project is currently in the Pre-construction, Engineering, and Design phase. This report documents coastal storm water level and wave hazards for the Port Arthur CSRM structures. Coastal storm water level (SWL) and wave loading and overtopping are quantified using high-fidelity hydrodynamic modeling and stochastic simulations. The CSTORM coupled water level and wave modeling system simulated 195 synthetic tropical storms on three relative sea level change scenarios for with- and without-project meshes. Annual exceedance probability (AEP) mean values were reported for the range of 0.2 to 0.001 for peak SWL and wave height (Hm0) along with associated confidence limits. Wave period and mean wave direction associated with Hm0 were also computed. A response-based stochastic simulation approach is applied to compute AEP runup and overtopping for levees and overtopping, nappe geometry, and combined hydrostatic and hydrodynamic fluid pressures for floodwalls. CSRM structure crest design elevations are defined based on overtopping rates corresponding to incipient damage. Survivability and resilience are evaluated. A system-wide hazard level assessment was conducted to establish final recommended system-wide CSRM structure elevations.
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