Academic literature on the topic 'Epitaxial stack design'

Tackling issues of implantation-caused defects and contamination, this paper presents a new complementary metal–oxide–semiconductor (CMOS) image sensor (CIS) pixel design concept based on a native epitaxial layer for photon detection, charge storage, and charge transfer to the sensing node. To prove this concept, a backside illumination (BSI), p-type, 2-µm-pitch pixel was designed. It integrates a vertical pinned photo gate (PPG), a buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide–nitride–oxide (ONO) stack. The designed pixel was fabricated with variations of key parameters for optimization. Testing results showed the following achievements: 13,000 h+ full-well capacity with no lag for charge transfer, 80% quantum efficiency (QE) at 550-nm wavelength, 5 h+/s dark current at 60 °C, 2 h+ temporal noise floor, and 75 dB dynamic range. In comparison with conventional pixel design, the proposed concept could improve CIS performance.

This paper constitutes the analysis of the impact of low doped intrinsic p-type EPI thickness (20 µm and 30 µm) and bottom anti-reflective coating on the electrical and optical performance of various PIN photodiodes designs. The intrinsic p-type layer with a target resistivity of 400 Ω cm is an epitaxial layer (iEPI) grown on a low resistive substrate of 20 mΩ cm. Optimization of the photodiode’s spectral responsivity (for a specific wavelength) includes a Bottom Anti-Reflective Coating (BARC) layer deposited over the silicon surface. BARC thickness is optimized for λ = 425 nm, λ = 750 nm and λ = 900 nm wavelengths. With respective BARC in place, the photodiode’s quantum efficiency (QE) approaches 100% for λ = 750 nm with 20 µm and 30 µm iEPI thickness and for λ = 900 nm with 30 µm iEPI reaching also a maximum spectral response of 0.63 A/W at 800 nm. QE of 72% could be achieved at 425 nm. The leakage current varies from 3.5 pA for 20 µm iEPI thickness to 10 pA for 30 µm at 1 V reverse biasing for 365 µm circular PIN photodiode.

Both forksheet and CFET device layouts contain local dielectric isolation layers to circumvent junction isolation trade-offs which are specific for these designs. Typical fabrication schemes start with the epitaxial growth of complicated SiGe/Si multi stacks with at least two different Ge concentrations where a Ge-rich SiGe layer is later replaced by an isolating dielectric. This work proposes a low temperature Br2-based vapor etching process as an option for the selective SiGe removal in the isolation fabrication. After initial process screening on blanket epi layers to compare etching behavior for different process gases as function of material composition and crystallinity, it is demonstrated on patterned test structures that Br2 etching enables high etching selectivity of Si0.5Ge0.5 towards Si and Si1-xGex (x = 0.2 - 0.3).

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future.

Abstract. Nano-ionic materials made of strontium titanate (SrTiO3, STO) and solid solutions of strontium ferrite in STO (SrTi1 − xFexO3, STF) are grown on single crystalline STO substrates and characterized. Since STF exhibits an oxygen deficiency and, simultaneously, enables oxygen interstitial defects, a space charge area close to the STO | STF interface is present. Oxygen tracer diffusion experiments and impedance spectroscopy at temperatures from 500 to 700 °C and at oxygen partial pressure ranging from 10−3 to 10−23 bar confirm fast oxygen transport caused by enhanced ionic conductivity at the interface. There, an oxygen diffusion coefficient of 3. 4 × 10−10 m2 s−1 at 600 °C and a p type conductivity of about 360 S m−1 at 700 °C are calculated. Such structures open new options in design of nano-ionic materials for oxygen sensors and energy conversion at temperatures lower than those of conventional materials such as yttrium-doped zirconia.

Abstract Stress/strain engineering techniques are employed to boost the performance of Gate-all-around (GAA) vertically stacked nanosheet field-effect transistors (NSFETs) for 7nm technology nodes and beyond. In this work, we report on the 3D numerical simulation study of the impacts of source/drain epitaxial and uniaxial strained-SiGe channel stresses on p-type NSFETs. It is shown that the uniaxial strained-SiGe channel improves the drive current by up to 107% due to higher compressive stress while the 3-stack NSFET can achieve an enhancement in drive current even up to 187% using a 30% Ge mole fraction. Furthermore, we compare the multiple stacked channel NSFETs and nanowire FETs (NWFETs) considering different strain techniques. As compared to a 3-stack strained-SiGe NWFET, NSFETs show 27% and 10% enhancements in ION and SS, respectively. Vertically stacked NSFETs are shown to be the best option to improve the hole mobility under biaxial and uniaxial compressive strain rather than NWFETs. We also look at how the Ge mole fraction affects various electrical properties in a uniaxial strained-SiGe channel with shrinking dimensions of scaled NSFETs. It is observed that for a fixed Lg, ION/IOFF ratio, SS and DIBL decrease with the increase in Ge mole fraction.

Beta gallium oxide (β-Ga2O3) shows significant promise in high-temperature, high-power, and sensing electronics applications. However, long-term stable metallization layers for Ohmic contacts at high temperatures present unique thermodynamic challenges. The current most common Ohmic contact design based on 20 nm of Ti has been repeatedly demonstrated to fail at even moderately elevated temperatures (300–400 °C) due to a combination of nonstoichiometric Ti/Ga2O3 interfacial reactions and kinetically favored Ti diffusion processes. Here, we demonstrate stable Ohmic contacts for Ga2O3 devices operating up to 500–600 °C using ultrathin Ti layers with a self-limiting interfacial reaction. The ultrathin Ti layer in the 5 nm Ti/100 nm Au contact stack is designed to fully oxidize while forming an Ohmic contact, thereby limiting both thermodynamic and kinetic instability. This novel contact design strategy results in an epitaxial conductive anatase titanium oxide interface layer that enables low-resistance Ohmic contacts that are stable both under long-term continuous operation (>500 h) at 600 °C in vacuum (≤10−4 Torr), as well as after repeated thermal cycling (15 times) between room temperature and 550 °C in flowing N2. This stable Ohmic contact design will accelerate the development of high-temperature devices by enabling research focus to shift toward rectifying interfaces and other interfacial layers.

Abstract Due to their inherent physical properties, thin-film Si/SiGe heterostructures have specific thermal management applications in advanced integrated circuits and this in turn is essential not only to prevent a high local temperature and overheat inside the circuit, but also generate electricity through the Seebeck effect. Here, we were able to enhance the Seebeck effect in the germanium composite quantum dots (CQDs) embedded in silicon by increasing the number of thin silicon layers inside the dot (multi-fold CQD material). The Seebeck effect in the CQD structures and multi-layer boron atomic layer-doped SiGe epitaxial films was studied experimentally at temperatures in the range from 50 to 300 K and detailed calculations for the Seebeck coefficient employing different scattering mechanisms were made. Our results show that the Seebeck coefficient is enhanced up to ≈40% in a 3-fold CQD material with respect to 2-fold Ge/Si CQDs. This enhancement was precisely modeled by taking into account the scattering of phonons by inner boundaries and the carrier filtering by the CQD inclusions. Our model is also able to reproduce the observed temperature dependence of the Seebeck coefficient in the B atomic layer-doped SiGe fairly well. We expect that the phonon scattering techniques developed here could significantly improve the thermoelectric performance of Ge/Si materials through further optimization of the layer stacks inside the quantum dot and of the dopant concentrations.

AbstractHere we report a comprehensive numerical study for the operating behavior and physical mechanism of nitride micro-light-emitting-diode (micro-LED) at low current density. Analysis for the polarization effect shows that micro-LED suffers a severer quantum-confined Stark effect at low current density, which poses challenges for improving efficiency and realizing stable full-color emission. Carrier transport and matching are analyzed to determine the best operating conditions and optimize the structure design of micro-LED at low current density. It is shown that less quantum well number in the active region enhances carrier matching and radiative recombination rate, leading to higher quantum efficiency and output power. Effectiveness of the electron blocking layer (EBL) for micro-LED is discussed. By removing the EBL, the electron confinement and hole injection are found to be improved simultaneously, hence the emission of micro-LED is enhanced significantly at low current density. The recombination processes regarding Auger and Shockley–Read–Hall are investigated, and the sensitivity to defect is highlighted for micro-LED at low current density.Synopsis: The polarization-induced QCSE, the carrier transport and matching, and recombination processes of InGaN micro-LEDs operating at low current density are numerically investigated. Based on the understanding of these device behaviors and mechanisms, specifically designed epitaxial structures including two QWs, highly doped or without EBL and p-GaN with high hole concentration for the efficient micro-LED emissive display are proposed. The sensitivity to defect density is also highlighted for micro-LED.

AbstractColor conversion by (tapered) nanowire arrays fabricated in GaInP with bandgap emission in the red spectral region are investigated with blue and green source light LEDs in perspective. GaInP nano- and microstructures, fabricated using top-down pattern transfer methods, are derived from epitaxial Ga0.51In0.49P/GaAs stacks with pre-determined layer thicknesses. Substrate-free GaInP micro- and nanostructures obtained by selectively etching the GaAs sacrificial layers are then embedded in a transparent film to generate stand-alone color converting films for spectrophotometry and photoluminescence experiments. Finite-difference time-domain simulations and spectrophotometry measurements are used to design and validate the GaInP structures embedded in (stand-alone) transparent films for maximum light absorption and color conversion from blue (450 nm) and green (532 nm) to red (~ 660 nm) light, respectively. It is shown that (embedded) 1 μm-high GaInP nanowire arrays can be designed to absorb ~ 100% of 450 nm and 532 nm wavelength incident light. Room-temperature photoluminescence measurements with 405 nm and 532 nm laser excitation are used for proof-of-principle demonstration of color conversion from the embedded GaInP structures. The (tapered) GaInP nanowire arrays, despite very low fill factors (~ 24%), can out-perform the micro-arrays and bulk-like slabs due to a better in- and out-coupling of source and emitted light, respectively.

Designs for deep ultraviolet (DUV) edge emitting laser diodes (LDs) based on the wurtzite III-nitride (III-N) material system are presented. A combination of proprietary and commercial advanced semiconductor LD simulation software is used to study the operation of III-N based DUV LDs theoretically. Critical factors limiting device performance are identified based on an extensive literature survey. A comprehensive design parameter space is investigated thoroughly with the help of advanced scripting capabilities. Several design strategies are proposed to eliminate the critical problems completely or partially. A DUV LD design is proposed based exclusively on AlInN active layers grown epitaxially on bulk AlN substrates because AlInN offers a promising alternative to AlGaN for the realization of LDs and LEDs operating in the DUV regime. The proposed AlInN-based design also features a tapered electron blocking layer (EBL) instead of a homogeneous one. Tapered EBLs redistribute the interfacial polarization charge volumetrically throughout the entire EBL thickness via compositional grading, and eliminate the parasitic inversion layer charge. AlGaN based DUV LD designs are explored also because at present, it may be difficult to grow AlInN epitaxially with superior crystalline quality. Polarization charge matching is proposed to improve electron and hole wavefunction overlap within the active region. Although the strategy of polarization charge matching has already been proposed in the literature to enhance performance of visible wavelength LEDs and LDs, the proposed design presents the first demonstration that polarization charge matching is also feasible for DUV LDs operating at sub-300 nm wavelengths. A lateral current injection (LCI) LD design is proposed featuring polarization-charge-matched barriers and regrown Ohmic contacts to avoid a group of issues related to the highly inefficient p-type doping of wide bandgap III-N materials in vertical injection designs. The proposed design partially decouples the problem of electrical injection from that of optical confinement. Although the idea of an LCI LD design has been proposed in the literature in the 90s to be used as longer wavelength active sources in optoelectronic integrated circuits using GaInAsP/InP and related material systems, the proposed design is the first theoretical demonstration that this concept can be applied to DUV LDs based on III-N material system. To solve the problem of hole transport in vertical injection designs, a DUV LD design based exclusively on AlGaN material system is presented, featuring an inverse-tapered p-waveguide layer instead of an EBL. Several EBL designs are investigated, and compared with conventionally-tapered EBL design. Through judicious volumetric redistribution of fixed negative polarization charge, inverse tapering may be exploited to achieve nearly flat valence band profiles free from barriers to hole injection into the active region, in contrast to conventional designs. Numerical simulations demonstrate that the inverse tapered strategy is a viable solution for efficient hole injection in vertical injection DUV LDs operating at shorter wavelengths (< 290 nm).

III-nitride HEMTs are strong contenders for next-generation power electronic applications. The superior material and electrical properties render GaN-based transistors suitable for high-power switching. The material characteristics such as high breakdown voltage, high electron mobility, and high operating temperature make GaN score over Si. Further, low ON resistance and high switching speed responsible for the subsequent reduction in both switching and ON/OFF state losses render GaN-based HEMT a foreboding device for power electronic applications. In this Doctoral Dissertation, we investigate the impact of epitaxial stack design and transistor architecture on the breakdown voltage characteristics and dynamic performances of AlGaN/GaN HEMT for power switching applications. The focus of the thesis starts with understanding the effect of threading dislocations in vertical leakage. This study discusses the mechanism of dislocation-mediated vertical leakage in MOCVD-grown Carbon (C)-doped AlGaN/GaN HEMTs on a 6-inch silicon wafer. Substrate bias polarity-dependent I-Vs, temperature-dependent fitting, and band diagram analysis pointed to the Poole-Frenkel type of conduction mechanism for vertical transport in the devices. We propose that higher dislocation density leads to shallower traps in the buffer and build an analytical model of dislocation-mediated vertical leakage around this. Based on the above evidence, vertical leakage can be reduced in an epitaxial HEMT stack with a higher dislocation density by introducing carbon. It reduces the unintentional doping in GaN, which acts as a carrier, conducted through the dislocation mediated leakage paths. Initially, we tried to incorporate carbon in GaN buffer by reducing the growth temperature, i.e., by auto doping and using CBr4 as an external source. The later part of the chapter reports on the experimental and analytical determination of the optimum carbon concentration in GaN to achieve enhanced breakdown voltage (voltage @ 1 A/cm2) in AlGaN/GaN HEMTs. Later, in the work, we tried to study the step-graded AlGaN transition layers (TL) in the HEMT stack to improve the breakdown voltage. The transition layers include three AlGaN epi-layers of 75%, 50%, and 25% Al-content, down-graded from bottom to top. The growth temperature and carbon doping are varied independently to assess the transition layer's role in leakage current. The introduction of C-doping in the top AlGaN transition layer with 25% Al-content improves lateral breakdown voltage in both mesa and 3-terminal configurations. The combination of HT AlGaN (75% Al-content) with C-doped AlGaN (25% Al-content) is found to be the optimal TL design. After optimizing the stack for low off-state leakage current, we focused on evaluating the on-state performance of the AlGaN/GaN HEMT. In GaN HEMT devices, dynamic RON is considered the most crucial issue in high voltage switching applications. Dynamic RON is a phenomenon in which the on-resistance (RON) of the device increases under high voltage switching conditions. This chapter tried to analyze the effect of growth variations like carbon doping and high growth temperatures on dynamic RON. A subtle balance between HEMT epitaxial stack and device design is crucial to achieving a high breakdown voltage in AlGaN/GaN HEMT. One of the main hurdles in the device design is surface passivation. In this work, we have investigated the material properties of PECVD (Plasma Enhanced Chemical Vapor Deposition) deposited amorphous SiN films and their influence on leakage current of AlGaN/GaN HEMT grown on Si. The device architecture is further improved by incorporating gate field plate design using the optimized SiN to enhance the breakdown voltage by distributing an electric field in the gate to the drain access region. In conclusion, we propose epitaxial stack design guidelines to achieve high breakdown voltage with low dynamic RON. The optimized epitaxial stack of 1.65 µm has the potential to be converted as a cost-effective technology for high voltage applications (400 V), which is in demand in the EV industry.

Vertical-cavity surface-emitting lasers (VCSEL's) fabricated by selective oxidation are attractive to achieve ultralow threshold currents [1-3]. Efficient heat dissipation, along with low threshold, is critical for uses as optical interconnects where massive integration is required. In this paper, we report an ultralow threshold of 8.7 µA and a high output power over 1.9 mW in single quantum well VCSEL's fabricated by selective oxidation from an all epitaxial structure with intracavity p-contact layers grown by metalorganic chemical vapor deposition. The design of this structure is optimized for low thermal resistance by using distributed Bragg reflectors (DBR's) composed completely of binary materials. Fig.l shows a schematic cross-section of the fabricated VCSEL's. The epitaxial structure consists of a 30-pair n-doped AlAs/GaAs quarter-wave stacks, an Al0.22Ga0.78As/GaAs/In0.2Ga0.8As resonant λ-cavity, p-doped contact layers, and a 22-pair undoped AlAs/GaAs quarter-wave stacks. The p-doped contact layers are formed from a 0.25 λ AlAs current constriction layer and a 0.75 λ GaAs intracavity contact layer. After growth, the top DBR is selectively wet etched into 14 and 5 µm square mesas down to the p-type GaAs contact layer. Then, 50 µm square mesas, whose centers coincide with the centers of the top mesas, are formed by wet chemical etching. Current flow apertures of 10 and ~3 µm are formed below the 14 and 5 µm square top mirrors, respectively, by selective oxidation.