Dissertations / Theses on the topic 'Energy chirp'

2008/2009
For an X-ray free electron laser (FEL), a high-quality electron bunch with low emittance, high peak current and energy is needed. During the phases of acceleration, bunch compression and transportation, the electron beam is subject to radio frequency curvature and to wakefields effects. Thus, the energy profile of the electron beam can present a parabolic profile, which has important electromagnetic effects on the FEL process. The quality of the electron beam is also degraded by the interaction with the low-gap undulator vacuum chamber. In our work we first analyze this interaction, deriving a formula to evaluate the longitudinal and the transversal wakefields for an elliptical cross section vacuum chamber, obtaining accurate results in the short range. Subsequently within the Vlasov-Maxwell one-dimensional model, we derive the Green functions necessary to evaluate the radiation envelope, having as initial conditions both an energy chirp and curvature on the electrons and eventually an initial bunching, which is useful to treat the harmonic generation FEL cascade configuration. This allows to study the impact of the elecron beam energy profile on the FEL performance. Using the derived Green functions we discuss FEL radiation properties such as bandwidth, frequency shift, frequency chirp and velocity of propagation. Finally, we propose a method to achieve ultra-short FEL pulses using a frequency chirp on the seed laser and a suitable electron energy profile.
XXII Ciclo
1980

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Page 198 blank.
Includes bibliographical references (p. 191-197).
On-chip interconnection networks (OCN) such as point-to-point networks and buses form the communication backbone in multiprocessor systems-on-a-chip, multicore processors, and tiled processors. OCNs consume significant portions of a chip's energy budget, so their energy analysis early in the design cycle becomes important for architectural design decisions. Although innumerable studies have examined OCN implementation and performance, there have been few energy analysis studies. This thesis develops an analytical framework for energy estimation in OCNs, for any given topology and arbitrary communication patterns, and presents OCN energy results based on both analytical communication models and real network traces from applications running on a tiled multicore processor. This thesis is the first work to address communication locality in analyzing multicore interconnect energy and to use real multicore interconnect traces extensively. The thesis compares the energy performance of point-to-point networks with buses for varying degrees of communication locality. The model accounts for wire length, switch energy, and network contention. This work is the first to examine network contention from the energy standpoint.
(cont.) The thesis presents a detailed analysis of the energy costs of a switch and shows that the estimated values for channel energy, switch control logic energy, and switch queue buffer energy are 34.5pJ, 17pJ, and 12pJ, respectively. The results suggest that a one-dimensional point-to-point network results in approximately 66% energy savings over a bus for 16 or more processors, while a two-dimensional network saves over 82%, when the processors communicate with each other with equal likelihood. The savings increase with locality. Analysis of the effect of contention on OCNs for the Raw tiled microprocessor reports a maximum energy overhead of 23% due to resource contention in the interconnection network.
by Theodoros K. Konstantakopoulos.
Ph.D.

The Network on Chip (NoC) paradigm was introduced as a scalable communication infrastructure for future System-on-Chip applications. Designing application specific customized communication architectures is critical for obtaining low power, high performance solutions. Two significant design automation problems are the creation of an optimized configuration, given application requirement the implementation of this on-chip network. Automating the design of on-chip networks requires models for estimating area and energy, algorithms to effectively explore the design space and network component libraries and tools to generate the hardware description. Chip architects are faced with managing a wide range of customization options for individual components, routers and topology. As energy is of paramount importance, the effectiveness of any custom NoC generation approach lies in the availability of good energy models to effectively explore the design space. This thesis describes a complete NoC synthesis ???ow, called NoCGEN, for creating energy-efficient custom NoC architectures. Three major automation problems are addressed: custom topology generation, energy modeling and generation. An iterative algorithm is proposed to generate application specific point-to-point and packet-switched networks. The algorithm explores the design space for efficient topologies using characterized models and a system-level ???oorplanner for evaluating placement and wire-energy. Prior to our contribution, building an energy model required careful analysis of transistor or gate implementations. To alleviate the burden, an automated linear regression-based methodology is proposed to rapidly extract energy models for many router designs. The resulting models are cycle accurate with low-complexity and found to be within 10% of gate-level energy simulations, and execute several orders of magnitude faster than gate-level simulations. A hardware description of the custom topology is generated using a parameterizable library and custom HDL generator. Fully reusable and scalable network components (switches, crossbars, arbiters, routing algorithms) are described using a template approach and are used to compose arbitrary topologies. A methodology for building and composing routers and topologies using a template engine is described. The entire flow is implemented as several demonstrable extensible tools with powerful visualization functionality. Several experiments are performed to demonstrate the design space exploration capabilities and compare it against a competing min-cut topology generation algorithm.

The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today’s shared buses with packet-switched router networks. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as three-dimensional (3D) graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. This work demonstrates that a computational fabric built using optimized building blocks can provide high levels of performance in an energy efficient manner. The thesis details an integrated 80- Tile NoC architecture implemented in a 65-nm process technology. The prototype is designed to deliver over 1.0TFLOPS of performance while dissipating less than 100W. This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power. In a 150-nm sixmetal CMOS process, the 12.2 mm2 router contains 1.9-million transistors and operates at 1 GHz at 1.2 V supply. We next describe a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulation loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. A combination of algorithmic, logic and circuit techniques enable multiply-accumulate operations at speeds exceeding 3GHz, with singlecycle throughput. This approach reduces the latency of dependent FPMAC instructions and enables a sustained multiply-add result (2FLOPS) every cycle. The optimizations allow removal of the costly normalization step from the critical accumulation loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230-K transistors. Silicon achieves 6.2-GFLOPS of performance while dissipating 1.2 W at 3.1 GHz, 1.3 V supply. We finally present the industry's first single-chip programmable teraFLOPS processor. The NoC architecture contains 80 tiles arranged as an 8×10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined singleprecision FPMAC units which feature a single-cycle accumulation loop for high throughput. The five-port router combines 100 GB/s of raw bandwidth with low fall-through latency under 1ns. The on-chip 2D mesh network provides a bisection bandwidth of 2 Tera-bits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100-M transistors. The fully functional first silicon achieves over 1.0TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07-V supply. It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results demonstrate that the NoC architecture successfully delivers on its promise of greater integration, high performance, good scalability and high energy efficiency.

The electrical energy consumption in thermomechanical pulping (TMP) is very high, in the range of 2 – 3 MWh/adt depending on process solution and on the product quality specifications for the paper product. Both pulpwood and energy prices have increased rapidly for some time. Due to this, the main focus of the research and development is on ways to reduce the electrical energy consumption in wood chip refining. As a step towards a more energy and cost ‐ effective refining process, Holmen Paper AB has invested in a new mechanical pulping process at its Braviken mill. In this case the primary refining stage consists of high consistency (HC) double disc refiners ‐ RGP68DD (machines with two counter rotating discs). Earlier studies on the refining conditions, such as intensity and temperature, have indicated that it should be possible to improve the energy efficiency in double disc refining while maintaining the functional pulp properties such as tensile index. The main goal of this project was to improve the energy efficiency in double disc chip refining with 150 kWh/adt to corresponding pulp properties as measured on pulp samples after refiner. In order to further improve the basic understanding of what happens to the wood fibre material when changing the process conditions, the morphological and ultrastructural changes of fibres were also studied. This part of the research work was performed in cooperation with the research program; Collaborative Research on the Ultrastructure of Wood Fibres (CRUW). This licentiate project is a part of a large development project where different techniques to improve the energy efficiency has been evaluated by means of mill scale trials at the Holmen Paper Braviken Mill. The high consistency double disc chip refining part of the project was financed by The Swedish Knowledge Foundation, Metso Paper and Holmen Paper, in cooperation with FSCN (Fiber Science & Communication Network) at Mid Sweden University. The trials were made on one of the TMP lines at the Holmen Paper Braviken mill with Norway spruce as raw material. The influence of increased specific      refining energy on pulp properties were studied at different refining temperatures, refining intensity, pulp consistency and production rate. Results from these trials were later validated by means of long term trials. Intensity models and simulations for intensity changes by new segment design were made by Juha‐ Pekka Huhtanen from Tampere University of Technology, Finland. The results show that the specific energy consumption to same tensile index can be improved by means of increasing the refining pressure/temperature. The energy efficiency was improved by 80     ‐150 kWh/adt depending on load and the inlet‐ and housing pressure. The largest relative specific energy efficiency improvement was reached at low specific energy consumption levels. Similar fibre surface ultrastructure characteristics are gained by pulps with high pressure/temperature and low specific energy consumption compared to low pressure/temperature and high specific energy consumption pulps. High pressure/temperature and high specific energy consumption resulted in significantly increase in the delamination/internal fibrillation of pulp fibres. The surface ultrastructure of these fibres exhibited exposed S2 layer with long ribbontype fibrillation compared to pulps produced with lower temperature and lower specific energy consumption. When the refiner was operated at high pressure, the tensile index was preserved over the whole plate life. The specific light scattering coefficient increased with increasing pressure/temperature. A reason for this could be increased intensity caused by decreased plate gap. Increased intensity by means of refiner segment design changes resulted in large specific light scattering coefficient increase at similar tensile index, lower shives content, lower average fibre length and lower CSF at same specific energy consumption. The fresh steam consumption was reduced by the increased refiner ressure/temperature.
Den höga elenergiförbrukningen vid produktion av mekanisk massa har ställtkrav på mer forskning för att elenergieffektivisera raffineringsprocessen. Som ettsteg mot en mer energi‐ och kostnadseffektiv raffineringsprocess, har HolmenPaper AB investerat i en ny tillverkning av termomekanisk (TMP) massa vidBravikens pappersbruk. Dubbeldiskraffinörerna i den nya massalinjens primäraraffineringssteget studerades i detta projekt. Det finns goda indikationer på att enminskning av energiförbrukningen är möjlig genom att studerar och optimeraraffineringparametrar såsom intensitet och temperatur. Projektets huvudmål varatt energieffektivisera det primära dubbeldiskraffineringssteget med 150 kWh/adttill motsvarande massaegenskaper, så som dragstyrka, mätt på massa efterraffinör. Tillfälle gavs också till att studera morfologiska förändringar på fibrer föratt ytterligare förstå hur massa och fibrerna påverkas av dubbeldiskraffinering ochförändringar i raffineringssystemet.Detta licentiatprojekt är en del av ett större projekt där olika tekniker för attförbättra energieffektiviteten har utvärderats i industriell skala på Holmen PaperBravikens pappersbruk. Licentiatprojektet är finansierat av KK‐stiftelsen, MetsoPaper och Holmen Paper, i samarbete med Mittuniversitetet.Fullskaleförsök gjordes på en av TMP linjerna vid Bravikens pappersbruk, därgran används som råvara. Studien utfördes på dubbeldiskraffinörerna i detprimära raffineringssteget. Malkurvor, med ökande specifik raffineringsenergi,gjordes vid olika raffineringstemperaturer, intensitet, massakoncentration ochproduktion. Resultat som erhållits från malkurvorna bekräftades med längrestudier på raffinörerna. Intensitetsmodeller och simuleringar utfördes av Juha‐Pekka Huhtanen från Tampere University of Technology.De erhållna resultaten visar på att energiförbrukningen till ett visst dragindexkan minskas genom att öka raffineringstrycket/temperaturen. Medraffineringstryck menas inlopp och hustryck i raffinören. Energibesparingen är iintervallet 80‐150 kWh/adt. Den största förbättringen kan uppnås vid lågaenergiinsatser. Massor producerade med högt tryck och temperatur och lägrespecifik energiförbrukning uppvisar liknande ultrastrukturella ytegenskaper sommassor producerade med lågt tryck och temperatur och hög specifik energi. Högttryck och temperaturer med hög specifik energiinsats gav en signifikant förbättringav delaminering/intern fibrillering av massafibrer. Dessa fibrer uppvisadebildningar av långa band‐liknande fibriller från fibrernas S2 skikt, i jämförelse medmassor tillverkade med lägre tryck och temperatur och lägre specifik energi.5Om raffineringen genomförs vid högt tryck/temperatur bevaras dragindexunder hela segmentlivslängden.Den specifika ljusspridningskoefficienten påverkades positivt av ökat tryck ochtemperatur. En orsak till detta kan vara högre intensitet som orsakas av minskadmalspalt.Ökad intensitet genom förändrad segmentdesign leder till stora ökningar i denspecifika ljusspridningskoefficienten. Samtidigt uppnås samma dragindex, lägrespethalt, lägre genomsnittlig fiberlängd och CSF vid samma specifikaenergiförbrukning.Förbrukningen av färskångan sänktes vid tillämning av högre tryck ochtemperatur i raffinören.

During the past two decades, thermal microfluidic chips have significantly been investigated. Due to their high capacity of heat transport, an increasing number of studies on different aspects of thermal microfluidic chips have been conducted. However, a comprehensive investigation on the geometry of microfluidic chips using state of the art finite element software is absent from the literature. In this thesis, geometric parameters of thermal microfluidic chips have been optimized, using finite element software. Consequently, micro and macro phenomena were investigated in different models. The micro modelling approach investigated single microchannels and optimized the microchannel cross-section. Furthermore, two-phase flows in the microchannel were modelled, using finite element software ANSYS CFX. Liquid accumulation in the sharp corners of the microchannel was captured in the model and the phase change phenomenon was observed. The results of the finite element analysis were compared to the literature and a good correlation was observed. The configuration of microchannels in a microfluidic chip was studied through the macro modelling approach. Dimensionless design charts were presented in this section to be employed for all kinds of thermal microfluidic chips with different boundary conditions. Based on the validity of the finite element software, two-phase flows in the optimized three-dimensional network of microchannels were modelled. The results showed the circulation of the two phases in the microchannels and demonstrated the proper operation of the thermal microfluidic chip.
Au cours des deux dernières décades, les puces thermiques micro-fluidiques ont été considérablement examinées. Du fait de leur haute capacité pour le transport de chaleur, de nombreuses études ont été réalisées sur différents aspects de leurs propriétés. Cependant, une étude de la géométrie des puces micro-fluidiques utilisant un logiciel d'analyse par éléments finis est absente de la littérature. Dans cette thèse, des paramètres géométriques des puces thermiques micro-fluidiques ont été optimisés en utilisant un logiciel d'analyse par éléments finis. Ainsi, les phénomènes micro et macro ont été étudiés dans différents modèles. L'approche micro a consisté à étudier les micro-canaux seuls, et à optimiser la géométrie de leur section transverse. De plus, deux phases d'écoulement ont été modélisées en utilisant le logiciel d'élément fini ANSYS CFX. L'accumulation de liquide dans les coins saillants a été saisie par le modèle et le phénomène de changement de phase a pu être également observé. Les résultats de l'analyse par élément finis ont été comparés à ceux trouvés dans la littérature, et une bonne corrélation a été observée. La configuration des micro-canaux dans la puce micro-fluidique a été étudiée par l'approche macro. Des graphes adimensionnels ont été présentés dans cette section afin d'être employés pour toutes sortes de puces ayant différentes conditions aux frontières. En se basant sur la validité du modèle micro, élaboré par élément finis, l'écoulement des deux phases dans un réseau tridimensionnel de micro-canaux avec une géométrie optimisée a été modélisé. Les résultats montrent une circulation des deux phases dans les micro-canaux et démontrent le bon fonctionnement des puces thermiques micro fluidiques.

This dissertation aims at improving the off-chip bandwidth utilization and energy efficiency in chip multiprocessor (CMP) architectures. This work consists of two main parts. The first part investigates the early write-back technique for a two-level cache hierarchy in a CMP with four processor cores. Early write-back can be viewed as a modified cache write policy that takes into account not only maintaining data consistency between on-chip and off-chip components of the memory hierarchy but also improving the off-chip bandwidth utilization. Early write-back will issue a write-back operation for some dead and dirty cache lines, from the shared second-level (L2) cache memory to the main memory, prior to those lines eviction. Early write-back operations will be issued when the off-chip bus is free. This technique would improve the processor's performance by avoiding or minimizing off-chip bus contention between write-back operations and demand fetch requests where one example is read and write misses in the shared L2 cache. Early write-back efficiency has been measured in terms of its impact on the L2 cache miss latency. Simulation results have proved early write-back efficacy in improving the off-chip bandwidth utilization of a CMP. Early write-back has achieved varying degrees of performance improvement among different benchmarks. The performance improvement that early write-back can achieve depends on two main factors. First, the sensitivity of the individual benchmark to changes in the available off-chip bandwidth. Second, the severity of off-chip bus contention between demand fetch requests and write-back operations. The second part of this work tackles dynamic voltage and frequency scaling (DVFS) of the off-chip bus that handles the communication between the processor chip and the off-chip memory. Off-chip bus DVFS will dynamically vary the power parameters of the off-chip bus such that off-chip bus energy can be minimized while at the same time the forward progress of the running application can be maintained. This technique captures the CPU and memory boundedness of the running applications, during the run time, such that a reasonable tradeoff between processor performance and off-chip bus energy can be attained. The off-chip bus can be tuned to low-energy settings in CPU-bound applications or CPU-bound phases of program execution. The CPU-boundedness of an application has been measured in terms of the off-chip access ratio (OCAR) which is defined as the ratio between the number of L2 cache misses and the number of instructions retired during a particular observation window. An application or a particular execution phase is said to be CPU-bound if its OCAR is less that a predefined threshold value. Off-chip bus DVFS has been evaluated in two types of processor configurations: First, a processor that relies on Instruction Level Parallelism (ILP) to improve its performance such as single-core superscalar processors, Second, a processor that depends on Thread Level Parallelism in conjunction with ILP to improve its performance such as a CMP with multiple superscalar cores. In applications with high ILP, even when executed on a single processor, the two systems have achieved similar results in terms of their off-chip bus energy savings. On the other hand, in applications with limited ILP when executed on a single processor, the second system has achieved better results in terms of its off-chip bus energy savings; executing the application as multiple concurrent threads has contributed to its CPU boundedness allowing the off-chip bus DVFS triggering condition to be satisfied for the majority of observation windows as compared to the case of a single processor.

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 65-69).
On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several contributions to low-swing signaling circuit design for the energy efficient on-chip networks in two separate projects: on-chip networks optimized for one-to-many multicasts and broadcasts, and link designs that allow on-chip networks to approach an ideal interconnection fabric. A low-swing crossbar switch, which is based on tri-state Reduced-Swing Drivers (RSDs), is presented for the first project. Measurement results of its test chip fabricated in 45nm SOI CMOS show that the tri-state RSD-based crossbar enables 55% power savings as compared to an equivalent full-swing crossbar and link. Also, the measurement results show that the proposed crossbar allows the broadcast-optimized on-chip networks using a single pipeline stage for physical data transmission to operate at 21% higher data rate, when compared with the full-swing networks. For the second project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such digital-intensive properties enable them to approach energy and delay performance of a point-to-point interconnect of variable lengths. Simulated in 45nm SOI CMOS, the 10mm SRLR featured with high energy efficiency consumes 338fJ/b at 5.4Gb/s/ch while the 10mm VLR raises its data rate up to 16.OGb/s/ch with 427fJ/b.
by Sunghyun Park.
S.M.

La photonique au silicium est une technologie émergente considérée comme l'une des solutions clés pour les interconnexions sur puce de génération future, offrant plusieurs avantages potentiels tels qu'une faible latence de transmission et une bande passante élevée. Cependant, elle reste confrontée à des défis en matière d'efficacité énergétique. Différentes topologies, layout et architectures offrent diverses options d'interconnexion. Ceci conduit à une grande variation des pertes optiques, qui est l'un des facteurs prédominants dans la consommation d'énergie. De plus, les composants photoniques au silicium sont très sensibles aux variations de température. Sous une activité de puces donnée, ceci conduit à une réduction de l’efficacité des lasers et à une dérive des longueurs d'onde des composants optiques, ce qui entraîne un «Bit Error Ratio (BER)» plus élevé et réduit par conséquent l'efficacité énergétique des interconnexions optiques. Dans cette thèse, nous travaillons sur des méthodologies de conception pour les interconnexions photoniques sur silicium économes-en-énergie et prenant en compte la topologie / le layout, la variation thermique et l'architecture
Silicon photonics is an emerging technology considered as one of the key solutions for future generation on-chip interconnects, providing several prospective advantages such as low transmission latency and high bandwidth. However, it still encounters challenges in energy efficiency. Different topologies, physical layouts, and architectures provide various interconnect options for on-chip communication. This leads to a large variation in optical losses, which is one of the predominant factors in power consumption. In addition, silicon photonic devices are highly sensitive to temperature variation. Under a given chip activity, this leads to a lower laser efficiency and a drift of wavelengths of optical devices (on-chip lasers and microring resonators (MRs)), which in turn results in a higher Bit Error Ratio (BER) and consequently reduces the energy efficiency of optical interconnects. In this thesis, we work on design methodologies for energy-efficient silicon photonic interconnects on chip related to topology/layout, thermal variation, and architecture

Network-on-Chip (NoC) is a developing and promising on-chip communication paradigm that improves scalability and performance of System-on-Chips. NoC design flow contains many problems from different areas, for example networking, embedded design and computer architecture. Application mapping is one of these problems, which is generally considered as a communication energy minimization problem. This dissertation approaches to this problem from a networking point of view and tries to find a mapping solution which improves the network performance in terms of the number of packets in the buffers while still minimizing the total communication energy consumption. For this purpose an on-chip network traffic model is required. Self similarity is a traffic model that is used to characterize Ethernet and/or wide area network traffic, as well as most of on-chip network traffic. In this thesis, by using an on-chip traffic characterization that contains self similarity, an application mapping problem definition that contains both energy and buffer utilization concerns is proposed. In order to solve this intractable problem a genetic algorithm based model is implemented. Execution of the algorithm on different test cases has proved that such a mapping formulation avoids high buffer utilizations while still keeping the communication energy low.

Gegenstand der vorliegenden Arbeit sind Experimente, in denen freie Elektronen in den Mikrowellenfeldern eines Quadrupolleiters manipuliert werden. Die Erzeugung der elektrischen Felder mit Hilfe eines planaren Mikrowellensubstrats ermöglicht es, die Bewegung langsamer Elektronen mit Energien unterhalb von 10 eV auf vielfältige Art und Weise zu beeinflussen. In diesem Zusammenhang bieten planare Substrate den zentralen Vorteil, dass fein strukturierte Potentiallandschaften im Nahfeld der Mikrowellenanregung erzeugt werden können. Zudem kann ein tiefer Einschluss der Elektronen in diesem Potential gewährleistet werden. Dies schafft ideale Voraussetzungen für die Realisierung von planaren Strahlteilern oder Resonatoren für Elektronen, die wiederum Perspektiven für neuartige Quantenoptikexperimente mit geführten Elektronen eröffnen. Im Rahmen dieser Arbeit ist es zum ersten Mal gelungen, einen geführten Elektronenstrahl an der Oberfläche eines strukturierten Mikrowellensubstrats aufzuspalten und die Funktionsweise des Strahlteilers experimentell zu untersuchen. Die erfolgreiche Durchführung dieses Experiments basiert auf der Erzeugung eines mikrostrukturierten Strahlteilerpotentials und dem Einsatz von Treiberfrequenzen im Gigahertzbereich. Zu diesem Zweck haben wir ein Mikrowellensubstrat entwickelt, das ein einschließendes Potential erzeugt, in dem Elektronen entlang eines Pfades geführt werden, der sukzessive in zwei Pfade auffächert. In unserem Experiment beobachten wir hinter dem Strahlteilersubstrat zwei symmetrisch aufgespaltene Elektronenstrahlen. Außerdem stellen wir fest, dass ab einer Elektronenenergie von 3 eV erhebliche Verluste das Elektronensignal dominieren. Aus diesem Grund präsentieren wir Simulationen, die die Welleneigenschaften der Elektronen berücksichtigen und das Strahlteilerpotential in der Hinsicht verbessern, dass Anregungen der Elektronenbewegung während der Aufspaltung minimiert werden. Ein weiterer Schwerpunkt liegt auf dem Entwurf und der experimentellen Vermessung einer Elektronenkanone, die auf eine scharfe Metallspitze als Elektronenquelle zurückgreift. Mit Hilfe dieser Elektronenkanone wollen wir einen gepulsten, beugungslimitierten Elektronenstrahl erzeugen und diesen in den Elektronenleiter einspeisen. Des Weiteren können wir im Rahmen dieses Experiments mittels Elektroneninterferenz nachweisen, dass ein von einer lasergetriebenen Metallspitze photoemittierter Elektronenstrahl hervorragende räumliche Kohärenzeigenschaften besitzt. Diese Beobachtung ist für alle zeitaufgelösten Anwendungen relevant, die eine lasergetrieben Metallspitze zur Erzeugung kohärenter Elektronenstrahlen einsetzen. In zukünftigen Experimenten wollen wir die hohe zeitliche Kontrolle der lasergetriebenen Elektronenquelle mit der räumlichen Kontrolle über geführte Elektronen vereinen. Der transversale Einschluss geführter Elektronen führt naturgemäß dazu, dass die Dynamik im einschließenden Potential durch diskrete Quantenzustände beschrieben wird. Im Prinzip sollte es daher möglich sein, Elektronen in quantisierten Bewegungszuständen zu erzeugen, die tief im Potential des Elektronenleiters liegen. Grundvoraussetzung dafür ist eine beugungslimitierte Elektronenquelle, sowie ein Potential, das Elektronen einen sanften Übergang in den Elektronenleiter erlaubt. In dieser Arbeit zeigen wir, dass mit Hilfe einer optimierten Einkoppelstruktur und einer gepulsten Elektronenquelle Elektronen nahezu störungsfrei in das einschließende Potential überführt werden können. Dies ist eine wichtige Maßnahme, um Elektronen in weiterführenden Experimenten direkt in Quantenzustände des Elektronenleiters einzuspeisen.
This work reports on the manipulation of slow electrons in free space using a microwave quadrupole guide. The generation of the electric fields by means of a planar microwave chip provides an entirely new electron toolkit that allows the guidance and steerage of electrons with kinetic energies below 10 eV. As a key feature, this chip-based technology combines the flexibility to engineer microstructured guiding potentials in the near-field of the microwave excitation with tight transverse confinement of the guided electrons. This renders planar guiding structures ideally suited for the implementation of electron beam splitters or resonators with prospects for novel quantum optics experiments with guided electrons. We present an experiment that demonstrates, for the first time, the realization of a chip-based beam splitter for low-energy electrons. Crucial for the success of the experiment is the generation of a finely structured beam splitter potential and the operation at drive frequencies in the gigahertz range. We report on the design of an optimized microwave chip that generates a beam splitter guiding potential by gradually transforming from a single-well harmonic confinement into a double well along the chip. In the experiment we observe an electron signal with two symmetrically split up output beams. Furthermore we find that with increasing electron kinetic energy, electron loss starts to dominate the electron signal for energies above 3 eV. To this end, we present results of wave-optical simulations that further optimize the guiding potential to reduce excitations in the electron motion as an adverse effect of the splitting process. A second main result of this thesis is the construction and experimental characterization of an electron gun that is based on a nanotip electron emitter. It is specifically designed to provide a pulsed, diffraction-limited electron beam for injection into the guide. We prove that photoemitted electron beams from a laser-triggered nanotip are spatially highly coherent using an electron interference setup. This finding is of importance for all time-resolved applications that employ coherent electron beams from a laser-triggered nanotip. Unprecedented spatial and temporal control over guided electrons can be achieved when combining this coherent laser-triggered electron source with a microwave electron guide. The transverse guiding potential naturally provides discretized motional quantum states that govern the dynamics of guided electrons. Ultimately, it should be possible to directly inject electrons into low-lying motional quantum states of the guiding potential. As prerequisites, this necessitates a diffraction-limited electron gun and a guiding potential that provides electrons a smooth passage into the guide. Therefore, we employ an optimized coupling electrode structure as well as a pulsed electron source to demonstrate experimentally that electron excitations at the guide entrance can be greatly reduced. This paves the way towards the direct injection of electrons into motional quantum states of the guide.

This thesis deals with the study and comparison of on-chip LC Oscillators, used in energy recovery clocking, in terms of Power, Area of Inductor and change in load capacitance. Simulations show how the frequency of the two oscillators varies when the load capacitance is changed from 5pF to 105pF for a given network resistance. A conventional driver is used as a reference for comparisons of power consumptions of the two oscillators. It has been shown that the efficiency of the two oscillators can exceed that of a conventional driver provided the distribution network resistance is low and the on-chip inductor has a high enough Q value. Conclusions drawn from the simulations, using network resistances varying from 0Ω to 4Ω, show that the selection of the oscillator would depend on the network resistance and the amount of area available for the inductors.

This thesis uses a case study of the Community Home Energy Retrofit Project (CHERP) and it analyzes the larger statewide effort in California to increase energy efficiency in existing residential buildings to reduce greenhouse gas emissions. CHERP’s primary strategy is to embed itself into a community, educate residents on the multiple benefits of energy efficiency, and inspire them to take energy-saving actions in their own homes. It then builds its own community by connecting like-minded individuals together and provides an opportunity for them to exercise their political agency. This thesis analyzes CHERP’s effort in the context of the political, social, and economic climate of California. It identifies three obstacles for widespread energy efficiency adoption: one, CHERP’s lack of funding to support permanent staff and pay for collateral materials; two, low access to energy efficiency measures for low-income households and renters; and three, a lack of high quality home performance contractors that perform energy efficiency upgrades utilizing a whole-house energy systems approach. The thesis concludes with five recommendations to overcome these issues.

There is seemingly a never-ending consumer demand for mobileterminals such as cellular phones and personal digitalassistants (PDAs). Each new generation of terminals comes withmore elaborate functions than in the previous generation. Thistrend results in a higher performance demand on the computerarchitecture that performs the required computations within theterminal. To satisfy the projected requirements on cominggenerations of mobile terminals, we propose an architecturethat when intelligently managed can provide the necessaryperformance at low power and energy consumption. Thisarchitecture, a chip-multiprocessor (CMP), thus amulti-processor implemented on a single chip, has incombination with adaptive scheduling strategies the potentialto efficiently fullfill future requirements.

This licentiate thesis spans over several studies done onthe effectiveness of the adaptive CMP. In our studies, we haveshown that an adaptive CMP can satisfy the same performancerequirements as a comparable uni-processor, still consumingless power and energy. Furthermore, we have made an effort toaccurately model the workload behaviour of mobile terminals,which is of paramount importance when comparing candidatearchitectures. In the future, apart from proposing moreadaptive scheduling techniques, we expect to do more thoroughstudies on workload modeling as well as on the operating systeminfluence on the overall performance and power consumption.

Magnetoelectric (ME) effect is defined as the change in dielectric polarization (P) of a material under an applied magnetic field (H) or an induced magnetization (M) under an external electric field (E). ME materials have attracted number of investigators due to their potential for improving applications such as magnetic field sensors, filters, transformers, memory devices and energy harvesters. It has been shown both experimentally and theoretically that the composite structures consisting of piezoelectric and magnetostrictive phases possess stronger ME coupling in comparison to that of single phase materials. Giant magnetoelectric effect has been reported in variety of composites consisting of bulk-sized ME composites and thin film ME nanostructures. In this dissertation, novel ME composite systems are proposed, synthesized and characterized in both bulk and thin films to address the existing challenges in meeting the needs of practical applications. Two applications were the focused upon in this study, tunable transformer and dual phase energy harvester, where requirements can be summarized as: high ME coefficient under both on-resonance and off-resonance conditions, broad bandwidth, and low applied DC bias. In the first chapter, three challenges related to the conventional ME behavior in bulk ME composites have been addressed (1) The optimized ME coefficient can be achieved without external DC magnetic field by using a self-biased ME composite with a homogenous magnetostrictive material. The mechanism of such effect and its tunability are studied; (2) A near-flat ME response regardless of external magnetic field is obtained in a self-biased ME composite with geometry gradient structure; (3) By optimizing interfacial coupling with co-firing techniques, the ME coefficient can be dramatically enhanced. Theses co-fired ME laminates not only exhibit high coupling coefficient due to direct bonding, but also illustrate a self-biased effect due to the built-in stress during co-sintering process. These results present significant advancement toward the development of multifunctional ME devices since it eliminates the need for DC bias, expands the working bandwidth and enhances the ME voltage coefficient. Next, magnetoelectric nanocomposites were developed for understanding the nature of the growth of anisotropic thin film structures. In this chapter following aspects were addressed: (1) Controlled growth of nanostructures with well-defined morphology was obtained. Microstructure and surface morphology evolution of the piezoelectric BaTiO3 films was systematically analyzed. A growth model was proposed by considering the anisotropy of surface energy and the formation of twin lamellae structure within the frame work of Structure Zone Model (SZM) and Dynamic Scaling Theory (DST). In parallel to BaTiO3 films, well-ordered nanocomposite arrays [Pb1.1(Zr0.6Ti0.4)O3/CoFe2O4] with controlled grain orientation were developed and investigated by a novel hybrid deposition method. The influence of the pre-deposited template film orientation on the growth of ME composite array was studied. (2) PZT/CFO/PZT thick composite film and BTO/CFO thin film were synthesized using sol-gel deposition (SGD) and pulsed laser deposition (PLD) techniques, respectively. The HRTEM analysis revealed local microstructure at the interface of consecutive constituents. The interfacial property variation of these films was found to affect the coupling coefficient of corresponding ME nanocomposites. Subsequently, a novel complex three-dimensional ME composite with highly anisotropic structure was developed using a hybrid synthesis method. The influence of growth condition on the microstructure and property of the grown complex composites was studied. The film with highly anisotropic structure was found to possess tailored ferroelectric response indicating the promise of this synthesis method and microstructure. Based on the laminated ME composites, three types of ME tunable transformer designs were designed and fabricated. The goal was to develop a novel ME transformer with tunable performance (voltage gain and/or working resonance frequency) under applied DC magnetic field. Conventional ME transformers need either winding coil or large external magnetic field to achieve the tunable feature. Considering the high ME coupling of ME laminate, two ME transformers were developed by epoxy bonding Metglas with transversely/longitudinally poled piezoelectric ceramic transformer. The influence of different operation modes toward magnetoelectric tunability was analyzed. In addressing the concern of the epoxy bonding interface, a co-fired ME transformer with unique piezoelectric transformer/magnetostrictive layer/piezoelectric transformer trilayer structure was designed. The design and development strategy of thin film ME transformer was discussed to illustrate the potential for ME transformer miniaturization and on-chip integration. Lastly, motivated by the increasing demand of energy harvesting (EH) systems to support self-powered sensor nodes in structural health monitoring system, a magnetoelectric composite based energy harvester was developed. The development and design concept of the magnetoelectric energy harvester was systematically discussed. In particular, the first dual-phase self-biased ME energy harvester was designed which can simultaneously harness both vibration and stray magnetic field (Hac) in the absence of DC magnetic field. Strain distribution of the EH was simulated using the finite element model (FEM) at the first three resonance frequencies. Additionally, the potential of transferring this simple EH structure into MEMS scalable components was mentioned. These results provide significant advancement toward high energy density multimode energy harvesting system.
Ph. D.

Over the last two decades, functions of the embedded systems have evolved from simple real-time control and monitoring to more complicated services. Embedded systems equipped with powerful chips can provide the performance that computationally demanding information processing applications need. However, due to the power issue, the easy way to gain increasing performance by scaling up chip frequencies is no longer feasible. Recently, low-power architecture designs have been the main trend in embedded system designs. In this dissertation, we present our approaches to attack the energy-related issues in embedded system designs, such as thermal issues in the 3D chip multiprocessor (CMP), the endurance issue in the phase-change memory(PCM), the battery issue in the embedded system designs, the impact of inaccurate information in embedded system, and the cloud computing to move the workload to remote cloud computing facilities. We propose a real-time constrained task scheduling method to reduce peak temperature on a 3D CMP, including an online 3D CMP temperature prediction model and a set of algorithm for scheduling tasks to different cores in order to minimize the peak temperature on chip. To address the challenging issues in applying PCM in embedded systems, we propose a PCM main memory optimization mechanism through the utilization of the scratch pad memory (SPM). Furthermore, we propose an MLC/SLC configuration optimization algorithm to enhance the efficiency of the hybrid DRAM + PCM memory. We also propose an energy-aware task scheduling algorithm for parallel computing in mobile systems powered by batteries. When scheduling tasks in embedded systems, we make the scheduling decisions based on information, such as estimated execution time of tasks. Therefore, we design an evaluation method for impacts of inaccurate information on the resource allocation in embedded systems. Finally, in order to move workload from embedded systems to remote cloud computing facility, we present a resource optimization mechanism in heterogeneous federated multi-cloud systems. And we also propose two online dynamic algorithms for resource allocation and task scheduling. We consider the resource contention in the task scheduling.

Depuis quelques années, les réseaux optiques sur puce (ONoC) sont devenus une solution intéressante pour surpasser les limitations des interconnexions électriques, compte tenu de leurs caractéristiques attractives concernant la consommation d’énergie, le délai de transfert et la bande passante. Cependant, les éléments optiques nécessaires pour définir un tel réseau souffrent d’imperfections qui introduisent des pertes durant les communications. De plus, l'utilisation de la technique de multiplexage en longueurs d'ondes (WDM) permet d'augmenter les performances, mais introduit de nouvelles pertes et de la diaphonie entre les longueurs d'ondes, ce qui a pour effet de réduire le rapport signal sur bruit et donc la qualité de la communication. Les contributions présentées dans ce manuscrit adressent cette problématique d’amélioration de performance des liens optiques dans un ONoC. Pour cela, nous proposons tout d’abord un modèle analytique des pertes et de la diaphonie dans un réseau optique sur puce WDM. Nous proposons ensuite une méthodologie pour améliorer les performances globales du système s'appuyant sur l'utilisation de codes correcteurs d'erreurs. Nous présentons deux types de codes, le premier(Hamming) est d'une complexité d'implémentation faible alors que le second(Reed-Solomon) est plus complexe, mais offre un meilleur taux de correction. Nous avons implémenté des blocs matériels supportant ces corrections d'erreurs avec une technologie 28nm FDSOI. Finalement, nous proposons la définition d'une interface complète entre le domaine électrique et le domaine optique permettant d'allouer les longueurs d'ondes, de coder l'information, de sérialiser le flux de données et de contrôler le driver du laser pour obtenir la modulation à la puissance optique souhaitée
Electrical Network-on-Chip (ENoC) has long been considered as the de facto technology for interconnects in multiprocessor systems-on-chip (MPSoCs). However, with the increase of the number of cores integrated on a single chip, ENoCs are less and less suitable to adapt the bandwidth and latency requirements of nowadays complex and highly-parallel applications. In recent years, due to power consumption constraint, low latency, and high data bandwidth requirements, optical interconnects became an interesting solution to overcome these limitations. Indeed, Optical Networks on Chip (ONoC) are based on waveguides which drive optical signals from source to destination with very low latency. Unfortunately, the optical devices used to built ONoCs suffer from some imperfections which introduce losses during communications. These losses (crosstalk noises and optical losses) are very important factors which impact the energy efficiency and the performance of the system. Furthermore, Wavelength Division Multiplexing (WDM) technology can help the designer to improve ONoC performance, especially the bandwidth and the latency. However, using the WDM technology leads to introduce new losses and crosstalk noises which negatively impact the Signal to Noise Ratio (SNR) and Bit Error Rate (BER). In detail, this results in higher BER and increases power consumption, which therefore reduces the energy efficiency of the optical interconnects. The contributions presented in this manuscript address these issues. For that, we first model and analyze the optical losses and crosstalk in WDM based ONoC. The model can provide an analytical evaluation of the worst case of loss and crosstalk with different parameters for optical ring network-on-chip. Based on this model, we propose a methodology to improve the performance and then to reduce the power consumption of optical interconnects relying on the use of forward error correction (FEC). We present two case studies of lightweight FEC with low implementation complexity and high error-correction performance under 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology. The results demonstrate the advantages of using FEC on the optical interconnect in the context of the CHAMELEON ONoC. Secondly, we propose a complete design of Optical Network Interface (ONI) which is composed of data flow allocation, integrated FECs, data serialization/deserialization, and control of the laser driver. The details of these different elements are presented in this manuscript. Relying on this network interface, an allocation management to improve energy efficiency can be supported at runtime depending on the application demands. This runtime management of energy vs. performance can be integrated into the ONI manager through configuration manager located in each ONI. Finally, the design of an ONoC configuration sequencer (OCS), located at the center of the optical layer, is presented. By using the ONI manager, the OCS can configure ONoC at runtime according to the application performance and energy requirements

Storage of biomass is often associated with problems such as heat development, drymatter losses and reduction of fuel quality. The rise in temperature can potentiallycause a risk of self-ignition in the fuel storage. Moreover, emissions from storage pilescan cause health problems in the surrounding. The dry matter losses and reduction offuel quality can have economical effects. The aim of this thesis project is to developguidelines on how to store large amount of biomass at Vattenfalls heat and powerplants in an optimal way. Storage trials at Idbäckens CHP were done in order to studythe effect of storage on fuel quality, dry matter losses and temperature development.Two storage trials were performed over six weeks with waste wood chips and stemwood chips stored in about 4.5 m high outdoor piles. A trial over four days in whichwaste wood chips was placed on a heated surface was evaluated. A study to test thepossibility of using waste heat to dry waste wood chips was performed.Small but not negligible dry matter losses were observed in both of the piles of storedmaterial. The largest weekly losses were found during the first week of storage and adeclining behavior could thereafter be seen. The accumulated losses during six weeksof storage were 2.0 % and 1.7 % respectively, for waste wood and stem wood. Storageduring six weeks of waste wood and newly chipped stem wood did not cause anymajor deterioration of the fuel quality as such, beside the substance losses.No drying effect could be seen in the heated surface trial. The surface became warm,about 50°C, but it was not sufficient to dry the chips. The conclusion is that it is notpossible to dry large amount of chips on a heated surface with the design used hereand during four days.The overall conclusion is that in order to minimize the dry matter losses the materialshould be handled according to the LIFO (last in first out) principle. Wheneverpossible, try to purchase fuel that has been stored for a while since the more easilydegraded compounds has already been degraded through microbial activity. There is apossibility that the largest losses has already occurred. Furthermore, try also tocomminute the material (reduce the particle size) at the plant and as close in time tocombustion as possible.

The path towards realizing next-generation petascale and exascale computing is increasingly dependent on building supercomputers with unprecedented numbers of processors. Given the rise of multicore processors, the number of network endpoints both on-chip and off-chip is growing exponentially, with systems in 2018 anticipated to contain thousands of processing elements on-chip and billions of processing elements system-wide. To prevent the interconnect from dominating the overall cost of future systems, there is a critical need for scalable interconnects that capture the communication requirements of target ultrascale applications. It is therefore essential to understand high-end application communication characteristics across a broad spectrum of computational methods, and utilize that insight to tailor interconnect designs to the specific requirements of the underlying codes. This work makes several unique contributions towards attaining that goal. First, the communication traces for a number of high-end application communication requirements, whose computational methods include: finite-difference, lattice-Boltzmann, particle-in-cell, sparse linear algebra, particle mesh ewald, and FFT-based solvers. This thesis presents an introduction to the fit-tree approach for designing network infrastructure that is tailored to application requirements. A fit-tree minimizes the component count of an interconnect without impacting application performance compared to a fully connected network. The last section introduces a methodology for reconfigurable networks to implement fit-tree solutions called Hybrid Flexibly Assignable Switch Topology (HFAST). HFAST uses both passive (circuit) and active (packet) commodity switch components in a unique way to dynamically reconfigure interconnect wiring to suit the topological requirements of scientific applications. Overall the exploration points to several promising directions for practically addressing both the on-chip and off-chip interconnect requirements of future ultrascale systems.
Master of Science

Power consumption of CMOS digital logic designs has increased rapidly for the last several years. It has become an important issue, not only in battery-powered applications, but also in high-performance digital designs because of packaging and cooling requirements. At multi-GHz clock rates in use today, charging and discharging CMOS gates and wires, especially in clocks with their relatively large capacitances, leads to significant power consumption. Recovering and recycling the stored charge or energy about to be lost when these nodes are discharged to ground is a potentially good strategy that must be explored for use in future energy-efficient design methodologies. This dissertation investigates a number of novel clock energy recycling techniques to improve the overall power dissipation of high-performance logic circuits. If efficient recycling energy of the clock network can be demonstrated, it might be used in many high-performance chip designs, to lower power and save energy. A number of chip prototypes were designed and constructed to demonstrate that this energy can be successfully recycled or recovered in different ways: • Recycling clock network energy by supplying a secondary DC-DC power converter: the output of this power converter can be used to supply another region of the chip, thereby avoiding the need to draw additional energy from the primary supply. One test chip demonstrates energy in the final clock load can be recycled, while another demonstrates that clock distribution energy can be recycled. • Recovering clock network energy and returning it back to the power grid: each clock cycle, a portion of the energy just drawn from the supply is transferred back at the end of the cycle, effectively reducing the power consumption of the clock network. The recycling methods described in this thesis are able to preserve the more ideal square clock shape which has been a limitation of previous work in this area. Overall, the results provided in this thesis demonstrate that energy recycling is very promising and must be pursued in a number of other areas of the chip in order to obtain an energy-efficient design.

Shifting the design entry point up to the system level is the most important countermeasure adopted to manage the increasing complexity of SoCs. The reason is that decisions taken at this level, early in the design cycle, have the greatest impact on the final design in terms of performance, energy efficiency and silicon area occupation. However, taking decisions at this level is very difficult, since the design space is extremely wide, and it has so far been mostly a manual activity. Efficient system-level estimation tools are therefore necessary to enable proper design-space exploration and the development of system-level synthesis tools. Proposing an efficient approach to system-level estimation is the main contribution of this thesis. The approach consists of three layers. The bottom layer relies on building a library of IP energy and performance models, where each IP functionality is pre-characterized. Characterization is done only once at the gate level, which gives high accuracy to the approach. The implementation of an energy and performance model for a Leon3 processor is reported as an example. The impact that the IP-to-IP communication infrastructure has over individual IP properties is also taken into account, for bus-based and NoC-based architectures. The intermediate layer is where the actual estimation takes place. At this level, applications are run and profiled on a development host (a common PC). This allows us to create a trace of the executed source code, which is then mapped to the assembly code of the target architecture. This operation allows a trace of target instructions to be indirectly built and confers high speed on the whole methodology. Once the target trace is inferred, energy and performance figures can be extracted by using the IP models from the bottom layer. To make the whole process possible, changes are made to the GNU GCC compiler. Estimation is shown for a few common image/video codec applications. The top layer is a refinement layer that accounts for the presence of caches and for the fact that multiple applications normally run concurrently, share the same resources and are controlled by an operating system. Statistical models are built to account for the impact of each of these components. An MPSoC hosting up to 15 processors and using both fixed-priority and round robin bus arbitration is used for modeling bus contention. The RTEMS operating system is taken as a reference to model the OS impact. Validation for each layer is also carried out. The results show that the approach is within 15% of gate-level accuracy and exhibits an average speed-up of 30X compared to transaction-level modeling (TLM).
QC 20110315

In recent decades, the use of electronic systems, especially embedded systems such as mobile phones has been expanding rapidly. Such products use minimal amount of materials, generate less waste and noise, save space, and are considered cost-effective and attractive. In such devices, consideration needs to be given to both high power density and high chip working temperature.  According to the advanced scaling technology, leakage power becomes a major issue in terms of power consumption and this in turn influences temperature. Consequently, energy optimization is an important issue in the design of such electronic products.   Techniques for energy optimization have been proposed for circuit-level up to the system-level. This study is focused on a system-level model for a multiprocessor system, considering the inter-dependency between leakage power and temperature. The study applies an on-line temperature-aware dynamic voltage selection (DVS) approach to save energy. The method is evaluated and compared to the static approach, which assumes that tasks always execute their worst case number of clock cycles (WNC) allowing for the exploitation of only the static slack. On-line thermal aware DVS allows the exploitation of both the static and dynamic slacks, since the actual number of clock cycles is usually less than the WNC.

Ultracold atomic gases have proven to be an excellent tool for research in quantum systems. A Bose gas can be trapped on an atom chip using very well defined and tunable spatially-dependent potentials. The proximity of the atoms to the chip permits the use of low currents allowing for highly accurate temporal changes. Excellent experimental apparatus is needed to achieve Bose-Einstein condensation with a sufficient atom number to study low-dimensional physics. The setup described in this document utilises a set of current-carrying structures on top of which an atom chip sits. For improved atom loading rate, a two-dimensional loading stage was added, extending the lifetime of the magnetic trap. From this loading stage to the atom chip, Bose-Einstein condensation of 105 Rubidium-87 atoms was achieved in less than 30 s, allowing for a large rate of experimental cycles. The high spatial and temporal tunability of this setup results in the ability to split the atomic cloud and quench the trapping potential geometry. Maximising the ratio between trapping frequencies for different spatial directions leads to the system presenting features of a one-dimensional gas. Manipulating the coherence dynamics of a one-dimensional Bose-Einstein condensate creates fluctuations in the phase properties of the wavefunction. These fluctuations are observed as atom density perturbations after releasing the trapping potentials, and are a tool for temperature measurements. When the cloud of atoms is positioned at a few tens of micrometres from the surface of the atom chip, corrugations in the microstructures of the chip affect the trapping potentials at very low temperatures 1 μK. This effect is simulated and quantified in the thesis, with the aim of improving future setups. Additionally, the effect is explored for microscopy purposes. The behaviour of a Bose-Einstein condensate, especially the expansion rate, has long been studied. In this thesis, the Gross-Pitaevskii Equation is introduced, finding its numerical solutions to the two-dimensional and three-dimensional forms, using the Split-Step Fourier Method. The results show very good agreement with the experimental results, as well as with other well- established theories of condensates. The creation of such a toolbox opens up the opportunity to further investigate the coherence dynamics of low-dimensional systems.

Thesis (Ph. D.)--Michigan State University. Dept. of Electrical and Computer Engineering, 2006.
Title from PDF t.p. (viewed on Nov. 17, 2008) Includes bibliographical references (p. 183-195). Also issued in print.

Computer hardware researchers have perennially focussed on improving the performance of computers while stipulating the energy consumption under a strict budget. While several innovations over the years have led to high performance and energy efficient computers, more challenges have also emerged as a fallout. For example, smaller transistor devices in modern multi-core systems are afflicted with several reliability and security concerns, which were inconceivable even a decade ago. Tackling these bottlenecks happens to negatively impact the power and performance of the computers. This dissertation explores novel techniques to gracefully solve some of the pressing challenges of the modern computer design. Specifically, the proposed techniques improve the reliability of on-chip communication fabric under a high power supply noise, increase the energy-efficiency of low-power graphics processing units, and demonstrate an unprecedented security loophole of the low-power computing paradigm through rigorous hardware-based experiments.

Thesis (M.Sc.Eng.)PLEASE NOTE: Boston University Libraries did not receive an Authorization To Manage form for this thesis or dissertation. It is therefore not openly accessible, though it may be available by request. If you are the author or principal advisor of this work and would like to request open access for it, please contact us at open-help@bu.edu. Thank you.
The exploration and production of oil and gas resources require innovative information acquisition strategies for wellbore environments to improve reservoir management. In this study, a microfluidic channel data retrieval platform was proposed for multiple sensor chip manipulation, wireless charging and information extraction in fluidic mediums. The working principle of near-field magneto inductive coupling was investigated and a prototype of a microfluidic channel integrated with a spiral reader antenna was designed and fabricated. Sensor chip manipulations and dynamic couplings between readers and sensors were demonstrated inside the proposed microfluidic channel. Furthermore, solid fluidic interaction between sensors and flows was analyzed. Comsol simulation was conducted to quantitatively characterize flow drag forces inside the channel. To prevent communication interference between sensors in the proposed coupling region, sensor separation strategies based on side channel and meander channel design were proposed and realized to separate sensors one by one by the desired distance. To enhance the efficiency of the sensor separation process, a new channel design based on a spinning blade with real-time image processing was also developed for feedback control of separation. Additionally, a 500-micron cubic sensor antenna was cut by a dicing saw and assembled into an 800-micron cubic package. Magneto inductive couplings between readers and the assembly package were conducted out of the channel. The results show that the coupling effect is strongly related with the orientation between the reader and the assembly package. Finally, the assembly package control with desired velocity and direction in oil mediums was successfully realized inside the channel.
2031-01-01

A Chip Multiprocessor for a Large-scale Neural SimulatorEustace PainkrasA thesis submitted to The University of Manchesterfor the degree of Doctor of Philosophy, 17 December 2012The modelling and simulation of large-scale spiking neural networks in biologicalreal-time places very high demands on computational processing capabilities andcommunications infrastructure. These demands are difficult to satisfy even with powerfulgeneral-purpose high-performance computers. Taking advantage of the remarkableprogress in semiconductor technologies it is now possible to design and buildan application-driven platform to support large-scale spiking neural network simulations.This research investigates the design and implementation of a power-efficientchip multiprocessor (CMP) which constitutes the basic building block of a spikingneural network modelling and simulation platform. The neural modelling requirementsof many processing elements, high-fanout communications and local memoryare addressed in the design and implementation of the low-level modules in the designhierarchy as well as in the CMP. By focusing on a power-efficient design, the energyconsumption and related cost of SpiNNaker, the massively-parallel computation engine,are kept low compared with other state-of-the-art hardware neural simulators.The SpiNNaker CMP is composed of many simple power-efficient processors withsmall local memories, asynchronous networks-on-chip and numerous bespoke modulesspecifically designed to serve the demands of neural computation with a globallyasynchronous, locally synchronous (GALS) architecture.The SpiNNaker CMP, realised as part of this research, fulfills the demands of neuralsimulation in a power-efficient and scalable manner, with added fault-tolerancefeatures. The CMPs have, to date, been incorporated into three versions of SpiNNakersystem PCBs with up to 48 chips onboard. All chips on the PCBs are performing successfully, during both functional testing and their targeted role of neural simulation.

付記する学位プログラム名: 京都大学卓越大学院プログラム「先端光・電子デバイス創成学」
京都大学
新制・課程博士
博士(情報学)
甲第23325号
情博第761号
京都大学大学院情報学研究科通信情報システム専攻
(主査)教授 小野寺 秀俊, 教授 大木 英司, 教授 佐藤 高史
学位規則第4条第1項該当
Doctor of Informatics
Kyoto University
DFAM

The energy consumption to make the off-chip memory writing and readings are aknown problem. In the image processing field structure from motion simpler compressiontechniques could be used to save energy. A balance between the detected features suchas corners, edges, etc., and the degree of compression becomes a big issue to investigate.In this thesis a deeper study of this balance are performed. A number of more advancedcompression algorithms for processing of still images such as JPEG is used for comparisonwith a selected number of simpler compression algorithms. The simpler algorithms canbe divided into two categories: individual block-wise compression of each image andcompression with respect to all pixels in each image. In this study the image sequences arein grayscale and provided from an earlier study about rolling shutters. Synthetic data setsfrom a further study about optical flow is also included to see how reliable the other datasets are.
Energikonsumtionen för att skriva och läsa till off-chip minne är ett känt problem. Inombildbehandlingsområdet struktur från rörelse kan enklare kompressionstekniker användasför att spara energi. En avvägning mellan detekterade features såsom hörn, kanter, etc.och grad av kompression blir då en fråga att utreda. I detta examensarbete har en djuparestudie av denna avvägning utförts. Ett antal mer avancerade kompressionsalgoritmer förbearbetning av stillbilder som tex. JPEG används för jämförelse med ett antal utvaldaenklare kompressionsalgoritmer. De enklare algoritmerna kan delas in i två kategorier:individuell blockvis kompression av vardera bilden och kompression med hänsyn tillsamtliga pixlar i vardera bilden. I studien är bildsekvenserna i gråskala och tillhandahållnafrån en tidigare studie om rullande slutare. Syntetiska data set från ytterligare en studie om’optical flow’ ingår även för att se hur pass tillförlitliga de andra dataseten är.

Electronic systems of the future require a very high bandwidth communications infrastructure within the system. This way the massive amount of compute power which will be available can be inter-connected to realize future powerful advanced electronic systems. Today, electronic inter-connects between 3D chip-stacks, as well as intra-connects within 3D chip-stacks are approaching data rates of 100 Gbit/s soon. Hence, the question to be answered is how to efficiently design the communications infrastructure which will be within electronic systems. Within this paper approaches and results for building this infrastructure for future electronics are addressed.

Améliorer uniquement les performances et l'efficacité énergétique des transistors n'est pas suffisant pour les futurs systèmes sur puce. Les interconnexions sont également essentielles et ont de graves répercussions sur les performances globales du circuit et l'efficacité énergétique. Le cuivre (Cu) est le matériau d'interconnexion conventionnel qui a aujourd’hui atteint ses limites par suite de l’effet de la miniaturisation. Les effets de barrière et de dispersion induisent une résistivité élevée et une forte éléctromigration aggravent la fiabilité d'interconnexion. Les Nanotubes de carbone (CNT) et les composites de Cuivre et Nanotube de carbone (Cu-CNT) sont intéressants grâce à leur transport balistique, à la grande évolutivité, à la conductivité thermique élevée et à la densité de courant élevée. Dans ce travail, nous étudions les propriétés physiques fondamentales et électriques des CNT et des composite de Cu-CNT de l’échelle atomique à l’échelle macroscopique pour les applications d’interconnexions locales et globales. Nous évaluons les différentes sources de variabilité et leurs impacts sur les performances d'interconnexion des CNT et l'efficacité énergétique. Le dopage basé sur le transfert de charge des CNT est également étudié en tant que moyen important de réduire davantage sa résistivité et d’atténuer les variations de chiralité des CNT ainsi que d’alléger les effets sur la résistance de contact. Les résultats des mesures expérimentales sont utilisés pour démontrer la validité et la précision de nos modèles établis. Les modèles d'interconnexion sont enfin appliqués aux études à l’échelle de portes et de circuits en tant qu'interconnexions locales et globales pour évaluer leurs performances
Improving only the performance and energy efficiency of transistors is not sufficient for future systems-on-chip. On-chip interconnects have become equally critical to transistors and can detriment the system’s performance and energy efficiency. Copper (Cu) is the state-of-the-art interconnect material and is reaching its physical limitations due to scaling. Barrier and scattering effects induce high resistivity and electromigration exacerbates interconnect reliability. Carbon Nanotubes (CNTs) and Copper-Carbon Nanotube (Cu-CNT) composite materials are of interest due to ballistic transport, high scalability, high thermal conductivity, and high current density. We investigate from fundamental atomistic level to macroscopic level the physical understanding and electrical compact modeling on CNT and Cu-CNT composite for on-chip local and global interconnect applications. We evaluate and assess the different sources of variations and their impacts on CNT interconnect performance and energy efficiency. Charge transfer based doping of CNT is also investigated as an alternative method to further reduce its resistivity, mitigate CNT chirality variations and contact resistance drawbacks. Experimental measurement results are used to demonstrate the validity and accuracy of our established models. The interconnect models are finally applied to the gate- and circuit- level studies as local and global interconnects to evaluate their performance

Esta tese de doutorado apresenta o projeto de uma arquitetura de memória híbrida energeticamente eficiente baseada em memórias do tipo scratchpad (Hy-SVM) para a codificação paralela de vídeos segundo o padrão HEVC. A codificação de vídeo se destaca como uma parte extremamente complexa nas aplicações de processamento de vídeo. O padrão HEVC traz inovações que complicam fortemente os requerimentos de memória de tais aplicações, principalmente devido a: (a) novas estruturas de codificação, as quais agravam a complexidade computacional por proporcionarem muitas modos possíveis de codificação que devem ser analisados; além do (b) suporte de alto nível à paralelização da codificação por meio do particionamento das unidades de codificação em múltiplos Tiles, o qual provê a aceleração da performance dos codificadores, porém, ao mesmo tempo, adiciona grandes desafios à infraestrutura de memória. O principal gargalo em termos de comunicação com a memória externa e de armazenamento interno (dentro do chip do codificador) é dados pelas informações dos quadros de referência: que consiste em uma série de quadros completos já codificados (e reconstruídos) que devem ser mantidos em memória e acessados de forma intensa durante o processamento dos quadros futuros. Devido ao grande volume de dados que são necessários para representar os quadros de referência, estes são tipicamente armazenados na memória externa dos codificadores (principalmente quando vídeos de alta e ultra alta resolução são processados) A arquitetura proposta Hy-SVM está inserida em um sistema de codificação baseado no particionamento dos quadros do vídeo de entrada em múltiplos Tiles, de forma a habilitar a codificação paralela das informações segundo o padrão HEVC: neste cenário, cada Tile é assinalado para uma específica unidade de processamento do codificador HEVC, o qual executa o processamento dos diferentes Tiles em paralelo. A ideias chave da arquitetura Hy- SVM incluem: projeto e gerenciamento de memórias para a aplicação específica de codificação de vídeo; uso de múltiplos níveis de memórias privadas e compartilhadas, com o objetivo de explorar o reuso de dados intra-Tile e inter-Tiles de forma combinada; uso de memórias do tipo scratchpad (SPMs) para o armazenamento interno da informações de forma eficiente em termos de consumo de energia; projeto de memórias híbridas utilizando as tecnologias SRAM e STTRAM como base. Uma metodologia de projeto é proposta para a arquitetura Hy-SVM, a qual aproveita propriedades específicas da aplicação para, de forma adequada, definir os parâmetros de projeto das memórias híbridas. De forma a prover adaptação em tempo de execução (para ambas as memórias on-chip e off-chip), a arquitetura Hy-SVM integra uma camada de gerenciamento composta pelas seguintes estratégias (1) predição do overlap (sobreposição de acessos), o qual busca identificar o comportamento dos acessos redundantes entre diferentes unidades de processamento do codificador HEVC a partir da análise dos acessos à memória das codificações dos quadros passados do vídeo, com o objetivo de aumentar o potencial de exploração do reuso de dados inter-Tiles; (2) gerenciamento dos acessos à memória externa, responsável por balancear a vazão de dados com a memória acumulada entre as múltiplas unidades de processamento do codificador HEVC paralelo, com o objetivo de melhorar o uso do barramento de comunicação com a memória externa; e (3) gerenciamento de dados das SPMs implementadas a partir de células de memória STT-RAM, o qual alivia estas células de acessos de escrita com alta atividade de chaveamento dos bits armazenados, com o objetivo de aumentar o tempo de vide destas células, bem como reduzir as penalidades relativas à ineficiência dos acessos de escrita nas memórias STT-RAM. O conhecimento específico da aplicação foi utilizado nas estratégias de gerenciamento em tempo de execução das seguintes formas: explorando parâmetros da codificação HEVC e realizando monitorando em tempo real dos acessos à memória realizados pelo codificador Estas informações são utilizadas tanto pelas técnicas de gerenciamento, quanto pelas metodologias de projeto das memórias. Baseadas nas decisões tomadas pela camada de gerenciamento, a arquitetura Hy-SVM integra unidades de gerenciamento de acessos à memória (memory access management units – MAMUs) para controlar as dinâmicas de acesso das memórias SPM privadas e compartilhadas. Além disso, unidades adaptativas de gerenciamento de potência (adaptive power management units – APMUs) são capazes de reduzir o consumo de energia interno do chip do codificador a partir das estimativas precisas de formação dos overlaps. Os resultados obtidos por meio dos experimentos realizados demonstram economias de consumo energético da arquitetura Hy-SVM, quando comparada a trabalhos relacionados, sob diversos cenários de teste. Quando comparada a estratégias de reuso de dados tradicionais para codificadores de vídeo, como o esquema Level-C, a exploração do reuso de dados combinado nos níveis intra-Tile e inter-Tiles provê 69%-79% de redução de energia. Considerando as arquiteturas de memória de vídeo com foco no padrão HEVC, os ganhos variaram desde 2,8% (pior caso) até 67% (melhor caso) Da perspectiva do consumo de energia relacionado à comunicação com a memória externa, a arquitetura Hy-SVM é capaz de melhorar o reuso de dados (por explorar também o reuso de dados inter-Tiles), resultando em um consumo de energia on-chip 11%-17% menor. Além disso, as APMUs contribuem para reduzir o consumo de energia on-chip da arquitetura Hy-SVM em 56%-95%, para os cenários de teste analisados. Desta forma, comparada aos trabalhos relacionados, a arquitetura Hy-SVM apresenta o menor consumo energético on-chip. O gerenciamento da vazão da comunicação com a memória externa é capaz de reduzir as variações de largura de banda em 37%-83%, quando comparado à ordem tradicional de processamento, para cenários de teste com 4 e 16 Tiles sendo processados em paralelo pelo codificador HEVC. O gerenciamento de dados pôde, de forma significativa, estender o tempo de vida das células de memória STT-RAM, alcançando 0,83 de tempo de vida normalizado (métrica adotada para comparação, ficando muito próximo do caso ideal). Além disso, as sobrecargas causadas pela implementação das unidades de gerenciamento não afetam de foram significativa a performance e a eficiência energética da arquitetura Hy- SVM propostas por este trabalho.
This Thesis presents the design of an energy-efficient hybrid scratchpad video memory architecture (called Hy-SVM) for parallel High-Efficiency Video Coding. Video coding stands out as a high complex part in the video processing applications. HEVC standard brought innovations that increase the memory requirements, mainly due to: (a) the novel coding structures, which aggravates the computational complexity by providing a wider range of possibilities to be analyzed; and (b) the high-level parallelism features provided by the Tiles partitioning, which provides performance acceleration, but, at the same time, strongly adds hard challenges to the memory infrastructure. The main bottleneck in terms of external memory transmission and on-chip storage is the reference frames data: which consists of already coded (and reconstructed) entire frames that must be stored and intensively accessed during the encoding process of future frames. Due to the large volume of data required to represent the reference frames, they are typically stored in the external memory (especially when highdefinition videos are targeted). The proposed Hy-SVM architecture is inserted in a video coding system, which is based on multiple Tiles partitioning to enable parallel HEVC encoding: each Tile is assigned to a specific processing unit. The key ideas of Hy-SVM include: applicationspecific design and management; combined multiple levels of private and shared memories that jointly exploit intra-Tile and inter-Tiles data reuse; scratchpad memories (SPMs) as energyefficient on-chip data storage; combined SRAM and STT-RAM hybrid memory (HyM) design We propose a design methodology for Hy-SVM that leverages application-specific properties to properly define the HyMs parameters. In order to provide run-time adaptation (for both offand on-chip parts), Hy-SVM integrates a memory management layer composed of: (1) overlap prediction, which has the goal of identifying the redundant memory access behavior by analyzing monitored past frames encoding to increase inter-Tiles data reuse exploitation; (2) memory pressure management, which aims on balancing the Tiles-accumulated memory pressure targeting on improving external memory communication channel usage; and (3) lifetime-aware data management scheme that alleviates STT-RAM SPMs of high bit-toggling write accesses to increase the their cells lifetime, as well as to reduce overhead issues related to poor write characteristics of STT-RAM. Application-specific knowledge was exploited by inheriting HEVC properties and performing run-time monitoring of memory accesses. Such information is used to properly design the on-chip video memories, as well as being utilized as input parameters of the run-time memory management layer. Based on the run-time decisions from the proposed Hy-SVM management strategies, Hy-SVM integrates distributed memory access management units (MAMUs) to control the access dynamics of private and shared SPMs. Additionally, adaptive power management units (APMUs) are able to strongly reduce on-chip energy consumption due to an accurate overlap prediction The experimental results demonstrate Hy-SVM overall energy savings over related works under various HEVC encoding scenarios. Compared to traditional data reuse schemes, like Level-C, the combined intra-Tile and inter-Tiles data reuse provides 69%-79% of energy reduction. Regarding related HEVC video memory architectures, the savings varied from 2.8% (worst case) to 67% (best case). From the external memory perspective, Hy-SVM can improve data reuse (by also exploiting inter-Tiles data redundancy), resulting on 11%-71%% of reduced off-chip energy consumption. Additionally, our APMUs contribute by reducing on-chip energy consumption of Hy-SVM by 56%-95%, for the evaluated HEVC scenarios. Thus, compared to related works, Hy-SVM presents the lowest on-chip energy consumption. The memory pressure management scheme can reduce the variations in the memory bandwidth by 37%-83% when compared to the traditional raster scan processing for 4- and 16-core parallelized HEVC encoder. The lifetime-aware data management significantly extends the STT-RAM lifetime, achieving 0.83 of normalized lifetime (near to the optimal case). Moreover, the overhead of implementing our management units insignificantly affects the performance and energyefficiency of Hy-SVM.

Hybrid pixel detectors have been demonstrated to provide excellent quality detection of ionising photon radiation, particularly in X-ray imaging. Recently, there has been interest in developing a hybrid pixel detector specifically for photon dosimetry. This thesis is on the design, implementation, and preliminary characterisation of the Dosepix readout chip. Dosepix has 256 square pixels of 220 mm side-length, constituting 12.4 mm2 of photo-sensitive area per detector. The combination of multiple pixels provides many parallel processors with limited input flux, resulting in a radiation dose monitor which can continuously record data and provide a real-time report on personal dose equivalent. Energy measurements are obtained by measuring the time over threshold of each photon and a state machine in the pixel sorts the detected photon event into appropriate energy bins. Each pixel contains 16 digital thresholds with 16 registers to store the associated energy bins. Preliminary measurements of Dosepix chips bump bonded to silicon sensors show very promising results. The pixel has a frontend noise of 120 e-. In low power mode, each chip consumes 15 mW, permitting its use in a portable, battery-powered system. Direct time over threshold output from the hybrid pixel detector assembly reveal distinctive photo-peaks correctly identifying the nature of incident photons, and verification measurements indicate that the pixel binning state machines accurately categorise charge spectra. Personal dose equivalent reconstruction using this data has a flat response for a large range of photon energies and personal dose equivalent rates.

Die Menschheit steht vor der großen Herausforderung der Energieversorgung des 21. Jahrhundert. Nirgendwo ist diese noch dringlicher geworden als im Bereich der Energiespeicherung und Umwandlung. Konventionelle Energie kommt hauptsächlich aus fossilen Brennstoffen, die auf der Erde nur begrenzt vorhanden sind, und hat zu einer starken Belastung der Umwelt geführt. Zusätzlich nimmt der Energieverbrauch weiter zu, insbesondere durch die rasante Verbreitung von Fahrzeugen und verschiedener Kundenelektronik wie PCs und Mobiltelefone. Alternative Energiequellen sollten vor einer Energiekrise entwickelt werden. Die Gewinnung erneuerbarer Energie aus Sonne und Wind sind auf jeden Fall sehr wichtig, aber diese Energien sind oft nicht gleichmäßig und andauernd vorhanden. Energiespeichervorrichtungen sind daher von großer Bedeutung, weil sie für eine Stabilisierung der umgewandelten Energie sorgen. Darüber hinaus ist es eine enttäuschende Tatsache, dass der Akku eines Smartphones jeglichen Herstellers heute gerade einen Tag lang ausreicht, und die Nutzer einen zusätzlichen Akku zur Hand haben müssen. Die tragbare Elektronik benötigt dringend Hochleistungsenergiespeicher mit höherer Energiedichte. Der erste Teil der vorliegenden Arbeit beinhaltet Lithium-Ionen-Batterien unter Verwendung von einzelnen aufgerollten Siliziumstrukturen als Anoden, die durch nanotechnologische Methoden hergestellt werden. Eine Lab-on-Chip-Plattform wird für die Untersuchung der elektrochemischen Kinetik, der elektrischen Eigenschaften und die von dem Lithium verursachten strukturellen Veränderungen von einzelnen Siliziumrohrchen als Anoden in einer Lithium-Ionen-Batterie vorgestellt. In dem zweiten Teil wird ein neues Design und die Herstellung von flexiblen on-Chip, Festkörper Mikrosuperkondensatoren auf Basis von MnOx/Au-Multischichten vorgestellt, die mit aktueller Mikroelektronik kompatibel sind. Der Mikrosuperkondensator erzielt eine maximale Energiedichte von 1,75 mW h cm-3 und eine maximale Leistungsdichte von 3,44 W cm-3. Weiterhin wird ein flexibler und faserartig verwebter Superkondensator mit einem Cu-Draht als Substrat vorgestellt. Diese Dissertation wurde im Rahmen des Forschungsprojekts GRK 1215 "Rolled-up Nanotechnologie für on-Chip Energiespeicherung" 2010-2013, finanziell unterstützt von der International Research Training Group (IRTG), und dem PAKT Projekt "Elektrochemische Energiespeicherung in autonomen Systemen, no. 49004401" 2013-2014, angefertigt. Das Ziel der Projekte war die Entwicklung von fortschrittlichen Energiespeichermaterialien für die nächste Generation von Akkus und von flexiblen Superkondensatoren, um das Problem der Energiespeicherung zu addressieren. Hier bedanke ich mich sehr, dass IRTG mir die Möglichkeit angebotet hat, die Forschung in Deutschland stattzufinden
Human beings are facing the grand energy challenge in the 21st century. Nowhere has this become more urgent than in the area of energy storage and conversion. Conventional energy is based on fossil fuels which are limited on the earth, and has caused extensive environmental pollutions. Additionally, the consumptions of energy are still increasing, especially with the rapid proliferation of vehicles and various consumer electronics like PCs and cell phones. We cannot rely on the earth’s limited legacy forever. Alternative energy resources should be developed before an energy crisis. The developments of renewable conversion energy from solar and wind are very important but these energies are often not even and continuous. Therefore, energy storage devices are of significant importance since they are the one stabilizing the converted energy. In addition, it is a disappointing fact that nowadays a smart phone, no matter of which brand, runs out of power in one day, and users have to carry an extra mobile power pack. Portable electronics demands urgently high-performance energy storage devices with higher energy density. The first part of this work involves lithium-ion micro-batteries utilizing single silicon rolled-up tubes as anodes, which are fabricated by the rolled-up nanotechnology approach. A lab-on-chip electrochemical device platform is presented for probing the electrochemical kinetics, electrical properties and lithium-driven structural changes of a single silicon rolled-up tube as an anode in lithium ion batteries. The second part introduces the new design and fabrication of on chip, all solid-state and flexible micro-supercapacitors based on MnOx/Au multilayers, which are compatible with current microelectronics. The micro-supercapacitor exhibits a maximum energy density of 1.75 mW h cm-3 and a maximum power density of 3.44 W cm-3. Furthermore, a flexible and weavable fiber-like supercapacitor is also demonstrated using Cu wire as substrate. This dissertation was written based on the research project supported by the International Research Training Group (IRTG) GRK 1215 "Rolled-up nanotech for on-chip energy storage" from the year 2010 to 2013 and PAKT project "Electrochemical energy storage in autonomous systems, no. 49004401" from 2013 to 2014. The aim of the projects was to design advanced energy storage materials for next-generation rechargeable batteries and flexible supercapacitors in order to address the energy issue. Here, I am deeply indebted to IRTG for giving me an opportunity to carry out the research project in Germany. September 2014, IFW Dresden, Germany Wenping Si

Esta dissertação de mestrado propõe uma hierarquia de memória para a Estimação de Movimento e de Disparidade (ME/DE) centrada nas referências da codificação, estratégia chamada de Reference-Centered Data Reuse (RCDR), com foco em redução de energia em codificadores de vídeo multivistas (MVC - Multiview Video Coding). Nos codificadores MVC, a ME/DE é responsável por praticamente 98% do consumo total de energia. Além disso, até 90% desta energia está relacionada com a memória do codificador: (a) acessos à memória externa para a busca das referências da ME/DE (45%) e (b) memória interna (cache) para manter armazenadas as amostras da área de busca e enviá-las para serem processadas pela ME/DE (45%). O principal objetivo deste trabalho é minimizar de maneira conjunta a energia consumida pelo módulo de ME/DE com relação às memórias externa e interna necessárias para a codificação MVC. A hierarquia de memória é composta por uma memória interna (a qual armazena a área de busca inteira), um controle dinâmico para a estratégia de power-gating da memória interna e um compressor de resultados parciais. Um controle de buscas foi proposto para explorar o comportamento da busca com o objetivo de atingir ainda mais reduções de energia. Além disso, este trabalho também agrega à hierarquia de memória um compressor de quadros de referência de baixa complexidade. A estratégia RCDR provê reduções de até 68% no consumo de energia quando comparada com estratégias estadoda- arte que são centradas no bloco atual da codificação. O compressor de resultados parciais é capaz de reduzir em 52% a comunicação com memória externa necessária para o armazenamento desses elementos. Quando comparada a técnicas de reuso de dados que não acessam toda área de busca, a estratégia RCDR também atinge os melhores resultados em consumo de energia, visto que acessos regulares a memórias externas DDR são energeticamente mais eficientes. O compressor de quadros de referência reduz ainda mais o número de acessos a memória externa (2,6 vezes menos acessos), aliando isso a perdas insignificantes na eficiência da codificação MVC. A memória interna requerida pela estratégia RCDR é até 74% menor do que estratégias centradas no bloco atual, como Level C. Além disso, o controle dinâmico para a técnica de power-gating provê reduções de até 82% na energia estática, o que é o melhor resultado entre os trabalho relacionados. A energia dinâmica é tratada pela técnica de união dos blocos candidatos, atingindo ganhos de mais de 65%. Considerando as reduções de consumo de energia atingidas pelas técnicas propostas neste trabalho, conclui-se que o sistema de hierarquia de memória proposto nesta dissertação atinge seu objetivo de atender às restrições impostas pela codificação MVC, no que se refere ao processamento do módulo de ME/DE.
This Master Thesis proposes a memory hierarchy for the Motion and Disparity Estimation (ME/DE) centered on the encoding references, called Reference-Centered Data Reuse (RCDR), focusing on energy reduction in the Multiview Video Coding (MVC). In the MVC encoders the ME/DE represents more than 98% of the overall energy consumption. Moreover, in the overall ME/DE energy, up to 90% is related to the memory issues, and only 10% is related to effective computation. The two items to be concerned with: (1) off-chip memory communication to fetch the reference samples (45%) and (2) on-chip memory to keep stored the search window samples and to send them to the ME/DE processing core (45%). The main goal of this work is to jointly minimize the on-chip and off-chip energy consumption in order to reduce the overall energy related to the ME/DE on MVC. The memory hierarchy is composed of an onchip video memory (which stores the entire search window), an on-chip memory gating control, and a partial results compressor. A search control unit is also proposed to exploit the search behavior to achieve further energy reduction. This work also aggregates to the memory hierarchy a low-complexity reference frame compressor. The experimental results proved that the proposed system accomplished the goal of the work of jointly minimizing the on-chip and off-chip energies. The RCDR provides off-chip energy savings of up to 68% when compared to state-of-the-art. the traditional MBcentered approach. The partial results compressor is able to reduce by 52% the off-chip memory communication to handle this RCDR penalty. When compared to techniques that do not access the entire search window, the proposed RCDR also achieve the best results in off-chip energy consumption due to the regular access pattern that allows lots of DDR burst reads (30% less off-chip energy consumption). Besides, the reference frame compressor is capable to improve by 2.6x the off-chip memory communication savings, along with negligible losses on MVC encoding performance. The on-chip video memory size required for the RCDR is up to 74% smaller than the MB-centered Level C approaches. On top of that, the power-gating control is capable to save 82% of leakage energy. The dynamic energy is treated due to the candidate merging technique, with savings of more than 65%. Due to the jointly off-chip communication and on-chip storage energy savings, the proposed memory hierarchy system is able to meet the MVC constraints for the ME/DE processing.

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Elétrica, 2017.
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A evolução da indústria eletrônica que permitiu a implementação de arquiteturas de múltiplos núcleos foi motivada principalmente pelo consumo de energia, pois elas oferecem melhor desempenho e menor dissipação de potência do que os sistemas de processamento único. Com o aumento do número de núcleos em um único chip, a arquitetura de comunicação que interliga esses núcleos começou a ganhar importância. Assim, para resolver os problemas de interconectividade e comunicação dos sistemas em chip, a arquitetura de comunicação do tipo redes-em-chip (NoC - Network-on-Chip) tem sido proposta como uma solução altamente estruturada pela comunidade científica. Estimativas do consumo de energia das arquiteturas de comunicação devem ser realizadas no início do projeto, pois a comunicação do chip representa uma porção significante do total de energia e área consumida pelo chip. Neste contexto, este trabalho objetiva estudar sobre o consumo de energia em NoCs baseadas em dispositivos nanoeletrônicos, por meio de um modelo analítico previamente apresentado. Para obter o consumo total de energia da comunicação do chip, esse modelo utiliza como base alguns parâmetros, tais como, a energia das interconexões e dos roteadores, e a distribuição de probabilidade de comunicação. O objetivo principal deste trabalho é verificar quantitativamente qual a contribuição da nanoeletrônica na redução do consumo de energia, na arquitetura de comunicação do tipo NoC, com ênfase no estudo das interconexões. Desta forma, são feitas simulações para verificar o comportamento da latência e da energia das interconexões que conectam os roteadores da rede, em função dos nós de tecnologia, bem como, é realizada a comparação do consumo de energia entre redes com roteadores nanoeletrônicos e redes com roteadores CMOS. Por fim, é realizada uma análise comparativa entre o consumo de energia de redes com interconexões de cobre e nanotubo de carbono, utilizando roteadores nanoeletrônicos. Os resultados obtidos neste trabalho mostram que a nanoeletrônica é uma tecnologia que aparenta ser uma solução promissora na redução do consumo de energia dos futuros chips e dispositivos.
The evolution of the electronic industry that allowed the implementation of multi-core architectures was motivated mainly by the energy consumption, since they offer better performance and less power dissipation than the single processing systems. With the increase in the number of cores on a single chip, the communication architecture that interconnects these cores began to gain importance. Thus, to solve the problems of interconnectivity and communication of the systems in chip, Networks-on-Chip (NoC) communication architecture has been proposed as a solution highly structured by the scientific community. Estimates of the energy consumption of communication architectures should be carried out at the beginning of the project because the communication of the chip represents a significant portion of the total energy and area consumed by the chip. In this context, this work aims to study energy consumption in NoCs based on nanoelectronic devices, through an analytical model previously presented. To obtain the total energy consumption of the chip communication, this model uses as base some parameters, such as the energy of the interconnections and the routers, and the Communication Probability Distribution. The main objective of this work is to verify quantitatively the contribution of nanoelectronics in the reduction of energy consumption in NoC communication architecture, with emphasis on the study of interconnections. In this way, simulations are performed to verify the latency and energy behavior of the interconnections that connect the routers of the network, as a function of the technology nodes, as well as, the comparison of the energy consumption between networks with nanoelectronic routers and networks with CMOS routers is made. Finally, a comparative analysis was performed between the energy consumption of networks with copper and carbon nanotube interconnections using nanoelectronic routers. The results obtained in this work show that nanoelectronics is a technology that appears to be a promising solution in reducing the energy consumption of future chips and devices.

What are the elementary particles and how did the universe originate are the main driving forces in the high energy physics. In order to further demonstrate the standard model and discover new physics, several detectors are built for the high energy physics experiments. CMOS pixel sensors (CPS) can achieve an attractive tradeoff among many performance parameters, such as readout speed, granularity, material budget, power dissipation, radiation tolerance and integrating readout circuitry on the same substrate, compared with the hybrid pixel sensors and charge coupled devices. Thus, the CPS is a good candidate for tracking the charged particles in vertex detectors and beam telescopes.The power distribution becomes an important issue in the future detectors, since a considerable amount of sensors will be installed. Unfortunately, the independent powering has been proved to fail. In order to solve the power distribution challenges and to provide noiseless voltages, this thesis focuses on the design of a low noise, limited area, low power consumption and full on-chip power management in CPS chips. The CPS are firstly introduced drawing the design requirements of the power management. The power distribution dedicated to CPS chips is then proposed, in which the power management is utilized as the second power conversion stage. Two full on-chip regulators are proposed to generate the analog power supply voltage and the reference voltage required by correlated double sampling operation, respectively. Two prototypes have verified these regulators. They can meet the requirements of CPS. Moreover, the power management techniques and the radiation tolerance design are also presented in this thesis.