Relevant bibliographies by topics / Energy chirp

Academic literature on the topic 'Energy chirp'

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Published: 11 March 2023

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Journal articles on the topic "Energy chirp"

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GUPTA, D. N., and H. SUK. "Electron acceleration to high energy by using two chirped lasers." Laser and Particle Beams 25, no. 1 (February 28, 2007): 31–36. http://dx.doi.org/10.1017/s026303460707005x.

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A scheme for electron acceleration by two crossing chirped lasers has been proposed. An important effect of a frequency chirp of the laser is investigated. Two high intensity chirped lasers, with the same amplitude and frequency, crossing at an arbitrary angle in a vacuum, interfere, causing modulation of laser intensity. An electron experiences a ponderomotive force due to the resultant field of lasers and gains considerable energy. For a certain crossing angle, the electron gains maximum energy due to the constructive interference. A frequency chirp of the laser plays an important role during the electron acceleration in a vacuum. The electron momentum increases due to the frequency chirp. Hence, the electron energy is enhanced during acceleration.
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Cheong, Kah-Meng, Yih-Liang Shen, and Tai-Shih Chi. "Active acoustic scene monitoring through spectro-temporal modulation filtering for intruder detection." Journal of the Acoustical Society of America 151, no. 4 (April 2022): 2444–52. http://dx.doi.org/10.1121/10.0010070.

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An indoor acoustic scene monitoring system using a periodic impulse signal was previously developed. Compared with the impulse signal, the chirp signal is more robust against environmental noise due to its specific spectro-temporal structure. Such specific structure makes the chirp sound easily detected using a spectro-temporal modulation filtering mechanism. In this paper, we demonstrated a system that employs a two-dimensional spectro-temporal filtering mechanism on a Fourier spectrogram to measure the total energy of the reverberations of the chirp signal as the representation of the acoustic scene. The system compares the reverberation energy difference between consecutive chirps with a predefined threshold to automatically detect the change in the acoustic scene. Simulations were conducted in real living rooms with various types of background noise. Test results demonstrated that the proposed system is much more effective than previously developed systems for detecting the acoustic scene changes due to the intruder silently walking in the rooms. In the biggest test room (18 × 9.8 × 2.5 m3) with heavy background noise, the proposed system can still yield a correct identification rate higher than 80% to the intruder walking at 7 m from the microphone without producing any false alarms.
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Liu, Weici. "Effect of initial chirp for input pulse on supercontinuum generation." Journal of Physics: Conference Series 2029, no. 1 (September 1, 2021): 012019. http://dx.doi.org/10.1088/1742-6596/2029/1/012019.

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Abstract The generation of supercontinuum spectrum is a very complex nonlinear process. Based on the nonlinear Schrodinger equation (NLSE), the effect of initial chirp on supercontinuum generation is numerically studied by split-step Fourier (SSF) method. The positive chirp and negative chirp have different effects on the supercontinuum generation. The results show that the energy distribution of supercontinuum spectrum can be improved by selecting appropriate chirp value.
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Mao, Dong, Zhiwen He, Qun Gao, Chao Zeng, Ling Yun, Yueqing Du, Hua Lu, Zhipei Sun, and Jianlin Zhao. "Birefringence-Managed Normal-Dispersion Fiber Laser Delivering Energy-Tunable Chirp-Free Solitons." Ultrafast Science 2022 (July 30, 2022): 1–12. http://dx.doi.org/10.34133/2022/9760631.

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Chirp-free solitons have been mainly achieved with anomalous-dispersion fiber lasers by the balance of dispersive and nonlinear effects, and the single-pulse energy is constrained within a relatively small range. Here, we report a class of chirp-free pulse in normal-dispersion erbium-doped fiber lasers, termed birefringence-managed soliton, in which the birefringence-related phase-matching effect dominates the soliton evolution. Controllable harmonic mode locking from 5 order to 85 order is obtained at the same pump level of ~10 mW with soliton energy fully tunable beyond ten times, which indicates a new birefringence-related soliton energy law, which fundamentally differs from the conventional soliton energy theorem. The unique transformation behavior between birefringence-managed solitons and dissipative solitons is directly visualized via the single-shot spectroscopy. The results demonstrate a novel approach of engineering fiber birefringence to create energy-tunable chirp-free solitons in normal-dispersion regime and open new research directions in fields of optical solitons, ultrafast lasers, and their applications.
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Wu, Yan Jun, Gang Fu, and Peng Yu. "Performance Analysis on Three Methods for Chirp Signal Parameters Estimation Based on FRFT." Advanced Materials Research 989-994 (July 2014): 3942–45. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3942.

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Chirp signal has been used widely in radar signals, and the Fractional Fourier transform is one of the most effective tools to analyze Chirp signal. In this paper, the concept of FRFT and the estimation theory of Chirp signal are introduced firstly. Then, we study three Chirp signal detection algorithms based on character of Chirp signal energy concentrated in a certain FRFT domain. Finally, in order to test the estimation abilities of the frequency modulation rate and the central frequency of FRFT to Chirp signal, and compare the operation time of parameters estimation under different SNR of the three algorithms, we simulate performance of the Three methods, and the final simulation results show that the three method have remarkable capabilities of detecting Chirp signal with low SNR. In contrast, the two-searching method doesn’t need planar search, consumedly reducing the computation cost at the same precision.
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Lu, Xiang, Volker Pickert, Maher Al-Greer, Cuili Chen, Xiang Wang, and Charalampos Tsimenidis. "Temperature Estimation of SiC Power Devices Using High Frequency Chirp Signals." Energies 14, no. 16 (August 11, 2021): 4912. http://dx.doi.org/10.3390/en14164912.

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Silicon carbide devices have become increasingly popular in electric vehicles, predominantly due to their fast-switching speeds, which allow for the construction of smaller power converters. Temperature sensitive electrical parameters (TSEPs) can be used to determine the junction temperature, just like silicon-based power switches. This paper presents a new technique to estimate the junction temperature of a single-chip silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET). During off-state operation, high-frequency chirp signals below the resonance frequency of the gate-source impedance are injected into the gate of a discrete SiC device. The gate-source voltage frequency response is captured and then processed using the fast Fourier transform. The data is then accumulated and displayed over the chirp frequency spectrum. Results show a linear relationship between the processed gate-source voltage and the junction temperature. The effectiveness of the proposed TSEPs is demonstrated in a laboratory scenario, where chirp signals are injected in a stand-alone biased discrete SiC module, and in an in-field scenario, where the TSEP concept is applied to a MOSFET operating in a DC/DC converter.
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Fleming, A. J., A. A. Lindeman, A. L. Carroll, and J. E. Yack. "Acoustics of the mountain pine beetle (Dendroctonus ponderosae) (Curculionidae, Scolytinae): sonic, ultrasonic, and vibration characteristics." Canadian Journal of Zoology 91, no. 4 (April 2013): 235–44. http://dx.doi.org/10.1139/cjz-2012-0239.

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Acoustic signaling is widespread in bark beetles (Scolytinae), although little is known about the physical characteristics of signals, how they are transmitted, and how they differ among behavioural contexts. Signals were studied in the male mountain pine beetle (Dendroctonus ponderosae Hopkins, 1902) during stress, male–female, and male–male interactions. Sounds are broadband with significant energy in the ultrasound (peaks between 15 and 26 kHz) and low amplitude (55 and 47 dB SPL at 2 and 4 cm, respectively), indicating that signaling functions at close range. Signal trains vary among contexts primarily in the proportions of chirp types. Chirps were categorized as being simple or interrupted, with the former having significantly lower tooth strike rates and shorter chirp durations. Stress chirps are predominantly simple with characteristics resembling other insect disturbance signals. Male–female interactions begin with the male producing predominantly interrupted chirps prior to gallery entrance, followed by simple chirps. Male–male (rivalry) chirps are predominantly simple, with evidence of antiphonal calling. Substrate-borne vibrations were detectable with a laser-doppler vibrometer at short distances (1–3 cm), suggesting that sensory organs could be tuned to either air or substrate-borne vibrations. These results have important implications for future research on the function and reception of acoustic signals in bark beetles.
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Wang, Guanglei, Chao Feng, Haixiao Deng, Tong Zhang, and Dong Wang. "Beam energy chirp effects in seeded free-electron lasers." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 753 (July 2014): 56–60. http://dx.doi.org/10.1016/j.nima.2014.03.015.

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Singh, K. P., and H. K. Malik. "Resonant enhancement of electron energy by frequency chirp during laser acceleration in an azimuthal magnetic field in a plasma." Laser and Particle Beams 26, no. 3 (June 19, 2008): 363–69. http://dx.doi.org/10.1017/s0263034608000372.

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AbstractElectron acceleration by a chirped laser pulse in an azimuthal magnetic field in a plasma has been studied. The betatron resonance saturates and the electrons start losing energy beyond a specific point of time without a frequency chirp. The resonance can be maintained for a longer duration and the energy of the electrons can be enhanced if a suitable frequency chirp is introduced. The duration of interaction increases for a lower plasma density or a lower initial electron energy which causes increase in the electron energy gain. The value of magnetic field required for resonance increases with an increase in plasma density and with a decrease in initial electron energy.
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Ginzburg, N. S., I. V. Zotova, R. M. Rozental, A. S. Sergeev, M. Kamada, K. Kurihara, H. Shirasaka, R. Ando, and K. Kamada. "Increasing superradiant pulse peak power by using electron energy chirp." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 507, no. 1-2 (July 2003): 61–64. http://dx.doi.org/10.1016/s0168-9002(03)00838-6.

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Dissertations / Theses on the topic "Energy chirp"

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Lutman, Alberto. "Impact of the wakefields and of an initial energy curvature on a Free Electron Laser." Doctoral thesis, Università degli studi di Trieste, 2010. http://hdl.handle.net/10077/3678.

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2008/2009
For an X-ray free electron laser (FEL), a high-quality electron bunch with low emittance, high peak current and energy is needed. During the phases of acceleration, bunch compression and transportation, the electron beam is subject to radio frequency curvature and to wakefields effects. Thus, the energy profile of the electron beam can present a parabolic profile, which has important electromagnetic effects on the FEL process. The quality of the electron beam is also degraded by the interaction with the low-gap undulator vacuum chamber. In our work we first analyze this interaction, deriving a formula to evaluate the longitudinal and the transversal wakefields for an elliptical cross section vacuum chamber, obtaining accurate results in the short range. Subsequently within the Vlasov-Maxwell one-dimensional model, we derive the Green functions necessary to evaluate the radiation envelope, having as initial conditions both an energy chirp and curvature on the electrons and eventually an initial bunching, which is useful to treat the harmonic generation FEL cascade configuration. This allows to study the impact of the elecron beam energy profile on the FEL performance. Using the derived Green functions we discuss FEL radiation properties such as bandwidth, frequency shift, frequency chirp and velocity of propagation. Finally, we propose a method to achieve ultra-short FEL pulses using a frequency chirp on the seed laser and a suitable electron energy profile.
XXII Ciclo
1980
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Konstantakopoulos, Theodoros K. 1977. "Energy scalability of on-chip interconnection networks." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/40315.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.
This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Page 198 blank.
Includes bibliographical references (p. 191-197).
On-chip interconnection networks (OCN) such as point-to-point networks and buses form the communication backbone in multiprocessor systems-on-a-chip, multicore processors, and tiled processors. OCNs consume significant portions of a chip's energy budget, so their energy analysis early in the design cycle becomes important for architectural design decisions. Although innumerable studies have examined OCN implementation and performance, there have been few energy analysis studies. This thesis develops an analytical framework for energy estimation in OCNs, for any given topology and arbitrary communication patterns, and presents OCN energy results based on both analytical communication models and real network traces from applications running on a tiled multicore processor. This thesis is the first work to address communication locality in analyzing multicore interconnect energy and to use real multicore interconnect traces extensively. The thesis compares the energy performance of point-to-point networks with buses for varying degrees of communication locality. The model accounts for wire length, switch energy, and network contention. This work is the first to examine network contention from the energy standpoint.
(cont.) The thesis presents a detailed analysis of the energy costs of a switch and shows that the estimated values for channel energy, switch control logic energy, and switch queue buffer energy are 34.5pJ, 17pJ, and 12pJ, respectively. The results suggest that a one-dimensional point-to-point network results in approximately 66% energy savings over a bus for 16 or more processors, while a two-dimensional network saves over 82%, when the processors communicate with each other with equal likelihood. The savings increase with locality. Analysis of the effect of contention on OCNs for the Raw tiled microprocessor reports a maximum energy overhead of 23% due to resource contention in the interconnection network.
by Theodoros K. Konstantakopoulos.
Ph.D.
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Chan, Jeremy Computer Science &amp Engineering Faculty of Engineering UNSW. "Energy-aware synthesis for networks on chip architectures." Awarded by:University of New South Wales. School of Computer Science and Engineering, 2007. http://handle.unsw.edu.au/1959.4/35313.

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The Network on Chip (NoC) paradigm was introduced as a scalable communication infrastructure for future System-on-Chip applications. Designing application specific customized communication architectures is critical for obtaining low power, high performance solutions. Two significant design automation problems are the creation of an optimized configuration, given application requirement the implementation of this on-chip network. Automating the design of on-chip networks requires models for estimating area and energy, algorithms to effectively explore the design space and network component libraries and tools to generate the hardware description. Chip architects are faced with managing a wide range of customization options for individual components, routers and topology. As energy is of paramount importance, the effectiveness of any custom NoC generation approach lies in the availability of good energy models to effectively explore the design space. This thesis describes a complete NoC synthesis ???ow, called NoCGEN, for creating energy-efficient custom NoC architectures. Three major automation problems are addressed: custom topology generation, energy modeling and generation. An iterative algorithm is proposed to generate application specific point-to-point and packet-switched networks. The algorithm explores the design space for efficient topologies using characterized models and a system-level ???oorplanner for evaluating placement and wire-energy. Prior to our contribution, building an energy model required careful analysis of transistor or gate implementations. To alleviate the burden, an automated linear regression-based methodology is proposed to rapidly extract energy models for many router designs. The resulting models are cycle accurate with low-complexity and found to be within 10% of gate-level energy simulations, and execute several orders of magnitude faster than gate-level simulations. A hardware description of the custom topology is generated using a parameterizable library and custom HDL generator. Fully reusable and scalable network components (switches, crossbars, arbiters, routing algorithms) are described using a template approach and are used to compose arbitrary topologies. A methodology for building and composing routers and topologies using a template engine is described. The entire flow is implemented as several demonstrable extensible tools with powerful visualization functionality. Several experiments are performed to demonstrate the design space exploration capabilities and compare it against a competing min-cut topology generation algorithm.
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Vangal, Sriram. "Performance and Energy Efficient Network-on-Chip Architectures." Doctoral thesis, Linköpings universitet, Institutionen för systemteknik, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-11439.

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The scaling of MOS transistors into the nanometer regime opens the possibility for creating large Network-on-Chip (NoC) architectures containing hundreds of integrated processing elements with on-chip communication. NoC architectures, with structured on-chip networks are emerging as a scalable and modular solution to global communications within large systems-on-chip. NoCs mitigate the emerging wire-delay problem and addresses the need for substantial interconnect bandwidth by replacing today’s shared buses with packet-switched router networks. With on-chip communication consuming a significant portion of the chip power and area budgets, there is a compelling need for compact, low power routers. While applications dictate the choice of the compute core, the advent of multimedia applications, such as three-dimensional (3D) graphics and signal processing, places stronger demands for self-contained, low-latency floating-point processors with increased throughput. This work demonstrates that a computational fabric built using optimized building blocks can provide high levels of performance in an energy efficient manner. The thesis details an integrated 80- Tile NoC architecture implemented in a 65-nm process technology. The prototype is designed to deliver over 1.0TFLOPS of performance while dissipating less than 100W. This thesis first presents a six-port four-lane 57 GB/s non-blocking router core based on wormhole switching. The router features double-pumped crossbar channels and destinationaware channel drivers that dynamically configure based on the current packet destination. This enables 45% reduction in crossbar channel area, 23% overall router area, up to 3.8X reduction in peak channel power, and 7.2% improvement in average channel power. In a 150-nm sixmetal CMOS process, the 12.2 mm2 router contains 1.9-million transistors and operates at 1 GHz at 1.2 V supply. We next describe a new pipelined single-precision floating-point multiply accumulator core (FPMAC) featuring a single-cycle accumulation loop using base 32 and internal carry-save arithmetic, with delayed addition techniques. A combination of algorithmic, logic and circuit techniques enable multiply-accumulate operations at speeds exceeding 3GHz, with singlecycle throughput. This approach reduces the latency of dependent FPMAC instructions and enables a sustained multiply-add result (2FLOPS) every cycle. The optimizations allow removal of the costly normalization step from the critical accumulation loop and conditionally powered down using dynamic sleep transistors on long accumulate operations, saving active and leakage power. In a 90-nm seven-metal dual-VT CMOS process, the 2 mm2 custom design contains 230-K transistors. Silicon achieves 6.2-GFLOPS of performance while dissipating 1.2 W at 3.1 GHz, 1.3 V supply. We finally present the industry's first single-chip programmable teraFLOPS processor. The NoC architecture contains 80 tiles arranged as an 8×10 2D array of floating-point cores and packet-switched routers, both designed to operate at 4 GHz. Each tile has two pipelined singleprecision FPMAC units which feature a single-cycle accumulation loop for high throughput. The five-port router combines 100 GB/s of raw bandwidth with low fall-through latency under 1ns. The on-chip 2D mesh network provides a bisection bandwidth of 2 Tera-bits/s. The 15-FO4 design employs mesochronous clocking, fine-grained clock gating, dynamic sleep transistors, and body-bias techniques. In a 65-nm eight-metal CMOS process, the 275 mm2 custom design contains 100-M transistors. The fully functional first silicon achieves over 1.0TFLOPS of performance on a range of benchmarks while dissipating 97 W at 4.27 GHz and 1.07-V supply. It is clear that realization of successful NoC designs require well balanced decisions at all levels: architecture, logic, circuit and physical design. Our results demonstrate that the NoC architecture successfully delivers on its promise of greater integration, high performance, good scalability and high energy efficiency.
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Muhic, Dino. "Improved energy efficiency in double disc chip refining." Licentiate thesis, Mittuniversitetet, Institutionen för naturvetenskap, teknik och matematik, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-12979.

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The electrical energy consumption in thermomechanical pulping (TMP) is very high, in the range of 2 – 3 MWh/adt depending on process solution and on the product quality specifications for the paper product. Both pulpwood and energy prices have increased rapidly for some time. Due to this, the main focus of the research and development is on ways to reduce the electrical energy consumption in wood chip refining. As a step towards a more energy and cost ‐ effective refining process, Holmen Paper AB has invested in a new mechanical pulping process at its Braviken mill. In this case the primary refining stage consists of high consistency (HC) double disc refiners ‐ RGP68DD (machines with two counter rotating discs). Earlier studies on the refining conditions, such as intensity and temperature, have indicated that it should be possible to improve the energy efficiency in double disc refining while maintaining the functional pulp properties such as tensile index. The main goal of this project was to improve the energy efficiency in double disc chip refining with 150 kWh/adt to corresponding pulp properties as measured on pulp samples after refiner. In order to further improve the basic understanding of what happens to the wood fibre material when changing the process conditions, the morphological and ultrastructural changes of fibres were also studied. This part of the research work was performed in cooperation with the research program; Collaborative Research on the Ultrastructure of Wood Fibres (CRUW). This licentiate project is a part of a large development project where different techniques to improve the energy efficiency has been evaluated by means of mill scale trials at the Holmen Paper Braviken Mill. The high consistency double disc chip refining part of the project was financed by The Swedish Knowledge Foundation, Metso Paper and Holmen Paper, in cooperation with FSCN (Fiber Science & Communication Network) at Mid Sweden University. The trials were made on one of the TMP lines at the Holmen Paper Braviken mill with Norway spruce as raw material. The influence of increased specific      refining energy on pulp properties were studied at different refining temperatures, refining intensity, pulp consistency and production rate. Results from these trials were later validated by means of long term trials. Intensity models and simulations for intensity changes by new segment design were made by Juha‐ Pekka Huhtanen from Tampere University of Technology, Finland. The results show that the specific energy consumption to same tensile index can be improved by means of increasing the refining pressure/temperature. The energy efficiency was improved by 80     ‐150 kWh/adt depending on load and the inlet‐ and housing pressure. The largest relative specific energy efficiency improvement was reached at low specific energy consumption levels. Similar fibre surface ultrastructure characteristics are gained by pulps with high pressure/temperature and low specific energy consumption compared to low pressure/temperature and high specific energy consumption pulps. High pressure/temperature and high specific energy consumption resulted in significantly increase in the delamination/internal fibrillation of pulp fibres. The surface ultrastructure of these fibres exhibited exposed S2 layer with long ribbontype fibrillation compared to pulps produced with lower temperature and lower specific energy consumption. When the refiner was operated at high pressure, the tensile index was preserved over the whole plate life. The specific light scattering coefficient increased with increasing pressure/temperature. A reason for this could be increased intensity caused by decreased plate gap. Increased intensity by means of refiner segment design changes resulted in large specific light scattering coefficient increase at similar tensile index, lower shives content, lower average fibre length and lower CSF at same specific energy consumption. The fresh steam consumption was reduced by the increased refiner ressure/temperature.
Den höga elenergiförbrukningen vid produktion av mekanisk massa har ställtkrav på mer forskning för att elenergieffektivisera raffineringsprocessen. Som ettsteg mot en mer energi‐ och kostnadseffektiv raffineringsprocess, har HolmenPaper AB investerat i en ny tillverkning av termomekanisk (TMP) massa vidBravikens pappersbruk. Dubbeldiskraffinörerna i den nya massalinjens primäraraffineringssteget studerades i detta projekt. Det finns goda indikationer på att enminskning av energiförbrukningen är möjlig genom att studerar och optimeraraffineringparametrar såsom intensitet och temperatur. Projektets huvudmål varatt energieffektivisera det primära dubbeldiskraffineringssteget med 150 kWh/adttill motsvarande massaegenskaper, så som dragstyrka, mätt på massa efterraffinör. Tillfälle gavs också till att studera morfologiska förändringar på fibrer föratt ytterligare förstå hur massa och fibrerna påverkas av dubbeldiskraffinering ochförändringar i raffineringssystemet.Detta licentiatprojekt är en del av ett större projekt där olika tekniker för attförbättra energieffektiviteten har utvärderats i industriell skala på Holmen PaperBravikens pappersbruk. Licentiatprojektet är finansierat av KK‐stiftelsen, MetsoPaper och Holmen Paper, i samarbete med Mittuniversitetet.Fullskaleförsök gjordes på en av TMP linjerna vid Bravikens pappersbruk, därgran används som råvara. Studien utfördes på dubbeldiskraffinörerna i detprimära raffineringssteget. Malkurvor, med ökande specifik raffineringsenergi,gjordes vid olika raffineringstemperaturer, intensitet, massakoncentration ochproduktion. Resultat som erhållits från malkurvorna bekräftades med längrestudier på raffinörerna. Intensitetsmodeller och simuleringar utfördes av Juha‐Pekka Huhtanen från Tampere University of Technology.De erhållna resultaten visar på att energiförbrukningen till ett visst dragindexkan minskas genom att öka raffineringstrycket/temperaturen. Medraffineringstryck menas inlopp och hustryck i raffinören. Energibesparingen är iintervallet 80‐150 kWh/adt. Den största förbättringen kan uppnås vid lågaenergiinsatser. Massor producerade med högt tryck och temperatur och lägrespecifik energiförbrukning uppvisar liknande ultrastrukturella ytegenskaper sommassor producerade med lågt tryck och temperatur och hög specifik energi. Högttryck och temperaturer med hög specifik energiinsats gav en signifikant förbättringav delaminering/intern fibrillering av massafibrer. Dessa fibrer uppvisadebildningar av långa band‐liknande fibriller från fibrernas S2 skikt, i jämförelse medmassor tillverkade med lägre tryck och temperatur och lägre specifik energi.5Om raffineringen genomförs vid högt tryck/temperatur bevaras dragindexunder hela segmentlivslängden.Den specifika ljusspridningskoefficienten påverkades positivt av ökat tryck ochtemperatur. En orsak till detta kan vara högre intensitet som orsakas av minskadmalspalt.Ökad intensitet genom förändrad segmentdesign leder till stora ökningar i denspecifika ljusspridningskoefficienten. Samtidigt uppnås samma dragindex, lägrespethalt, lägre genomsnittlig fiberlängd och CSF vid samma specifikaenergiförbrukning.Förbrukningen av färskångan sänktes vid tillämning av högre tryck ochtemperatur i raffinören.
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Rahmat, Meysam. "Geometric optimization for a thermal microfluidic chip." Thesis, McGill University, 2007. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=18408.

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During the past two decades, thermal microfluidic chips have significantly been investigated. Due to their high capacity of heat transport, an increasing number of studies on different aspects of thermal microfluidic chips have been conducted. However, a comprehensive investigation on the geometry of microfluidic chips using state of the art finite element software is absent from the literature. In this thesis, geometric parameters of thermal microfluidic chips have been optimized, using finite element software. Consequently, micro and macro phenomena were investigated in different models. The micro modelling approach investigated single microchannels and optimized the microchannel cross-section. Furthermore, two-phase flows in the microchannel were modelled, using finite element software ANSYS CFX. Liquid accumulation in the sharp corners of the microchannel was captured in the model and the phase change phenomenon was observed. The results of the finite element analysis were compared to the literature and a good correlation was observed. The configuration of microchannels in a microfluidic chip was studied through the macro modelling approach. Dimensionless design charts were presented in this section to be employed for all kinds of thermal microfluidic chips with different boundary conditions. Based on the validity of the finite element software, two-phase flows in the optimized three-dimensional network of microchannels were modelled. The results showed the circulation of the two phases in the microchannels and demonstrated the proper operation of the thermal microfluidic chip.
Au cours des deux dernières décades, les puces thermiques micro-fluidiques ont été considérablement examinées. Du fait de leur haute capacité pour le transport de chaleur, de nombreuses études ont été réalisées sur différents aspects de leurs propriétés. Cependant, une étude de la géométrie des puces micro-fluidiques utilisant un logiciel d'analyse par éléments finis est absente de la littérature. Dans cette thèse, des paramètres géométriques des puces thermiques micro-fluidiques ont été optimisés en utilisant un logiciel d'analyse par éléments finis. Ainsi, les phénomènes micro et macro ont été étudiés dans différents modèles. L'approche micro a consisté à étudier les micro-canaux seuls, et à optimiser la géométrie de leur section transverse. De plus, deux phases d'écoulement ont été modélisées en utilisant le logiciel d'élément fini ANSYS CFX. L'accumulation de liquide dans les coins saillants a été saisie par le modèle et le phénomène de changement de phase a pu être également observé. Les résultats de l'analyse par élément finis ont été comparés à ceux trouvés dans la littérature, et une bonne corrélation a été observée. La configuration des micro-canaux dans la puce micro-fluidique a été étudiée par l'approche macro. Des graphes adimensionnels ont été présentés dans cette section afin d'être employés pour toutes sortes de puces ayant différentes conditions aux frontières. En se basant sur la validité du modèle micro, élaboré par élément finis, l'écoulement des deux phases dans un réseau tridimensionnel de micro-canaux avec une géométrie optimisée a été modélisé. Les résultats montrent une circulation des deux phases dans les micro-canaux et démontrent le bon fonctionnement des puces thermiques micro fluidiques.
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Al-Tarawneh, Mutaz. "Improving the Off-chip Bandwidth Utilization and Energy Efficiency in Chip Multiprocessor (CMP) Architectures." OpenSIUC, 2010. https://opensiuc.lib.siu.edu/dissertations/216.

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This dissertation aims at improving the off-chip bandwidth utilization and energy efficiency in chip multiprocessor (CMP) architectures. This work consists of two main parts. The first part investigates the early write-back technique for a two-level cache hierarchy in a CMP with four processor cores. Early write-back can be viewed as a modified cache write policy that takes into account not only maintaining data consistency between on-chip and off-chip components of the memory hierarchy but also improving the off-chip bandwidth utilization. Early write-back will issue a write-back operation for some dead and dirty cache lines, from the shared second-level (L2) cache memory to the main memory, prior to those lines eviction. Early write-back operations will be issued when the off-chip bus is free. This technique would improve the processor's performance by avoiding or minimizing off-chip bus contention between write-back operations and demand fetch requests where one example is read and write misses in the shared L2 cache. Early write-back efficiency has been measured in terms of its impact on the L2 cache miss latency. Simulation results have proved early write-back efficacy in improving the off-chip bandwidth utilization of a CMP. Early write-back has achieved varying degrees of performance improvement among different benchmarks. The performance improvement that early write-back can achieve depends on two main factors. First, the sensitivity of the individual benchmark to changes in the available off-chip bandwidth. Second, the severity of off-chip bus contention between demand fetch requests and write-back operations. The second part of this work tackles dynamic voltage and frequency scaling (DVFS) of the off-chip bus that handles the communication between the processor chip and the off-chip memory. Off-chip bus DVFS will dynamically vary the power parameters of the off-chip bus such that off-chip bus energy can be minimized while at the same time the forward progress of the running application can be maintained. This technique captures the CPU and memory boundedness of the running applications, during the run time, such that a reasonable tradeoff between processor performance and off-chip bus energy can be attained. The off-chip bus can be tuned to low-energy settings in CPU-bound applications or CPU-bound phases of program execution. The CPU-boundedness of an application has been measured in terms of the off-chip access ratio (OCAR) which is defined as the ratio between the number of L2 cache misses and the number of instructions retired during a particular observation window. An application or a particular execution phase is said to be CPU-bound if its OCAR is less that a predefined threshold value. Off-chip bus DVFS has been evaluated in two types of processor configurations: First, a processor that relies on Instruction Level Parallelism (ILP) to improve its performance such as single-core superscalar processors, Second, a processor that depends on Thread Level Parallelism in conjunction with ILP to improve its performance such as a CMP with multiple superscalar cores. In applications with high ILP, even when executed on a single processor, the two systems have achieved similar results in terms of their off-chip bus energy savings. On the other hand, in applications with limited ILP when executed on a single processor, the second system has achieved better results in terms of its off-chip bus energy savings; executing the application as multiple concurrent threads has contributed to its CPU boundedness allowing the off-chip bus DVFS triggering condition to be satisfied for the majority of observation windows as compared to the case of a single processor.
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Park, Sunghyun Ph D. Massachusetts Institute of Technology. "Low-swing signaling for energy efficient on-chip networks." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66474.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 65-69).
On-chip networks have emerged as a scalable and high-bandwidth communication fabric in many-core processor chips. However, the energy consumption of these networks is becoming comparable to that of computation cores, making further scaling of core counts difficult. This thesis makes several contributions to low-swing signaling circuit design for the energy efficient on-chip networks in two separate projects: on-chip networks optimized for one-to-many multicasts and broadcasts, and link designs that allow on-chip networks to approach an ideal interconnection fabric. A low-swing crossbar switch, which is based on tri-state Reduced-Swing Drivers (RSDs), is presented for the first project. Measurement results of its test chip fabricated in 45nm SOI CMOS show that the tri-state RSD-based crossbar enables 55% power savings as compared to an equivalent full-swing crossbar and link. Also, the measurement results show that the proposed crossbar allows the broadcast-optimized on-chip networks using a single pipeline stage for physical data transmission to operate at 21% higher data rate, when compared with the full-swing networks. For the second project, two clockless low-swing repeaters, a Self-Resetting Logic Repeater (SRLR) and a Voltage-Locked Repeater (VLR), have been proposed and analyzed in simulation only. They both require no reference clock, differential signaling, and bias current. Such digital-intensive properties enable them to approach energy and delay performance of a point-to-point interconnect of variable lengths. Simulated in 45nm SOI CMOS, the 10mm SRLR featured with high energy efficiency consumes 338fJ/b at 5.4Gb/s/ch while the 10mm VLR raises its data rate up to 16.OGb/s/ch with 427fJ/b.
by Sunghyun Park.
S.M.
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Li, Hui. "Design methods for energy-efficient silicon photonic interconnects on chip." Thesis, Lyon, 2016. http://www.theses.fr/2016LYSEC059/document.

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La photonique au silicium est une technologie émergente considérée comme l'une des solutions clés pour les interconnexions sur puce de génération future, offrant plusieurs avantages potentiels tels qu'une faible latence de transmission et une bande passante élevée. Cependant, elle reste confrontée à des défis en matière d'efficacité énergétique. Différentes topologies, layout et architectures offrent diverses options d'interconnexion. Ceci conduit à une grande variation des pertes optiques, qui est l'un des facteurs prédominants dans la consommation d'énergie. De plus, les composants photoniques au silicium sont très sensibles aux variations de température. Sous une activité de puces donnée, ceci conduit à une réduction de l’efficacité des lasers et à une dérive des longueurs d'onde des composants optiques, ce qui entraîne un «Bit Error Ratio (BER)» plus élevé et réduit par conséquent l'efficacité énergétique des interconnexions optiques. Dans cette thèse, nous travaillons sur des méthodologies de conception pour les interconnexions photoniques sur silicium économes-en-énergie et prenant en compte la topologie / le layout, la variation thermique et l'architecture
Silicon photonics is an emerging technology considered as one of the key solutions for future generation on-chip interconnects, providing several prospective advantages such as low transmission latency and high bandwidth. However, it still encounters challenges in energy efficiency. Different topologies, physical layouts, and architectures provide various interconnect options for on-chip communication. This leads to a large variation in optical losses, which is one of the predominant factors in power consumption. In addition, silicon photonic devices are highly sensitive to temperature variation. Under a given chip activity, this leads to a lower laser efficiency and a drift of wavelengths of optical devices (on-chip lasers and microring resonators (MRs)), which in turn results in a higher Bit Error Ratio (BER) and consequently reduces the energy efficiency of optical interconnects. In this thesis, we work on design methodologies for energy-efficient silicon photonic interconnects on chip related to topology/layout, thermal variation, and architecture
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Celik, Coskun. "Energy And Buffer Aware Application Mapping For Networks On Chip." Phd thesis, METU, 2013. http://etd.lib.metu.edu.tr/upload/12615753/index.pdf.

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Network-on-Chip (NoC) is a developing and promising on-chip communication paradigm that improves scalability and performance of System-on-Chips. NoC design flow contains many problems from different areas, for example networking, embedded design and computer architecture. Application mapping is one of these problems, which is generally considered as a communication energy minimization problem. This dissertation approaches to this problem from a networking point of view and tries to find a mapping solution which improves the network performance in terms of the number of packets in the buffers while still minimizing the total communication energy consumption. For this purpose an on-chip network traffic model is required. Self similarity is a traffic model that is used to characterize Ethernet and/or wide area network traffic, as well as most of on-chip network traffic. In this thesis, by using an on-chip traffic characterization that contains self similarity, an application mapping problem definition that contains both energy and buffer utilization concerns is proposed. In order to solve this intractable problem a genetic algorithm based model is implemented. Execution of the algorithm on different test cases has proved that such a mapping formulation avoids high buffer utilizations while still keeping the communication energy low.
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Books on the topic "Energy chirp"

1

1983-, Hodge Nick, and Nelder Chris 1964-, eds. Investing in renewable energy: Making money on green chip stocks. Hoboken, N.J: John Wiley & Sons, 2008.

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Tanzawa, Toru. On-chip high-voltage generator design. New York: Springer, 2013.

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Maker, Timothy M. Wood-chip heating systems: A guide for institutional and commercial biomass installations. 2nd ed. Montpelier, Vt: Biomass Energy Resource Center, 2004.

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Tanzawa, Toru. On-chip High-Voltage Generator Design. New York, NY: Springer New York, 2013.

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Hu, John. CMOS High Efficiency On-chip Power Management. New York, NY: Springer Science+Business Media, LLC, 2011.

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Tanzawa, Toru. On-chip High-Voltage Generator Design. Springer, 2012.

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Tanzawa, Toru. On-chip High-Voltage Generator Design. Springer, 2014.

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Hu, John, and Mohammed Ismail. CMOS High Efficiency On-chip Power Management. Springer, 2011.

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Hu, John, and Mohammed Ismail. CMOS High Efficiency On-chip Power Management. Springer, 2013.

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Chakrabarty, Krishnendu, Sukanta Bhattacharjee, and Bhargab B. Bhattacharya. Algorithms for Sample Preparation with Microfluidic Lab-On-Chip. River Publishers, 2019.

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Book chapters on the topic "Energy chirp"

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Bertozzi, Davide, Luca Benini, and Giovanni De Micheli. "Energy-Reliability trade-Off for NoCs." In Networks on Chip, 107–29. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/0-306-48727-6_6.

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Chen, Sao-Jie, Ying-Cherng Lan, Wen-Chung Tsai, and Yu-Hen Hu. "Performance-Energy Tradeoffs for Noc Reliability." In Reconfigurable Networks-on-Chip, 51–67. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9341-0_4.

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Chen, Sao-Jie, Ying-Cherng Lan, Wen-Chung Tsai, and Yu-Hen Hu. "Energy-Aware Application Mapping for BiNoC." In Reconfigurable Networks-on-Chip, 173–92. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9341-0_9.

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Nigussie, Ethiopia Enideg. "Energy Efficient Semi-Serial Interconnect." In Variation Tolerant On-Chip Interconnects, 93–117. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4614-0131-5_6.

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Kim, John. "Energy-Aware On-Chip Networks." In Energy-Aware System Design, 93–118. Dordrecht: Springer Netherlands, 2011. http://dx.doi.org/10.1007/978-94-007-1679-7_5.

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Manoli, Yiannos, Thorsten Hehn, Daniel Hoffmann, Matthias Kuhl, Niklas Lotze, Dominic Maurath, Christian Moranz, Daniel Rossbach, and Dirk Spreemann. "Energy Harvesting and Chip Autonomy." In The Frontiers Collection, 393–420. Berlin, Heidelberg: Springer Berlin Heidelberg, 2011. http://dx.doi.org/10.1007/978-3-642-23096-7_19.

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Yang, Kun, Shupeng Zhong, Quan Kong, Changyou Men, and Nianxiong Nick Tan. "Low Power Energy Metering Chip." In Ultra-Low Power Integrated Circuit Design, 145–68. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4419-9973-3_7.

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Katiyar, Jitendra Kumar, and Vinay K. Patel. "Nano-energetic Materials on a Chip." In Energy, Environment, and Sustainability, 123–39. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-3269-2_6.

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Chen, Sao-Jie, Ying-Cherng Lan, Wen-Chung Tsai, and Yu-Hen Hu. "Energy-Aware Task Scheduling for Noc-Based DVS System." In Reconfigurable Networks-on-Chip, 69–88. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9341-0_5.

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Fu, Bo, and Paul Ampadu. "Energy Efficient Error Control Implementation." In Error Control for Network-on-Chip Links, 79–116. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9313-7_5.

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Conference papers on the topic "Energy chirp"

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Kang, Wei, Jing Guo, Heming Li, and Xiangwu Yan. "Voltage Flicker Detection Based on Chirp-z Transform." In 2010 Asia-Pacific Power and Energy Engineering Conference. IEEE, 2010. http://dx.doi.org/10.1109/appeec.2010.5448684.

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Namdar, Mustafa, Baris Sahin, Haci Ilhan, and Lutfiye Durak-Ata. "Chirp Z transform based spectrum sensing via energy detection." In 2012 20th Signal Processing and Communications Applications Conference (SIU). IEEE, 2012. http://dx.doi.org/10.1109/siu.2012.6204563.

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Uddin, Wasi, Tausif Husain, Rakesh Mitra, Ernest Ofori, Yilmaz Sozer, and Iqbal Husain. "A chirp PWM scheme for brushless DC motor drives." In 2012 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2012. http://dx.doi.org/10.1109/ecce.2012.6342336.

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Kwak, Chulyoung, Seongwon Kim, Soonwon Ka, Jihwan Lee, and Sunghyun Choi. "No Entry: Anti-Noise Energy Detector for Chirp-Based Acoustic Communication." In 2019 16th Annual IEEE International Conference on Sensing, Communication, and Networking (SECON). IEEE, 2019. http://dx.doi.org/10.1109/sahcn.2019.8824986.

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Islam, M. N., C. J. Chen, and C. E. Soccolich. "All-optical time domain chirp switches with one picojoule switching energy." In Integrated Photonics Research. Washington, D.C.: Optica Publishing Group, 1991. http://dx.doi.org/10.1364/ipr.1991.tue1.

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Soliton dragging logic gates1 are one example of a novel time domain chirp switch (TDCS) architecture that is applicable to materials other than fibers. The logic in a TDCS is based on time shift keying where a "1" corresponds to a pulse that arrives within the clock window and a "0" to either no pulse or an improperly timed pulse. Although TDCS's generally incur a latency penalty, for high bit-rate applications TDCS's lead to low switching energies. For example, we illustrate an all-fiber inverter with a 1pJ switching energy and a fan-out of 28.
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Aroge, Fabusuyi A., and Paul S. Barendse. "Time-Frequency Analysis of the Chirp Response for Rapid Electrochemical Impedance Estimation." In 2018 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2018. http://dx.doi.org/10.1109/ecce.2018.8558129.

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Aguergaray, Claude, Antoine Runge, Miro Erkintalo, and Neil G. R. Broderick. "Raman-driven destabilization of giant-chirp oscillators: Fundamental limitations to energy scalability." In 2013 Conference on Lasers & Electro-Optics Europe & International Quantum Electronics Conference CLEO EUROPE/IQEC. IEEE, 2013. http://dx.doi.org/10.1109/cleoe-iqec.2013.6801356.

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Islam, M. N., C. F. Soccolich, and C. J. Chen. "All-optical time domain chirp switches." In OSA Annual Meeting. Washington, D.C.: Optica Publishing Group, 1990. http://dx.doi.org/10.1364/oam.1990.wm2.

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We demonstrate the first all-optical sequential circuit by looping the output from a soliton dragging logic gate1 back to its input. Previously we demonstrated an ultrafast soliton dragging NOR-gate with logic level restoration at the output, fan-out of six, and switching energy of 5.8 pJ. To prove the cascadability and fan-out of the logic gate, we implement a ring oscillator by connecting the NOR-gate as an inverter and adding a feedback loop. The logic gate consists of a 325 m long biréfringent optical fiber surrounded by two polarizing beam splitters. The fiber is carefully laid in a 1 m diameter track and enclosed in an insulating box for thermal stability. A passively mode-locked color center laser supplies the clock pulses (τ = 500 fs, λ = 1.685µm, 54-pJ energy in the fiber) that are coupled along the fast axis of the fiber. We place a 50:50 beam splitter at the output and send half of the output through a delay line and half wave plate to the orthogonally polarized input. The other half of the output is combined with a reference pulse and sent to a cross-correlator. With the feedback blocked the output is a string of l's. When the feedback is added, the output becomes an alternating train of l's and 0's whose period is twice the fiber latency (1.75µs). More complicated functionalities are possible by encoding the clock pulses at the input and decoding at the output.
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Li, Yu, Fei Chen, Woogeun Rhee, and Zhihua Wang. "A chirp-UWB transceiver with embedded bulk PPM for energy efficient data transmission." In 2014 IEEE International Wireless Symposium (IWS). IEEE, 2014. http://dx.doi.org/10.1109/ieee-iws.2014.6864217.

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Vicario, C., A. Trisorio, C. P. Hauri, and G. Arisholm. "High-energy deep-UV temporal pulse shaping by chirp-assisted broadband frequency conversion." In 12th European Quantum Electronics Conference CLEO EUROPE/EQEC. IEEE, 2011. http://dx.doi.org/10.1109/cleoe.2011.5942683.

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Reports on the topic "Energy chirp"

1

Huang, Z., D. Ratner, G. Stupakov, and D. Xiang. Effects of Energy Chirp on Echo-Enabled Harmonic Generation Free-Electron Lasers. Office of Scientific and Technical Information (OSTI), February 2009. http://dx.doi.org/10.2172/948487.

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Hovav, Ran, Peggy Ozias-Akins, and Scott A. Jackson. The genetics of pod-filling in peanut under water-limiting conditions. United States Department of Agriculture, January 2012. http://dx.doi.org/10.32747/2012.7597923.bard.

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Pod-filling, an important yield-determining stage is strongly influenced by water stress. This is particularly true for peanut (Arachishypogaea), wherein pods are developed underground and are directly affected by the water condition. Pod-filling in peanut has a significant genetic component as well, since genotypes are considerably varied in their pod-fill (PF) and seed-fill (SF) potential. The goals of this research were to: Examine the effects of genotype, irrigation, and genotype X irrigation on PF and SF. Detect global changes in mRNA and metabolites levels that accompany PF and SF. Explore the response of the duplicate peanut pod transcriptome to drought stress. Study how entire duplicated PF regulatory processes are networked within a polyploid organism. Discover locus-specific SNP markers and map pod quality traits under different environments. The research included genotypes and segregating populations from Israel and US that are varied in PF, SF and their tolerance to water deficit. Initially, an extensive field trial was conducted to investigate the effects of genotype, irrigation, and genotype X irrigation on PF and SF. Significant irrigation and genotypic effect was observed for the two main PF related traits, "seed ratio" and "dead-end ratio", demonstrating that reduction in irrigation directly influences the developing pods as a result of low water potential. Although the Irrigation × Genotype interaction was not statistically significant, one genotype (line 53) was found to be more sensitive to low irrigation treatments. Two RNAseq studies were simultaneously conducted in IL and the USA to characterize expression changes that accompany shell ("source") and seed ("sink") biogenesis in peanut. Both studies showed that SF and PF processes are very dynamic and undergo very rapid change in the accumulation of RNA, nutrients, and oil. Some genotypes differ in transcript accumulation rates, which can explain their difference in SF and PF potential; like cvHanoch that was found to be more enriched than line 53 in processes involving the generation of metabolites and energy at the beginning of seed development. Interestingly, an opposite situation was found in pericarp development, wherein rapid cell wall maturation processes were up-regulated in line 53. Although no significant effect was found for the irrigation level on seed transcriptome in general, and particularly on subgenomic assignment (that was found almost comparable to a 1:1 for A- and B- subgenomes), more specific homoeologous expression changes associated with particular biosynthesis pathways were found. For example, some significant A- and B- biases were observed in particular parts of the oil related gene expression network and several candidate genes with potential influence on oil content and SF were further examined. Substation achievement of the current program was the development and application of new SNP detection and mapping methods for peanut. Two major efforts on this direction were performed. In IL, a GBS approach was developed to map pod quality traits on Hanoch X 53 F2/F3 generations. Although the GBS approach was found to be less effective for our genetic system, it still succeeded to find significant mapping locations for several traits like testa color (linkage A10), number of seeds/pods (A5) and pod wart resistance (B7). In the USA, a SNP array was developed and applied for peanut, which is based on whole genome re-sequencing of 20 genotypes. This chip was used to map pod quality related traits in a Tifrunner x NC3033 RIL population. It was phenotyped for three years, including a new x-ray method to phenotype seed-fill and seed density. The total map size was 1229.7 cM with 1320 markers assigned. Based on this linkage map, 21 QTLs were identified for the traits 16/64 weight, kernel percentage, seed and pod weight, double pod and pod area. Collectively, this research serves as the first fundamental effort in peanut for understanding the PF and SF components, as a whole, and as influenced by the irrigation level. Results of the proposed study will also generate information and materials that will benefit peanut breeding by facilitating selection for reduced linkage drag during introgression of disease resistance traits into elite cultivars. BARD Report - Project4540 Page 2 of 10
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