Journal articles: 'Emerging Non-Volatile memories'

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Fujisaki, Yoshihisa. "Overview of emerging semiconductor non-volatile memories." IEICE Electronics Express 9, no. 10 (2012): 908–25. http://dx.doi.org/10.1587/elex.9.908.

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Melanotte, M., R. Bez, and G. Crisenza. "Non volatile memories-status and emerging trends." Microelectronic Engineering 15, no. 1-4 (October 1991): 603–12. http://dx.doi.org/10.1016/0167-9317(91)90293-m.

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Si, Mengwei, Huai-Yu Cheng, Takashi Ando, Guohan Hu, and Peide D. Ye. "Overview and outlook of emerging non-volatile memories." MRS Bulletin 46, no. 10 (October 2021): 946–58. http://dx.doi.org/10.1557/s43577-021-00204-2.

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Dieny, B., and Chennupati Jagadish. "Emerging non-volatile memories: magnetic and resistive technologies." Journal of Physics D: Applied Physics 46, no. 7 (February 1, 2013): 070301. http://dx.doi.org/10.1088/0022-3727/46/7/070301.

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Fujisaki, Yoshihisa. "Review of Emerging New Solid-State Non-Volatile Memories." Japanese Journal of Applied Physics 52, no. 4R (April 1, 2013): 040001. http://dx.doi.org/10.7567/jjap.52.040001.

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Makarov, Alexander, Viktor Sverdlov, and Siegfried Selberherr. "Modeling Emerging Non-volatile Memories: Current Trends and Challenges." Physics Procedia 25 (2012): 99–104. http://dx.doi.org/10.1016/j.phpro.2012.03.056.

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Wang, Yan, Ziyu Lv, Li Zhou, Xiaoli Chen, Jinrui Chen, Ye Zhou, V. A. L. Roy, and Su-Ting Han. "Emerging perovskite materials for high density data storage and artificial synapses." Journal of Materials Chemistry C 6, no. 7 (2018): 1600–1617. http://dx.doi.org/10.1039/c7tc05326f.

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Khan, Mohammad Nasim Imtiaz, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. "Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 28, 2021): 38. http://dx.doi.org/10.3390/jlpea11040038.

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Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache.

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Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 24, 2021): 36. http://dx.doi.org/10.3390/jlpea11040036.

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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

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Waser, Rainer. "Emerging Non-Volatile Memories by Exploiting Redox Reactions on the Nanoscale." ECS Transactions 25, no. 7 (December 17, 2019): 441–46. http://dx.doi.org/10.1149/1.3203981.

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A, Ragavi, and Arivasanth M. "Design of Look up Table for Emerging Non Volatile Memories in FRAM." IJIREEICE 5, no. 6 (May 15, 2017): 59–65. http://dx.doi.org/10.17148/ijireeice.2017.5610.

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Golubović, D. S., A. H. Miranda, N. Akil, R. T. F. van Schaijk, and M. J. van Duuren. "Vertical poly-Si select pn-diodes for emerging resistive non-volatile memories." Microelectronic Engineering 84, no. 12 (December 2007): 2921–26. http://dx.doi.org/10.1016/j.mee.2007.03.009.

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Wang, L., C. H. Yang, and J. Wen. "Physical principles and current status of emerging non-volatile solid state memories." Electronic Materials Letters 11, no. 4 (July 2015): 505–43. http://dx.doi.org/10.1007/s13391-015-4431-4.

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Hakert, Christian, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von der Brüggen, Hussam Amrouch, Jörg Henkel, and Jian-Jia Chen. "Software-Managed Read and Write Wear-Leveling for Non-Volatile Main Memory." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3483839.

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In-memory wear-leveling has become an important research field for emerging non-volatile main memories over the past years. Many approaches in the literature perform wear-leveling by making use of special hardware. Since most non-volatile memories only wear out from write accesses, the proposed approaches in the literature also usually try to spread write accesses widely over the entire memory space. Some non-volatile memories, however, also wear out from read accesses, because every read causes a consecutive write access. Software-based solutions only operate from the application or kernel level, where read and write accesses are realized with different instructions and semantics. Therefore different mechanisms are required to handle reads and writes on the software level. First, we design a method to approximate read and write accesses to the memory to allow aging aware coarse-grained wear-leveling in the absence of special hardware, providing the age information. Second, we provide specific solutions to resolve access hot-spots within the compiled program code (text segment) and on the application stack. In our evaluation, we estimate the cell age by counting the total amount of accesses per cell. The results show that employing all our methods improves the memory lifetime by up to a factor of 955×.

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Awais, Muhammad, Feng Zhao, and Kuan Yew Cheong. "Bio-Organic Based Resistive Switching Random-Access Memory." Solid State Phenomena 352 (October 30, 2023): 85–93. http://dx.doi.org/10.4028/p-tbxv2r.

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A non-volatile memory is a solid-state device that can retain data even power supply is terminated. It is an essential data storage device that serves as a backbone for the advancement of Internet-of-Things. There are various emerging non-volatile memory technologies in different technology-readiness levels, to replace the existing technologies with limited memory density, operating speed, power consumption, manufacturability, and data security. Of the emerging technologies, resistive switching technology is one of the most promising next generation non-volatile random-access memories. The fundamental working principle of the resistive-switching random-access memory (ReRAM) is based on memristor characterises with metal-insulator-metal stacking structure. Same as other solid-state devices, ReRAM is also facing issue of electronic waste when the memory device is discarded. To overcome this issue, bio-organic materials as green and sustainable engineering materials have been used to fabricate ReRAM. In this review, development of bio-organic based ReRAM, in particular the resistive switching mechanisms and device performance, have been discussed and challenging and future applications of this memory have been provided.

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Spassov, D., A. Paskaleva, T. A. Krajewski, E. Guziewicz, and G. Luka. "Hole and electron trapping in HfO2/Al2O3 nanolaminated stacks for emerging non-volatile flash memories." Nanotechnology 29, no. 50 (October 18, 2018): 505206. http://dx.doi.org/10.1088/1361-6528/aae4d3.

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Walden, Candace, Devesh Singh, Meenatchi Jagasivamani, Shang Li, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce Jacob, and Donald Yeung. "Monolithically Integrating Non-Volatile Main Memory over the Last-Level Cache." ACM Transactions on Architecture and Code Optimization 18, no. 4 (December 31, 2021): 1–26. http://dx.doi.org/10.1145/3462632.

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Many emerging non-volatile memories are compatible with CMOS logic, potentially enabling their integration into a CPU’s die. This article investigates such monolithically integrated CPU–main memory chips. We exploit non-volatile memories employing 3D crosspoint subarrays, such as resistive RAM (ReRAM), and integrate them over the CPU’s last-level cache (LLC). The regular structure of cache arrays enables co-design of the LLC and ReRAM main memory for area efficiency. We also develop a streamlined LLC/main memory interface that employs a single shared internal interconnect for both the cache and main memory arrays, and uses a unified controller to service both LLC and main memory requests. We apply our monolithic design ideas to a many-core CPU by integrating 3D ReRAM over each core’s LLC slice. We find that co-design of the LLC and ReRAM saves 27% of the total LLC–main memory area at the expense of slight increases in delay and energy. The streamlined LLC/main memory interface saves an additional 12% in area. Our simulation results show monolithic integration of CPU and main memory improves performance by 5.3× and 1.7× over HBM2 DRAM for several graph and streaming kernels, respectively. It also reduces the memory system’s energy by 6.0× and 1.7×, respectively. Moreover, we show that the area savings of co-design permits the CPU to have 23% more cores and main memory, and that streamlining the LLC/main memory interface incurs a small 4% performance penalty.

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Huang, Shanshi, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, and Shimeng Yu. "Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices." ACM Transactions on Design Automation of Electronic Systems 27, no. 4 (July 31, 2022): 1–19. http://dx.doi.org/10.1145/3500929.

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On-device embedded artificial intelligence prefers the adaptive learning capability when deployed in the field, and thus in situ training is required. The compute-in-memory approach, which exploits the analog computation within the memory array, is a promising solution for deep neural network (DNN) on-chip acceleration. Emerging non-volatile memories are of great interest, serving as analog synapses due to their multilevel programmability. However, the asymmetry and nonlinearity in the conductance tuning remain grand challenges for achieving high in situ training accuracy. In addition, analog-to-digital converters at the edge of the memory array introduce quantization errors. In this work, we present an algorithm-hardware co-optimization to overcome these challenges. We incorporate the device/circuit non-ideal effects into the DNN propagation and weight update steps. By introducing the adaptive “momentum” in the weight update rule, in situ training accuracy on CIFAR-10 could approach its software baseline even under severe asymmetry/nonlinearity and analog-to-digital converter quantization error. The hardware performance of the on-chip training architecture and the overhead for adding “momentum” are also evaluated. By optimizing the backpropagation dataflow, 23.59 TOPS/W training energy efficiency (12× improvement compared to naïve dataflow) is achieved. The circuits that handle “momentum” introduce only 4.2% energy overhead. Our results show great potential and more relaxed requirements that enable emerging non-volatile memories for DNN acceleration on the embedded artificial intelligence platforms.

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Jafari, Atousa, Christopher Münch, and Mehdi Tahoori. "A Spintronic 2M/7T Computation-in-Memory Cell." Journal of Low Power Electronics and Applications 12, no. 4 (December 6, 2022): 63. http://dx.doi.org/10.3390/jlpea12040063.

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Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead.

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Hosseini, Fateme S., Fanruo Meng, Chengmo Yang, Wujie Wen, and Rosario Cammarota. "Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–21. http://dx.doi.org/10.1145/3477016.

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Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work either requires extra redundancy in hardware or performs defect-aware retraining, imposing significant overhead. In comparison, this paper proposes a set of algorithms that exploit the flexibility in setting the fault-free bits in weight memory to effectively approximate weight values, so as to mitigate defect-induced accuracy drop. These algorithms can be applied as a one-step solution when loading the weights to embedded devices. They only require trivial hardware support and impose negligible run-time overhead. Experiments on popular DNN models show that the proposed techniques successfully boost inference accuracy even in the face of elevated defect rates in the weight memory.

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TAKAI, Yoshiki, Mamoru FUKUCHI, Chihiro MATSUI, Reika KINOSHITA, and Ken TAKEUCHI. "Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs)." IEICE Transactions on Electronics E103.C, no. 4 (April 1, 2020): 171–80. http://dx.doi.org/10.1587/transele.2019cdp0006.

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Sharma, Yogesh, Pankaj Misra, Shojan P. Pavunny, and Ram S. Katiyar. "Unipolar resistive switching behavior of high-k ternary rare-earth oxide LaHoO3 thin films for non-volatile memory applications." MRS Proceedings 1729 (2015): 23–28. http://dx.doi.org/10.1557/opl.2015.92.

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ABSTRACTRare-earth oxides have attracted considerable research interest in resistive random access memories (ReRAMs) due to their compatibility with complementary metal-oxide semiconductor (CMOS) process. To this end we report unipolar resistive switching in a novel ternary rare-earth oxide LaHoO3 (LHO) to accelerate progress and to support advances in this emerging densely scalable research architecture. Amorphous thin films of LHO were fabricated on Pt/TiO2/SiO2/Si substrate by pulsed laser deposition, followed by sputter deposition of platinum top electrode through shadow mask in order to elucidate the resistive switching behavior of the resulting Pt/LHO/Pt metal-insulator-metal (MIM) device structure. Stable unipolar resistive switching characteristics with interesting switching parameters like, high resistance ratio of about 105 between high resistance state (HRS) and low resistance state (LRS), non-overlapping switching voltages with narrow dispersion, and excellent retention and endurance features were observed in Pt/LHO/Pt device structure. The observed resistive switching in LHO was explained by the formation/rupture of conductive filaments formed out of oxygen vacancies and metallic Ho atom. From the current-voltage characteristics of Pt/LHO/Pt structure, the conduction mechanism in LRS and HRS was found to be dominated by Ohm’s law and Poole-Frenkel emission, respectively.

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Izadpanah, Ramin, Christina Peterson, Yan Solihin, and Damian Dechev. "PETRA." ACM Transactions on Architecture and Code Optimization 18, no. 2 (March 2021): 1–26. http://dx.doi.org/10.1145/3446391.

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Emerging byte-addressable Non-Volatile Memories (NVMs) enable persistent memory where process state can be recovered after crashes. To enable applications to rely on persistent data, durable data structures with failure-atomic operations have been proposed. However, they lack the ability to allow users to execute a sequence of operations as transactions. Meanwhile, persistent transactional memory (PTM) has been proposed by adding durability to Software Transactional Memory (STM). However, PTM suffers from high performance overheads and low scalability due to false aborts, logging, and ordering constraints on persistence. In this article, we propose PETRA, a new approach for constructing persistent transactional linked data structures. PETRA natively supports transactions, but unlike PTM, relies on the high-level information from the data structure semantics. This gives PETRA unique advantages in the form of high performance and high scalability. Our experimental results using various benchmarks demonstrate the scalability of PETRA in all workloads and transaction sizes. PETRA outperforms the state-of-the-art PTMs by an order of magnitude in transactions of size greater than one, and demonstrates superior performance in transactions of size one.

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Kamath, Rachana, Parantap Sarkar, Sindhoora Kaniyala Melanthota, Rajib Biswas, Nirmal Mazumder, and Shounak De. "Resistive Memory-Switching Behavior in Solution-Processed Trans, trans-1,4-bis-(2-(2-naphthyl)-2-(butoxycarbonyl)-vinyl) Benzene–PVA-Composite-Based Aryl Acrylate on ITO-Coated PET." Polymers 16, no. 2 (January 12, 2024): 218. http://dx.doi.org/10.3390/polym16020218.

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Resistive switching memories are among the emerging next-generation technologies that are possible candidates for in-memory and neuromorphic computing. In this report, resistive memory-switching behavior in solution-processed trans, trans-1,4-bis-(2-(2-naphthyl)-2-(butoxycarbonyl)-vinyl) benzene–PVA-composite-based aryl acrylate on an ITO-coated PET device was studied. A sandwich configuration was selected, with silver (Ag) serving as a top contact and trans, trans-1,4-bis-(2-(2-naphthyl)-2-(butoxycarbonyl)-vinyl) benzene–PVA-composite-based aryl acrylate and ITO-PET serving as a bottom contact. The current–voltage (I–V) characteristics showed hysteresis behavior and non-zero crossing owing to voltages sweeping from positive to negative and vice versa. The results showed non-zero crossing in the devices’ current–voltage (I–V) characteristics due to the nanobattery effect or resistance, capacitive, and inductive effects. The device also displayed a negative differential resistance (NDR) effect. Non-volatile storage was feasible with non-zero crossing due to the exhibition of resistive switching behavior. The sweeping range was −10 V to +10 V. These devices had two distinct states: ‘ON’ and ‘OFF’. The ON/OFF ratios of the devices were 14 and 100 under stable operating conditions. The open-circuit voltages (Voc) and short-circuit currents (Isc) corresponding to memristor operation were explained. The DC endurance was stable. Ohmic conduction and direct tunneling mechanisms with traps explained the charge transport model governing the resistive switching behavior. This work gives insight into data storage in terms of a new conception of electronic devices based on facile and low-temperature processed material composites for emerging computational devices.

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Wen, Fei, Mian Qin, Paul Gratz, and Narasimha Reddy. "Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–18. http://dx.doi.org/10.1145/3494536.

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Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of current mobile applications. Recently emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of distinct memory classes render a new challenge for memory system design. Ideally, pages should be placed or migrated between the two types of memories according to the data objects’ access properties. Prior system software approaches exploit the program information from OS but at the cost of high software latency incurred by related kernel processes. Hardware approaches can avoid these latencies, however, hardware’s vision is constrained to a short time window of recent memory requests, due to the limited on-chip resources. In this work, we propose OpenMem: a hardware-software cooperative approach that combines the execution time advantages of pure hardware approaches with the data object properties in a global scope. First, we built a hardware-based memory manager unit (HMMU) that can learn the short-term access patterns by online profiling, and execute data migration efficiently. Then, we built a heap memory manager for the heterogeneous memory systems that allows the programmer to directly customize each data object’s allocation to a favorable memory device within the presumed object life cycle. With the programmer’s hints guiding the data placement at allocation time, data objects with similar properties will be congregated to reduce unnecessary page migrations. We implemented the whole system on the FPGA board with embedded ARM processors. In testing under a set of benchmark applications from SPEC 2017 and PARSEC, experimental results show that OpenMem reduces 44.6% energy consumption with only a 16% performance degradation compared to the all-DRAM memory system. The amount of writes to the NVM is reduced by 14% versus the HMMU-only, extending the NVM device lifetime.

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Reuben, John, Dietmar Fey, Suzanne Lancaster, and Stefan Slesazeck. "A Low-Power Ternary Adder Using Ferroelectric Tunnel Junctions." Electronics 12, no. 5 (February 28, 2023): 1163. http://dx.doi.org/10.3390/electronics12051163.

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Computing systems are becoming more and more power-constrained due to unconventional computing requirements like computing on the edge, in-sensor, or simply an insufficient battery. Emerging Non-Volatile Memories are explored to build low-power computing circuits, and adders are one among them. In this work, we propose a low-power adder using a Ferroelectric Tunnel Junction (FTJ). FTJs are two-terminal devices where the data is stored in the polarization state of the device. An FTJ-based majority gate is proposed, which uses a current-mode sensing technique to evaluate the majority of the inputs. By conditionally selecting between the majority and its complement, an XOR operation is implemented, thereby achieving full-adder functionality. Since FTJ-based majority operation is slow, a ternary adder architecture is used to compensate for the speed loss. The ternary adder proposed by us has two stages of full adder and requires O(1) time for n-bit addition. The proposed adder is verified using a simulation in CMOS 130 nm technology. A 32-bit addition can be achieved in 100 μs and consumes 0.78 pJ, which is very power efficient (7.8 nW). The proposed adder can be used in applications where power consumption is crucial, and speed is not a strict requirement.

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Saraswat, Vivek, and Udayan Ganguly. "Stochasticity invariance control in Pr_1−xCa_xMnO₃ RRAM to enable large-scale stochastic recurrent neural networks." Neuromorphic Computing and Engineering 2, no. 1 (December 28, 2021): 014001. http://dx.doi.org/10.1088/2634-4386/ac408a.

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Abstract Emerging non-volatile memories have been proposed for a wide range of applications, from easing the von-Neumann bottleneck to neuromorphic applications. Specifically, scalable RRAMs based on Pr1−x Ca x MnO3 (PCMO) exhibit analog switching have been demonstrated as an integrating neuron, an analog synapse, and a voltage-controlled oscillator. More recently, the inherent stochasticity of memristors has been proposed for efficient hardware implementations of Boltzmann machines. However, as the problem size scales, the number of neurons increases and controlling the stochastic distribution tightly over many iterations is necessary. This requires parametric control over stochasticity. Here, we characterize the stochastic set in PCMO RRAMs. We identify that the set time distribution depends on the internal state of the device (i.e., resistance) in addition to external input (i.e., voltage pulse). This requires the confluence of contradictory properties like stochastic switching as well as deterministic state control in the same device. Unlike ‘stochastic-everywhere’ filamentary memristors, in PCMO RRAMs, we leverage the (i) stochastic set in negative polarity and (ii) deterministic analog Reset in positive polarity to demonstrate 100× reduced set time distribution drift. The impact on Boltzmann machines’ performance is analyzed and as opposed to the ‘fixed external input stochasticity’, the ‘state-monitored stochasticity’ can solve problems 20× larger in size. State monitoring also tunes out the device-to-device variability effect on distributions providing 10× better performance. In addition to the physical insights, this study establishes the use of experimental stochasticity in PCMO RRAMs in stochastic recurrent neural networks reliably over many iterations.

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Asad, Arghavan, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy, and Farah Mohammadi. "An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors." Journal of Circuits, Systems and Computers 28, no. 13 (March 12, 2019): 1950224. http://dx.doi.org/10.1142/s0218126619502244.

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Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.

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Chen, An. "(Invited, Digital Presentation) Emerging Materials and Devices for Energy-Efficient Computing." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1073. http://dx.doi.org/10.1149/ma2022-01191073mtgabs.

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As the CMOS scaling driven by the Moore’s Law approaching the fundamental limits, high energy consumption and heat dissipation have been recognized as the most critical device challenges. Novel switching devices with significantly lower power based on unconventional mechanisms have been explored to replace CMOS in various research programs, e.g., Nanoelectronics Research Initiative (NRI). The major categories of these devices include steep-slope transistors, spintronic devices, ferroelectric devices, and van der Waals devices [1]. These devices are often implemented on emerging materials with unique properties. As the foundation of nanoelectronic devices and systems, novel materials (including dielectrics) present both great challenges and promising opportunities. For example, dielectric layers for gating and electrical insulation are critical for low-dimension devices; magnetic insulators are promising for low-power high-efficiency spintronic devices; ferroelectric materials have been utilized to realize “negative-capacitance” transistors with steep subthreshold slope. Despite abundant scientific breakthroughs achieved on these emerging devices, comprehensive benchmarking has revealed that most of them do not outperform CMOS for Boolean logic and von Neumann architectures [2]. Therefore, the focus of emerging materials and devices has increasingly shifted toward novel computing paradigms. Novel computing paradigms beyond Boolean logic and von Neumann architectures may provide solutions for energy-efficient computing. For example, in-memory computing reduces data movement between computing and memory units, and exploits the intrinsic parallelism in memory arrays. Neural-inspired computing implements cognitive and intelligent functions through a wide range of approaches, e.g., deep neural network, spiking neural network, hyperdimensional computing, probabilistic network, dynamic systems, etc. Although many of these approaches can be implemented in CMOS technologies, more efficient solutions may originate from the engineering and optimization of materials and devices that could enable native implementations of novel computing paradigms. For example, ferroelectric materials, binary and complex oxides, and chalcogenides have been utilized in a wide range of nonvolatile memories and analog devices, which may enable highly efficient in-memory computing and analog computing solutions. At the same time, stringent requirements exist for emerging devices to significantly outperform CMOS in novel computing paradigms, e.g., high density, fast speed, low power, high endurance, long retention, wide analog tunability, asymmetry, etc. [3] Specific requirements vary from application to application. Therefore, device-architecture co-design and co-optimization are important to address these requirements. A holistic approach from basic material exploration to device engineering and further up to architecture co-design has been adopted in more recent research programs, e.g., Energy-Efficient Computing from Devices to Architectures (E2CDA) [4]. This presentation will review the opportunities and challenges of emerging materials and devices for energy-efficient nanoelectronics, and highlight the approaches and perspectives of the E2CDA program. References: K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” IEEE Proc. 98(12), 2169-2184 (2010). C. Pan and A. Naeemi, “Non-Boolean computing benchmarking for beyond-CMOS devices based on cellular neural network,” IEEE J. Explor. Solid-State Comp. Dev. & Circ 2, 36-43 (2016). G.W. Burr, et al, “Neuromorphic computing using non-volatile memory,” Advances in Physics: X, 2(1), 89-124 (2017). A. Chen, “New directions of nanoelectronics research for computing,” 14th IEEE ICSICT (2018).

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Rashid Mahmood, Muhammad Imran, and Sayyid Kamran Hussain. "Assessment of Network & Processor Virtualization in Cloud Computing." Journal of Computing & Biomedical Informatics 2, no. 01 (March 15, 2021): 111–27. http://dx.doi.org/10.56979/201/2021/26.

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Cloud Computing is an emerging field in applied computer science. Cloud computing depends on virtualization, where a sole physical resource is virtualized into numerous virtual resources. Resources that are being virtualized include physical storage, processing units, volatile memories, network, and further physical resources. Processor and network virtualization offer several advantages like lessening hardware cost, energy consumption, and the human struggle for administration and management of resources. In this article, the primary concentration was on the evaluation and assessment of network virtualization between different cloud computing hypervisors and to contrast their evaluated results. This comparison is based on a few experiments performed on Citrix XenServer, Microsoft Hyper-V, and VMware vSphere hypervisors. XenServer uses Open vSwitch for its network virtualization whereas Hyper-V and vSphere use Microsoft network virtualization and vSphere switch for managing their network virtualization respectively. We have found that virtual networks are further scalable and secure than physical networks. We can assign multiple virtual interfaces or connections to a single virtual machine. In light of various experiments, in which we have compared non-virtualized with virtualized scenarios, for all these above-mentioned hypervisors, we found out that we can use virtual networks with and without VLAN Tags or VLAN Ids. Hyper-V provides further flexibility and options regarding VLAN Tag in comparison with XenServer or vSphere. We have also found that XenServer and vSphere give us extra network throughput in comparison with Hyper-V in terms of TCP and UDP whereas Round Trip Time (RTT) in the virtual network of all hypervisors are high in comparison with the non-virtual environment. Network CPU usage is also measured and found that vSphere and XenServer together consume more CPU during network activity in comparison with Hyper-V. We also found that processor virtualization did not majorly result from the average schedule time in comparison with a non-virtualized machine. We consequently conclude that in general a small reduction in the performance, in the case of virtualization is insignificant as compared with the advantages we get from virtualization when using cloud hypervisors. For the application of virtualization, this work will motivate to set up of data centers using a virtualized environment.

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Ahmed, Soyed Tuhin, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, and Mehdi B. Tahoori. "SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures." ACM Transactions on Embedded Computing Systems 22, no. 5s (September 9, 2023): 1–25. http://dx.doi.org/10.1145/3609116.

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Recent development in neural networks (NNs) has led to their widespread use in critical and automated decision-making systems, where uncertainty estimation is essential for trustworthiness. Although conventional NNs can solve many problems accurately, they do not capture the uncertainty of the data or the model during optimization. In contrast, Bayesian neural networks (BNNs), which learn probabilistic distributions for their parameters, offer a sound theoretical framework for estimating uncertainty. However, traditional hardware implementations of BNNs are expensive in terms of computational and memory resources, as they (i) are realized with inefficient von Neumann architectures, (ii) use a significantly large number of random number generators (RNGs) to implement the distributions of BNNs, and (iii) have a substantially greater number of parameters than conventional NNs. Computing-in-memory (CiM) architectures with emerging resistive non-volatile memories (NVMs) are promising candidates for accelerating classical NNs. In particular, spintronic technology, which is distinguished by its low latency and high endurance, aligns very well with these requirements. In the specific context of Bayesian neural networks (BNNs), spintronics technologies are very valuable, thanks to their inherent potential to act as stochastic or as deterministic devices. Consequently, BNNs mapped on spintronic-based CiM architectures could be a highly efficient implementation strategy. However, the direct implementation on CiM hardware of the learned probabilistic distributions of BNN may not be feasible and can incur high overhead. In this work, we propose a new Bayesian neural network topology, named SpinBayes , that is able to perform efficient sampling during the Bayesian inference process. Moreover, a Bayesian approximation method, called in-memory approximation , is proposed that approximates the original probabilistic distributions of BNN with a distribution that can be efficiently mapped to spintronic-based CiM architectures. Compared to state-of-the-art methods, the memory overhead is reduced by 8× and the energy consumption by 80×. Our method has been evaluated on several classification and semantic segmentation tasks and can detect up to 100% of various types of out-of-distribution data, highlighting the robustness of our approach, without any performance sacrifice.

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Feng, Guangdi, Qiuxiang Zhu, Xuefeng Liu, Luqiu Chen, Xiaoming Zhao, Jianquan Liu, Shaobing Xiong, et al. "A ferroelectric fin diode for robust non-volatile memory." Nature Communications 15, no. 1 (January 13, 2024). http://dx.doi.org/10.1038/s41467-024-44759-5.

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AbstractAmong today’s nonvolatile memories, ferroelectric-based capacitors, tunnel junctions and field-effect transistors (FET) are already industrially integrated and/or intensively investigated to improve their performances. Concurrently, because of the tremendous development of artificial intelligence and big-data issues, there is an urgent need to realize high-density crossbar arrays, a prerequisite for the future of memories and emerging computing algorithms. Here, a two-terminal ferroelectric fin diode (FFD) in which a ferroelectric capacitor and a fin-like semiconductor channel are combined to share both top and bottom electrodes is designed. Such a device not only shows both digital and analog memory functionalities but is also robust and universal as it works using two very different ferroelectric materials. When compared to all current nonvolatile memories, it cumulatively demonstrates an endurance up to 1010 cycles, an ON/OFF ratio of ~102, a feature size of 30 nm, an operating energy of ~20 fJ and an operation speed of 100 ns. Beyond these superior performances, the simple two-terminal structure and their self-rectifying ratio of ~ 104 permit to consider them as new electronic building blocks for designing passive crossbar arrays which are crucial for the future in-memory computing.

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Piccinini, Enrico. "Editorial: Emerging non-volatile memories and beyond: From fundamental physics to applications." Frontiers in Physics 10 (September 13, 2022). http://dx.doi.org/10.3389/fphy.2022.1006756.

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Sivakumar, S., John Jose, and Vijaykrishnan Narayanan. "Enhancing Lifetime and Performance of MLC NVM Caches using Embedded Trace buffers." ACM Transactions on Design Automation of Electronic Systems, April 16, 2024. http://dx.doi.org/10.1145/3659102.

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Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies like SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84x less space and 2.62x less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilised Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36x, and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41x and 11%, respectively, compared to baseline MLC LLCs.

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Jangra, Payal, and Manoj Duhan. "Performance-based comparative study of existing and emerging non-volatile memories: a review." Journal of Optics, December 23, 2022. http://dx.doi.org/10.1007/s12596-022-01058-w.

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Khurana, Geetika, Nitu Kumar, Manish Chhowalla, James F. Scott, and Ram S. Katiyar. "Non-Polar and Complementary Resistive Switching Characteristics in Graphene Oxide devices with Gold Nanoparticles: Diverse Approach for Device Fabrication." Scientific Reports 9, no. 1 (October 22, 2019). http://dx.doi.org/10.1038/s41598-019-51538-6.

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Abstract Downscaling limitations and limited write/erase cycles in conventional charge-storage based non-volatile memories stimulate the development of emerging memory devices having enhanced performance. Resistive random-access memory (RRAM) devices are recognized as the next-generation memory devices for employment in artificial intelligence and neuromorphic computing, due to their smallest cell size, high write/erase speed and endurance. Unipolar and bipolar resistive switching characteristics in graphene oxide (GO) have been extensively studied in recent years, whereas the study of non-polar and complementary switching is scarce. Here we fabricated GO-based RRAM devices with gold nanoparticles (Au Nps). Diverse types of switching behavior are observed by changing the processing methods and device geometry. Tri-layer GO-based devices illustrated non-polar resistive switching, which is a combination of unipolar and bipolar switching. Five-layer GO-based devices depicted complementary resistive switching having the lowest current values ~12 µA; and this structure is capable of resolving the sneak path issue. Both devices show good retention and endurance performance. Au Nps in tri-layer devices assisted the conducting path, whereas in five-layer devices, Au Nps layer worked as common electrodes between co-joined cells. These GO-based devices with Au Nps comprising different configuration are vital for practical applications of emerging non-volatile resistive memories.

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Yang, Fang, Hong Kuan Ng, Xin Ju, Weifan Cai, Jing Cao, Dongzhi Chi, Ady Suwardi, et al. "Emerging Opportunities for Ferroelectric Field‐Effect Transistors: Integration of 2D Materials." Advanced Functional Materials, February 2024. http://dx.doi.org/10.1002/adfm.202310438.

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AbstractThe rapid development in information technologies necessitates rapid advancements of their supporting hardware. In particular, new computing paradigms are needed to overcome the bottleneck of traditional von Neumann architecture. Bottom‐up innovation, especially at the materials and devices level, has the potential to disrupt existing technologies through their emergent phenomena. As a new type of conceptual device, 2D ferroelectric field‐effect transistor (FeFET) is highly sought after due to its potential integration with modern semiconductor processes. Its low power consumption, area efficiency, and ultra‐fast operation provide an extra edge over traditional technologies. This review highlights recent developments in 2D FeFET, covering their device construction, working mechanisms, 2D ferroelectric polarization mechanism, multi‐functional applications and prospects. In particular, the combination of 2D semiconductor and ferroelectric dielectric materials for multi‐functionality applications is discussed. This includes non‐volatile memories (NVM), neural network computing, non‐volatile logic operation, and photodetectors. As a novel device platform, 2D semiconductor and ferroelectric interfaces are bestowed with a plethora of emergent physical mechanisms and applications.

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Amouroux, J., V. Della Marca, E. Petit, D. Deleruyelle, M. Putero, Ch Muller, P. Boivin, et al. "Growth and In-line Characterization of Silicon Nanodots Integrated in Discrete Charge Trapping Non-volatile Memories." MRS Proceedings 1337 (2011). http://dx.doi.org/10.1557/opl.2011.975.

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ABSTRACTNon-Volatile Memories (NVM) integrating silicon nanodots (noted SDs) are considered as an emerging solution to extend Flash memories downscaling. In this alternative memory technology, silicon nanocrystals act as discrete traps for injected charges.Si-dots were grown by Low Pressure Chemical Vapor Deposition (LPCVD) on top of tunnel oxide. Depending on the pre-growth surface treatment, tunnel oxide surface may present either siloxane or silanol groups. SDs deposition relies on a 2–steps process: nucleation by SiH4 and selective growth with SiH2Cl2.In a context of technological industrialization, it is of primary importance to develop in-line metrology tools dedicated to Si-dots growth process control. Hence, silicon-dots were observed in top view by using an in-line Critical Dimension Scanning Electron Microscopy CDSEM and their average size and density were extracted from image processing. In addition, Haze measurement, generally used for bare silicon surface characterization, was customized to quantify Si-dots deposition uniformity over the wafer. Finally, Haze value was correlated to Si nanodots density and size determined by CDSEM.

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Puglisi, Francesco Maria, Tommaso Zanotti, and Paolo Pavan. "Optimized Synthesis Method for Ultra-Low Power Multi-Input Material Implication Logic With Emerging Non-Volatile Memories." IEEE Transactions on Circuits and Systems I: Regular Papers, 2021, 1–11. http://dx.doi.org/10.1109/tcsi.2021.3079986.

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Ryu, Hojoon, Haonan Wu, Fubo Rao, and Wenjuan Zhu. "Ferroelectric Tunneling Junctions Based on Aluminum Oxide/ Zirconium-Doped Hafnium Oxide for Neuromorphic Computing." Scientific Reports 9, no. 1 (December 2019). http://dx.doi.org/10.1038/s41598-019-56816-x.

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AbstractFerroelectric tunneling junctions (FTJs) with tunable tunneling electroresistance (TER) are promising for many emerging applications, including non-volatile memories and neurosynaptic computing. One of the key challenges in FTJs is the balance between the polarization value and the tunneling current. In order to achieve a sizable on-current, the thickness of the ferroelectric layer needs to be scaled down below 5 nm. However, the polarization in these ultra-thin ferroelectric layers is very small, which leads to a low tunneling electroresistance (TER) ratio. In this paper, we propose and demonstrate a new type of FTJ based on metal/Al2O3/Zr-doped HfO2/Si structure. The interfacial Al2O3 layer and silicon substrate enable sizable TERs even when the thickness of Zr-doped HfO2 (HZO) is above 10 nm. We found that F-N tunneling dominates at read voltages and that the polarization switching in HZO can alter the effective tunneling barrier height and tune the tunneling resistance. The FTJ synapses based on Al2O3/HZO stacks show symmetric potentiation/depression characteristics and widely tunable conductance. We also show that spike-timing-dependent plasticity (STDP) can be harnessed from HZO based FTJs. These novel FTJs will have high potential in non-volatile memories and neural network applications.

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Yin, Shong, Steven K. Volkman, and Vivek Subramanian. "Solution Processed Silver Sulfide Filament Memories." MRS Proceedings 1113 (2008). http://dx.doi.org/10.1557/proc-1113-f02-09.

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ABSTRACTIonic resistive switches are emerging as a potential successor for flash in non!volatile memory applications. In ionic switches, metal cations migrate through a solid electrolyte forming filaments on an inert cathode that results in an abrupt increase in conductivity. This process is reversible, and the switches may be reverted to a low!conductive state. These switches have low transition voltages and fast read speed. The low switching energy potentially makes them more scalable than many other resistive memories. Silver Sulfide Resistive switches have been fabricated by sulfidizing evaporated silver films in Sulfur solutions. XPS is used to quantify stoichiometry of resultant films. SEM and AFM indicate that surface roughness increases with sulfidation time as the bulk silver film is consumed in forming the silver sulfide. XRD has confirmed presence of the acanthite phase of silver sulfide in the films. The entire process is performed at temperatures below 200C, so the devices are potentially stackable over conventional CMOS substrates in a BEOL process, and are applicable to printable electronics on plastic substrates. Initial characteristics measured on these cells are very promising, exhibiting low energy switching and good programming margins. Write/Erase voltages for cells were about 400mV and !200mV respectively. Ron/Roff ratios range from 10 to as high as 10, 000 depending on process conditions. Impact of bath concentration, bath temperature and post!annealing on the silver sulfide film structure are studied. Ionic switching is demonstrated in the films.

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Nagarajan, Karthikeyan, Mohammad Nasim Imtiaz Khan, and Swaroop Ghosh. "ENTT/ENTTR: A Family of Improved Emerging NVM-Based Trojan Triggers and Resets." Frontiers in Nanotechnology 4 (April 20, 2022). http://dx.doi.org/10.3389/fnano.2022.822017.

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Hardware Trojans in Integrated Circuits (ICs), that are inserted as hostile modifications in the design phase and/or the fabrication phase, are a security threat since the semiconductor manufacturing process is increasingly becoming globalized. These Trojans are devised to stay hidden during standard structural and functional testing procedures and only activate under pre-determined rare conditions (e.g., after a large number of clock cycles or the assertion of an improbable net). Once triggered, they can deliver malicious payloads (e.g., denial-of-service and information leakage attacks). Current literature identifies a collection of logic Trojans (both trigger circuits and payloads), but minimal research exists on memory Trojans despite their high feasibility. Emerging Non-Volatile Memories (NVMs), such as Resistive RAM (RRAM), have special properties such as non-volatility and gradual drift in bitcell resistance under a pulsing voltage input that make them prime targets to deploy hardware Trojans. In this paper, we present two delay-based and two voltage-based Trojan triggers using emerging NVM (ENTT) by utilizing RRAM’s resistance drift under a pulsing voltage input. Simulations show that ENTTs can be triggered by reading/writing to a specific memory address N times (N could be 2,500–3,500 or a different value for each ENTT design). Since the RRAM is non-volatile, address accesses can be intermittent and therefore stay undetected from system-level techniques that can identify continuous hammering as a possible security threat. We also present three reset techniques to de-activate the triggers. The resulting static/dynamic power overhead and maximum area overhead incurred by the proposed ENTTs are 104.24 μW/0.426 μW and 9.15 μm2, respectively in PTM 65 nm technology. ENTTs are effective against contemporary Trojan detection techniques and system level protocols. We also propose countermeasures to detect ENTT during the test phase and/or prevent fault-injection attacks during deployment.

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Shen, Yang, He Tian, Yanming Liu, Fan Wu, Zhaoyi Yan, Thomas Hirtz, Xuefeng Wang, and Tian-Ling Ren. "Modeling of Gate Tunable Synaptic Device for Neuromorphic Applications." Frontiers in Physics 9 (December 24, 2021). http://dx.doi.org/10.3389/fphy.2021.777691.

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The emerging memories are great candidates to establish neuromorphic computing challenging non-Von Neumann architecture. Emerging non-volatile resistive random-access memory (RRAM) attracted abundant attention recently for its low power consumption and high storage density. Up to now, research regarding the tunability of the On/Off ratio and the switching window of RRAM devices remains scarce. In this work, the underlying mechanisms related to gate tunable RRAMs are investigated. The principle of such a device consists of controlling the filament evolution in the resistive layer using graphene and an electric field. A physics-based stochastic simulation was employed to reveal the mechanisms that link the filament size and the growth speed to the back-gate bias. The simulations demonstrate the influence of the negative gate voltage on the device current which in turn leads to better characteristics for neuromorphic computing applications. Moreover, a high accuracy (94.7%) neural network for handwritten character digit classification has been realized using the 1-transistor 1-memristor (1T1R) crossbar cell structure and our stochastic simulation method, which demonstrate the optimization of gate tunable synaptic device.

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Parra, Jorge, Juan Navarro-Arenas, Miroslavna Kovylina, and Pablo Sanchis. "Impact of GST thickness on GST-loaded silicon waveguides for optimal optical switching." Scientific Reports 12, no. 1 (June 13, 2022). http://dx.doi.org/10.1038/s41598-022-13848-0.

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AbstractPhase-change integrated photonics has emerged as a new platform for developing photonic integrated circuits by integrating phase-change materials like GeSbTe (GST) onto the silicon photonics platform. The thickness of the GST patch that is usually placed on top of the waveguide is crucial for ensuring high optical performance. In this work, we investigate the impact of the GST thickness in terms of optical performance through numerical simulation and experiment. We show that higher-order modes can be excited in a GST-loaded silicon waveguide with relatively thin GST thicknesses (<100 nm), resulting in a dramatic reduction in the extinction ratio. Our results would be useful for designing high-performance GST/Si-based photonic devices such as non-volatile memories that could find utility in many emerging applications.

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Rietz, Vincent, Christopher Münch, Mahta Mayahinia, and Mehdi Tahoori. "Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration." it - Information Technology, May 3, 2023. http://dx.doi.org/10.1515/itit-2023-0019.

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Abstract Data-intensive applications have a huge demand on processor-memory communication. To reduce the amount of data transfers and their associated latency and energy, Compute-in-Memory (CIM) architectures can be used to perform operations ranging from simple binary operations to more complex operations such as additions and matrix-vector multiplications directly within the memory. However, proper adjustments to the memory hierarchy are needed to enable the execution of CIM operations. To evaluate the trade-off between the usage of different emerging non-volatile memories for CIM and conventional computing architectures, this work extends the widely used gem5 simulation framework with an extensible timing-aware main memory CIM simulation capability. This framework is used to analyze the performance of CIM extended main memory with various emerging memory technologies, namely Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), Redox-based RAM (ReRAM) and Phase-Change Memory (PCM). We evaluate different workloads from the PolyBench/C benchmark suite and other selected examples. In comparison to a processor-centric system, the results show a significant reduction in execution time for the majority of applications.

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Chen, Bo, Chengcheng Wang, Xuepeng Zhan, Shuhao Wu, Lu Tai, Junyao Mei, Jixuan Wu, and Jiezhi Chen. "Sub-10nm HfZrO ferroelectric synapse with multiple layers and different ratios for neuromorphic computing." Nanotechnology, September 19, 2023. http://dx.doi.org/10.1088/1361-6528/acfb0c.

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Abstract To break the von Neumanan bottleneck, emerging non-volatile memories have gain extensive attentions in hardware implementingimplementing neuromorphic computing. The device scaling with low operating voltage is of great importance for delivering a high-integrating and energy-efficient neuromorphic system. In this paper, we fabricated sub-10nm ferroelectric capacitors based on HfZrO (HZO) film withbased on HfZrO (HZO) film with varyingvarying HHffOO andand ZrO components. Compared to the conventional HZO capacitors (constant component of 1:1), the varying component ferroelectric capacitors show similar remnant polarization but a lower coercive electric field (Ec). This enables the partial domain switching processed at lower pulse amplitude and width, which is essential for emulating typical synaptic features. In the MNIST recognition task, the accuracy of sub-10nm ferroelectric artificial synapse can approach to ~ 84.54%. Our findings may provide great potentials for developing next-generation neuromorphic computing based ultra-scaled ferroelectric artificial synapses.

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de Moura, Rafael Fão, João Paulo Cardoso de Lima, and Luigi Carro. "Data and Computation Reuse in CNNs using Memristor TCAMs." ACM Transactions on Reconfigurable Technology and Systems, July 20, 2022. http://dx.doi.org/10.1145/3549536.

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Exploiting computational and data reuse in CNNs is crucial for the successful design of resource-constrained platforms. In image recognition applications, high levels of input locality and redundancy present in CNNs have become the golden goose for skipping costly arithmetic operations. One promising technique for this consists in storing function responses of some input patterns into offline lookup tables and replacing online computation with search operations, which are highly efficient when implemented by emerging non-volatile memory technologies. In this work, we rethink both algorithm and architecture for exploiting locality and reuse opportunities by replacing entire convolutions with searches on Content-Addressable Memories. By previously calculating convolution results and building compact lookup tables with our novel clustering algorithm, one can evaluate activations at constant time complexity, also requiring a single read operation of the current input tensor. Then, we devise a reconfigurable array of processing elements based on memristive Ternary Content-addressable Memories to efficiently implement the algorithmic solution and meet the flexibility requirements of several CNN architectures. Results show that our design reduces the number of multiplications and memory accesses proportionally to the number of convolutional layer channels. The average performance is 1172 and 82 FPS for AlexNet and VGG-16 models, thus outperforming state-of-the-art works by 13 ×.

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Verma, Gaurav, Sandeep Soni, Arshid Nisar Laway, and Brajesh Kumar Kaushik. "Multi-bit MRAM based high performance neuromorphic accelerator for image classification." Neuromorphic Computing and Engineering, February 20, 2024. http://dx.doi.org/10.1088/2634-4386/ad2afa.

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Abstract Binary neural networks (BNNs) are the most efficient solution to bridge the design gap of the hardware implementation of neural networks in a resource-constrained environment. Spintronics is a prominent technology among emerging fields for next-generation on-chip non-volatile memory (NVM). Spin transfer torque (STT) and spin-orbit torque (SOT) based magnetic random-access memory (MRAM) offer non-volatility and negligible static power. Over the last few years, STT and SOT-based multilevel spintronic memories have emerged as a promising solution to attain high storage density. This paper presents the operation principle and performance evaluation of spintronics-based single-bit STT and SOT MRAM, dual-level cells (DLCs), three-level cells (TLCs), and four-level cells (FLCs). Further, multi-layer perceptron (MLP) architectures have been utilized to perform MNIST image classification with these multilevel devices. The performance of the complete system level consisting of crossbar arrays with various MRAM bit cells in terms of area, energy, and latency is evaluated. The throughput efficiency of the BNN accelerator using TLCs is 26.6X, and 3.61X higher than conventional single-bit STT-MRAM, and SOT-MRAM respectively.

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Ahmed, Soyed Tuhin, Mahta Mayahinia, Michael Hefenbrock, Christopher Münch, and Mehdi B. Tahoori. "Design-Time Reference Current Generation for Robust Spintronic-Based Neuromorphic Architecture." ACM Journal on Emerging Technologies in Computing Systems, September 27, 2023. http://dx.doi.org/10.1145/3625556.

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Neural Networks (NN) can be efficiently accelerated in a neuromorphic fabric based on emerging resistive non-volatile memories (NVM), such as Spin Transfer Torque Magnetic RAM (STT-MRAM). Compared to other NVM technologies, STT-MRAM offers many benefits, such as fast switching, high endurance, and CMOS process compatibility. However, due to its low ON/OFF-ratio, process variations and runtime temperature fluctuations can lead to miss-quantizing the sensed current and in turn, degradation of inference accuracy. In this paper, we analyze the impact of the sensed accumulated current variation on the inference accuracy in Binary NNs and propose a design-time reference current generation method to improve the robustness of the implemented NN under different temperature and process variation scenarios (up to 125 °C). Our proposed method is robust to both process and temperature variations. The proposed method improves the accuracy of NN inference by up to \(20.51\% \) on the MNIST, Fashion-MNIST, and CIFAR-10 benchmark datasets in the presence of process and temperature variations without additional runtime hardware overhead compared to existing solutions.

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Chen, Lei, Jiacheng Zhao, Chenxi Wang, Ting Cao, John Zigman, Haris Volos, Onur Mutlu, et al. "Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories." ACM Transactions on Computer Systems, February 4, 2022. http://dx.doi.org/10.1145/3511211.

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Abstract:

To process real-world datasets, modern data-parallel systems often require extremely large amounts of memory, which are both costly and energy-inefficient. Emerging non-volatile memory (NVM) technologies offer high capacity compared to DRAM and low energy compared to SSDs. Hence, NVMs have the potential to fundamentally change the dichotomy between DRAM and durable storage in Big Data processing. However, most Big Data applications are written in managed languages and executed on top of a managed runtime that already performs various dimensions of memory management. Supporting hybrid physical memories adds in a new dimension, creating unique challenges in data replacement. This paper proposes Panthera, a semantics-aware, fully automated memory management technique for Big Data processing over hybrid memories. Panthera analyzes user programs on a Big Data system to infer their coarse-grained access patterns, which are then passed to the Panthera runtime for efficient data placement and migration. For Big Data applications, the coarse-grained data division information is accurate enough to guide the GC for data layout, which hardly incurs overhead in data monitoring and moving. We implemented Panthera in OpenJDK and Apache Spark. Based on Big Data applications’ memory access pattern, we also implemented a new profiling-guided optimization strategy, which is transparent to applications. With this optimization, our extensive evaluation demonstrates that Panthera reduces energy by 32 – 53% at less than 1% time overhead on average. To show Panthera’s applicability, we extend it to QuickCached, a pure Java implementation of Memcached. Our evaluation results show that Panthera reduces energy by 28.7% at 5.2% time overhead on average.

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Journal articles on the topic 'Emerging Non-Volatile memories'

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