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Academic literature on the topic 'Emerging Non-Volatile memories'

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Published: 25 May 2024

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Journal articles on the topic "Emerging Non-Volatile memories"

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Fujisaki, Yoshihisa. "Overview of emerging semiconductor non-volatile memories." IEICE Electronics Express 9, no. 10 (2012): 908–25. http://dx.doi.org/10.1587/elex.9.908.

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Melanotte, M., R. Bez, and G. Crisenza. "Non volatile memories-status and emerging trends." Microelectronic Engineering 15, no. 1-4 (October 1991): 603–12. http://dx.doi.org/10.1016/0167-9317(91)90293-m.

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Si, Mengwei, Huai-Yu Cheng, Takashi Ando, Guohan Hu, and Peide D. Ye. "Overview and outlook of emerging non-volatile memories." MRS Bulletin 46, no. 10 (October 2021): 946–58. http://dx.doi.org/10.1557/s43577-021-00204-2.

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Dieny, B., and Chennupati Jagadish. "Emerging non-volatile memories: magnetic and resistive technologies." Journal of Physics D: Applied Physics 46, no. 7 (February 1, 2013): 070301. http://dx.doi.org/10.1088/0022-3727/46/7/070301.

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Fujisaki, Yoshihisa. "Review of Emerging New Solid-State Non-Volatile Memories." Japanese Journal of Applied Physics 52, no. 4R (April 1, 2013): 040001. http://dx.doi.org/10.7567/jjap.52.040001.

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Makarov, Alexander, Viktor Sverdlov, and Siegfried Selberherr. "Modeling Emerging Non-volatile Memories: Current Trends and Challenges." Physics Procedia 25 (2012): 99–104. http://dx.doi.org/10.1016/j.phpro.2012.03.056.

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Wang, Yan, Ziyu Lv, Li Zhou, Xiaoli Chen, Jinrui Chen, Ye Zhou, V. A. L. Roy, and Su-Ting Han. "Emerging perovskite materials for high density data storage and artificial synapses." Journal of Materials Chemistry C 6, no. 7 (2018): 1600–1617. http://dx.doi.org/10.1039/c7tc05326f.

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Khan, Mohammad Nasim Imtiaz, Shivam Bhasin, Bo Liu, Alex Yuan, Anupam Chattopadhyay, and Swaroop Ghosh. "Comprehensive Study of Side-Channel Attack on Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 28, 2021): 38. http://dx.doi.org/10.3390/jlpea11040038.

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Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache.
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Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Comprehensive Study of Security and Privacy of Emerging Non-Volatile Memories." Journal of Low Power Electronics and Applications 11, no. 4 (September 24, 2021): 36. http://dx.doi.org/10.3390/jlpea11040036.

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Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.
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Waser, Rainer. "Emerging Non-Volatile Memories by Exploiting Redox Reactions on the Nanoscale." ECS Transactions 25, no. 7 (December 17, 2019): 441–46. http://dx.doi.org/10.1149/1.3203981.

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Dissertations / Theses on the topic "Emerging Non-Volatile memories"

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GROSSI, Alessandro. "Emerging non volatile memories reliability." Doctoral thesis, Università degli studi di Ferrara, 2017. http://hdl.handle.net/11392/2488205.

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This work presents the results of the research activity performed during the XXIX-th cycle of the Ph.D. school in Engineering Science of Università degli Studi di Ferrara. In particular the thesis focuses on the electrical characterization, physics, modeling and reliability of innovative non-volatile memories, addressing three of the most promising candidates for the floating gate based memories replacement which are currently facing a technology dead end. The manuscript is organized as follows. In Chapter 1 planar CT-NAND memory arrays are considered, showing that the main reliability issues affecting such technology are endurance and retention. Enhanced program and read algorithm able to reduce such limitations will be presented and characterized, highlighting the advantages obtained in terms of reliability. After that, the performances of Solid State Drives (SSD) integrating CT-based memories and using the proposed algorithms will be simulated and evaluated. In Chapter 2 the results obtained on RRAM will be presented and discussed focusing on the variability, which is the main reliability issue of these nonvolatile memories. The impact of Forming, Set and Reset operations on variability will be evaluated, starting from single pulse operations up to program and verify algorithms. The quantum point contact model will be used to give a physical explanation of the results obtained in characterization. After that, the process parameters impact on variability and reliability will be discussed. Finally, the fundamental variability limits of such technologies will be defined through an extensive array characterization and radiation hard application perspectives will be provided. In Chapter 3, the results obtained on TAS-MRAM technology will be reported. The reliability and the cell-to-cell variability will be evaluated during endurance tests by extracting a set of characteristic parameters from measurements performed on 1kbits arrays. After a preliminary optimization of the writing parameters on fresh devices, the effectiveness of the optimized parameters will be verified during cycling by evaluating their advantages in terms of cell-to-cell variability and breakdown reduction. After that, a novel TAS-MRAM array with optimized read procedure (Self Referenced) will be tested and compared with the previous one to highlight its advantages in terms of reliability. The conclusions of this work will be reported at the end of the manuscript outlining what has been accomplished, proposing possible applications for the technologies studied in this thesis and suggesting future works that could extend and improve the understanding of the reliability issues on such memory technologies.
Questa tesi presenta i risultati dell’attività di ricerca svolta durante il ciclo XXIX di dottorato in Scienze dell’Ingegneria presso l’Università degli Studi di Ferrara. In particolare la tesi tratta la caratterizzazione elettrica, la analisi statistica ed il modeling dei meccanismi fisici e dell’affidabilità di memorie non volatili innovative. Nel manoscritto vengono considerate tre delle tecnologie più promettenti per la futura sostituzione delle memorie flash, che stanno attualmente raggiungendo i loro limiti di scalabilità tecnologici. Il manoscritto è organizzato come segue. Nel capitolo 1 vengono studiate matrici di celle di memoria CT-NAND planari, mostrando che l’affidabilità di tale tecnologia è principalmente limitata dalla bassa capacità di ritenzione dei dati e dalla breve durata in termini di cicli di scrittura e cancellazione. Nella prima parte del capitolo sono stati caratterizzati algoritmi di programmazione e lettura innovativi in grado di ridurre tali limitazioni, analizzandone i vantaggi ottenuti in termini di affidabilità. In seguito sono state simulate e valutate le prestazioni che sarebbero ottenute in dischi a stato solido (SSD) nel caso in cui tali memorie ed algoritmi fossero utilizzati. Nel capitolo 2 i risultati ottenuti sulla tecnologia RRAM sono presentati e discussi prestando particolare attenzione alla variabilità, che è il problema principale di questa tecnologia di memorizzazione. L’impatto delle operazioni di Forming, Set e Reset sulla variabilità viene valutato sia per operazioni a singolo impulso che per complessi algoritmi di programmazione che prevedono operazioni di verifica della corretta memorizzazione dei dati. Il modello quantum point contact è stato utilizzato per fornire una spiegazione fisica dei risultati ottenuti durante la caratterizzazione elettrica. Successivamente è stato discusso l’impatto dei parametri di processo su variabilità ed affidabilità delle celle di memoria. Infine, nella parte finale del capitolo i limiti intrinseci di variabilità di tale tecnologia sono stati definiti attraverso una caratterizzazione estensiva di matrici di celle di memoria e sono state fornite alcune prospettive di utilizzo per applicazioni spaziali. Nel capitolo 3 vengono riportati i risultati ottenuti sulla tecnologia TAS-MRAM. L’affidabilità e la variabilità tra celle di memoria sono state valutate durante test di durata in cui sono state svolte milioni di operazioni di programmazione e cancellazione, estraendo dalle misure su matrici di celle i parametri caratteristici in grado di descriverne il funzionamento. Dopo un’ottimizzazione preliminare delle operazioni di scrittura, l’efficacia delle condizioni di programmazione ottimizzate è stata verificata con test di durata valutandone i vantaggi nella riduzione sia della variabilità tra celle che del numero di celle degradate durante il test. In seguito è stata testata una matrice di celle TAS-MRAM in cui la procedura di lettura è stata ottimizzata (Self Referenced) ed i risultati ottenuti sono stati confrontati con i precedenti per evidenziarne i vantaggi in termini di affidabilità. Nelle conclusioni di questo lavoro riportate alla fine del manoscritto sono riassunti i risultati ottenuti, proposte possibili applicazioni per le tecnologie analizzate e suggerite eventuali attività future che potrebbero estendere e migliorare la comprensione delle problematiche di affidabilità sulle tecnologie di memoria considerate.
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Books on the topic "Emerging Non-Volatile memories"

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Hong, Seungbum, Orlando Auciello, and Dirk Wouters, eds. Emerging Non-Volatile Memories. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9.

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Wouters, Dirk, Orlando Auciello, and Seungbum Hong. Emerging Non-Volatile Memories. Springer, 2016.

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Wouters, Dirk, Orlando Auciello, and Seungbum Hong. Emerging Non-Volatile Memories. Springer, 2014.

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Wouters, Dirk, Orlando Auciello, and Seungbum Hong. Emerging Non-Volatile Memories. Springer, 2014.

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Dimitrakis, Panagiotis. Charge-Trapping Non-Volatile Memories: Volume 2--Emerging Materials and Structures. Springer, 2017.

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Dimitrakis, Panagiotis. Charge-Trapping Non-Volatile Memories: Volume 2--Emerging Materials and Structures. Springer, 2018.

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Dimitrakis, Panagiotis. Charge-Trapping Non-Volatile Memories: Volume 2--Emerging Materials and Structures. Springer, 2017.

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In Search of the Next Memory: Inside the Circuitry from the Oldest to the Emerging Non-Volatile Memories. Springer, 2017.

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Campardo, Giovanni, and Roberto Gastaldi. In Search of the Next Memory: Inside the Circuitry from the Oldest to the Emerging Non-Volatile Memories. Springer, 2018.

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Campardo, Giovanni, and Roberto Gastaldi. In Search of the Next Memory: Inside the Circuitry from the Oldest to the Emerging Non-Volatile Memories. Springer, 2017.

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Book chapters on the topic "Emerging Non-Volatile memories"

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Martin, Lane W., Ying-Hao Chu, and R. Ramesh. "Emerging Multiferroic Memories." In Emerging Non-Volatile Memories, 103–66. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_3.

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Yu, Shimeng. "Emerging Non-volatile Memories." In Semiconductor Memory Devices and Circuits, 133–93. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003138747-5.

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Lee, Myoung-Jae. "Emerging Oxide Resistance Change Memories." In Emerging Non-Volatile Memories, 195–218. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_5.

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Auciello, Orlando, Carlos A. Paz de Araujo, and Jolanta Celinska. "Review of the Science and Technology for Low- and High-Density Nonvolatile Ferroelectric Memories." In Emerging Non-Volatile Memories, 3–35. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_1.

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Dieny, B., R. Sousa, G. Prenat, L. Prejbeanu, and O. Redon. "Hybrid CMOS/Magnetic Memories (MRAMs) and Logic Circuits." In Emerging Non-Volatile Memories, 37–101. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_2.

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Lencer, Dominic, Martin Salinga, and Matthias Wuttig. "Phase-Change Materials for Data Storage Applications." In Emerging Non-Volatile Memories, 169–93. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_4.

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Yang, J. Joshua, and Gilberto Medeiros-Ribeiro. "Oxide Based Memristive Nanodevices." In Emerging Non-Volatile Memories, 219–56. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_6.

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Hong, Seungbum, and Yunseok Kim. "Ferroelectric Probe Storage Devices." In Emerging Non-Volatile Memories, 259–73. Boston, MA: Springer US, 2014. http://dx.doi.org/10.1007/978-1-4899-7537-9_7.

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Pirovano, Agostino. "Physics and Technology of Emerging Non-Volatile Memories." In In Search of the Next Memory, 27–46. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-47724-4_3.

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Wei, Wei, Dejun Jiang, Jin Xiong, and Mingyu Chen. "Exploring Opportunities for Non-volatile Memories in Big Data Applications." In Big Data Benchmarks, Performance Optimization, and Emerging Hardware, 209–20. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-13021-7_16.

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Conference papers on the topic "Emerging Non-Volatile memories"

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Xue, Chun Jason, Youtao Zhang, Yiran Chen, Guangyu Sun, J. Jianhua Yang, and Hai Li. "Emerging non-volatile memories." In the seventh IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2039370.2039420.

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Sandhu, Gurtej S. "Emerging memories technology landscape." In 2013 13th Non-Volatile Memory Technology Symposium (NVMTS). IEEE, 2013. http://dx.doi.org/10.1109/nvmts.2013.6851050.

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"SESSION 26 - Emerging Non-Volatile Memories." In 2004 Symposium on VLSI Circuits. Digest of Technical Papers. IEEE, 2004. http://dx.doi.org/10.1109/vlsic.2004.1346643.

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Imtiaz Khan, Mohammad Nasim, Karthikeyan Nagarajan, and Swaroop Ghosh. "Hardware Trojans in Emerging Non-Volatile Memories." In 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2019. http://dx.doi.org/10.23919/date.2019.8714843.

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Gao, Bin. "Emerging Non-Volatile Memories for Computation-in-Memory." In 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE, 2020. http://dx.doi.org/10.1109/asp-dac47756.2020.9045394.

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Hamdioui, Said, Peyman Pouyan, Huawei Li, Ying Wang, Arijit Raychowdhur, and Insik Yoon. "Test and Reliability of Emerging Non-volatile Memories." In 2017 IEEE 26th Asian Test Symposium (ATS). IEEE, 2017. http://dx.doi.org/10.1109/ats.2017.42.

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Tyagi, Vivek, Vikas Rana, Laura Capecchi, Marcella Carissimi, and Marco Pasotti. "Power Efficient Sense Amplifier For Emerging Non Volatile Memories." In 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID). IEEE, 2020. http://dx.doi.org/10.1109/vlsid49098.2020.00019.

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Shamsi, Kaveh, and Yier Jin. "Security of emerging non-volatile memories: Attacks and defenses." In 2016 IEEE 34th VLSI Test Symposium (VTS). IEEE, 2016. http://dx.doi.org/10.1109/vts.2016.7477293.

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Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Test challenges and solutions for emerging non-volatile memories." In 2018 IEEE 36th VLSI Test Symposium (VTS). IEEE, 2018. http://dx.doi.org/10.1109/vts.2018.8368632.

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Khan, Mohammad Nasim Imtiaz, and Swaroop Ghosh. "Assuring Security and Reliability of Emerging Non-Volatile Memories." In 2020 IEEE International Test Conference (ITC). IEEE, 2020. http://dx.doi.org/10.1109/itc44778.2020.9325231.

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