Journal articles: 'Embedded Processors'

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Pflanz, M., and H. T. Vierhaus. "Generating reliable embedded processors." IEEE Micro 18, no. 5 (1998): 33–41. http://dx.doi.org/10.1109/40.735942.

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Wei, Xiaotong, Ying Yang, and Jie Chen. "A Low-Latency Divider Design for Embedded Processors." Sensors 22, no. 7 (March 23, 2022): 2471. http://dx.doi.org/10.3390/s22072471.

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Division is generally regarded as a low-frequency, high-latency operation in integer operations. Division is also the operation that stalls the processor pipeline most frequently. In order to improve the overall performance of embedded processors, a low-delay divider for embedded processors was designed. Based on the non-restoring algorithm, the divider uses a compound adder to execute addition and subtraction simultaneously and reduces the iteration path delay. By shifting the operands to align the most effective bits, the divider dynamically adjusts the number of iteration cycles to reduce the average number of cycles in the division process. The divider design was simulated by Modelsim and implemented on a FPGA board for verification. Synthesized in a Semiconductor Manufacturing International Corporation (SMIC) 65 nm Low Leakage process, the achieved frequency of the design was up to 500 MHz and the area cost was 5670.36 μm2. Compared with other dividers, the proposed divider design can reduce the delay of single iteration by up to 45.3%, save the average number of iteration cycles by 20–50%, and save the area by 23.3–86.1%. Compared with other dividers implemented on FPGA, it saves LUTs by 36.47–59.6% and FFs by 67–84.28%, runs 2–6.36 times faster. Therefore, the proposed design is suitable for embedded processors that require low power consumption, low resource consumption, and high performance.

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KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm profiles memory access pattern of the application, produces the access conflict graph, relocates decomposed memory sub-pages based on the access conflict graph, and finally generates a synthesizable code of the address shuffler. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler removes 80% of access conflicts on average for benchmarks where the hardware overhead of the shuffler is 1592 LUTs which is 14% of LUT size of the processor core.

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Doraipandian, Manivannan, and Periasamy Neelamegam. "Wireless Sensor Network Using ARM Processors." International Journal of Embedded and Real-Time Communication Systems 4, no. 4 (October 2013): 48–59. http://dx.doi.org/10.4018/ijertcs.2013100103.

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The hardware design of Wireless Sensor Networks (WSN) is the crux of its effective deployment. Nowadays these networks are used in microscopic, secure and high-end embedded products. WSN's potentiality in terms of efficient data sensing and distributed data processing has led to its usage in applications for measurement and tracking. WSN comprises of small number of embedded devices known as sensor nodes, gateways and base stations. Sensor nodes consist of sensors, processors and transceivers. The property of embedded sensor devices, also called motes, is to determine the strength of WSN. Thus processor selection for the motes plays a critical role in determining a WSN's competency. In this article, the absolute and obvious hardware characteristics of available and proposed sensor nodes are discussed. The objective of this work was to increase the efficiency and provision of sensor nodes by evaluating their processing and transceiver units. During this work, a sensor node was developed with ARM processor and XBee series 2 Unit. LPC 2148, LPC 2378 ARM processors were posed as processing unit and XBee series 2 acted as communication unit. Results of this experimental setup were recorded. Also a comparative study of the various available sensor nodes and proposed sensor nodes was done extensively.

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Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

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In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy consumption in a signal processing application for nondispersive infrared (NDIR) CO2 sensors.The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation to enhance the accuracy of the measurements. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.

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Muralidharan, K., and S. Uma Maheswari. "Design of Low Power Cam Memory Cell for the Next Generation Network Processors." IRO Journal on Sustainable Wireless Systems 3, no. 4 (December 3, 2021): 208–18. http://dx.doi.org/10.36548/jsws.2021.4.001.

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In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that are used in the next generation network processors. The main data path resources of the processor use CAM+RAM structure which is the major power consuming unit in the overall out-of-order processor design. The proposed new design of CAM+RAM with power-gating technique reduces the overall average power consumption compared to the conventional design without any significant impact on their performance.

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Levy, Markus, and Thomas M. Conte. "Embedded Multicore Processors and Systems." IEEE Micro 29, no. 3 (May 2009): 7–9. http://dx.doi.org/10.1109/mm.2009.41.

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Dutt, N., and Kiyoung Choi. "Configurable processors for embedded computing." Computer 36, no. 1 (January 2003): 120–23. http://dx.doi.org/10.1109/mc.2003.1160063.

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Shin, Youngsoo, Kiyoung Choi, and Takayasu Sakurai. "Power-conscious Scheduling for Real-time Embedded Systems Design." VLSI Design 12, no. 2 (January 1, 2001): 139–50. http://dx.doi.org/10.1155/2001/23925.

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Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.

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Wang, Tun, and Yu Tian. "Design of Embedded Ai Engine Based on the Microkernel Operating System." Wireless Communications and Mobile Computing 2022 (April 21, 2022): 1–9. http://dx.doi.org/10.1155/2022/9304019.

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At present, the application of the embedded microkernel operating system in military and civil fields has begun to take shape, but it has not yet formed a unified method and standard. Due to its high performance, low frequency, and high reliability, dual-core embedded processors are getting the attention of many chip manufacturers. Compatibility has been favored by many telecom equipment manufacturers and embedded high-end application integrators, but the dual-core embedded processor needs a new real-time operating system to support it, so that it can give full play to the high performance of the dual-core. It paves the way for the application of its processor in the embedded field, but the design of embedded AI engine is not transparent to it; so, it needs the support of operating system. The user code is used to be in the operating system processor environment; so, it can be used on dual core processor first. In the real-time operating system that supports dual-core processors, the part that needs to be modified is mainly concentrated in the kernel part; so, the core design is the key point to support dual-core processors. This article is to seize this key point to carry out in-depth research. The difference and influence of hardware architecture between dual-core processor and single-core processor are the primary content of the study. Through the research of the dual-core processor architecture, the general abstraction of the dual-core processor architecture is obtained, which is the starting point of the follow-up research. This paper mainly studies the design of embedded AI engine based on the microkernel operating system, extracts the security requirements of the operating system, designs and implements the operating system from the perspective of formal verification, and considers the verification problem under the background of RTOS development, so as to avoid using too many complex data structures and algorithms in the system design and reduce the difficulty of experimental verification. In this paper, we use the spatiotemporal data model, data sharing security in the cloud environment, symmetric encryption scheme, and Paillier homomorphic encryption method to study the design of embedded AI engine based on the microkernel operating system. According to the idea of microkernel architecture, the kernel is divided into four main modules: task processing, semaphore, message queue, interrupt, and exception processing, and the lock mechanism to prevent reentrancy in software is analyzed separately. Three core function modules, initialization, process grinding, and interrupt processing, are extracted from the microkernel operating system to form the formal verification area of the operating system. At the same time, the system syntax and semantics of related rights are separated, and the main rationalization rules are described. The results show that the core of the microkernel operating system in five states adopts the microkernel architecture in the dual core environment. The microkernel architecture is a compact system kernel with good adjustability. Based on the analysis of the microkernel operating system, the internal structure of each module in the kernel is summarized, and the modules are modified according to the machine characteristics of the dual core processor; it corresponds to adding modules to meet the characteristics of dual core architecture. Kernel design is a systematic theoretical research process. This paper only uncovers the tip of the iceberg of real-time operating system kernel design on dual-core embedded processors. It is necessary to understand the kernel more deeply and master the kernel in the future work and study.

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Xia, Jun. "An Energy-Efficient Approach to Hot-Plugging of Embedded Multiprocessors." Advanced Materials Research 756-759 (September 2013): 4229–34. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4229.

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With the increasing of the number of processors in one chip, the energy consumption became increasingly important in the low power design of embedded system. In time-sharing OS, different application scenarios lead to different workload. A novel policy for energy saving is that some processors can be hot-plugged on while the workload of the system becomes high and some processors can be hot-plugged off while the workload becomes low. This paper proposed an energy-efficient workload prediction approach called PID prediction algorithm (PPA) which aims dynamic processors number changes for energy saving and reduces the frequency of processors switch on/off for saving extra energy costs. The experiments show that energy consumption is reduced by 19% and the frequency of processors switch on/off is reduced by 30%.

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Talawar, Arun K., Sunita S. Malaj, and Raju Hiremath. "An Analysis of : Embedded Systems in Embedded Processors Knack." Gyan Management Journal 17, no. 1 (March 6, 2023): 78–84. http://dx.doi.org/10.48165/gmj.2022.17.1.9.

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The mechanisms via way of means of which software program interacts with the bodily international are converting rapidly. Today’s fashion is “smart” sensors and drives with microprocessors, community interfaces and software program that permit far flung get entry to to sensor records and far flung unit activation. There is likewise the Internet of Things (IoT), Industry 4.0, Industrial Internet, Machine to Machine, Internet of Everything, Smart Planet, TSensors (trillions of sensors) or Fog (similar, however towards the cloud). Earth is an expression of era that deeply connects our bodily and informational worlds. In the IoT international, the interfaces among those worlds are stimulated and derived from statistics era, specially net era. Our recognition is on interacting with the bodily surroundings wherein software program and hardware operate. This calls for a unique modeling of the time dynamics of the software program and networks and a clean specification of the parallel nature of the application. The truth that implementation era has now no longer but reached this factor need to now no longer educate a incorrect technonical approach. All need to learn design and modeling and enrich them with a critical reflection on what it is. Today’s embedded systems technology should be presented in a neutral way, not as a collection of facts and tricks, as in many of the recent trends in, but as a cornerstone to a better design experience.

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Vojtko, Martin, and Tibor Krajčovič. "Semi-automated process of adaptation of platform dependent parts of embedded operating systems." Journal of Electrical Engineering 68, no. 2 (March 28, 2017): 87–98. http://dx.doi.org/10.1515/jee-2017-0013.

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Abstract Each year manufacturers develop new processors. As a reaction to this continuous development, the developers of software have to adapt their software to those new processors. As a minimal requirement, the code of an operating system has to be changed to enable the execution of other user applications. This change is a complicated process during which incompatible parts of an operating system have to be redesigned and missing parts have to be implemented. Complications arise when there is a need to adapt an operating system to completely different processor architecture. In this paper we present a novel adaptation process that has preconditions to reduce the impact of these complications. This process uses a file for the formal description of a processor, which is also described in this paper. The formal description could act as a standard for processor manufacturers and could allow the generation of a platform dependent code of an operating system. This paper presents concepts, definitions and ideas of the adaptation process and shows possible solutions for an automatic generation of code parts of an operating system.

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Hyodo, Kazuhito, Hirokazu Noborisaka, and Takashi Yada. "Development of Mechatronics Teaching Materials for Embedded System Engineer Education." Journal of Robotics and Mechatronics 23, no. 5 (October 20, 2011): 611–17. http://dx.doi.org/10.20965/jrm.2011.p0611.

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We have developed a learning environment for embedded system design. The learning environment consists of a multi-purpose controller and terminal devices. The controller consists of main processor (arm) and a multi-core microprocessor (Propeller). The main processor provides the software development environment. The Propeller chip has eight 32-bit processors and can perform simultaneous tasks for multiple users. In addition, the Propeller chip provides a reconfigurable peripheral module. This feature is very useful for the development of educational materials. Teachers can develop various educational materials with this control module.

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Shreya Mane. "Theoretical Study on Embedded Processor and Networking." international journal of engineering technology and management sciences 7, no. 3 (2023): 861–67. http://dx.doi.org/10.46647/ijetms.2023.v07i03.131.

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Embedded processors are specialized microprocessors designed to perform specific tasks within a larger system or device. They are commonly used in various applications such as consumer electronics, automotive systems, industrial automation, and Internet of Things (IoT) devices. This abstract focuses on the role of embedded processors in networking applications. Networking refers to the interconnection of devices and systems to enable communication and data exchange. Embedded processors play a crucial role in networking by providing the necessary computational power and functionality to handle networking protocols, data processing, and network management tasks. They are often integrated into network devices such as routers, switches, gateways, and network interface cards. The utilisation of networked embedded systems in contemporary network situations is undeniably significant, and they are receiving an increasing amount of attention. For network connectivity, data processing, and service delivery, the research community and industry are putting forth cutting-edge embedded solutions, frequently based on network processors. Despite this, it appears to be quite difficult to get quantitative performance comparisons of such systems.

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Coombs, Joseph, Rahul Prabhu, and Greg Peake. "Overcoming the Challenges of Porting OpenCV to TI's Embedded ARM + DSP Platforms." International Journal of Electrical Engineering & Education 49, no. 3 (July 2012): 260–74. http://dx.doi.org/10.7227/ijeee.49.3.6.

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The growing performance and decreasing price of embedded processors are opening many doors, for both developers in the industry and in academia. However, the complexities of these systems can create serious developmental bottlenecks. Sophisticated software packages such as OpenCV can assist in both the functional development and educational aspects of these otherwise complex applications; such tools lend themselves very well to use by the academic community, in particular in providing examples of algorithm implementation. However the task of migrating this software to embedded platforms poses its own challenges. This paper will review how to mitigate some of these issues, including C++ implementation, memory constraints, floating-point support, and opportunities to maximise performance using vendor-optimised libraries and integrated accelerators or co-processors. Finally, we will introduce a new effort by Texas Instruments to optimise vision systems by running OpenCV on the C6000™ digital signal processor architecture. Benchmarks will show the advantage of using the DSP by comparing the performance of a DSP+ARM® system-on-chip (SoC) processor against an ARM-only device.

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OSKIN, MARK, DIANA KEEN, JUSTIN HENSLEY, LUCIAN-VLAD LITA, and FREDERIC T. CHONG. "OPERATING SYSTEMS TECHNIQUES FOR PARALLEL COMPUTATION IN INTELLIGENT MEMORY." Parallel Processing Letters 12, no. 03n04 (September 2002): 311–26. http://dx.doi.org/10.1142/s0129626402001014.

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Advances in DRAM density have led to several proposals to perform computation in memory [1] [2] [3]. Active Pages is a page-based model of intelligent memory that can exploit large amounts of parallel computation in data-intensive applications. With a simple VLIW processor embedded near each page on DRAM, Active Page memory systems achieve up to 1000X speedups over conventional memory systems [4]. Active Pages are specifically designed to support virtualized hardware resources. In this study, we examine operating system techniques that allow Active Page memories to share, or multiplex, embedded VLIW processors across multiple physical Active Pages. We explore the trade-off between individual page-processor performance and page-level multiplexing. We find that hardware costs of computational logic can be reduced from 31% of DRAM chip area to 12%, through multiplexing, without significant loss in performance. Furthermore, manufacturing defects that disable up to 50% of the page processors can be tolerated through efficient resource allocation and associative multiplexing.

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Bui, Phuc, Minh Le, Binh Hoang, Nguyen Ngoc, and Huong Pham. "Data Partitioning and Asynchronous Processing to Improve the Embedded Software Performance on Multicore Processors." Informatics and Automation 21, no. 2 (February 17, 2022): 243–74. http://dx.doi.org/10.15622/ia.21.2.2.

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Nowadays, ensuring information security is extremely inevitable and urgent. We are also witnessing the strong development of embedded systems, IoT. As a result, research to ensure information security for embedded software is being focused. However, studies on optimizing embedded software on multi-core processors to ensure information security and increase the performance of embedded software have not received much attention. The paper proposes and develops the embedded software performance improvement method on multi-core processors based on data partitioning and asynchronous processing. Data are used globally to be retrieved by any threads. The data are divided into different partitions, and the program is also installed according to the multi-threaded model. Each thread handles a partition of the divided data. The size of each data portion is proportional to the processing speed and the cache size of the core in the multi-core processor. Threads run in parallel and do not need synchronization, but it is necessary to share a general global variable to check the executing status of the system. Our research on embedded software is based on data security, so we have tested and assessed the method with several block ciphers like AES, DES, etc., on Raspberry PI3. The average performance improvement rate achieved was 59.09%.

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Yoon, Young Hyun, Dong Hyun Hwang, Jun Hyeok Yang, and Seung Eun Lee. "Intellino: Processor for Embedded Artificial Intelligence." Electronics 9, no. 7 (July 18, 2020): 1169. http://dx.doi.org/10.3390/electronics9071169.

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The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose the intellino, a processor for embedded artificial intelligence. Intellino ensures low power operation based on optimized AI algorithms and reduces the workload of the system core through the hardware implementation of a neural network. In addition, intellino’s dedicated protocol helps the embedded system to enhance the performance. We measure intellino performance, achieving over 95% accuracy, and verify our proposal with an field programmable gate array (FPGA) prototyping.

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Wang, Jiandi. "Research Status and Prospect of Embedded System." Highlights in Science, Engineering and Technology 46 (April 25, 2023): 49–55. http://dx.doi.org/10.54097/hset.v46i.7663.

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Embedded system is one of the key research topics nowadays. The engineers found that embedded system can be applied in many electronic engineering fields, such as daily household appliances, industrial control, etc. A complete embedded system includes all of the necessary components, such as an embedded processor, hardware structure, software system, and operating system. The central characteristics of embedded systems are the heterogeneity of their implementation technologies (digital hardware, software), the tightness of their nonfunctional requirements, and their complexity. Despite the fact that embedded systems have been widely used in modern society, there is still a lack of unified understanding of the classification of embedded processors. Through the understanding of the overall structure of embedded systems and the research of the application status of embedded systems, researchers or engineers can make wiser choices when designing embedded systems.

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Moyer, B. "Low-power design for embedded processors." Proceedings of the IEEE 89, no. 11 (2001): 1576–87. http://dx.doi.org/10.1109/5.964439.

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Leupers, R. "Compiler design issues for embedded processors." IEEE Design & Test of Computers 19, no. 4 (July 2002): 51–58. http://dx.doi.org/10.1109/mdt.2002.1018133.

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Zhuang, Xiaotong, and Santosh Pande. "Power-efficient prefetching for embedded processors." ACM Transactions on Embedded Computing Systems 6, no. 1 (February 2007): 3. http://dx.doi.org/10.1145/1210268.1210271.

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Wang, Chenxu, Jiamin Zheng, and Mingyan Yu. "Cache Performance Research for Embedded Processors." Physics Procedia 25 (2012): 1322–28. http://dx.doi.org/10.1016/j.phpro.2012.03.239.

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Chocholac, Jaromir. "Embedded Processors for Networking and Communications." IFAC Proceedings Volumes 33, no. 1 (February 2000): 77–80. http://dx.doi.org/10.1016/s1474-6670(17)35590-8.

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Kozyrakis, C. E., and D. A. Patterson. "Scalable vector processors for embedded systems." IEEE Micro 23, no. 6 (November 2003): 36–45. http://dx.doi.org/10.1109/mm.2003.1261385.

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Sarma, M. Sandeep, K. V. Ravi Kumar, B. Rajesh Kumar, and P. H. S. T. Murthy. "Digital Signal Processing On Embedded Processors." International Journal of Engineering Trends and Technology 22, no. 5 (April 25, 2015): 222–24. http://dx.doi.org/10.14445/22315381/ijett-v22p247.

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Bonny, Talal, and JÖrg Henkel. "Efficient Code Compression for Embedded Processors." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16, no. 12 (December 2008): 1696–707. http://dx.doi.org/10.1109/tvlsi.2008.2001950.

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Jayaseelan, Ramkumar, and Tulika Mitra. "Temperature Aware Scheduling for Embedded Processors." Journal of Low Power Electronics 5, no. 3 (October 1, 2009): 363–72. http://dx.doi.org/10.1166/jolpe.2009.1036.

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Kondo, Hiroyuki, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, and Toru Shimizu. "Implementation of Face Recognition Processing Using an Embedded Processor." Journal of Robotics and Mechatronics 17, no. 4 (August 20, 2005): 428–36. http://dx.doi.org/10.20965/jrm.2005.p0428.

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Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.

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Ma, Wenheng, Qiao Cheng, Yudi Gao, Lan Xu, and Ningmei Yu. "An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture." Micromachines 12, no. 3 (March 10, 2021): 292. http://dx.doi.org/10.3390/mi12030292.

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Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 μW, 59.7 μW and 71.1 μW. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

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Cantero, David, Iker Esnaola-Gonzalez, Jose Miguel-Alonso, and Ekaitz Jauregi. "Benchmarking Object Detection Deep Learning Models in Embedded Devices." Sensors 22, no. 11 (May 31, 2022): 4205. http://dx.doi.org/10.3390/s22114205.

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Object detection is an essential capability for performing complex tasks in robotic applications. Today, deep learning (DL) approaches are the basis of state-of-the-art solutions in computer vision, where they provide very high accuracy albeit with high computational costs. Due to the physical limitations of robotic platforms, embedded devices are not as powerful as desktop computers, and adjustments have to be made to deep learning models before transferring them to robotic applications. This work benchmarks deep learning object detection models in embedded devices. Furthermore, some hardware selection guidelines are included, together with a description of the most relevant features of the two boards selected for this benchmark. Embedded electronic devices integrate a powerful AI co-processor to accelerate DL applications. To take advantage of these co-processors, models must be converted to a specific embedded runtime format. Five quantization levels applied to a collection of DL models are considered; two of them allow the execution of models in the embedded general-purpose CPU and are used as the baseline to assess the improvements obtained when running the same models with the three remaining quantization levels in the AI co-processors. The benchmark procedure is explained in detail, and a comprehensive analysis of the collected data is presented. Finally, the feasibility and challenges of the implementation of embedded object detection applications are discussed.

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Götze, Johannes. "Comparison of acceleration methods of matrix calculations in embedded systems." Embedded Selforganising Systems 6, no. 1 (December 27, 2019): 9–17. http://dx.doi.org/10.14464/ess61429.

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In today's algorithms for sound localization techniques, matrix calculations are ubiquitous. Therefore, this work deals with the analysis of matrix calculations and their possible realization on embedded systems. For this purpose, common acceleration technologies such as processors, GPU processing and acceleration with the help of FPGAs are compared. The results show that a graphics chip is capable to accelerate such a matrix vector multiplication compared to an implementation on a processor. Therefore a runtime of an implementation on an FPGA cannot be achieved by a GPU.

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Gauthier, Lovic, and Tohru Ishihara. "Processor Energy Characterization for Compiler-Assisted Software Energy Reduction." Journal of Electrical and Computer Engineering 2012 (2012): 1–16. http://dx.doi.org/10.1155/2012/786943.

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Energy consumption is a fundamental barrier in taking full advantage of today and future semiconductor manufacturing technologies. The paper presents our recent research activities and results on characterizing and reducing the energy consumption in embedded systems. Firstly, a technique for characterizing the energy consumption of embedded processors during an application execution is presented. The technique trains a per-processor linear approximation model for fitting it to the energy consumption of the processor obtained by postlayout simulation. Secondly, based on the energy model mentioned above, the paper shows techniques for reducing the energy consumption by optimally mapping program code, stack frames, and data items to the scratch-pad memory (SPM) of the processor memory space.

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Manor, Erez, Avrech Ben-David, and Shlomo Greenberg. "CORDIC Hardware Acceleration Using DMA-Based ISA Extension." Journal of Low Power Electronics and Applications 12, no. 1 (January 15, 2022): 4. http://dx.doi.org/10.3390/jlpea12010004.

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The use of RISC-based embedded processors aimed at low cost and low power is becoming an increasingly popular ecosystem for both hardware and software development. High-performance yet low-power embedded processors may be attained via the use of hardware acceleration and Instruction Set Architecture (ISA) extension. Recent publications of AI have demonstrated the use of Coordinate Rotation Digital Computer (CORDIC) as a dedicated low-power solution for solving nonlinear equations applied to Neural Networks (NN). This paper proposes ISA extension to support floating-point CORDIC, providing efficient hardware acceleration for mathematical functions. A new DMA-based ISA extension approach integrated with a pipeline CORDIC accelerator is proposed. The CORDIC ISA extension is directly interfaced with a standard processor data path, allowing efficient implementation of new trigonometric ALU-based custom instructions. The proposed DMA-based CORDIC accelerator can also be used to perform repeated array calculations, offering a significant speedup over software implementations. The proposed accelerator is evaluated on Intel Cyclone-IV FPGA as an extension to Nios processor. Experimental results show a significant speedup of over three orders of magnitude compared with software implementation, while applied to trigonometric arrays, and outperforms the existing commercial CORDIC hardware accelerator.

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Cooper, Keith D., and Nathaniel McIntosh. "Enhanced code compression for embedded RISC processors." ACM SIGPLAN Notices 34, no. 5 (May 1999): 139–49. http://dx.doi.org/10.1145/301631.301655.

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Ubal, R., J. Sahuquillo, S. Petit, H. Hassan, and P. López. "Power Reduction In Advanced Embedded IPC Processors." Intelligent Automation & Soft Computing 15, no. 3 (January 2009): 495–507. http://dx.doi.org/10.1080/10798587.2009.10643045.

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Kranitis, N., A. Paschalis, D. Gizopoulos, and G. Xenoulis. "Software-Based Self-Testing of Embedded Processors." IEEE Transactions on Computers 54, no. 4 (April 2005): 461–75. http://dx.doi.org/10.1109/tc.2005.68.

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Hyeran Jeon, Woo Hyong Lee, and Sung Woo Chung. "Load Unbalancing Strategy for Multicore Embedded Processors." IEEE Transactions on Computers 59, no. 10 (October 2010): 1434–40. http://dx.doi.org/10.1109/tc.2009.181.

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Levison, Nadav, and Shlomo Weiss. "Branch target buffer design for embedded processors." Microprocessors and Microsystems 34, no. 6 (October 2010): 215–27. http://dx.doi.org/10.1016/j.micpro.2010.04.005.

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Zhuang, Xiaotong, Tao Zhang, and Santosh Pande. "Hardware-managed register allocation for embedded processors." ACM SIGPLAN Notices 39, no. 7 (July 11, 2004): 192–201. http://dx.doi.org/10.1145/998300.997191.

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Ayala, José L., Cándido Méndez, and Marisa López-Vallejo. "Thermal analysis and modeling of embedded processors." Computers & Electrical Engineering 36, no. 1 (January 2010): 142–54. http://dx.doi.org/10.1016/j.compeleceng.2009.07.001.

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Kim, Jongmyon, Linda M. Wills, and D. Scott Wills. "Color-Aware Instructions for Embedded Superscalar Processors." Journal of Signal Processing Systems 64, no. 3 (May 22, 2010): 335–50. http://dx.doi.org/10.1007/s11265-010-0497-2.

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Nojiri, Tohru, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, and Hideo Maejima. "Domain Partitioning Technology for Embedded Multicore Processors." IEEE Micro 29, no. 6 (November 2009): 7–17. http://dx.doi.org/10.1109/mm.2009.96.

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Miller, Jason E., and Anant Agarwal. "Software-based instruction caching for embedded processors." ACM SIGOPS Operating Systems Review 40, no. 5 (October 20, 2006): 293–302. http://dx.doi.org/10.1145/1168917.1168894.

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Miller, Jason E., and Anant Agarwal. "Software-based instruction caching for embedded processors." ACM SIGPLAN Notices 41, no. 11 (November 2006): 293–302. http://dx.doi.org/10.1145/1168918.1168894.

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Miller, Jason E., and Anant Agarwal. "Software-based instruction caching for embedded processors." ACM SIGARCH Computer Architecture News 34, no. 5 (October 20, 2006): 293–302. http://dx.doi.org/10.1145/1168919.1168894.

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Park, Sungkyung, and Chester Sungchung Park. "Design of Low-Gate-Count Low-Power Microprocessors with High Code Density for Deeply Embedded Applications." Journal of Circuits, Systems and Computers 26, no. 09 (April 24, 2017): 1750132. http://dx.doi.org/10.1142/s0218126617501328.

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Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5[Formula: see text]m W, and 0.06[Formula: see text]m W, respectively, at 10[Formula: see text]MHz in a 0.18[Formula: see text][Formula: see text]m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50[Formula: see text][Formula: see text]W/MHz with 10,800 gates in a 0.18[Formula: see text][Formula: see text]m CMOS process.

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Hendarmawan, Morihiro Kuga, and Masahiro Iida. "Streaming Accelerator Design for Regular Expression on CPU+FPGA Embedded System." ECTI Transactions on Computer and Information Technology (ECTI-CIT) 16, no. 4 (October 11, 2022): 448–59. http://dx.doi.org/10.37936/ecti-cit.2022164.249268.

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A pattern matching application is one of the necessary tasks in streaming data processing. A hardware accelerator employing FPGA can be faster than a general-purpose processor in performing data pattern matching using regular expression methods. However, it is difficult and time-consuming to design the hardware on the FPGA for each regular expression pattern. We are researching a method for automatically designing hardware accelerators for higher efficiency and performance to improve user productivity. In this research, we propose rules and methods for translating regular expression patterns into supported hardware code as our contribution to providing an efficient design method for regular expression hardware accelerators and allowing the efficient utilization of FPGAs. The performance evaluation is compared with the regular expression algorithm on ARM processors, CPU servers, and FPGA data streaming applications. Our result shows that our FPGA accelerator enables speeding up data streaming applications on CPU processors. Our solution is 733 times faster than optimized C/C++ code. It is 70 times faster than using the Python library. It is twice as fast as PYNQ-Z2 and 1.5 faster than RE2C. Furthermore, our proposed accelerator Ultra-96 improves the performance 2 times with an 8[MB/J] high energy efficiency from the previous PYNQ-Z2 approach.

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Xing, Wen Qi, Qian Zhong Zhang, and Zi Wei Feng. "A Kind of Embedded Firewall Mechanism for ARM Processors." Applied Mechanics and Materials 556-562 (May 2014): 1757–60. http://dx.doi.org/10.4028/www.scientific.net/amm.556-562.1757.

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The traditional firewall is a protect mechanism usually between the internal and external network, through the input and output of data packets in real-time network monitoring, it will make protective response immediately if it find security threats. With short data processing time and high efficiency, it can satisfy most procedures of application, but it has high cost and is difficult to achieve. In this paper, in view of these problems, embedded firewall security protection mechanisms set based AMR processor innovation, given the overall framework of embedded firewall hardware and the design for software architecture ,I selected good performance S3C2410X embedded chip, the embedded firewall network card drivers, key technologies of application research in detail, based on the embedded firewall performance of AMR processor through the contrast test ,the communication rate can reach 15.5Mpbs, 2.15times higher than that of general processor communication performance.

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Journal articles on the topic 'Embedded Processors'

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