Relevant bibliographies by topics / Embedded Processors

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Embedded Processors'

Author: Grafiati
Published: 4 June 2021
Last updated: 6 September 2023

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Journal articles on the topic "Embedded Processors"

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Pflanz, M., and H. T. Vierhaus. "Generating reliable embedded processors." IEEE Micro 18, no. 5 (1998): 33–41. http://dx.doi.org/10.1109/40.735942.

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Wei, Xiaotong, Ying Yang, and Jie Chen. "A Low-Latency Divider Design for Embedded Processors." Sensors 22, no. 7 (March 23, 2022): 2471. http://dx.doi.org/10.3390/s22072471.

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Division is generally regarded as a low-frequency, high-latency operation in integer operations. Division is also the operation that stalls the processor pipeline most frequently. In order to improve the overall performance of embedded processors, a low-delay divider for embedded processors was designed. Based on the non-restoring algorithm, the divider uses a compound adder to execute addition and subtraction simultaneously and reduces the iteration path delay. By shifting the operands to align the most effective bits, the divider dynamically adjusts the number of iteration cycles to reduce the average number of cycles in the division process. The divider design was simulated by Modelsim and implemented on a FPGA board for verification. Synthesized in a Semiconductor Manufacturing International Corporation (SMIC) 65 nm Low Leakage process, the achieved frequency of the design was up to 500 MHz and the area cost was 5670.36 μm2. Compared with other dividers, the proposed divider design can reduce the delay of single iteration by up to 45.3%, save the average number of iteration cycles by 20–50%, and save the area by 23.3–86.1%. Compared with other dividers implemented on FPGA, it saves LUTs by 36.47–59.6% and FFs by 67–84.28%, runs 2–6.36 times faster. Therefore, the proposed design is suitable for embedded processors that require low power consumption, low resource consumption, and high performance.
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KWON, YOUNG-SU, and NAK-WOONG EUM. "APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR." Journal of Circuits, Systems and Computers 19, no. 07 (November 2010): 1435–47. http://dx.doi.org/10.1142/s0218126610006748.

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Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm profiles memory access pattern of the application, produces the access conflict graph, relocates decomposed memory sub-pages based on the access conflict graph, and finally generates a synthesizable code of the address shuffler. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler removes 80% of access conflicts on average for benchmarks where the hardware overhead of the shuffler is 1592 LUTs which is 14% of LUT size of the processor core.
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Doraipandian, Manivannan, and Periasamy Neelamegam. "Wireless Sensor Network Using ARM Processors." International Journal of Embedded and Real-Time Communication Systems 4, no. 4 (October 2013): 48–59. http://dx.doi.org/10.4018/ijertcs.2013100103.

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The hardware design of Wireless Sensor Networks (WSN) is the crux of its effective deployment. Nowadays these networks are used in microscopic, secure and high-end embedded products. WSN's potentiality in terms of efficient data sensing and distributed data processing has led to its usage in applications for measurement and tracking. WSN comprises of small number of embedded devices known as sensor nodes, gateways and base stations. Sensor nodes consist of sensors, processors and transceivers. The property of embedded sensor devices, also called motes, is to determine the strength of WSN. Thus processor selection for the motes plays a critical role in determining a WSN's competency. In this article, the absolute and obvious hardware characteristics of available and proposed sensor nodes are discussed. The objective of this work was to increase the efficiency and provision of sensor nodes by evaluating their processing and transceiver units. During this work, a sensor node was developed with ARM processor and XBee series 2 Unit. LPC 2148, LPC 2378 ARM processors were posed as processing unit and XBee series 2 acted as communication unit. Results of this experimental setup were recorded. Also a comparative study of the various available sensor nodes and proposed sensor nodes was done extensively.
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Núñez-Prieto, Ricardo, David Castells-Rufas, and Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing." Micromachines 14, no. 7 (July 4, 2023): 1371. http://dx.doi.org/10.3390/mi14071371.

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In the field of embedded systems, energy efficiency is a critical requirement, particularly for battery-powered devices. RISC-V processors have gained popularity due to their flexibility and open-source nature, making them an attractive choice for embedded applications. However, not all RISC-V processors are equally energy-efficient, and evaluating their performance in specific use cases is essential. This paper presents RisCO2, an RISC-V implementation optimized for energy efficiency. It evaluates its performance compared to other RISC-V processors in terms of resource utilization and energy consumption in a signal processing application for nondispersive infrared (NDIR) CO2 sensors.The processors were implemented in the PULPino SoC and synthesized using Vivado IDE. RisCO2 is based on the RV32E_Zfinx instruction set and was designed from scratch by the authors specifically for low-power signal demodulation in CO2 NDIR sensors. The other processors are Ri5cy, Micro-riscy, and Zero-riscy, developed by the PULP team, and CV32E40P (derived from Ri5cy) from the OpenHW Group, all of them widely used in the RISC-V community. Our experiments showed that RisCO2 had the lowest energy consumption among the five processors, with a 53.5% reduction in energy consumption compared to CV32E40P and a 94.8% reduction compared to Micro-riscy. Additionally, RisCO2 had the lowest FPGA resource utilization compared to the best-performing processors, CV32E40P and Ri5cy, with a 46.1% and a 59% reduction in LUTs, respectively. Our findings suggest that RisCO2 is a highly energy-efficient RISC-V processor for NDIR CO2 sensors that require signal demodulation to enhance the accuracy of the measurements. The results also highlight the importance of evaluating processors in specific use cases to identify the most energy-efficient option. This paper provides valuable insights for designers of energy-efficient embedded systems using RISC-V processors.
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Muralidharan, K., and S. Uma Maheswari. "Design of Low Power Cam Memory Cell for the Next Generation Network Processors." IRO Journal on Sustainable Wireless Systems 3, no. 4 (December 3, 2021): 208–18. http://dx.doi.org/10.36548/jsws.2021.4.001.

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In the modern world, high performance embedded applications in the field of multimedia, networking, and imaging are increasing day by day. These applications require high performance and more complex out-of-order superscalar processor. These complex dynamic instructions scheduling superscalar processors need higher levels of on-chip integration designs which are often associated with power dissipation. These out-of-order superscalar processors achieve higher performance compared to other processors by simultaneous fetching, decoding and execution for multiple instructions in out-of-order that are used in the next generation network processors. The main data path resources of the processor use CAM+RAM structure which is the major power consuming unit in the overall out-of-order processor design. The proposed new design of CAM+RAM with power-gating technique reduces the overall average power consumption compared to the conventional design without any significant impact on their performance.
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Levy, Markus, and Thomas M. Conte. "Embedded Multicore Processors and Systems." IEEE Micro 29, no. 3 (May 2009): 7–9. http://dx.doi.org/10.1109/mm.2009.41.

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Dutt, N., and Kiyoung Choi. "Configurable processors for embedded computing." Computer 36, no. 1 (January 2003): 120–23. http://dx.doi.org/10.1109/mc.2003.1160063.

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Shin, Youngsoo, Kiyoung Choi, and Takayasu Sakurai. "Power-conscious Scheduling for Real-time Embedded Systems Design." VLSI Design 12, no. 2 (January 1, 2001): 139–50. http://dx.doi.org/10.1155/2001/23925.

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Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. We address a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or bring a processor into a power-down mode to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.
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Wang, Tun, and Yu Tian. "Design of Embedded Ai Engine Based on the Microkernel Operating System." Wireless Communications and Mobile Computing 2022 (April 21, 2022): 1–9. http://dx.doi.org/10.1155/2022/9304019.

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At present, the application of the embedded microkernel operating system in military and civil fields has begun to take shape, but it has not yet formed a unified method and standard. Due to its high performance, low frequency, and high reliability, dual-core embedded processors are getting the attention of many chip manufacturers. Compatibility has been favored by many telecom equipment manufacturers and embedded high-end application integrators, but the dual-core embedded processor needs a new real-time operating system to support it, so that it can give full play to the high performance of the dual-core. It paves the way for the application of its processor in the embedded field, but the design of embedded AI engine is not transparent to it; so, it needs the support of operating system. The user code is used to be in the operating system processor environment; so, it can be used on dual core processor first. In the real-time operating system that supports dual-core processors, the part that needs to be modified is mainly concentrated in the kernel part; so, the core design is the key point to support dual-core processors. This article is to seize this key point to carry out in-depth research. The difference and influence of hardware architecture between dual-core processor and single-core processor are the primary content of the study. Through the research of the dual-core processor architecture, the general abstraction of the dual-core processor architecture is obtained, which is the starting point of the follow-up research. This paper mainly studies the design of embedded AI engine based on the microkernel operating system, extracts the security requirements of the operating system, designs and implements the operating system from the perspective of formal verification, and considers the verification problem under the background of RTOS development, so as to avoid using too many complex data structures and algorithms in the system design and reduce the difficulty of experimental verification. In this paper, we use the spatiotemporal data model, data sharing security in the cloud environment, symmetric encryption scheme, and Paillier homomorphic encryption method to study the design of embedded AI engine based on the microkernel operating system. According to the idea of microkernel architecture, the kernel is divided into four main modules: task processing, semaphore, message queue, interrupt, and exception processing, and the lock mechanism to prevent reentrancy in software is analyzed separately. Three core function modules, initialization, process grinding, and interrupt processing, are extracted from the microkernel operating system to form the formal verification area of the operating system. At the same time, the system syntax and semantics of related rights are separated, and the main rationalization rules are described. The results show that the core of the microkernel operating system in five states adopts the microkernel architecture in the dual core environment. The microkernel architecture is a compact system kernel with good adjustability. Based on the analysis of the microkernel operating system, the internal structure of each module in the kernel is summarized, and the modules are modified according to the machine characteristics of the dual core processor; it corresponds to adding modules to meet the characteristics of dual core architecture. Kernel design is a systematic theoretical research process. This paper only uncovers the tip of the iceberg of real-time operating system kernel design on dual-core embedded processors. It is necessary to understand the kernel more deeply and master the kernel in the future work and study.
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Dissertations / Theses on the topic "Embedded Processors"

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Gong, Shaojie, and Zhongping Deng. "Benchmarks for Embedded Multi-processors." Thesis, Halmstad University, School of Information Science, Computer and Electrical Engineering (IDE), 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:hh:diva-660.

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During the recent years, computer performance has increased dramatically. To measure

the performance of computers, benchmarks are ideal tools. Benchmarks exist in many

areas and point to different applications. For instance, in a normal PC, benchmarks can be

used to test the performance of the whole system which includes the CPU, graphic card,

memory system, etc. For multiprocessor systems, there also exist open source benchmark

programs. In our project, we gathered information about some open benchmark programs

and investigated their applicability for evaluating embedded multiprocessor systems

intended for radar signal processing. During our investigation, parallel cluster systems

and embedded multiprocessor systems were studied. Two benchmark programs, HPL and

NAS Parallel Benchmark were identified as particularly relevant for the application field.

The benchmark testing was done on a parallel cluster system which has an architecture

that is similar to the architecture of embedded multiprocessor systems, used for radar

signal processing.

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Dasarathan, Dinesh. "Benchmark Characterization of Embedded Processors." NCSU, 2005. http://www.lib.ncsu.edu/theses/available/etd-05152005-170108/.

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The design of a processor is an iterative process, with many cycles of simulation, performance analysis and subsequent changes. The inputs to these cycles of simulations are generally a selected subset of standard benchmarks. To aid in reducing the number of cycles involved in design, one can characterize these selected benchmarks and use those characteristics to hit at a good initial design that will converge faster. Methods and systems to characterize benchmarks for normal processors are designed and implemented. This thesis extends these approaches and defines an abstract system to characterize benchmarks for embedded processors, taking into consideration the architectural requirements, power constraints and code compressibility. To demonstrate this method, around 25 benchmarks are characterized (10 from SPEC, and 15 from standard embedded benchmark suites - Mediabench and Netbench), and compared. Moreover, the similarities between these benchmarks are also analyzed and presented.
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Ryu, Soojung. "Storage Management for Embedded SIMD Processors." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5122.

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SIMD parallelism offers a high performance and efficient execution approach for today's broad range of portable multimedia consumer products. However, new methods are needed to meet the complex demands of high performance, embedded systems. This research explores new storage management techniques for this focused but critical application. These techniques include memory design exploration based on the application retargeting technique, storage-based systolic instruction broadcast, and systolic virtual memory to improve both the performance and efficiency of embedded SIMD systems. For an efficient storage usage by memory design space exploration in embedded SIMD systems, an analysis method for assessing storage needs and costs of a given application automatically retargeted across a spectrum of storage configuration designs was developed. Using this technique, a SIMD processing element achieves optimal area and energy efficiency with a register file containing between 8 and 12 words for given workload. This configuration is between 15% and 25% more area and energy efficient than other memory configurations being considered. Systolic instruction broadcast is a high performance and area efficient instruction broadcasting scheme with short-wire interconnects by eliminating of wire latency bottleneck found in global instruction broadcast. Three implementation methods are defined and evaluated - software method, 2-write port register file method, and bypass method. In our evaluations, due to the system's short clock cycle time and scheduler, a speedup in system performance of up to 7.5 can be achieved by the year 2010. In addition, speedup of area efficiency also can be achieved up to 7.2 for a given workload. The ability of minimizing off-chip memory access latency while maximizing access frequency by scheduling techniques along with data prefetch techniques in systolic virtual memory mechanism was evaluated using our SIMD-systolic architecture simulator. Results show that, systolic virtual off-chip memory with shared address space can achieve over 50% higher area efficiency than that of an on-chip only system for a matrix multiplication application.
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Johnson, N. E. "Code size optimization for embedded processors." Thesis, University of Cambridge, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.605626.

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This thesis studies the problem of reducing code size produced by an optimizing compiler. We develop the Value State Dependence Graph (VSDG) as a powerful intermediate form. Nodes represent computation, and edges represent value (data) and state (control) dependencies between nodes. The edges specify a partial ordering of the nodes—sufficient ordering to maintain the I/O semantics of the source program, while allowing optimizers greater freedom to move nodes within the program to achieve better (smaller) code. Optimizations, both classical and new, transform the graph through graph rewriting rules prior to code generation. Additional (se-mantically inessential) state edges are added to transform the VSDG into a Control Flow Graph, from which target code is generated. We show how procedural abstraction can be advantageously applied to the VSDG. Graph patterns are extracted from a program's VSDG. We then select repeated patterns giving the greatest size reduction, generate new functions from these patterns, and replace all occurrences of the patterns in the original VSDG with calls to these abstracted functions. Several embedded processors have load- and store-multiple instructions, representing several loads (or stores) as one instruction. We present a method, benefiting from the VSDG form, for using these instructions to reduce code size by provisionally combining loads and stores before code generation. The final contribution of this thesis is a combined register allocation and code motion (RACM) algorithm. We show that our RACM algorithm formulates these two previously antagonistic phases as one combined pass over the VSDG, transforming the graph (moving or cloning nodes, or spilling edges) to fit within the physical resources of the target processor. We have implemented our ideas within a prototype C compiler and suite of VSDG optimizers, generating code for the Thumb 32-bit processor. Our results show improvements for each optimization and that we can achieve code sizes comparable to, and in some cases better than, that produced by commercial compilers with significant investments in optimization technology.
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Mucci, Claudio <1977&gt. "Software tools or embedded reconfigurable processors." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/402/1/claudiomucci_phdthesis.pdf.

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Mucci, Claudio <1977&gt. "Software tools or embedded reconfigurable processors." Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/402/.

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Hoffmann, Andreas Leupers Rainer Meyr Heinrich. "Architecture exploration for embedded processors with LISA /." Boston [u.a.] : Kluwer Acad. Publ, 2002. http://www.loc.gov/catdir/toc/fy037/2002043258.html.

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Hadjiyiannis, George Ioannou. "An architecture synthesis system for embedded processors." Thesis, Massachusetts Institute of Technology, 2000. http://hdl.handle.net/1721.1/86440.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000.
Includes bibliographical references (leaves 261-264).
by George Ioannou Hadjiyiannis.
Ph.D.
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Mistry, Jatin N. "Leakage power minimisation techniques for embedded processors." Thesis, University of Southampton, 2013. https://eprints.soton.ac.uk/348805/.

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Leakage power is a growing concern in modern technology nodes. In some current and emerging applications, speed performance is uncritical but many of these applications rely on untethered power making energy a primary constraint. Leakage power minimisation is therefore key to maximising energy efficiency for these applications. This thesis proposes two new leakage power minimisation techniques to improve the energy efficiency of embedded processors. The first technique, called sub-clock power gating,can be used to reduce leakage power during the active mode. The technique capitalises on the observation that there can be large combinational idle time within the clock period in low performance applications and therefore power gates it. Sub-clock power gating is the first study into the application of power gating within the clock period, and simulation results on post layout netlists using a 90nm technology library show 3.5x, 2x and 1.3x improvement in energy efficiency for three test cases: 16-bit multiplier, ARM Cortex-M0 and Event Processor at a given performance point. To reduce the energy cost associated with moving between the sleep and active mode of operation, a second technique called symmetric virtual rail clamping is proposed. Rather than shutting down completely during sleep mode, the proposed technique uses a pair of NMOS and PMOS transistors at the head and foot of the power gated logic to lower the supply voltage by 2Vth. This reduces the energy needed to recharge the supply rails and eliminates signal glitching energy cost during wake-up. Experimental results from a 65nm test chip shows application of symmetric virtual rail clamping in sub-clock power gating improves energy efficiency, extending its applicable clock frequency range by 400x. The physical layout of power gating requires dedicated techniques and this thesis proposes dRail, a new physical layout technique for power gating. Unlike the traditional voltage area approach, dRail allows both power gated and non-power gated cells to be placed together in the physical layout to reduce area and routing overheads. Results from a post layout netlist of an ARM Cortex-M0 with sub-clock power gating shows standard cell area and signal routing are improved by 3% and 19% respectively. Sub-clock power gating, symmetric virtual rail clamping and dRail are incorporated into power gating design flows and are compatible with commercial EDA tools and gate libraries.
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Zushi, Junpei, Gang Zeng, Hiroyuki Tomiyama, Hiroaki Takada, and Koji Inoue. "Improved Policies for Drowsy Caches in Embedded Processors." IEEE, 2008. http://hdl.handle.net/2237/12081.

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Books on the topic "Embedded Processors"

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Henkel, Jörg, and Sri Parameswaran, eds. Designing Embedded Processors. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1.

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Corporation, Intel, ed. Embedded microcontrollers & processors. Mt. Prospect, Ill: Intel Corporation, 1992.

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Corporation, Intel. Embedded microcontrollers and processors. Santa Clara: Intel Corporation, 1993.

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Corporation, Intel. Embedded microcontrollers and processors. Santa Clara: Intel Corporation, 1993.

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Marwedel, Peter, and Gert Goossens, eds. Code Generation for Embedded Processors. Boston, MA: Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-2323-9.

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Peter, Marwedel, and Goossens Gert, eds. Code generation for embedded processors. Boston: Kluwer Academic Publishers, 1995.

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Marwedel, Peter. Code Generation for Embedded Processors. Boston, MA: Springer US, 2002.

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Embedded DSP processor design: Application specific instruction set processors. Amsterdam: Morgan Kaufmann, 2008.

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Liem, Clifford. Retargetable Compilers for Embedded Core Processors. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4757-6422-2.

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Leupers, Rainer. Code Optimization Techniques for Embedded Processors. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4757-3169-9.

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Book chapters on the topic "Embedded Processors"

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Henkel, Jörg, Sri Parameswaran, and Newton Cheung. "Application-Specific Embedded Processors." In Designing Embedded Processors, 3–23. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_1.

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Quan, Gang, and Xiaobo Sharon Hu. "Static DVFS Scheduling." In Designing Embedded Processors, 231–42. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_10.

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Pillai, Padmanabhan S., and Kang G. Shin. "Dynamic DVFS Scheduling." In Designing Embedded Processors, 243–58. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_11.

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Andrei, Alexandru, Petru Eles, Zebo Peng, Marcus Schmitz, and Bashir M. Al-Hashimi. "Voltage Selection for Time-Constrained Multiprocessor Systems." In Designing Embedded Processors, 259–84. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_12.

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Kremer, Ulrich. "Compilation Techniques for Power, Energy, and Thermal Management." In Designing Embedded Processors, 287–303. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_13.

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Hsu, Chung-Hsing, and Ulrich Kremer. "Compiler-Directed Dynamic CPU Frequency and Voltage Scaling." In Designing Embedded Processors, 305–23. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_14.

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Li, Feihui, Guangyu Chen, Mahmut Kandemir, and Mustafa Karakoy. "Link Idle Period Exploitation for Network Power Management." In Designing Embedded Processors, 325–45. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_15.

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Li, Zhiyuan, and Cheng Wang. "Remote Task Mapping." In Designing Embedded Processors, 347–70. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_16.

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Martin, Grant. "A Power and Energy Perspective on MultiProcessors." In Designing Embedded Processors, 373–89. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_17.

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Chatha, Karam S., and Krishnan Srinivasan. "System-Level Design of Network-on-Chip Architectures." In Designing Embedded Processors, 391–422. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-5869-1_18.

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Conference papers on the topic "Embedded Processors"

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Butera, William, and V. Michael Bove, Jr. "Literally embedded processors." In Photonics West 2001 - Electronic Imaging, edited by Sethuraman Panchanathan, V. Michael Bove, Jr., and Subramania I. Sudharsanan. SPIE, 2001. http://dx.doi.org/10.1117/12.420800.

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Tillich, Stefan, Mario Kirschbaum, and Alexander Szekely. "SCA-resistant embedded processors." In the 26th Annual Computer Security Applications Conference. New York, New York, USA: ACM Press, 2010. http://dx.doi.org/10.1145/1920261.1920293.

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Lakshmi, Vinay Vijendra Kumar, Arindam Mukherjee, and Bharat Joshi. "Architecture exploration for embedded processors: Design framework for embedded bio-medical processors." In IEEE SOUTHEASTCON 2013. IEEE, 2013. http://dx.doi.org/10.1109/secon.2013.6567394.

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Sjödin, Jan, and Carl von Platen. "Storage allocation for embedded processors." In the international conference. New York, New York, USA: ACM Press, 2001. http://dx.doi.org/10.1145/502217.502221.

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Vinay Vijendra Kumar Lakshmi, Arindam Mukherjee, and Bharat Joshi. "Architecture exploration for embedded processors." In SOUTHEASTCON 2012. IEEE, 2012. http://dx.doi.org/10.1109/secon.2012.6196917.

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Gholamipour, Amir Hossein, Elaheh Bozorgzadeh, and Sudarshan Banerjee. "Energy-aware co-processor selection for embedded processors on FPGAs." In 2007 25th International Conference on Computer Design ICCD 2007. IEEE, 2007. http://dx.doi.org/10.1109/iccd.2007.4601895.

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"Session TA1: Embedded Processors for SOC." In IEEE International SOC Conference, 2004. Proceedings. IEEE, 2004. http://dx.doi.org/10.1109/socc.2004.1362400.

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Fisher, Joseph A. "Customized instruction-sets for embedded processors." In the 36th ACM/IEEE conference. New York, New York, USA: ACM Press, 1999. http://dx.doi.org/10.1145/309847.309923.

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Azarpeyvand, Ali, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, and Sied Mehdi Fakhraie. "Instruction reliability analysis for embedded processors." In 2010 IEEE 13th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). IEEE, 2010. http://dx.doi.org/10.1109/ddecs.2010.5491824.

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Deris, Kaveh Jokar, and Amirali Baniasadi. "Branchless cycle prediction for embedded processors." In the 2006 ACM symposium. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1141277.1141492.

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Reports on the topic "Embedded Processors"

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Lee, Edward A. System-Level Design Methodology for Embedded Signal Processors. Fort Belvoir, VA: Defense Technical Information Center, August 1997. http://dx.doi.org/10.21236/ada342899.

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Graham, Paul, and Brent Nelson. Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. Fort Belvoir, VA: Defense Technical Information Center, January 1999. http://dx.doi.org/10.21236/ada451425.

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Wheat, Jr., Robert Mitchell, Dale A. Dalmas, and Gregory E. Dale. A Four Channel Beam Current Monitor Data Acquisition System Using Embedded Processors. Office of Scientific and Technical Information (OSTI), August 2015. http://dx.doi.org/10.2172/1209457.

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Shen, Chung-Ching, Shenpei Wu, Lai-Huei Wang, Stephen Won, Kishan Sudusinghe, and Shuvra Bhattacharyya. Dataflow-Based Implementation of Layered Sensing Applications on High-Performance Embedded Processors. Fort Belvoir, VA: Defense Technical Information Center, March 2013. http://dx.doi.org/10.21236/ada582499.

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Chou, Pai, Ken Hines, Kurt Partridge, and Gaetano Borriello. Control Generation for Embedded Systems Based on Composition of Modal Processes. Fort Belvoir, VA: Defense Technical Information Center, January 1998. http://dx.doi.org/10.21236/ada416531.

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Wilcox, D. R., and P. N. Pham. Unix STREAMS Emulation of an Input/Output Controller (IOC) for an Embedded AN/UYK-44(V) Processor. Fort Belvoir, VA: Defense Technical Information Center, May 1993. http://dx.doi.org/10.21236/ada270867.

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Learn, Mark Walter. Mitigation of cache memory using an embedded hard-core PPC440 processor in a Virtex-5 Field Programmable Gate Array. Office of Scientific and Technical Information (OSTI), February 2010. http://dx.doi.org/10.2172/984165.

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Higdon, Grace Lyn. Nested Theories of Change for Adaptive Rigour. Institute of Development Studies (IDS), December 2020. http://dx.doi.org/10.19088/creid.2020.010.

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This learning brief provides illustrative examples of three major adaptations the Coalition for Religious Equality and Inclusive Development (CREID) programme has undertaken while working within fragile contexts to promote freedom of religion or beilief (FoRB). These examples highlight how the programme has utilised embedded monitoring, evaluation, and learning (MEL) strategies to encourage what Ramalingam et al. (2019) refer to as ‘adaptive rigour’, a concept which underscores the importance of transparent documentation of programmatic decision making processes during programme adaptations. In particular this learning brief discusses the use of nested theories of change as a mechanism to enable adaptive rigour within the 'multitude of smalls' approach in the CREID programme.
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Jha, Deepika, Sudeshna Mitra, Amlanjyoti Goswami, Sahil Sasidharan, and Kaye Lushington. Land Records Modernisation in India: Bihar. Indian Institute for Human Settlements, 2021. http://dx.doi.org/10.24943/9788195648535.

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This work provides an institutional, legal and policy review of crucial aspects of land records modernisation systems in Bihar. The state’s progress with land records modernisation efforts has been historically slow but in the last few years, it has taken long strides in computerisation of land records and associated processes, and is on the way to a more accessible land information system. Bihar is a significant example to understand that in certain parts of India, issues of land and property ownership are embedded in socio-historical conditions, which can be addressed only in part by current modernisation efforts. The state is undertaking an attempt to address some of these issues through a resurvey, supported by large scale strengthening of capacity, and legislative framework. The ability of the state to address multiple claims in a judicious and timebound manner would determine, to a large extent, how successful these ongoing surveys and computerisation initiatives will be.
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Clark, Louise. The Diamond of Influence: A Model For Exploring Behaviour in Research to Policy Linkages. Institute of Development Studies (IDS), November 2020. http://dx.doi.org/10.19088/apra.2020.011.

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This learning paper presents an initial analysis of the emerging research to policy linkages within the Agricultural Policy Research in Africa (APRA) programme of the Future Agricultures Consortium, which is funded by the Foreign, Commonwealth & Development Office (FCDO). APRA has an innovative monitoring, evaluation and learning approach known as the ‘Accompanied Learning on Relevance and Effectiveness’ (ALRE), which is being delivered by a small team of embedded evaluation specialists. This paper discusses how ALRE has applied the COM-B (Capability, Opportunity, Motivation and Behaviour) (Mayne 2018; Mayne 2016; Michie, van Stralen and West 2011) model of behaviour change to explore the interactions and influencing strategies between researchers and policymakers in the context of agricultural policy research in Africa. These insights have produced the Diamond of Influence, a new ALRE-adapted model, which applies each of the COM-B elements to discuss the different aspects of research to policy processes, drawing on examples of how researchers in each of the APRA focus countries (Ethiopia, Ghana, Malawi, Nigeria, Tanzania and Zimbabwe) are engaging in policy spaces.
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