Dissertations / Theses on the topic 'Electronic circuits development'

This dissertation focuses on the development of integrated circuits that employ InAs quantum well electronic devices. There are two InAs quantum well electronic devices studied in this work, the first being the pseudomorphic InAs/In₀.₅₃Ga₀.₄₇As/AlAs resonant tunneling diode (RTD) grown on an InP substrate, and the second being the InAs/AlSb HEMT. Because of there is no semi-insulating substrate near the InAs lattice constant of 6.06 Å this work develops monolithic and hybrid integration methods to realize integrated circuits. For the case of hybrid RTD circuits, a thin-film integration method was developed to integrate InAs/In₀.₅₃Ga₀.₄₇As/AlAs RTDs to prefabricated CMOS circuits, and this technique was employed to demonstrate a novel RTD-CMOS comparator. To achieve higher speed circuit operation, a next-generation RTD fabrication process was developed to minimize the parasitic capacitance associated with the thin-film hybridization process. This improved fabrication process is detailed and yield and uniformity analysis is included. Similar InP-based tunnel diodes can be integrated with InP-based HEMTs in monolithic RTD-HEMT integrated circuits, and in this work elementary microwave circuit components were characterized that co-integrate InP-based tunnel diodes with HEMTs. In the case of the InAs/AlSb HEMT, the monolithic approach grows the HEMT on a metamorphic buffer on a GaAs substrate. The semiconductor material and process development of the InAs/AlSb HEMT MMIC technology is described. The remarkable microwave and RF noise properties of the InAs/AlSb HEMT were characterized and analyzed, with special attention given to the strong effects of impact ionization in the narrow bandgap InAs channel. Results showed the extent to which impact ionization affects the small-signal gain and noise figure of the HEMT, and that these effects become less prevalent as the frequency of operation increases.

Thesis (M.S.)--Missouri University of Science and Technology, 2008.
Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed May 5, 2008) Includes bibliographical references (p. 21-22).

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2003.
Includes bibliographical references (leaves 70-72). Also available in electronic version. Access restricted to campus users.

Thesis (Masters Diploma (Electrical Engineering)--Cape Technikon, Cape Town, 1988
The subject of this thesis is the development of ahighly ruggedised, reliable electronic circuit. The circuit is to be used for the initiation of fuze heads and to charge a capacitor for later use in apyrotechnic chain. This circuit and its associated packaging will be called the firing unit. The thesis can be broadly divided into the following facets. I. The definition study, which defines what is needed and proposed means of achieving the customer requirements. 11. The design of the electronic circuitry in the system. Ii!. The design of the packaging containing the electronics. Iv. Adaptation of environmental testing, to verify system design. V. Implementation of environmental testing. Vi. Reliability analysis. Vii. Failure analysis and the determination of the effect of the supposed failure. Actions vto vii were used as inputs to improve 11 and ill, so achieving optimum performance and safety. The whole system was designed with the overriding objective of reliability and safety of personnel and equipment.

L’objectif de cette thèse était de démontrer les potentialités du procédé technologique d’impression jet d’encre pour la fabrication de circuits numériques à base de matériaux organiques. Une première étape sur le développement d’une structure de transistor couches minces organiques (OTFTs) fabriquée par impression jet d’encre a permis d’appréhender les mécanismes d’intéraction entre les différents matériaux déposés en solution. A partir de cette étude, la structure a pu être optimisée afin d’obtenir des performances électriques uniformes et reproductibles. Les transistors en couches minces organiques ont ensuite été modélisés électriquement à l’aide d’un modèle simple (Aim-Extract, Aim-Spice). La comparaison entre caractérisations et simulations électriques ont démontré la possibilité de prédire le comportement électrique de la structure OTFT imprimée.A partir de ce modèle, des portes logiques élémentaires ont été simulées puis fabriquées par la technologie d’impression jet d’encre. Les limitations en termes de temps de réponse des circuits et de tensions d’alimentation ont ainsi pu être déterminés. Finalement, des circuits électroniques combinatoires et séquentiels plus complexes, tel que des multiplexeurs et des bascules de type D, ont été fabriqués et caractérisés. La démarche employée au cours de cette étude, à savoir, l’optimisation de la structure OTFT, la modélisation électrique et la fabrication d’un circuit électronique complet a démontré les potentialités de l’impression jet d’encre pour la réalisation d’électronique bas-coût, grande surface, entièrement additive et potentiellement flexible
The main objective of this study was to demonstrate the capability of inkjet printing technology to fabricate organic based digital circuits. At first, development of an Organic Thin Film Transistor structure (OTFTs) fabricated with inkjet printing technology has highlighted interaction mechanisms between materials deposited with a fully solution process. From this study, the structure has been optimized to obtain uniform and reproducible electrical performance. The organic Thin Film Transistors were then electrically modeled using a simple model (Aim-Extract, Aim-Spice). The comparison between electrical characterizations and simulations has demonstrated the possibility to predict electrical behavior of printed OTFT. From this model, elementary logic gates were simulated and then fabricated by inkjet printing technology. Time response and supply voltage of such circuit has been determined. Finally, more complex combinational and sequential electronic circuits, such as multiplexers and D-latch, were fabricated and characterized. The Experimental protocol used in this study dealing with: i) OTFT electrical optimization, ii) electrical modeling and iii) electronic circuit fabrication has demonstrated the ability of inkjet printing to reach low-cost, large area, fully additive and potentially flexible electronics

In DC/DC converter systems, power electronic circuits are reaching switching efficiencies close to 100 percent nowadays. Thus, most of the energy loss appears inside the passive magnetic circuit of the converter, which at the same time is the component that requires most space in the system. In order to battle this issue, research during the last century has been focused on planarization, hybridization and integration techniques with the goal to achieve higher efficiencies and decrease the profile and volume of the devices. In addition, higher frequencies have been applied to achieve a higher power density of the magnetic systems, but with the negative consequence of stronger parasitic effects such as proximity and skin effects inside the magnetic circuit. This thesis deals with the development of an integrated magnetic system in a L-C-T (Inductor-Capacitor-Transformer) configuration, with the assistance of Finite Element Method (FEM) computer modeling, which is supportively used to accelerate the development process. Computational simulation method is used to indicate and address the physical issues, which cannot be identified with conventional measurement methods.
Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
Griffith School of Engineering
Science, Environment, Engineering and Technology
Full Text

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Systems Science and Industrial Engineering, 2007.
Includes bibliographical references.

Thesis submitted in fulfillment of the requirements for the degree Master of Technology:Electrical Engineering in the Faculty ofEngineering at the Cape Peninsula University of Technology Supervisor:Prof MTE KAHN Bellville December 2013
The work presented in this thesis consists of the simulation of a cooling plant for a future mobile satellite ground station in order to minimize the effects of the thermal noise and to maintain comfort temperatures onboard the same station. Thermal problems encountered in mobile satellite ground stations are a source of poor quality signals and also of the premature destruction of the front end microwave amplifiers. In addition, they cause extreme discomfort to the mission operators aboard the mobile station especially in hot seasons. The main concerns of effective satellite system are the quality of the received signal and the lifespan of the front end low noise amplifier (LNA). Although the quality of the signal is affected by different sources of noise observed at various stages of a telecommunication system, thermal noise resulting from thermal agitation of electrons generated within the LNA is the predominant type. This thermal noise is the one that affects the sensitivity of the LNA and can lead to its destruction. Research indicated that this thermal noise can be minimized by using a suitable cooling system. A moveable truck was proposed as the equipment vehicle for a mobile ground station. In the process of the cooling system development, a detailed quantitative study on the effects of thermal noise on the LNA was conducted. To cool the LNA and the truck, a 2 kW solar electric vapor compression system was found the best for its compliance to the IEA standards: clean, human and environment friendly. The principal difficulty in the development of the cooling system was to design a photovoltaic topology that would ensure the solar panels were always exposed to the sun, regardless the situation of the truck. Simulation result suggested that a 3.3 kW three sided pyramid photovoltaic topology would be the most effective to supply the power to the cooling system. A battery system rated 48 V, 41.6 Ah was suggested to be charged by the PV system and then supply the power to the vapor compression system. The project was a success as the objective of this project has been met and the research questions were answered.

Many modern digital systems use forms of CMOS logical implementation due to the straight forward design nature of CMOS logic and minimal device area since CMOS uses fewer transistors than other logic families. To achieve high-performance requirements in mixed-signal chip development and quiet, noiseless circuitry, this thesis provides an alternative toCMOSin the form of MOS Current Mode Logic (MCML). MCML dissipates constant current and does not produce noise during value changing in a circuit CMOS circuits do. CMOS logical networks switch during clock ticks and with every device switching, noise is created on the supply and ground to deal with the transitions. Creating a noiseless standard cell library with MCML allows use of circuitry that uses low voltage switching with 1.5V between logic levels in a quiet or mixed-signal environment as opposed to the full rail to rail swinging of CMOS logic. This allows cohesive implementation with analog circuitry on the same chip due to constant current and lower switching ranges not creating rail noise during digital switching. Standard cells allow for the Cadence tools to automatically generate circuits and Cadence serves as the development platform for the MCML standard cells. The theory surrounding MCML is examined along with current and future applications well-suited for MCML are researched and explored with the goal of highlighting valid candidate circuits for MCML. Inverters and NAND gates with varying current drives are developed to meet these specialized goals and are simulated to prove viability for quiet, mixed-signal applications. Analysis and results show that MCML is a superior implementation choice compared toCMOSfor high speed and mixed signal applications due to frequency independent power dissipation and lack of generated noise during operation. Noise results show rail current deviations of 50nA to 300nA during switching over an average operating current of 20µA to 80µA respectively. The multiple order of magnitude difference between noise and signal allow the MCML cells to dissipate constant power and thus perform with no noise added to a system. Additional simulated results of a 31-stage ring oscillator result in a frequency for MCML of 1.57GHz simulated versus the 150.35MHz that MOSIS tested on a fabricated 31-stage CMOS oscillator. The layouts designed for the standard cell library conform to existing On Semiconductor ami06 technology dimensions and allow for design of any logical function to be fabricated. The I/O signals of each cell operate at the same input and output voltage swings which allow seamless integration with each other for implementation in any logical configuration.

When an energetic ion strikes a microelectronic device it induces current transients that may lead to a variety of undesirable Single Event Effects (SEE). An important part of the activity of the SIRAD heavy ion facility at the 15 MV Tandem accelerator of the INFN Laboratories of Legnaro (Italy) concerns SEE studies of microelectronic devices destined for radiation hostile environments. An axial Ion Electron Emission Microscope (IEEM) is working at the SIRAD irradiation facility. It is devised to provide a micrometric sensitivity map of Single Event Effects of an electronic device. The IEEM system reconstructs the positions of individual random ion impacts over a circular area of 180 µm diameter by imaging the ion-induced secondary electrons emitted from the target surface. A fast Data Acquisition system (DAQ) is used to reconstruct the X and Y coordinates and the temporal information of every ion impact. Any signal induced by the SEE in a generic DUT can be used to tag the IEEM reconstructed event. This information is then used to display a map of the regions of the DUT surface which are sensitive to the impinging ions. In this thesis we introduce the subject of the effects of ionizing radiation on microelectronics circuits and systems. We then describe in detail the IEEM system, especially how it was modified and improved during the period of our work. We present the results of an extensive study of the IEEM resolution and image distortions, performed using high statistics acquisitions obtained with a 241 MeV 79Br ion beam by means of a fast SDRAM-based ion induced single event detection system, specifically designed for this purpose. We also describe a new feature implemented in the DAQ system which enables the IEEM to perform Time Resolved Ion Beam Induced Charge Collection (TRIBICC) studies, and show preliminary results obtained studying a MOSFET power transistor. We also studied a digital microelectronic circuit (SOI-Imager Shift Register) in two steps: we measured the SEU cross-section with our broad-beam facility at SIRAD, and then used the IEEM to acquire a SEU sensitivity map. At present the resolution of the IEEM at SIRAD is not close to the theoretical one. In this thesis we also describe an extensive set of studies we performed to investigate the origin of the resolution degradation. The conclusions follow and close this work.
Quando uno ione energetico colpisce un dispositivo microelettronico, induce impulsi di corrente che possono generare diversi Single Event Effect (SEE) indesiderati. Una parte importante dell'attività della facility di irraggiamento a ioni pesanti SIRAD, presso il tandem da 15 MV dei Laboratori Nazionali di Legnaro (Italia) dell'INFN, riguarda studi di SEE su dispositivi microelettronici destinati ad ambienti ostili per il livello delle radiazioni. Presso la facility di irraggiamento SIRAD, e' in funzione un Ion Electron Emission Microscope (IEEM). Esso e' concepito per generare mappe di sensibilità a Single Event Effect di un dispositivo elettronico, con risoluzione micrometrica: il sistema IEEM ricostruisce le posizioni degli impatti di singoli ioni distribuiti casualmente entro un'area di 180 µm di diametro, acquisendo gli elettroni secondari emessi dalla superficie del bersaglio colpita dallo ione. Un sistema di acquisizione veloce (DAQ) è utilizzato per ricostruire le coordinate X ed Y e l'informazione temporale di ogni impatto. Ogni segnale indotto da un SEE in un generico dispositivo sotto test può essere utilizzato per marcare gli eventi ricostruiti dal sistema. Queste informazioni sono in seguito utilizzate per generare una mappa delle aree della superficie del dispositivo che sono sensibili all'impatto ionico. In questa tesi introduciamo l'argomento degli effetti della radiazione ionizzante sui sistemi e i dispositivi microelettronici e in seguito descriviamo in dettaglio il sistema IEEM, soffermandoci in particolare sulle modifiche e le migliorie introdotte durante questo periodo di lavoro. Descriviamo un detector di singoli impatti ionici, basato su una SDRAM, con il quale abbiamo ottenuto acquisizioni ad alta statistica usando un un fascio di ioni 79Br da 241 MeV. Questi dati ci hanno consentito uno studio approfondito della risoluzione dell'IEEM e della distorsione dell'immagine generata. Descriviamo inoltre una nuova caratteristica implementata nel nostro sistema di acquisizione, che consente all'IEEM di effettuare analisi di Time Resolved Ion Beam Induced Charge Collection (TRIBICC), e illustriamo i risultati preliminari ottenuti studiando un transistor MOSFET di potenza. Abbiamo infine studiato un circuito microelettronico digitale (SOI-Imager Shift Register) in due fasi: dapprima e' stata misurata la sezione d'urto a SEU con la nostra facility di irraggiamento a fascio non focalizzato, e in seguito l'IEEM e' stato utilizzato per acquisire una mappa di sensibilità a SEU. Infine, verificato che allo stato attuale la risoluzione dell'IEEM presso SIRAD non e' vicina al valore teorico, in questo lavoro di tesi descriviamo la serie di studi approfonditi condotti al fine di indagare l'origine della degradazione della risoluzione.

The research presented in this thesis leverages silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technology to develop microwave front-end electronics for active phased-array antennas. The highly integrated electronics will reduce costs and improve the feasibility of snow measurements from airborne and space-borne platforms. Chapter 1 presents the motivation of this research, focusing on the technological needs of snow measurement missions. The fundamentals and benefits of SiGe HBTs and phased-array antennas for these missions are discussed as well. Chapter 2 discusses SiGe power amplifier design considerations for radar systems. Basic power amplifier design concepts, power limitations in SiGe HBTs, and techniques for increasing the output power of SiGe HBT PAs are reviewed. Chapter 3 presents the design and characterization of a robust medium power X-band SiGe power amplifier for integration into a SiGe transmit/receive module. The PA design process applies the concepts presented in Chapter 2. A detailed investigation into measurement-to-simulation discrepancies is outlined as well. Chapter 4 discusses the development and characterization of a single-chip X-band SiGe T/R module for integration into a very thin, lightweight active phased array antenna panel. The system-on-package antenna combines the high performance and integration potential of SiGe technologies with advanced substrates and packaging techniques to develop a high performance scalable antenna panel using relatively low-cost materials and silicon-based electronics. The antenna panel presented in this chapter will enable airborne SCLP measurements and advance the technology towards an eventual space-based SCLP measurement instrument that will satisfy a critical Earth science need. Finally, Chapter 5 provides concluding remarks and discusses future research directions.

The task of thermal management in electrical systems has never been simple and has only become more difficult in recent years as the power electronics industry pushes towards devices with higher power densities. At the Center for Power Electronic Systems (CPES), a new approach to power electronic design is being implemented with the Integrated Power Electronic Module (IPEM). It is believed that an IPEM-based design approach will significantly enhance the competitiveness of the U.S. electronics industry, revolutionize the power electronics industry, and overcome many of the technology limits in today's industry by driving down the cost of manufacturing and design turnaround time. But with increased component integration comes the increased risk of component failure due to overheating. This thesis addresses the issues associated with the thermal management of integrated power electronic devices. Two studies are presented in this thesis. The focus of these studies is on the thermal design of a DC-DC front-end power converter developed at CPES with an IPEM-based approach. The first study investigates how the system would respond when the fan location and heat sink fin arrangement are varied in order to optimize the effects of conduction and forced-convection heat transfer to cool the system. The set-up of an experimental test is presented, and the results are compared to the thermal model. The second study presents an improved methodology for the thermal modeling of large-scale electrical systems and their many subsystems. A zoom-in/zoom-out approach is used to overcome the computational limitations associated with modeling large systems. The analysis performed in this paper was completed using I-DEAS©,, a three-dimensional finite element analysis (FEA) program which allows the thermal designer to simulate the affects of conduction and convection heat transfer in a forced-air cooling environment.
Master of Science

Le travail de thèse porte sur l'étude de l'électronique front-end pour le télescope WFCTA (Wide Field of View Cherenkov Telescope Array,) qui est l'un des détecteurs de l’observatoire LHAASO (Large High Altitude Air shower Observatory,). Le manuscrit de thèse couvre six thèmes principaux allant de la simulation physique au développement d’un nouveau système d'acquisition de données.Tout d'abord, les principes de la physique des rayons cosmiques et de l'expérience LHAASO sont présentés donnant ainsi une introduction sur les sujets discutés dans la thèse. Des simulations ont été faites dans le but de comprendre la propagation des rayons cosmiques dans l'atmosphère et d’en déduire les caractéristiques du signal d'entrée de l'électronique. Ces simulations ont également été utilisées pour approfondir la compréhension des spécifications du télescope et de les vérifier.Un nouveau modèle de PMT a été élaboré pour être utilisé dans les simulations. Ce nouveau modèle est comparé aux autres modèles de PMT. Des modèles d’électronique pour les conceptions basées sur les composants électroniques classiques et sur l’ASIC (Application-specific Integrated Circuit) sont construites et étudiées. Ces deux solutions remplissent les spécifications du télescope WFCTA. Néanmoins, compte tenu du développement de la micro-électronique, il est proposé que l’électronique des télescopes de haute performance devrait être basée sur l’ASIC.L'ASIC sélectionné, PARISROC 2, est évalué en utilisant des bancs de tests existants. Les résultats montrent que ces bancs de tests ne peuvent pas démontrer pleinement la véritable performance de l’ASIC. Par conséquent, une carte électronique front-end prototype qui est basée sur ASIC a été conçu et fabriqué. Plusieurs modifications ont été apportées pour améliorer la performance de la nouvelle carte. Une description détaillée de ce développement est présentée dans la thèse. Un nouveau système d’acquisition de données a également été conçu pour améliorer la capacité de lecture de données dans le banc de tests de la carte front-end.Enfin, une série de tests ont été effectués pour vérifier le concept de design et pour évaluer la performance de la carte front-end. Ces résultats montrent la bonne performance générale de l'ASIC PARISROC 2 et que la carte front-end répond globalement aux spécifications de la WFCTA. Basé sur les résultats de ce travail de thèse, un nouveau ASIC, mieux adapté pour les télescopes de type WFCTA, a été conçu et est actuellement en cours de fabrication
This thesis is focused on the study of the front-end electronics for the wide field of view Cherenkov telescope array (WFCTA), which is one of the large high altitude air shower observatory (LHAASO) detectors. The thesis manuscript covers six main topics going from the physics simulations to the implementation of a new data acquisition system. The physics of cosmic rays and the LHAASO experiment is presented giving foundation for discussion of the main topics of the thesis. Simulations were performed to understand the propagation of cosmic rays in the atmosphere and to determine the characteristics of the input signal of the electronics. These simulations allow also understand the specifications of the telescope and to verify them. A new PMT model was successfully built for both physical and electronic simulations. This new model is compared to other models and its performance is evaluated. Behavior models for the designs based on the classical electronics and application-specific integrated circuit (ASIC) were built and studied. It is shown that both solutions fit the requirements of the telescope. However, considering the development of the micro-electronics, it is proposed that the electronics of the high-performance telescopes should be based on ASIC. The selected ASIC, PARISROC 2, is evaluated by using the existing application boards. The results showed that the designs considered could not fully demonstrate the real performance of the chip. Therefore, a prototype front-end electronics board, based on PARISROC 2, was designed, implemented and fabricated. Several modifications and enhancements were made to improve the performance of the new design. A detailed description of the development is presented and discussed in the manuscript. Furthermore, a new data acquisition system was developed to enhance the readout capabilities in the front-end test bench.Finally, a series of tests were performed to verify the concept of the design and to evaluate the front-end board. The results show the good general performance of the PARISROC 2 and that this design globally meets the specifications of the WFCTA. Based on the results of this thesis work, a new ASIC chip, better adapted for telescopes such as WFCTA, has been designed and is currently being fabricated

Phase change memory (PCM) is an emerging non-volatile memory technology that demonstrates promising performance characteristics. The presented research aims to study the feasibility of using resistive non-volatile PCM in embedded memory applications, and in bridging the performance gap in traditional memory hierarchy between volatile and non-volatile memories. The research studies the operation dynamics of PCM, including its electrical, thermal and physical properties; in order to determine its behaviour. A PCM cell circuit model is designed and simulated with the aid of SPICE tools (LTSPICE IV). The first step in the modelling process was to design a single-level PCM (SLPCM) cell circuit model that stores a single bit of data. To design the PCM circuit model; crystallization theory and heat transfer equation were utilized. The developed electrical circuit model evaluates the physical transformations that a PCM cell undergoes in response to an input pulse. Furthermore, the developed model accurately simulated the temperature profile, the crystalline fraction, and the resistance of the cell as a function of the programming pulse. The circuit model is then upgraded into a multilevel phase change memory (MLPCM) cell circuit model. The upgraded MLPCM circuit model stores two bits of data, and incorporates resistance drift with time. The multiple resistance levels were achieved by controlling the programming pulse width in the range of 10ns to 200ns. Additionally, the drift behaviour was precisely evaluated; by using statistical data of drift exponents, and evaluating the exact drift duration. Moreover, the simulation results for the designed SLPCM and MLPCM cell models were found to be in close agreement with experimental data. The simulated I-V characteristics for both SLPCM and MLPCM mimicked the experimentally produced I-V curves. Furthermore, the simulated drift resistance levels matched the experimental data for drift durations up to 103 seconds; which is the available experimental data duration in technical literature. Furthermore, the simulation results of MLPCM showed that the deviation between the programmed and drifted resistance can reach 6x106Ω in less than 1010 seconds. This resistance deviation leads to reading failures in less than 100 seconds after programming, if standard fixed sensing thresholds method was used. Therefore, to overcome drift reliability issues, and retain the density advantage offered by multilevel operation; a time-aware sensing scheme is developed. The designed sensing scheme compensates for the drift caused resistance deviation; by using statistical data of drift coefficients to forecast adaptive sensing thresholds. The simulation results showed that the use of adaptive time-aware sensing thresholds completely eliminated drift reliability issues and read errors. Furthermore, PCM based nanocrossbar memory structure performance in terms of delay and energy consumption is studied in simulation environment. The nanocrossbar is constructed with a grid of connecting wires; and the designed PCM cell circuit model is used as memory element and placed at junction points of the grid. Then the effect of connecting nanowires resistance in PCM nanocrossbar performance is studied in passive crossbars. The resistance of a connecting wire segment was evaluated with physical formulas that calculate nanoscaled conductors’ resistance. Then a resistor that is equivalent to each wire segment resistance is placed in the tested crossbar structure. Simulation results showed that due to connecting wires resistance; the PCM cells are not truly biased to programming voltage and ground. This leads to 40% deviation in the programed low resistive state from the targeted levels. Thus, affecting PCM reliability and decreasing the high to low resistance ratio by 90%. Therefore, programming and architectural solutions to wire resistance related reliability issue ar presented. Where dissipated power across wire resistance is compensated for; by controlling programming pulse duration. The programming solution retained reliability however; it increased programming energy consumption and delay by an average of 40pJ and 60ns respectively per operation. Additionally, the effects of leakage energy in PCM based nanocrossbars were studied in simulation environment. Then, a structural solution was developed and designed. In the designed structure; leakage sneak paths are eliminated by introducing individual word lines to each memory element. This method led to 30% reduction in reading delay, and consumed only about sixth the leakage energy consumed by the standard structure. Moreover, a sensing scheme that aims to reduce energy consumption in PCM based nanocrossbars during reading process was explored. The sensing method is developed using AC current in contrast to the standard DC current reading circuits. In the designed sensing circuit, a low pass filter is utilized. Accordingly, the filter attenuation of the applied AC reading signal indicates the stored state. The proposed circuit design of the AC sensing scheme was constructed and studied in simulation environment. Simulation results showed that AC sensing has reduced reading energy consumption by over 50%; compared to standard DC sensing scheme. Furthermore, the use of SLPCM and MLPCM in memory applications as crossbar memory elements, and in logic applications i.e. PCM based LUTs was explored and tested in simulation environment. The PCM performance in crossbar memory was then compared to current Static Random Access Memory (SRAM) technology and against one of the main emerging resistive non-volatile memory technologies i.e. Memristors. Simulation results showed that programming and reading energy consumption of PCM based crossbars were five orders of magnitude more than SRAM based crossbars. And reading delay of SRAM based crossbars was only 38% of reading delay of PCM based counterparts. However, PCM cells occupies less than 60% of the area required by SRAM and can store multiple bit in a single cell. Moreover, Memristor based nanocrossbars outperformed PCM based ones; in terms of delay and energy consumption. With PCM consuming 2 orders of magnitude more energy during programming and reading. PCM also required 10 times the programming delay. However, PCM crossbars offered higher switching resistance range i.e. 170kΩ compared to the 20kΩ offered by memristors; which support PCM multibit storage capability and higher density.

Thesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (leaf 153).
Due to the constraints on time and resources within the typical electrical engineering curriculum, it is difficult for students to obtain Integrated Circuit design experience prior to entering industry. This project establishes the foundation for a new laboratory course in power electronics and analog circuit design. There is an introduction to power electronics, particularly the buck converter, and several basic analog circuit building blocks are introduced. A process consisting of circuit design, simulation, construction, and evaluation is developed to provide students with an introduction to Integrated Circuit design. A peak current mode PWM controller for a buck converter is developed to illustrate the fundamental power electronic and analog circuit concepts that are presented.
by Candace N. Wilson.
M.Eng.and S.B.

Integrated circuit (IC) layer topology analysis methods are the main research topic of this doctoral thesis. Multiple methods are presented for IC layer feature analysis along with a software system where they are implemented and tested. Each of different IC layers has distinct features therefore it is very difficult to use universal algorithm for their analysis. A specialized software system was developed to test various analysis algorithms. The system and its architecture is a part of this thesis. Main tasks solved during research of this these were: finding or developing of optimal methods suitable for IC layer structure recognition, software system design and implementation, experimental testing of implemented methods accuracy and efficiency. Thesis consists of introduction, four chapters and the chapter of conclusions. In the introduction scientific novelty of the work is described as well as the aims and tasks of the work are formulated and the author’s publications and structure of the thesis are presented. The first chapter is dedicated to literature review. It covers existing IC layer structure analysis systems and algorithms which are used for this task. Generic image processing and analysis algorithms and methods are also covered as they are used as part of methodology developed in this thesis. The second chapter details different types of IC layers and their properties. Image processing and analysis methods suitable for each of these layer types are... [to full text]
Disertacijoje nagrinėjama integrinių grandynų (IG) topologijos elementų atpažinimo sistemos metodai ir algoritmai, jų taikymas bei pačios sistemos architektūra. Integrinių schemų projektavimo ir gamybos pramonėje problema yra automatinis kiekvieno technologinio lusto sluoksnio vaizdinės informacijos apdorojimas ir analizė, tiksliai išskiriant gamybos proceso metu suformuotas struktūras, tam kad šių duomenų pagalba galima būtų atlikti gamybos proceso tikslumo patikrinimą. Šio disertacijos darbo tyrimų objektas yra puslaidininkinių integrinių schemų sluoksniuose suformuoti elementai. Kiekvieno iš skirtingų sluoksnių struktūros pasižymi skirtingomis savybėmis, todėl labai sunku sukurti universalius analizės metodus. Dėl šios priežasties buvo sukurta speciali programinės įrangos (PĮ) sistema. PĮ architektūra yra disertacijos tyrimų objektas. Pagrindiniai disertacijoje sprendžiami uždaviniai: IG elementų struktūrų atpažinimo metodų pritaikymas ir kūrimas, PĮ sistemos projektavimas ir įgyvendinimas, eksperimentinis įdiegtų metodų efektyvumo ir tikslumo tyrimas. Disertaciją sudaro įvadas, keturi skyriai ir rezultatų apibendrinimas. Įvade nagrinėjamas problemos aktualumas, formuluojamas darbo tikslas bei uždaviniai, aprašomas mokslinis darbo naujumas, pristatomi autoriaus pranešimai ir publikacijos, disertacijos struktūra. Pirmasis skyrius skirtas analitinei literatūros apžvalgai. Jame nagrinėjamos žinomos IG topologijos elementų atpažinimo sistemos ir jose naudojami metodai... [toliau žr. visą tekstą]

The modules for processing of interconnection specifications which are provided in an input file of circuit analyzer were developed. A software package for creation of appropriate computer models on the basis of topology and library of network components was also constructed and implemented using SPICE program. A computer program, called LSPICE, has been developed by combining SPICE numerical techniques and the modal analysis of coupled transmission lines. This program can be used for simulating the transient response of networks containing coupled lossless transmission lines. Several example networks have been simulated using this program. The results have been compared with those generated by the circuit simulator program called UANTL. The LSPICE has several advantages over UANTL and SPICE in simulating the transient response of network containing coupled lossless transmission lines. A description of LSPICE and a summary of the results of numerical experiments are included.

The thermoelectric dimensionless figure-of-merit, ZT, which consists of the Seebeck coefficient, , electrical resistivity,  and thermal conductivity, , is an important parameter that characterizes the energy conversion performance of thermoelectric materials and devices. Larger ZT indicates higher performance of thermoelectric device. Current techniques for determining ZT involve measurements of ,  and  individually or ZT directly, but all techniques are carried out under a small temperature difference (T). In reality, a thermoelectric device generally operates under a much larger T and with an electrical current flowing through the thermoelectric materials. Clearly, ZT values are conventionally evaluated under a condition which differs significantly from the real operating conditions of thermoelectric devices. Recently, a novel principle for ZT measurement has been proposed, which has the capability of measuring ZT values under a large T and with an electrical current flowing through the samples. The main objective of the research embodied in this thesis is to investigate experimentally the feasibility of the proposed technique and subsequently to develop a laboratory measurement system for thermoelectric materials research. The feasibility of the proposed technique was investigated initially using thermoelectric modules. The results show a reasonable agreement with conventional techniques when it is used to measure ZT under a small T. Furthermore, the investigation reveals that ZT obtained under a large T differ significantly from those obtained under a small T. This confirms the unique capability of the proposed technique. The implementation of this technique for measuring the ZT of thermoelectric materials has proved to be very challenging due to the low electrical resistance (< 0.01 ) of the material samples. Following an in-depth experimental and theoretical investigation, a new design with a modified operating principle was proposed and carried out. The measurement system based on this new design was successfully developed, which has the capability of measuring single materials with different dimensions and under a larger T. The performance of this system was investigated using a standard Bi2Te3 sample as the reference for calibration. The results show that the system has a repeatability of <10% and an accuracy of 13-32%. Investigation on single materials and segmented structures showed that there were noticeable differences between a small and a large T, which can be attributed to the Thomson effect and changes in  values. This finding contributes to an improved understanding and new knowledge of thermoelectric behaviour under a large temperature difference. The measurement technique developed in this work will provide a useful tool for investigation and for the optimization of advanced thermoelectric structures.

Personal computers and portable electronics continue to rapidly advance and integrate into our lives as tools that facilitate efficient communication and interaction with the outside world. Now with a multitude of different devices available, personal computers are accessible to a wider audience than ever before. To continue to expand and reach new users, novel user interface technologies have been developed, such as touch input and gyroscopic motion, in which enhanced control fidelity can be achieved. For users with limited-to-no use of their hands, or for those who seek additional means to intuitively use and command a computer, novel sensory systems can be employed that interpret the natural electric signals produced by the human body as command inputs. One of these novel sensor systems is the myoelectric detection circuit, which can measure electromyographic (EMG) signals produced by contracting muscles through specialized electrodes, and convert the signals into a usable form through an analog circuit. With the goal of making a general-purpose myoelectric detection circuit platform for computer interface applications, several electrical circuit designs were iterated using OrCAD software, manufactured using PCB fabrication techniques, and tested with electrical measurement equipment and in a computer simulation. The analog circuit design culminated in a 1.35” x 0.8” manufactured analog myoelectric detection circuit unit that successfully converts a measured EMG input signal from surface skin electrodes to a clean and usable 0-5 V DC output that seamlessly interfaces with an Arduino Leonardo microcontroller for further signal processing and logic operations. Multiple input channels were combined with a microcontroller to create an EMG interface device that was used to interface with a PC, where simulated mouse cursor movement was controlled through the voluntary EMG signals provided by a user. Functional testing of the interface device was performed, which showed a long battery life of 44.6 hours, and effectiveness in using a PC to type with an on-screen keyboard.

Ground Fault Circuit Interrupter (GFCI) technology was first introduced in the NEC in 1971, yet four decades later the technology has not been introduced to a great extent outside of the home environment. This thesis introduces the difficulties encountered in low-voltage three phase ground fault current detection, and adopts a previously patented tripping scheme to develop and prototype a digital relay for 3-phase 480 volt systems capable of the sensitivity and speed required for personnel safety. Results demonstrate the feasibility of the concept and suggest commercial development should be pursued. The prototype is capable of mA sensitivity and reliably detects and removes the faulted feeder from the system, without causing false tripping on non-faulted feeders. The prototype system has been tested and responds appropriately for faults over the 1 mA to 1000 A range.

[EN] Positron Emission Tomography (PET) is a non-invasive nuclear medical imaging modality that makes it possible to observe the distribution of metabolic substances within a patient's body after marking them with radioactive isotopes and arranging an annular scanner around him in order to detect their decays. The main applications of this technique are the detection and tracing of tumors in cancer patients and metabolic studies with small animals. The Electronic Design for Nuclear Applications (EDNA) research group within the Instituto de Instrumentación para Imagen Molecular (I3M) has been involved in the study of high performance PET systems and maintains a small experimental setup with two detector modules. This thesis is framed within the necessity of developing a new data acquisition system (DAQ) for the aforementioned setup that corrects the drawbacks of the existing one. The main objective is to define a DAQ architecture that is completely scalable, modular, and guarantees the mobility and the possibility of reusing its components, so that it admits any extension of modification of the setup and it is possible to export it directly to the configurations used by other groups or experiments. At the same time, this architecture should be compatible with the best possible resolutions attainable at the present instead of imposing artificial limits on system performance. In particular, the new DAQ system should outperform the previous one. As a first step, a general study of DAQ arquitectures is carried out in the context of experimental setups for PET and other high energy physics applications. On one hand, the conclusion is reached that the desired specifications require early digitization of detector signals, exclusively digital communication between modules, and the absence of a centralized trigger. On the other hand, the necessity of a very precise distributed synchronization scheme between modules becomes apparent, with errors in the order of 100 ps, and operating directly over the data links. A study of the existing methods reveals their severe limitations in terms of achievable precision. A theoretical analysis of the situation is carried out with the goal of overcoming them, and a new synchronization algorithm is proposed that is able to reach the desired resolution while getting rid of the restrictions on clock alignment that are imposed by virtually all usual schemes. Since the measurement of clock phase difference plays a crucial role in the proposed algorithm, extensions to the existing methods are defined and analyzed that improve them significantly. The proposed scheme for synchronism is validated using commercial evaluation boards. Taking the proposed synchronization method as a starting point, a DAQ architecture for PET is defined that is composed of two types of module (acquisition and concentration) whose replication makes it possible to arrange a hierarchic system of arbitrary size, and circuit boards are designed and commissioned that implement a realization of the architecture for the particular case of two detectors. This DAQ is finally installed at the experimental setup, where their synchronization properties and resolution as a PET system are characterized and its performance is verified to have improved with respect to the previous system.
[ES] La Tomografía por Emisión de Positrones (PET) es una modalidad de imagen médica nuclear no invasiva que permite observar la distribución de sustancias metabólicas en el interior del cuerpo de un paciente tras marcarlas con isótopos radioactivos y disponer después un escáner anular a su alrededor para detectar su desintegración. Las principales aplicaciones de esta técnica son la detección y seguimiento de tumores en pacientes con cáncer y los estudios metabólicos en animales pequeños. El grupo de investigación Electronic Design for Nuclear Applications (EDNA) del Instituto de Instrumentación para Imagen Molecular (I3M) ha estado involucrado en el estudio de sistemas PET de alto rendimiento y mantiene un pequeño setup experimental con dos módulos detectores. La presente tesis se enmarca dentro de la necesidad de desarrollar un nuevo sistema de adquisición de datos (DAQ) para dicho setup que corrija los inconvenientes del ya existente. En particular, el objetivo es definir una arquitectura de DAQ que sea totalmente escalable, modular, y que asegure la movilidad y la posibilidad de reutilización de sus componentes, de manera que admita cualquier ampliación o alteración del setup y pueda exportarse directamente a los de otros grupos o experimentos. Al mismo tiempo, se desea que dicha arquitectura no limite artificialmente el rendimiento del sistema sino que sea compatible con las mejores resoluciones disponibles en la actualidad, y en particular que sus prestaciones superen a las del DAQ instalado previamente. En primer lugar, se lleva a cabo un estudio general de las arquitecturas de DAQ para setups experimentales para PET y otras aplicaciones de física de altas energías. Por un lado, se determina que las características deseadas implican la digitalización temprana de las señales del detector, la comunicación exclusivamente digital entre módulos, y la ausencia de trigger centralizado. Por otro lado, se hace patente la necesidad de un esquema de sincronización distribuida muy preciso entre módulos, con errores del orden de 100 ps, que opere directamente sobre los enlaces de datos. Un estudio de los métodos ya existentes revela sus graves limitaciones a la hora de alcanzar esas precisiones. Con el fin de paliarlos, se lleva a cabo un análisis teórico de la situación y se propone un nuevo algoritmo de sincronización que es capaz de alcanzar la resolución deseada y elimina las restricciones de alineamiento de reloj impuestas por casi todos los esquemas usuales. Dado que la medida de desfase entre relojes juega un papel crucial en el algoritmo propuesto, se definen y analizan extensiones a los métodos ya existentes que suponen una mejora sustancial. El esquema de sincronismo propuesto se valida utilizando placas de evaluación comerciales. Partiendo del método de sincronismo propuesto, se define una arquitectura de DAQ para PET compuesta de dos tipos de módulos (adquisición y concentración) cuya replicación permite construir un sistema jerárquico de tamaño arbitrario, y se diseñan e implementan placas de circuito basadas en dicha arquitectura para el caso particular de dos detectores. El DAQ así construído se instala finalmente en el setup experimental, donde se caracterizan tanto sus propiedades de sincronización como su resolución como sistema PET y se comprueba que sus prestaciones son superiores a las del sistema previo.
[CAT] La Tomografia per Emissió de Positrons (PET) és una modalitat d'imatge mèdica nuclear no invasiva que permet observar la distribució de substàncies metabòliques a l'interior del cos d'un pacient després d'haver-les marcat amb isòtops radioactius disposant un escàner anular al seu voltant per a detectar la seua desintegració. Aquesta tècnica troba les seues principals aplicacions a la detecció i seguiment de tumors a pacients amb càncer i als estudis metabòlics en animals petits. El grup d'investigació Electronic Design for Nuclear Applications (EDNA) de l'Instituto de Instrumentación para Imagen Molecular (I3M) ha estat involucrat en l'estudi de sistemes PET d'alt rendiment i manté un petit setup experimental amb dos mòduls detectors. Aquesta tesi neix de la necessitat de desenvolupar un nou sistema d'adquisició de dades (DAQ) per al setup esmentat que corregisca els inconvenients de l'anterior. En particular, l'objectiu és definir una arquitectura de DAQ que sigui totalment escalable, modular, i que asseguri la mobilitat i la possibilitat de reutilització dels seus components, de tal manera que admeta qualsevol ampliació o alteració del setup i pugui exportar-se directament a aquells d'altres grups o experiments. Al mateix temps, es desitja que aquesta arquitectura no introduisca límits artificials al rendiment del sistema sinó que sigui compatible amb les millors resolucions disponibles a l'actualitat, i en particular que les seues prestacions siguin superiors a les del DAQ instal.lat amb anterioritat. En primer lloc, es porta a terme un estudi general de les arquitectures de DAQ per a setups experimentals per a PET i altres aplicacions de física d'altes energies. Per una banda, s'arriba a la conclusió que les característiques desitjades impliquen la digitalització dels senyals del detector el més aviat possible, la comunicació exclusivament digital entre mòduls, i l'absència de trigger centralitzat. D'altra banda, es fa palesa la necessitat d'un mecanisme de sincronització distribuïda molt precís entre mòduls, amb errors de l'ordre de 100 ps, que treballi directament sobre els enllaços de dades. Un estudi dels mètodes ja existents revela les seues greus limitacions a l'hora d'assolir aquest nivell de precisió. Amb l'objectiu de pal.liar-les, es duu a terme una anàlisi teòrica de la situació i es proposa un nou algoritme de sincronització que és capaç d'obtindre la resolució desitjada i es desfà de les restriccions d'alineament de rellotges imposades per gairebé tots els esquemes usuals. Atès que la mesura del desfasament entre rellotges juga un paper cabdal a l'algoritme proposat, es defineixen i analitzen extensions als mètodes ja existents que suposen una millora substancial. L'esquema de sincronisme proposat es valida mitjançant plaques d'avaluació comercials. Prenent el mètode proposat com a punt de partida, es defineix una arquitectura de DAQ per a PET composta de dos tipus de mòduls (d'adquisició i de concentració) tals que la replicació d'aquests elements permet construir un sistema jeràrquic de mida arbitrària, i es dissenyen i implementen plaques de circuit basades en aquesta arquitectura per al cas particular de dos detectors. L'electrònica desenvolupada s'instal.la finalment al setup experimental, on es caracteritzen tant les seues propietats de sincronització com la seua resolució com a sistema PET i es comprova que les seues prestacions són superiors a les del sistema previ.
Aliaga Varea, RJ. (2016). Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/63271
TESIS
Premiado

The aim of this thesis is to present a solution for the readout of Silicon Photo-Multipliers (SiPMs) arrays improving currently implemented systems. Using as a starting point previous designs with similar objectives a novel current mode input stage has been designed and tested. To start with the design a valid model has been used to generate realistic output from the SiPMs depending on light input. Design has been performed in first place focusing in general applications for medical imaging Positron Emission Tomography (PET) and then using the same topology for a more constrained design in particle detectors (upgrade of Tracker detector at LHCb experiment). A 16 channel ASIC for PET applications including the novel input stage has demonstrated an excellent timing measurement with good energy resolution measurement and pile-up detection. This document starts with the analysis of the requirements needed to fit such a system, followed by a detailed description of the input stage and analog processing. Signal is divided in the input stage into three different signal paths: timing, energy and pileup. Every channel performs different signal analysis to deliver; a fast time signal output (digital edge), energy output (a linear time over threshold digital output) and a digital bit to signal pile-up. The time information is then ORed between all channels to generate a single timing output. All the pile-up bits are combined in a digital word ready to be readout for the 16 channels. Design has been optimized for reduced power consumption and no components needed to interface inputs and outputs. Digital slow control to tune the circuit behaviour is also included. The prototype measurements have proved to be a valid option for integration in a full system scanner. An adapted prototype of the input stage using different technology and adapted to the different constraints from a particle detector is also presented. Only simulation results are available since device is still under production. An analysis of the different requirements needed by the SciFi tracker design is summarized. Current specifications are still evolving since final sensor is still not defined, but other requirements and some tunable elements permits to design such prototypes.
L’objectiu d’aquesta tesi és presentar una solució per a la lectura de matrius de fotomultiplicadors de silici (SiPM) millorant les característiques de sistemes actuals. Amb aquesta finalitat s’ha dissenyat i provat el circuit d’una nova etapa d’entrada. En primer lloc s’ha dissenyat pensant en aplicacions genèriques i per a imatge mèdica, concretament per a escàners PET (Positron Emission Tomography). Però més endavant s’aplica la mateixa topologia per a una aplicació més concreta i específica com és un detector de partícules (l’actualització del Tracker a l’experiment LHCb). Els SiPM són uns dispositius electrònics relativament nous amb la possibilitat de comptar fotons i millorant algunes característiques dels sensors actuals, com serien la tensió d’operació més baixa, més guany o immunitat a camps magn`etics, mentre manté unes prestacions excel•lents respecte el guany, resolució temporal i rang dinàmic. Aquest tipus de dispositius es troben en constant evolució encara i una gran varietat de fabricants intenten millorar les prestacions, sobretot respecte la eficiència en la detecció de llum, reduir el corrent d’obscuritat, construir matrius més grans i augmentar l’espectre al qual són sensibles. En aquest document es presenta el disseny d’un circuit integrat específic amb les següents característiques: gran rang dinàmic, alta velocitat, multicanal, amb entrada en corrent i baixa impedància d’entrada, baix consum, control de la tensió de polarització del SiPM i amb les sortides de; temps, càrrega i apilament.

Les circuits intégrés (CI) devenant de plus en plus complexes et vulnérables face aux décharges électrostatiques (ESD pour ElectroStatic Discharge), la capacité à vérifier de manière fiable la présence de défauts de conception ESD sur des puces comptant plusieurs milliards de transistors avant tout envoi en fabrication est devenu un enjeu majeur dans l’industrie des semi-conducteurs. Des outils commerciaux automatisés de dessin électronique (EDA pour Electronic Design Automation) et leur flot de vérification associé permettent d’effectuer différents types de contrôles qui se sont révélés être efficaces pour des circuits avec une architecture classique. Cependant, ils souffrent de limitations lorsqu’ils sont confrontés à des architectures inhabituelles, dites custom. De plus, ces méthodes de vérification sont généralement effectuées tard dans le flot de conception, rendant toute rectification de dessin coûteuse en termes d’efforts correctifs et de temps. Cette thèse de doctorat propose une méthodologie de vérification ESD systématique et multi-échelle introduite dans un outil appelé ESD IP Explorer qui a été spécifiquement implémenté pour couvrir le flot de conception dans sa globalité et pour adresser des circuits dits custom. Il est composé d’un module de reconnaissance et d’un module de vérification. Le module de reconnaissance identifie tout d’abord et de manière automatisée les structures de protection ESD, embarquées sur silicium dans le circuit intégré pour améliorer leur robustesse ESD, selon un mécanisme de reconnaissance topologique. Le module de vérification convertit ensuite le réseau de protection ESD, formé des structures de protection ESD, en un graphe dirigé. Finalement, une analyse ESD quasi-statique reposant sur des algorithmes génériques issus de la théorie des graphes est effectuée sur la globalité du circuit à vérifier. Des algorithmes d’apprentissage automatique ont été employés pour prédire les comportements quasi-statiques des protections ESD à partir des paramètres d’instance de leurs composants élémentaires sous la forme d’une liste d’interconnexions. L’avantage ici est qu’aucune simulation électrique n’est requise pendant toute la durée d’exécution d’ESD IP Explorer, ce qui simplifie l’architecture de l’outil et accélère l’analyse. Les efforts d’implémentation ont été concentrés sur la compatibilité d’ESD IP Explorer avec le nœud technologique 28nm FD-SOI (pour Fully Depleted Silicon On Insulator). L’outil de vérification développé a été utilisé avec succès pour l’analyse d’un circuit incorporant des parties numériques et à signaux mixtes et comprenant plus de 1,5 milliard de transistors en seulement quelques heures. Des circuits custom qui n’ont pas pu être vérifiés au moyen d’outils de vérification traditionnels du fait de problèmes d’incompatibilité ont également pu être soumis à analyse grâce à ESD IP Explorer
As Integrated Circuits (ICs) become more complex and susceptible to ElectroStatic Discharges (ESD), the ability to reliably verify the presence of ESD design weaknesses over a multi-billion transistor chip prior to the tape-out is a major topic in the semiconductor industry. Commercial tools dedicated to Electronic Design Automation (EDA) and related verification flows are in charge of providing checks that have been proven to be efficient for circuits with a mainstream architecture. However, they suffer limitations when confronted with custom designs. Moreover, these verification methods are often run late in the design flow, making any design re-spin costly in terms of corrective efforts and time. This Ph. D. thesis proposes a systematic and scalable ESD verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. It is composed of a recognition module and a verification module. The recognition module first automatically identifies ESD protection structures, embedded in integrated circuits to enhance their ESD hardness, according to a topology-aware recognition mechanism. The verification module then converts the ESD protection network that is formed by ESD protection structures into a directed graph. There, technology-independent and graph-based verification mechanisms perform a chip-scale quasistatic ESD analysis. Machine learning algorithms have been used in order to infer the quasistatic behavior of ESD IPs from the netlist instance parameters of their primary devices. This approach has the advantage that no simulation is required during the execution of ESD IP Explorer, which makes the tool architecture simpler and improves execution times. Implementation efforts pertained to the compliance of ESD IP Explorer with the 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The developed verification tool has been used to successfully analyze a digital and mixed-signal circuit prototype counting more than 1.5 billion transistors in several hours, as well as custom designs that could not be analyzed by means of traditional verification tools due to incompatibility issues

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008.
Includes bibliographical references.

Les nouveaux composants à semi-conducteur de type grand gap ont été développés pour des applications de conversion de puissance en raison de leurs hautes fréquences de commutation (de centaine kHz à quelques MHz) et pertes faibles. Afin de bien profiter ses avantages, la technologie des circuits imprimés (PCB) est intéressante pour une intégration à haute densité de puissance grâce à sa flexibilité et son faible coût. Cependant, à cause de la mauvaise conductivité thermique du matériau FR-4 utilisé pour le substrat PCB et la haute densité de puissance réalisée, il est primordial de trouver des solutions thermiques pour améliorer les performances thermiques de la structure de PCB. Dans cette thèse, trois solutions thermiques pour les structures de PCB ont été proposées, y compris des solutions avec des vias thermiques, de cuivre épais sur le substrat de PCB ainsi que des dispositifs de refroidissement thermoélectrique (TEC). Nos études sont basées sur la modélisation électrothermique et la méthode d’éléments finis en 3D. Tout d’abord, l’optimisation des paramètres des vias (diamètre, épaisseur de placage, surface formée par des vias, la distance entre des vias etc.) a été réalisée pour optimiser l’effet de refroidissement. Ensuite, on constate que les performances thermiques des structures de PCB peuvent être améliorées en utilisant cuivre épais sur le substrat de PCB. Cuivre épais augmente le flux thermique latéral dans la couche de cuivre. Les influences de l’épaisseur de cuivre (35 à 500 µm) ont été étudiées. Cette solution est facile à réaliser et peut être combinée à d’autres solutions de refroidissement. Enfin, le dispositif thermoélectrique comme les modules Peltier est une technologie de refroidissement local. Les influences des paramètres de Peltier (Propriétés du matériau thermoélectrique, nombre d’éléments Peltier, distance entre la source de chaleur et les dispositifs Peltier, etc.) ont été identifiées. Il est démontré que des modules Peltier ont l’application potentielle pour le développement d’intégration de PCB attendu que son active contrôle des températures
The emerging wide bandgap (WBG) semiconductor devices have been developed for power conversion applications instead of silicon devices due to higher switching frequencies (from few 100 kHz to several MHz) and lower on-state losses resulting in a better efficiency. In order to take full advantage of the WBG components, PCB technology is attractive for high power density integration thanks to its flexibility and low cost. However, due to poor thermal conductivity of the commonly used material Flame Retardant-4 (FR4), efficient thermal solutions are becoming a challenging issue in integrated power boards based on PCB substrates. So it is of the first importance to seek technological means in order to improve the thermal performances. In this thesis, three main thermal management solutions for PCB structures have been investigated including thermal vias, thick copper thickness on the PCB substrate as well as thermoelectric cooling (TEC) devices. Our studies are based on the electro-thermal modeling and 3D finite element (FE) methods. Firstly, optimization of the thermal via parameters (via diameter, via plating thickness, via-cluster surface, via pattern, pitch distance between vias etc.) has been realized to improve their cooing performances. We presented and evaluated thermal performances of the PCB structures by analyzing the thermal resistance of the PCB substrate with different thermal vias. Secondly, it is found that thermal performances of the PCB structures can be enhanced by using thick copper thickness on top of the PCB substrate, which increases the lateral heat flux along the copper layer. Influences of the copper thickness (35 µm to 500 µm) has been discussed. This solution is easy to realize and can be combined with other cooling solutions. Thirdly, thermoelectric cooler like Peltier device is a solid-state cooling technology that can meet the local cooling requirements. Influences of Peltier parameters (Thermoelectric material properties, number of Peltier elements, distance between the heating source and the Peltier devices etc.) have been identified. All these analyses demonstrate the potential application of Peltier devices placed beside the heating source for PCB structures, which is a benefit for developing the embedding technology in such structures

The Cold-Electron Bolometer (CEB) is a sensitive detector of millimeter-wave radiation, in which tunnel junctions are used as temperature sensors of a nanoscale normal metal strip absorber. The absorber is fed by an antenna via two Superconductor-Insulator-Normal metal (SIN) tunnel junctions, fabricated at both ends of the absorber. Incoming photons excite electrons, heating the whole electron system. The incoming RF power is determined by measuring the tunneling current through the SIN junctions. Since electrons at highest energy levels escape the absorber through the tunnel junctions, it causes cooling of the absorber. This electron cooling provides electro-thermal feedback that makes the saturation power of a CEB well above that of other types of millimeter-wave receivers. The key features of CEB detectors are high sensitivity, large dynamic range, fast response, easy integration in arrays on planar substrates, and simple readout. The high dynamic range allows the detector to operate under relatively high background levels. In this thesis, we present the development and successful operation of CEB, focusing on the fabrication technology and different implementations of the CEB for efficient detection of electromagnetic signals. We present the CEB detector integrated across a unilateral finline deposited on a planar substrate. We have measured the finline-integrated CEB performance at 280-315 mK using a calibrated black-body source mounted inside the cryostat. The results have demonstrated strong response to the incoming RF power and reasonable sensitivity. We also present CEB devices fabricated with advanced technologies and integrated in log-periodic, double-dipole and cross-slot antennas. The measured CEB performance satisfied the requirements of the balloon-borne experiment BOOMERANG and could be considered for future balloon-borne and ground-based instruments. In this thesis we also investigated a planar phase switch integrated in a back-to-back finline for modulating the polarization of weak electromagnetic signals. We examine the switching characteristics and demonstrate that the switching speed of the device is well above the speed required for phase modulation in astronomical instruments. We also investigated the combination of a detector and a superconducting phase switch for modulating the polarization of electromagnetic radiation.

碩士
國立臺北科技大學
材料科學與工程研究所
107
In the experiment, screen printing with specially blended silver glues is adopted to develop stretchable electronic circuits for wearable device application. The silver paste is screen printed on an elastic TPU carrier film of 20um thickness. It can sustain 20% stretched deformation and still have degraded electronic conductivities which show recovery behaviors after removing external loading. The stretchable silver glue was used with conditions of “three heat treatment recipes”, “three line widths” and “four geometric designs” to investigate electronic resistance variation phenomena under “repetitive 20% stretched deformation by 10,000 times” and “static 10~30% stretched deformation”, respectively. Experimental results show that electronic conductivity recovery speed is faster by widening line width. To prevent printing open lines due to the screen clogging caused from wider coagulation size distribution ranges of this specially synthesized silver paste, line width is suggested to be larger than 300um. Polymer materials have the minimum variation for resistance per unit length under heat treatment of 100°C /30mins. By combining Z-shape line designs, it can get benefits of “fastest electronic conductivity recovery” and “minimum variation for resistance per unit length.”

Ching Ngai-hung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves 81-83).
Abstracts in English and Chinese.
Chapter CHAPTER 1 ´ؤ --- INTRODUCTION --- p.1
Chapter 1.1 --- Background on Micro Power Supply --- p.1
Chapter 1.2 --- Literature Survey --- p.3
Chapter 1.2.1 --- Comparison Among Different Power Sources & Transduction Mechanisms --- p.3
Chapter 1.2.2 --- Previous Works in Vibration Based Generator --- p.6
Chapter CHAPTER 2 一 --- DESIGN OF THE MICRO-POWER GENERATOR --- p.8
Chapter 2.1 --- Concept of Power Generation --- p.8
Chapter 2.2 --- Design Objectives of the Micro Power Generation --- p.9
Chapter 2.3 --- System Modelling and Configuration of the Generator --- p.10
Chapter 2.4 --- RESONATING STRUCTURE --- p.13
Chapter 2.4.1 --- Material Selection --- p.13
Chapter 2.4.2 --- Fabrication Method --- p.14
Chapter CHAPTER 3 一 --- INDUCTING STRUCTURE --- p.17
Chapter 3.1 --- Selection of Winding Method --- p.17
Chapter 3.2 --- Solenoid Windings --- p.19
Chapter 3.2.1 --- Fabrication Process --- p.19
Chapter 3.3 --- PCB Windings --- p.20
Chapter 3.3.1 --- Fabrication Process of the Prototype of Six-layer PCB --- p.21
Chapter CHAPTER 4 一 --- EXPERIMENTAL RESULTS --- p.27
Chapter 4.1 --- Experimental Setup --- p.27
Chapter 4.1.1 --- Generator Systems --- p.27
Chapter 4.1.2 --- Measurement of Vibration and Output from the Generator --- p.28
Chapter 4.1.3 --- Observations of Vibration Motions --- p.31
Chapter 4.2 --- SPRING FOR THE MICRO GENERATOR --- p.32
Chapter 4.2.1 --- Spring Micromachining Optimization --- p.32
Chapter 4.2.2 --- Mode Shapes and Spiral-spring Structures --- p.35
Chapter 4.3 --- MAGNET FOR THE MICRO GENEARTOR --- p.37
Chapter 4.3.1 --- Generator Output and Magnetic Dipole Orientation --- p.37
Chapter 4.4 --- HAND-WIRED COIL GENEARTOR --- p.45
Chapter 4.4.1 --- Performance of Different Design of Housings --- p.45
Chapter 4.5 --- PCB COIL GENERATOR --- p.48
Chapter 4.5.1 --- Size of PCB Coils vs. Generator Output --- p.48
Chapter 4.5.2 --- Effect of Number of PCB Layers --- p.54
Chapter 4.5.3 --- Array of Generators --- p.61
Chapter CHAPTER 5 一 --- MODELLING AND COMPUTER SIMULATION --- p.63
Chapter 5.1 --- Modelling the Second-Order System --- p.63
Chapter CHAPTER 6 一 --- APPLICATION DEMONSTRATIONS --- p.69
Chapter 6.1 --- INFRARED SIGNAL TRANSMISSION --- p.69
Chapter 6.2 --- RF WIRELESS TEMPERATURE SENSING SYSTEM --- p.70
Chapter CHAPTER 7 ´ؤ --- CONCLUSION --- p.75
Chapter CHAPTER 8 一 --- FUTURE WORK --- p.77
BIBLIOGRAPHY --- p.81
APPENDIX --- p.84

碩士
臺灣大學
工程科學及海洋工程學研究所
95
In this thesis, a processing platform based on inkjet printing technology was developed to facilitate the possibility of producing flexbile electronic devices. in academia and industry of Taiwan. To serve as a prototyupe for the complete in-line manufacturing system and fabricating procedures, this processing platform integrates optomechatronic systems include machine vision, liquid/gas pressure control, flexible programming environment, inkjet printing heads, ink preparation, moving platform, and thermal processing equipments, etc. The success in fabricating electronic components and circuits such as resistor, capacitors, thin film transistors, and inverters by producing printed pattern of different functional layers with different materials on flexible substrates proved the potential of using this newly developed inkjet printing system to serve as a manufacturing system. The silver mirror process was developed to create the electric connection between components, which led to very high conductivity electric connections in the circuit created. The improvement in on/off ratio and mobility of flexible thin film transistor with all organic materials and polymeric semiconductor P3HT were attribed to better humidity control, well controlled air particles, and a novel packaging process developed. The final data obtained verified the internationally competitive performance including 104 on/off ratio and 10-1 mobility of printed P3HT OTFT measured at the ambient environments.

I sistemi di imaging ad ultrasuoni (US), sebbene siano stati oggetto di intense indagini da parte di molti gruppi di ricerca in tutto il mondo, non hanno ancora raggiunto la piena maturità. Le sonde ad ultrasuoni, in particolare, hanno ampi margini di miglioramento, non solo in termini di materiali e configurazione degli elementi, ma anche di modalità di eccitazione. Il mio lavoro di dottorato è stato impegnato nello sviluppo di circuiti elettronici e metodi per l'imaging ad ultrasuoni basati su sonde innovative. In primo luogo, ho sviluppato i circuiti elettronici necessari per rendere compatibile un sistema di ricerca a ultrasuoni per scopi di ricerca (ULA-OP 256) con le sonde CMUT. La tecnologia CMUT è sempre più utilizzata perché offre ampia banda, elevata sensibilità e grande flessibilità nella progettazione della geometria degli elementi ma, a differenza della tecnologia piezoelettrica, necessita di alte tensioni di polarizzazione (dell’ordine delle centinaia di Volt). Poiché ULA-OP 256 è stato originariamente progettato per funzionare solo con sonde piezoelettriche, ho contribuito allo sviluppo di circuiti in grado di adattare questo scanner aperto per lavorare anche con sonde CMUT. Inoltre, in collaborazione con ST Microelectronics, ho sviluppato una scheda elettronica che permette di testare un nuovo amplificatore di potenza a nove livelli per la trasmissione di segnali sia alle sonde piezoelettriche che alle sonde CMUT. La seconda parte del mio lavoro è stata dedicata allo studio del possibile utilizzo di sonde ad array "sparse" per ecografie 3D Doppler e ad alto frame rate. Le sonde sparse sono array 2D in cui un numero limitato di elementi, paragonabile al numero di canali presenti nella maggior parte degli scanner ad ultrasuoni, è distribuito secondo specifiche geometrie, progettate per ottimizzare il fascio acustico in trasmissione e ricezione. CMUT è la tecnologia ideale per l'implementazione di sonde sparse array, in quanto garantisce la massima flessibilità nella distribuzione degli elementi in posizioni arbitrarie. Il mio lavoro con gli Sparse Array ha incluso prima di tutto lo studio di possibili limitazioni legate al loro utilizzo quando sono usati per trasmettere onde divergenti (DWs). Si tratta di onde non focalizzate che permettono di aumentare notevolmente il frame rate nell'imaging volumetrico (3D). In questa attività, ho fatto simulazioni ed esperimenti nel laboratorio CREATIS (Lione) per confrontare le prestazioni ottenibili in termini di contrasto e risoluzione quando si utilizzano diverse configurazioni di DW e di elementi sparsi. Infine, una parte consistente del mio dottorato di ricerca è stata focalizzata sulla valutazione dell'uso di array sparse in applicazioni Doppler spettrali. L'intenzione di questo studio era di valutare in che misura la dispersione degli elementi sulla superficie della sonda può influenzare le prestazioni del Doppler spettrale. Per raggiungere questo obiettivo, l'uso di un array 2D a 1024 elementi a griglia completa è stato confrontato con l'uso di array sparse ottenuti selezionando opportunamente 256 elementi sulla stessa matrice completa. Gli esperimenti sono stati sviluppati sia su un disco di agar rotante (dove sono raggiungibili alti SNR) che su un phantom di flusso (per testare una condizione più realistica) al CREATIS. I risultati di questo lavoro confermano quantitativamente l'idoneità degli array sparse per misure di velocità Doppler spettrali, a condizione che la perdita di rapporto segnale/rumore dovuto all'utilizzo di meno elementi attivi sia adeguatamente compensata. Ultrasound (US) imaging systems, although intensively investigated by many research groups worldwide, have not achieved full maturity yet. US probes, in particular, have wide margins of improvement, not only in terms of materials and elements configuration but also of excitation modalities. This PhD work has been committed to the development of electronic circuits and methods for US imaging based on innovative ultrasound probes. First, I’ve developed the electronic circuits necessary to make an open ultrasound research system (ULA-OP 256) compatible with CMUT probes. CMUT technology is increasingly used because it offers wide band, high sensitivity and great flexibility in the design of elements geometry but, differently from the piezoelectric technology, needs high polarization and peak-to-peak voltages (hundreds of Volt). Since ULA-OP 256 was originally designed to work only with piezoelectric probes, I contributed to the development of circuits capable of adapting this open scanner to work also with CMUT array probes. Furthermore, within a collaboration with ST Microelectronics, I’ve developed an electronic board that allows to test a new 9-level power amplifier for the transmission of signals to both piezoelectric and CMUT probes. The second part of my work has been dedicated to the investigation of possible use of “sparse” array probes for 3D high-frame rate and Doppler imaging. Sparse probes are 2D arrays in which a limited number of elements, comparable to the number of channels present in most US scanners, is distributed according to specific geometries, designed to optimize the transmit/receive acoustic beam. CMUT is the ideal technology for implementing sparse array probes, since it guarantees maximum flexibility in distributing the elements into arbitrary positions. My work with sparse arrays has first included the investigation of possible limitations related to their use when they are committed to transmit Diverging Waves (DWs). These are unfocused waves that may notably increase the frame rate in volumetric (3D) imaging. In this activity, I’ve done simulations and experiments at CREATIS (Lyon) to compare the achievable performance in terms of contrast and resolution when different DWs and sparse elements configurations are used. Finally, a consistent part of my PhD has been focused on the evaluation of the use of sparse arrays in spectral Doppler applications. The intention of this study was to evaluate at which extent the sparsification of probe elements may affect the spectral Doppler performance. To achieve this goal, the use of a full-gridded 1024-element 2D array was compared with the use of a sparse arrays obtained by properly selecting 256 elements out of the same full array. The experiments were developed on both a rotating agar disc (where high SNR are achievable) and on a flow phantom (to test a more realistic condition) at CREATIS. The results of this work quantitatively confirm the suitability of sparse arrays for spectral Doppler velocity measurements, provided the poor signal-to-noise ratio due to the use of few active elements is properly compensated.

Ultrasound imaging techniques have become increasingly successful in the medical field as they provide relatively low cost and totally safe diagnosis. Doppler methods focus on blood flow for the diagnosis and follow-up of cardiovascular diseases. First Doppler methods only measured the axial component of the motion. More recently, advanced methods have solved this problem, by estimating two or even all three velocity components. In this context, high frame rate (HFR) imaging techniques, based on the transmission of plane waves (PW), lead to the reconstruction of 2-D and 3-D vector maps of blood velocity distribution. The aim of this Ph.D. project was to develop novel acquisition schemes and processing methods for advanced ultrasound Doppler systems. Each development step was based on simulations and experimental tests. Simulations were based on Field II©, while experiments were conducted by using the ULA OP 256 open scanner. In particular, the recently proposed 2-D HFR vector flow imaging (VFI) method (DOI: 10.1109/TUFFC.2014.3064), based on the frequency domain for displacement estimation, was thoroughly investigated. Three main issues were addressed: the high underestimation of blood flow velocity observed when examining vessels at great depths, the high computational load, which hindered any real-time implementation and the lack of information about the third velocity component. Specifically, the progressive broadening of the transmitted beam on the elevation plane due to the acoustic lens was demonstrated to be responsible for the underestimation. The computational cost was reduced by processing demodulated and down-sampled baseband data instead of radiofrequency data, and a preliminary real time version of the 2-D VFI method was implemented. It was also found that a more efficient implementation could be obtained by exploiting parallel computing and graphic processing units (GPUs). An expansion circuit board for the ULA-OP 256 hardware, which allocates GPU resources, was thus designed and built. This new system architecture may allow the implementation of even more complex algorithms, such as the 3-D VFI methods. In particular, it will be possible to implement the novel method for 3D VFI that was developed and tested during this Ph.D. project. Such method suitably extended the 2D VFI approach by proposing an efficient estimation strategy that considerably limits the overall computational load.

Process design for integrated circuit manufacturing has traditionally been implemented with little simulation prior to fabrication. As with circuit design of a decade ago, the available simulation tools were mainframe-based, often incompatible, and lacked accurate physical models. Recent developments in process and device simulation allow accurate process modeling which reflect actual fabrication plant capabilities. A highly structured simulation environment implemented for development of Texas Instruments' PRISM$\rm\sp{TM}$ technology is described, together with results of a simulation approach to circuit model development for a new class of silicon power transistors. A new analytical model for field effect transistor modeling is also proposed. This new model preserves continuity of both the drain current and conductance over all bias conditions. It also accurately models the effects of substrate bias on device behavior.

Indiana University-Purdue University Indianapolis (IUPUI)
This paper presents a novel approach of particulate material (soot) measurement in a Diesel particulate filter using Electrical Capacitance Tomography. Modern Diesel Engines are equipped with Diesel Particulate Filters (DPF), as well as on-board technologies to evaluate the status of DPF because complete knowledge of DPF soot loading is very critical for robust efficient operation of the engine exhaust after treatment system. Emission regulations imposed upon all internal combustion engines including Diesel engines on gaseous as well as particulates (soot) emissions by Environment Regulatory Agencies. In course of time, soot will be deposited inside the DPFs which tend to clog the filter and hence generate a back pressure in the exhaust system, negatively impacting the fuel efficiency. To remove the soot build-up, regeneration of the DPF must be done as an engine exhaust after treatment process at pre-determined time intervals. Passive regeneration use exhaust heat and catalyst to burn the deposited soot but active regeneration use external energy in such as injection of diesel into an upstream DOC to burn the soot. Since the regeneration process consume fuel, a robust and efficient operation based on accurate knowledge of the particulate matter deposit (or soot load)becomes essential in order to keep the fuel consumption at a minimum. In this paper, we propose a sensing method for a DPF that can accurately measure in-situ soot load using Electrical Capacitance Tomography (ECT). Simulation results show that the proposed method offers an effective way to accurately estimate the soot load in DPF. The proposed method is expected to have a profound impact in improving overall PM filtering efficiency (and thereby fuel efficiency), and durability of a Diesel Particulate Filter (DPF) through appropriate closed loop regeneration operation.

Modelling an electric arc within a circuit breaker, sending it to an IED and outputting it to a COMTRADE file. With the COMTRADE, develop an algorithm to create the Health Index of the circuit breaker. This allows to evaluate the condition of various circuit breakers based on COMTRADE files.

Modelling an electric arc within a circuit breaker, sending it to an IED and outputting it to a COMTRADE file. With the COMTRADE, develop an algorithm to create the Health Index of the circuit breaker. This allows to evaluate the condition of various circuit breakers based on COMTRADE files.

Glaucoma is the leading cause of irreversible blindness worldwide. While current therapies aim to lower elevated intraocular pressure (IOP) to prevent blindness, they often do not provide the desired long-term efficacy, can fail over time, and have systemic side effects. Electroceutical stimulation can be a solution to many of these current issues with glaucoma treatment, as it is believed to have fewer systemic side effects and quicker response times. The goal of this work is to develop and demonstrate a novel system using electrical stimulation to lower intraocular pressure. I present data from a human clinical study and an ongoing clinical trial of the IOPTx™ system, a wearable electroceutical for treating glaucoma, that provides preliminary evidence of efficacy and safety. Furthermore, no current glaucoma treatments allow for closed-loop, continuous monitoring of IOP, requiring more frequent doctor visits or forcing patients and clinicians to operate in the dark. Using an electroceutical therapeutic device with closed-loop feedback and continuous IOP recording can improve glaucoma management. I combined a pressure sensor with this electroceutical therapy, implanted the sensor and stimulation coils in rabbits, and stimulated the eyes. However, to better understand the optimal stimulation parameters, long-term effects, and mechanisms of action, an integrated circuit is designed as part of a fully implantable, closed-loop device. The chip was fabricated in 0.18 µm CMOS process and validated on the benchtop and in vivo. In the future, this electroceutical device has the potential to be a novel treatment for patients suffering from glaucoma.

Low reflow temperature solder interconnect technology based on Sn-Bi alloys is currently being considered as an alternative for Sn-Ag-Cu solder alloys to form solder interconnects at significantly lower melting temperatures than required for Sn-Ag-Cu alloys.

A new low temperature interconnect technology based on Sn-Bi alloys is being considered for attaching Sn-Ag-Cu (SAC) solder BGAs to circuit boards at temperatures significantly lower than for homogeneous SAC joints. Microstructure development studies of reflow and annealing, including Bi diffusion and precipitation, are important in understanding mechanical reliability and failures paths in the resulting heterogeneous joints. Experiments in several SAC-SnBi geometries revealed that Bi concentration profiles deviate from local equilibrium expected from the phase diagram, with much higher local concentrations and lower volume fractions of liquid than expected during short-time high temperature anneals in the two-phase region. As annealing time increased and Sn grain coarsening occurred, the compositions and fractions revert to the phase diagram, suggesting an “anti-Scheil” effect. A Bi interface segregation model based on Bi segregation at Sn grain boundaries was developed to explain the Bi distribution characteristics in Sn during two-phase annealing process.

Besides hybrid joints, microstructural evolution after reflow and aging, especially of intermetallic compound (IMC) growth at solder/pad surface finish interfaces in homogeneous SnBi LTS joints, is also important to understanding fatigue life and crack paths in the solder joints. This study describes intermetallic growth in homogeneous solder joints of Sn-Bi eutectic alloy and Sn-Bi-Ag alloys formed with electroless nickel-immersion gold (ENIG) and Cu-organic surface protection (Cu-OSP) surface finishes. Experimental observations revealed that, during solid state annealing following reflow, the 50nm Au from the ENIG surface finish catalyzed rapid (Au,Ni)Sn₄ intermetallic growth at the Ni-solder interface in both Sn-Bi and Sn-Bi-Ag homogeneous joints, which led to significant solder joint embrittlement during fatigue testing. Further study found that the growth rate of (Au,Ni)Sn₄ intermetallic could be reduced by In and Sb alloying of SnBi solders and is totally eliminated with Cu addition. Fatigue testing revealed Au embrittlement is always present in solder joints without Cu, even with In and Sb additions due to (Au,Ni)Sn₄ formation. The fatigue reliability of Cu-containing alloys is better on ENIG due to the formation of (Ni,Cu,Au)₆Sn₅ at the solder-surface finish interface instead of (Au,Ni)Sn₄.

With the development of SnBi LTSs, a new generation alloy called HRL1 stands out for its outstanding reliability during thermal cycling and drop shock testing. This study focused on microstructure evolution in SnBi eutectic, SnBiAg eutectic and HRL1 solders (MacDermid Alpha) homogeneous joints and hybrid joints with SAC305 formed with ENIG and Cu-OSP surface finishes. Experimental results revealed that with more microalloying elements, HRL1 has significantly refined microstructure and slower Sn grain growth rate during solid-state aging compared with SnBi and SnBiAg eutectic alloys. Intermetallic compound growth study showed that during solid state annealing following reflow, the (50nm) Au from the ENIG finish catalyzed rapid (Au,Ni)Sn₄ intermetallic growth at the Ni-solder interface in both Sn-Bi and Sn-Bi-Ag homogeneous joints, which led to significant solder joint embrittlement during creep and fatigue loading. However, (Au,Ni)Sn₄ growth and gold embrittlement was completely eliminated for HRL1 due to Cu additions in it, and HRL1 has significantly better fatigue reliability than SnBi and SnBiAg eutectic alloys on both OSP and ENIG surface finishes.

碩士
國立彰化師範大學
工業教育與技術學系
98
Focusing on the courses of automobile circuit system overhaul for the department Auto Mechanics in vocational high schools, this study aimed to explore the elements and functions of digital materials for the units of starter systems, charger systems, and electronic ignition systems. Based on the web-based learning theories and web-based collaborative learning, the digital materials have been designed and developed to realize the web-based collaborative learning and the adaptability of digital materials for the automobile circuit system overhaul in vocational high schools. There were two research goals: 1. To design and develop the digital materials which meet the SCORM 2004 digital materials standards, based on the ADDIE digital curriculum development model; 2.To understand the adaptability of web-based learning platform for automobile circuit system overhaul courses in the department of auto mechanics in vocational high schools. This study adopted the CCU-e-Learning 2.0 Chung-Cheng Web-Based Learning System as the web-based instruction platform. After the design, experts and scholars have been invited to evaluate the curriculum. The result indicated the adaptability of the web-based learning platform for the automobile circuit system overhaul courses in vocational high schools. With the opinions from the experts and auto-mechanics teachers of vocational high schools, the researcher has evaluated and then finalized the construction of the web-based learning materials. This web-based learning platform is expected to realize experimental instruction and then to finalize the evaluative stage of teaching-material development.

In the face of environmental issues and aiming at electronic devices of rapid production at low cost, this doctoral thesis proposed two new and innovative approaches to obtain substrates, dielectrics, and electrodes from a single biopolymer: cellulose. In a first moment, a simple approach to produce low-cost flexible ionic conductive cellulose mats (ICCMs) using solution blow spinning (SB-Spinning) is reported. The electrochemical properties of the ICCMs were adjusted through infiltration with alkali hydroxides (LiOH, NaOH, or KOH), which enabled of ICCMs application as dielectric and substrate in oxide-based field effect transistors (FETs) and pencil-drawn resistorloaded inverters. The FETs showed good electrical performance under operating voltage <2.5 V, which was strictly associated with the type of alkali ion incorporated, presenting satisfactory performance for the ICCM infiltrated with K+ ion. The inverters with K+ ions also presented good dynamic performance, with a gain close to 2. Regarding the cellulose-based electrodes, a second innovative approach is reported to synthetize laser-induced graphene (LIG) structures from carboxymethyl cellulose (CMC)-based ink containing LIG obtained from cellulose nanocrystals (CNCs) extracted from pineapple leaf fibers (PALFs). To prove this concept, zinc oxide ultraviolet (ZnO UV) sensors were designed varying the amount of LIG from CNCs. Sensor obtained from LIG written directly on paper substrate were also performed. The ZnO UV sensors designed with CMC-based ink showed responsivity 40-fold higher than that of paper direct-written LIG, as well as excellent electrical performance under flexion. These findings may open new promising possibilities for low-consumption wearable electronics, allowing the use of concepts such as the "Internet of Things" and opening the possibility of generating 100% organic cellulose-produced electronic devices.
Frente às questões ambientais e visando dispositivos eletrônicos de rápida produção e baixo custo, este projeto de pesquisa de doutorado propôs duas abordagens inovadoras para a obtenção de substratos, materiais dielétricos e eletrodos a partir de um único biopolímero: a celulose. Em um primeiro momento relata-se uma abordagem simples para produzir mantas condutoras iônicas de celulose (ICCM) flexíveis aplicando fiação por sopro em solução (SB-Spinning) seguido da infiltração com hidróxidos alcalinos (LiOH, NaOH ou KOH), permitindo sua aplicação como dielétrico e substrato em transistores e inversores com resistor desenhado a lápis. Os transistores exibiram um bom desempenho sob tensão de operação abaixo de 2,5 V, apresentando desempenho satisfatório para as mantas infiltradas com K+, além do inversor apresentar um ganho próximo de dois. Visando também eletrodos oriundos da celulose, este projeto relatou uma abordagem inovadora para sintetizar grafeno induzido por laser (LIG) a partir de tinta à base de carboximetilcelulose (CMC) contendo LIG obtido de nanocristais de celulose (CNCs) do abacaxi. Como prova de conceito, sensores de ZnO UV foram projetados variando a quantidade de LIG dos CNCs na tinta a base de CMC, assim como sensores obtidos por escrita direta de LIG em substrato de papel. Os sensores de ZnO UV flexíveis formulados com tinta apresentaram responsividade 40 vezes maior que os sensores contendo LIG direto do papel. Essas descobertas podem inaugurar uma nova Era na geração de eletrônicos vestíveis de baixo consumo, permitindo conceitos como "Internet das Coisas", e abrindo a possibilidade de dispositivos 100% orgânicos oriundos da celulose.