Relevant bibliographies by topics / ELECTRONIC AND DESIGN AUTOMATION (EDA)

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'ELECTRONIC AND DESIGN AUTOMATION (EDA)'

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Published: 11 September 2023

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Journal articles on the topic "ELECTRONIC AND DESIGN AUTOMATION (EDA)"

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Camp, B. H. "Electronic Design Automation (EDA '84)." Electronics and Power 31, no. 4 (1985): 327. http://dx.doi.org/10.1049/ep.1985.0202.

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Huang, Guyue, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, et al. "Machine Learning for Electronic Design Automation: A Survey." ACM Transactions on Design Automation of Electronic Systems 26, no. 5 (June 5, 2021): 1–46. http://dx.doi.org/10.1145/3451179.

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With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.
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Henkel, Jorg. "Open-Source Electronic Design Automation (EDA) Tools." IEEE Design & Test 38, no. 2 (April 2021): 4. http://dx.doi.org/10.1109/mdat.2021.3066119.

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Tian, Zeyu. "Introduction to machine leaning in electronic design automation (EDA)." Applied and Computational Engineering 6, no. 1 (June 14, 2023): 520–26. http://dx.doi.org/10.54254/2755-2721/6/20230849.

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The rapid growth of the intergraded circuit industry as predicted by Moores law has significantly increased the importance of efficient design processes. In addition, due to physical constraint, we will soon reach the limit of how small the size of the transistor can become, and the design processes will become more complex than ever. In order to cope with those challenges and introduce the product to the market within the time to market, the industry has been developing ways to apply machine learning to concurrent EDA tools. This paper will aim to introduce how machine learning is applied to varies processes of electronic design and how they improve the current EDA tools. We will also show the limitations and opportunities of ML based EDA tools and provide a rough idea of the potential future to those who are looking into this area.
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Kim, TaeWoong, and SoYoung Kim. "Electronic design automation requirements for R2R printing foundry." Flexible and Printed Electronics 7, no. 1 (February 4, 2022): 013001. http://dx.doi.org/10.1088/2058-8585/ac4d3d.

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Abstract Roll-to-roll (R2R) printed electronic devices have been in the spotlight over the decades as a potential replacement for Si-based semiconductors, research into this technology is still being actively conducted over the world. These printed electronic devices can be used in a variety of applications, so the demand for them is expected to reach over USD 20.7 billion in 2025 given a compound annual growth rate (CAGR) of 21.5%. As the new ink materials and printing technologies being researched are commercialized, foundry companies that produce printed electronics need to provide appropriate work flow that will allow engineers to design these kind of circuits using commercial electronic design automation (EDA) tools. This review paper describes the key parameters that should be found process design kit (PDK), including the contained design rules and the simulation program with integrated circuit emphasis model. We cover the factors that need to be considered when a fabless company develops circuits for the R2R process, including the design methodology from the beginning of the design to the final graphic data stream (GDS) completion stage, we also discuss other essential technological hurdles that must be overcome in this process. The overall process of design and analysis for printed electronic technique is based on the silicon design flow. We describe the full custom design flow for analog integrated circuits (ICs) and explain how the automatic placement and routing based design of digital integrated circuits can be carried out. In addition, the necessity of sign-off verification using post-simulation, electromagnetic (EM) simulation and bias check simulation required for commercial product development will be explained. The development of PDKs and EDA tools for circuit design in the R2R printed electronics foundry industry will have a potentially tremendous impact on the semiconductor ecosystem by lowering the barriers to producing these devices.
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Patterson, E. B., P. G. Holmes, and D. Morley. "Electronic design automation (EDA) techniques for the design of power electronic control systems." IEE Proceedings G Circuits, Devices and Systems 139, no. 2 (1992): 191. http://dx.doi.org/10.1049/ip-g-2.1992.0033.

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Liu, Yong Qin, Guo Qiang Li, Zhi Ping Zhu, and Bao Hui Guo. "Design and Implementation of Automatic Schematics Verification Platform." Advanced Materials Research 529 (June 2012): 343–46. http://dx.doi.org/10.4028/www.scientific.net/amr.529.343.

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Design and implementation of Automatic Schematics Verification Platform based on open EDA (Electronic Design Automation) tools has been discussed. This platform adopts client/server pattern and provides an environment of design Verification and sharing data for designers separately, and at the same time, this platform has strong transplantable ability because of it’s strong cohesion and weak coupling with the open EDA tool, therefore we can transplant this platform to other open EDA tools expediently.
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Chu, Hong-Son, Oka Kurniawan, Wenzu Zhang, Dongying Li, and Er-Ping Li. "Integrated System-Level Electronic Design Automation (EDA) for Designing Plasmonic Nanocircuits." IEEE Transactions on Nanotechnology 11, no. 4 (July 2012): 731–38. http://dx.doi.org/10.1109/tnano.2012.2194507.

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CHAN, PHILIP C. "DESIGN AUTOMATION FOR MULTICHIP MODULE — ISSUES AND STATUS." International Journal of High Speed Electronics and Systems 02, no. 04 (December 1991): 263–85. http://dx.doi.org/10.1142/s0129156491000132.

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In this paper we will review the current state of commercial electronic design automation (EDA) tools for the design of multichip modules. MCM can be classified in terms of its substrate technology. The choice of substrate technology has important implications for the selection of design automation tools. A PCB EDA system seems more appropriate for MCMs with stacked via substrate which closely resembles the through-hole printed circuit board (PCB). A chip layout system may be more appropriate for MCMs with low-cost thin-film silicon substrate which typically uses staircase vias. The cofired ceramic substrate MCM which evolved from the hybrid integrated circuit technology may use the specialized hybrid EDA software packages available for the designing of hybrid integrated circuits. Historically, printed circuit board and integrated circuit design automation software evolved separately. There exists a boundary between the printed circuit board and integrated circuit design automation tools in the physical design hierarchy. This boundary can be an important limitation for the repartitioning of the physical design hierarchy within the MCM. We shall discuss in detail the impact of MCM on various aspects of EDA. In the area of physical design, we must face the traditional placement and routing problem for any high speed design. Problems such as system clock skew and tight timing requirements must be considered. As one push clock frequency higher, one also must consider discontinuities due to vias and bends besides the classical transmission line effect due to long wires. Other traditional physical design problems such as ground and power plane generation, physical design verification and mask tooling must be revisited in the context of various MCM substrate technologies. The thermal aspects of MCM design are strongly influenced by the placement of chips on the MCM substrate. Thermal design is especially important for high density MCMs using the flip-chip mounting technology. Here, the heat must be dissipated through the back of the substrate via thermal pillars or bumps. We still need to deal with the traditional coupled transmission line problems. Due to the small cross section, high performance MCM substrate interconnects are resistive and the transmission lines they form are lossy. Noise is another main problem for MCM design. For high speed MCM with many CMOS buffers, the ground bouncing noise resulting from simultaneous switching of a large number of CMOS drivers must be controlled through proper substrate and package design. We will conclude the paper by comparing existing VLSI and PCB EDA tools for MCM design.
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Mirkovic, Dejan, and Predrag Petkovic. "Design automation of ΔΣ switched capacitor modulators using spice and MATLAB." Serbian Journal of Electrical Engineering 11, no. 1 (2014): 47–59. http://dx.doi.org/10.2298/sjee131017005m.

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Concerning the fact that the design of contemporary integrated circuits (IC) is practically impossible without using sophisticated Electronic Design Automation (EDA) software, this paper gives some interesting thoughts and considerations about that issue. As technology processes advances on year basis consequently EDA industry is forced to follow this trend as well. This, on the other hand, requires IC designer to frequently and efficiently accommodate to new working environments. Authors of this paper suggest a method for high level circuit analysis that is based on using common (open source or low cost) circuit simulators but precise and fast enough to meet requirements imposed by demanding mixed-signal blocks. The paper demonstrates the proposed EDA procedure on an example of second order ?? modulator design. It illustrates considerable simulation time saving which is more than welcome in a world of analogue and mixed-signal design.
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Dissertations / Theses on the topic "ELECTRONIC AND DESIGN AUTOMATION (EDA)"

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Vila, Garcia Francesc. "From characterization strategies to PDK & EDA Tools for Printed Electronics." Doctoral thesis, Universitat Autònoma de Barcelona, 2015. http://hdl.handle.net/10803/322813.

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Durant els últims anys, les tecnologies d’electrònica impresa (PE) estan atraient molta atenció, principalment degut a que es poden fabricar grans àrees, i són una alternativa de baix cost a la microelectrònica tradicional. D’entre totes les tecnologies disponibles, la fabricació emprant impresores d’injecció de tinta (inkjet) resulta particularment interessant, al ser un mètode d’impressió digital (reduint els residus generats al fabricar), i no tenir contacte amb el substrat (per tant permet la utilització de molts tipus diferents de substrats). La tecnologia inkjet encara està patint un gran desenvolupament, cosa que fa difícil que es puguin dissenyar circuits i sistemes sense tenir un gran coneixement sobre els processos que hi ha al darrere. A més a més, la mancança d’eines específicament dissenyades per a inkjet crea un gran distància entre els dissenyadors i els tecnòlecs responsables de desenvolupar la tecnologia, dificultant així una adopció generalitzada de la tecnologia inkjet. Aquesta tèsi contribueix a apropar els dissenyadors a la tecnologia, proposant i adaptant fluxes i kits de disseny existents i basats en microelectrònica, a les tecnologies inkjet, complementant-los amb eines específiques per adaptar-los a les peculiaritats de l’inkjet. D’aquesta manera aconseguim un camí directe des del disseny a la fabricació, abstraient els detalls tecnològics del disseny. A més a més, per tancar el camí entre disseny i la fabricació, aquesta tèsi proposa un entorn semi-automàtic de caracterització, que es fa servir per analitzar el comportament de la tinta dipositada, inferint quines correccions són necessàries per a què el resultat fabricat correspongui tant com sigui possible al disseny. El coneixement extret d’aquest pas s’incorporarà en una eina EDA específica que analitza i aplica automàticament les correccions extretes a un disseny.
During last years, Printed Electronics technologies have attracted a great deal of attention due to being a low-cost, large area electronics manufacturing process. From all available technologies, inkjet printing is of special interest, because of its digital nature, which reduces material waste; and being a non-contact process, which allows printing on a great variety of substrates. Inkjet printing is still on heavy development, thus making designing for it difficult without an in-depth knowledge of how the manufacturing process works. In addition, currently there is a lack of specific tools aiding to design for it, creating a large gap between designers and technology developers and difficulting a wide adoption of this particular technologies. The work presented on this thesis contributes to bridge the existing gap between designers and technology developers by proposing and adapting existing microelectronics-based design flows and kits, while complementing them with custom, PE specific Electronic Design Automation tools; to achieve a direct path from design to manufacturing, and abstract technology specific details from the design stages. This is achieved by combining a design flow with a PE Process/Physical Design Kit, and a set of EDA tools adapted to PE. In addition, to finally bridge design and manufacturing, this thesis proposes a semi-automated characterization methodology, used to analyze the deposited ink behavior, and infer all necessary corrections needed to ensure that the final fabricated result corresponds as much as possible to the intended design. This knowledge is then integrated into an specific EDA framework which will perform the aformentioned corrections automatically.
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GUPTA, NITIN. "MACHINE LEARNING PREDICTIVE ANALYTIC MODEL TO REDUCE COST OF QUALITY FOR SOFTWARE PRODUCTS." Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2021. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18484.

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In today’s world, high quality product are need of the time. The low-quality product results in the high cost. This can be explained from the quality graph below 1) Prevention cost can be define as the issue/bugs found out before the deployment/delivered to customer. This cost is initially very low but in the longer run goes up 2) Failure cost includes cost of losing customers, Root cause analysis and rectification. This cost is defiantly very huge Figure 11 : Cost of Quality Source: https://www.researchgate.net/ 5 If there can be any mechanism that can help to identify the expected issues in the prevention cost then the overall all cost of quality can be reduce as shown in below graph Figure 12 : Modified Cost of Quality Source: https://www.researchgate.net/ Electronic and Design Automation (EDA) Industry is backbone of Semiconductor Industry as it provide software tool aiding in the development of Semi-Conductors chips. EDA tools are from specification to the foundry input. Below figure shows mapping of Chip design verification and currently available tools technologies Modified prevention cost Modified TCQ 6 Figure 13 : Tools offered by EDA Industry Sourced: https://en.wikipedia.org/wiki/Electronic_design_automation Term tape out means the chip out of foundry and ready for use in electronic circuit. Re- spin means incident post Tape-out chips does not function as required and re-build is required. Cost of the tape out is minimum 5 million of dollars. Major re-spin reason is functionality issues, therefore function verification tools delivered by EDA needs to be always of high quality. A major problem faced by the Functional verification tool R&D team is to predict the numbers of the bugs that might have been introduced during the design phase to sign off the completeness and quality. If these bugs can be predicted, then the COQ can be reduced. Hence saving million of dollar to company and customer. Machine learning, a upcoming new discipline, define scientific study of algorithm and using computing power develop prediction model so that certainty of the task can be managed. In this project, prediction model for expected bugs during the development of the software is designed to help the Product manager to get confidence on quality. For the data, explanatory research and Interview was conducted with-in the Synopsys. This project has been successfully adopted with-in the Verification IP group of EDA leader and is in process to get it implemented in all different Business Units.
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Meister, Tilo. "Pinzuordnungs-Algorithmen zur Optimierung der Verdrahtbarkeit beim hierarchischen Layoutentwurf." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2012. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-96764.

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Sie entwickeln Entwurfssysteme für elektronische Baugruppen? Dann gehören für Sie die mit der Pinzuordnung verbundenen Optimierungskriterien - die Verdrahtbarkeit im Elektronikentwurf - zum Berufsalltag. Um die Verdrahtbarkeit unter verschiedenen Gesichtspunkten zu verbessern, werden in diesem Buch neu entwickelte Algorithmen vorgestellt. Sie ermöglichen erstmals die automatisierte Pinzuordnung für eine große Anzahl von Bauelementen in hochkomplexen Schaltungen. Alle Aspekte müssen in kürzester Zeit exakt erfasst, eingeschätzt und im Entwurfsprozess zu einem optimalen Ergebnis geführt werden. Die beschriebenen Methoden reduzieren den Entwicklungsaufwand für elektronische Systeme auf ein Minimum und ermöglichen intelligente Lösungen auf der Höhe der Zeit. Die vorliegende Arbeit behandelt die Optimierung der Pinzuordnung und die dafür notwendige Verdrahtbarkeitsvorhersage im hierarchischen Layoutentwurf. Dabei werden bekannte Methoden der Verdrahtbarkeitsvorhersage aus allen Schritten des Layoutentwurfs zusammengetragen, gegenübergestellt und auf ihre Eignung für die Pinzuordnung untersucht. Dies führt schließlich zur Entwicklung einer Vorhersagemethode, die speziell an die Anforderungen der Pinzuordnung angepasst ist. Die Pinzuordnung komplexer elektronischer Geräte ist bisher ein vorwiegend manueller Prozess. Es existieren also bereits Erfahrungen, welche jedoch weder formalisiert noch allgemein verfügbar sind. In den vorliegenden Untersuchungen werden Methoden der Pinzuordnung algorithmisch formuliert und damit einer Automatisierung zugeführt. Besondere Merkmale der Algorithmen sind ihre Einsetzbarkeit bereits während der Planung des Layouts, ihre Eignung für den hierarchisch gegliederten Layoutentwurf sowie ihre Fähigkeit, die Randbedingungen differenzieller Paare zu berücksichtigen. Die beiden untersuchten Aspekte der Pinzuordnung, Verdrahtbarkeitsvorhersage und Zuordnungsalgorithmen, werden schließlich zusammengeführt, indem die neue entwickelte Verdrahtbarkeitsbewertung zum Vergleichen und Auswählen der formulierten Zuordnungsalgorithmen zum Einsatz kommt
This work deals with the optimization of pin assignments for which an accurate routability prediction is a prerequisite. Therefore, this contribution introduces methods for routability prediction. The optimization of pin assignments, for which these methods are needed, is done after initial placement and before routing. Known methods of routability prediction are compiled, compared, and analyzed for their usability as part of the pin assignment step. These investigations lead to the development of a routability prediction method, which is adapted to the specific requirements of pin assignment. So far pin assignment of complex electronic devices has been a predominantly manual process. Hence, practical experience exists, yet, it had not been transferred to an algorithmic formulation. This contribution develops pin assignment methods in order to automate and improve pin assignment. Distinctive characteristics of the thereby developed algorithms are their usability during layout planning, their capability to integrate into a hierarchical design flow, and the consideration of differential pairs. Both aspects, routability prediction and assignment algorithms, are finally brought together by using the newly developed routability prediction to evaluate and select the assignment algorithms
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Knechtel, Johann. "Interconnect Planning for Physical Design of 3D Integrated Circuits." Doctoral thesis, Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2014. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-143635.

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Vertical stacking—based on modern manufacturing and integration technologies—of multiple 2D chips enables three-dimensional integrated circuits (3D ICs). This exploitation of the third dimension is generally accepted for aiming at higher packing densities, heterogeneous integration, shorter interconnects, reduced power consumption, increased data bandwidth, and realizing highly-parallel systems in one device. However, the commercial acceptance of 3D ICs is currently behind its expectations, mainly due to challenges regarding manufacturing and integration technologies as well as design automation. This work addresses three selected, practically relevant design challenges: (i) increasing the constrained reusability of proven, reliable 2D intellectual property blocks, (ii) planning different types of (comparatively large) through-silicon vias with focus on their impact on design quality, as well as (iii) structural planning of massively-parallel, 3D-IC-specific interconnect structures during 3D floorplanning. A key concept of this work is to account for interconnect structures and their properties during early design phases in order to support effective and high-quality 3D-IC-design flows. To tackle the above listed challenges, modular design-flow extensions and methodologies have been developed. Experimental investigations reveal the effectiveness and efficiency of the proposed techniques, and provide findings on 3D integration with particular focus on interconnect structures. We suggest consideration of these findings when formulating guidelines for successful 3D-IC design automation
Dreidimensional integrierte Schaltkreise (3D-ICs) beruhen auf neuartigen Herstellungs- und Integrationstechnologien, wobei vor allem “klassische” 2D-ICs vertikal zu einem neuartigen 3D-System gestapelt werden. Dieser Ansatz zur Erschließung der dritten Dimension im Schaltkreisentwurf ist nach Expertenmeinung dazu geeignet, höhere Integrationsdichten zu erreichen, heterogene Integration zu realisieren, kürzere Verdrahtungswege zu ermöglichen, Leistungsaufnahmen zu reduzieren, Datenübertragungsraten zu erhöhen, sowie hoch-parallele Systeme in einer Baugruppe umzusetzen. Aufgrund von technologischen und entwurfsmethodischen Schwierigkeiten bleibt jedoch bisher die kommerzielle Anwendung von 3D-ICs deutlich hinter den Erwartungen zurück. In dieser Arbeit werden drei ausgewählte, praktisch relevante Problemstellungen der Entwurfsautomatisierung von 3D-ICs bearbeitet: (i) die Verbesserung der (eingeschränkten) Wiederverwendbarkeit von zuverlässigen 2D-Intellectual-Property-Blöcken, (ii) die komplexe Planung von verschiedenartigen, verhältnismäßig großen Through-Silicion Vias unter Beachtung ihres Einflusses auf die Entwurfsqualität, und (iii) die strukturelle Einbindung von massiv-parallelen, 3D-IC-spezifischen Verbindungsstrukturen während der Floorplanning-Phase. Das Ziel dieser Arbeit besteht darin, Verbindungsstrukturen mit deren wesentlichen Eigenschaften bereits in den frühen Phasen des Entwurfsprozesses zu berücksichtigen. Dies begünstigt einen qualitativ hochwertigen Entwurf von 3D-ICs. Die in dieser Arbeit vorgestellten modularen Entwurfsprozess-Erweiterungen bzw. -Methodiken dienen zur effizienten Lösung der oben genannten Problemstellungen. Experimentelle Untersuchungen bestätigen die Wirksamkeit sowie die Effektivität der erarbeiten Methoden. Darüber hinaus liefern sie praktische Erkenntnisse bezüglich der Anwendung von 3D-ICs und der Planung deren Verbindungsstrukturen. Diese Erkenntnisse sind zur Ableitung von Richtlinien für den erfolgreichen Entwurf von 3D-ICs dienlich
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Nalbantis, Dimitris. "World Wide Web based layout synthesis for analogue modules." Thesis, University of Kent, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.365218.

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Greenwood, Rob. "Semantic analysis for system level design automation." Thesis, This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-10062009-020216/.

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Han, Yiding. "Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation." DigitalCommons@USU, 2014. https://digitalcommons.usu.edu/etd/3868.

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The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow.
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Farsaei, Ahmadreza. "On the electronic-photonic integrated circuit design automation : modelling, design, analysis, and simulation." Thesis, University of British Columbia, 2017. http://hdl.handle.net/2429/61272.

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Photonic networks form the backbone of the data communication infrastructure. In particular, in current and future wireless communication systems, photonic networks are becoming increasingly popular for data distribution between the central office and the remote antenna units at base stations. As wireless-photonic systems become increasingly more popular, not only low-cost implementation of such systems is desirable, but also a reliable electronic-photonic design automation (EPDA) framework supporting such complex circuits and systems is crucial. This work investigates the foundation and presents implementation of various aspects of such EPDA framework. Various building blocks of silicon-photonic systems are reviewed in the first chapter of the thesis. The review discusses an example of a 60-GHz wireless system based on photonic technology, which could be suitable for the emerging 5th-generation (5G) cellular networks, and also provides design use cases that need to be supported by the EPDA framework. Integrated photonic circuits, which are the building blocks of wireless-photonic systems, will achieve their potential only if designers can efficiently and reliably design, model, simulate, and tune the performance of electro-optical components. The developed EPDA framework supports an integrated optical solver, INTERCONNECT, to provide optical time and frequency domain simulations so that a designer would be able to simulate electrical, optical, and electro-optical circuits using two developed and implemented methodologies: sequential electro-optical simulation and co-simulation. We propose an algorithm to enhance the performance of electronic simulation engines that can be integrated into the EPDA simulation methods such as Harmonic Balance. It will be shown that body-biasing of CMOS transistors can be used as an effective method for tuning the performance of the electronic section of an electro-optical design. This can help designers adjusting the performance of their designs after fabrication. Modelling of electro-optical components is discussed in this thesis; It is shown that some traditional passive components such as inductors, which take a large amount of space in CMOS processes, could be fabricated in the much lower cost photonic process and consequently the overall cost of silicon-photonic systems can be reduced significantly.
Applied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
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Tang, Dennis. "Evaluation of EDA tools for electronic development and a study of PLM for future development businesses." Thesis, Linköpings universitet, Fysik och elektroteknik, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-104011.

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Electronic Design Automation (EDA) tools are today very capable computer programs supporting electronic engineers with the design of printed circuit board (PCB). All tools have their strengths and weaknesses; when choosing the right tool many factors needs to be taken into consideration aside from the tools themselves. Companies need to focus on the product and revenues for a business to be viable. Depending on the knowledge and strengths of the company, the choice of tools varies. The decision should be based on the efficiency of the tools and the functions necessity for the company rather than the price tags. The quality and availability of support for the tools, training costs, how long will it take to put the tool in operation and present or future collaboration partners is equally important factors when deciding the right tool. The absence of experience and knowledge of the current tool within a company is a factor which could affect important operation; therefore it is important to provide training and education on how to use the tool to increase its efficiency. Providing training and education can be a large expense, but avoids changes within and makes the business competitive. The choice of EDA tool should be based on the employed engineer’s current knowledge and experience of the preferred tool. If the employed engineer’s knowledge and experience varies too much, it might be preferable to make a transition to one of the tool by training and education. Product lifecycle management (PLM) is a data management system and business activity management system which focuses on the lifecycle of a product. To manage the lifecycle of a product it is necessary to split the lifecycle into stages and phases for a more manageable and transparent workflow. By overseeing a product’s entire lifecycle there are benefits which affects many areas. PLM greatest benefits for EDA are collaboration across separate groups and companies by working together through a PLM platform, companies can forge strong design chains that combine their best capabilities to deliver the product to the customers. This report is a study on evaluating which EDA suits the company with consideration of the employed engineer’s demands, requests and competence. The interests in PLM made the company suggest a short theory study on PLM and EDA benefits.
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Feng, Wenyuan. "Evolutionary design automation for control systems with practical constraints." Thesis, University of Glasgow, 2000. http://theses.gla.ac.uk/4507/.

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The aim of this work is to explore the potential and to enhance the capability of evolutionary computation in the development of novel and advanced methodologies that enable control system structural optimisation and design automation for practical applications. Current design and optimisation methods adopted in control systems engineering are in essence based upon conventional numerical techniques that require derivative information of performance indices. These techniques lack robustness in solving practical engineering problems, which are often of a multi-dimensional, multi-modal nature. Using those techniques can often achieve neither global nor structural optimisation. In contrast, evolutionary mechanism learning tools have the ability to search in a multi-dimensional, multi-modal space, but they can not approach a local optimum as a conventional calculus-based method. The first objective of this research is to develop a reliable and effective evolutionary algorithm for engineering applications. In this thesis, a globally optimal evolutionary methodology and environment for control system structuring and design automation is developed, which requires no design indices to be differentiable. This is based on the development of a hybridised GA search engine, whose local tuning is tremendously enhanced by the incorporation of Hill-Climbing (HC), Simulated Annealing (SA) and Simplex techniques to improve the performance in search and design. A Lamarckian inheritance technique is also developed to improve crossover and mutation operations in GAs. Benchmark tests have shown that the enhanced hybrid GA is accurate, and reliable. Based on this search engine and optimisation core, a linear and nonlinear control system design automation suite is developed in a Java based platform-independent format, which can be readily available for design and design collaboration over corporate Intranets and the Internet. Since it has also made cost function unnecessary to be differentiable, hybridised indices combining time and frequency domain measurement and accommodating practical constraints can now be incorporated in the design. Such type of novel indices are proposed in the thesis and incorporated in the design suite. The Proportional plus Integral plus Derivative (PID) controller is very popular in real world control applications. The development of new PID tuning rules remains an area of active research. Many researchers, such as Åström and Hägglund, Ho, Zhuang and Atherton, have suggested many methods. However, their methods still suffer from poor load disturbance rejection, poor stability or shutting of the derivative control etc. In this thesis, Systematic and batch optimisation of PID controllers to meet practical requirements is achieved using the developed design automation suite. A novel cost function is designed to take disturbance rejection, stability in terms of gain and phase margins and other specifications into account in-the same time. Comparisons made with Ho's method confirm that the derivative action can play an important role to improve load disturbance rejection yet maintaining the same stability margins. Comparisons made with Åström’s method confirm that the results from this thesis are superior not only in load disturbance rejection but also in terms of stability margins. Further robustness issues are addressed by extending the PID structure to a free form transfer function. This is realised by achieving design automation. Quantitative Feedback Theory (QFT), method offers a direct frequency-domain design technique for uncertain plants, which can deal non-conservatively with different types of uncertainty models and specifications. QFT design problems are often multi-modal and multi-dimensional, where loop shaping is .the most challenging part. Global solutions can hardly be obtained using analytical and convex or linear programming techniques. In addition, these types of conventional methods often impose unrealistic or unpractical assumptions and often lead to very conservative designs. In this thesis, GA-based automatic loop shaping for QFT controllers suggested by the Research Group is being furthered. A new index is developed for the design which can describe stability, load rejection and reduction of high frequency gains, which has not been achieved with existing methods. The corresponding prefilter can also be systematically designed if tracking is one of the specifications. The results from the evolutionary computing based design automation suite show that the evolutionary technique is much better than numerical methods and manual designs, i.e., 'high frequency gain' and controller order have been significantly reduced. Time domain simulations show that the designed QFT controller combined with the corresponding prefilter performs more satisfactorily.
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Books on the topic "ELECTRONIC AND DESIGN AUTOMATION (EDA)"

1

Essential electronic design automation (EDA). Upper Saddle River, N.J: Prentice Hall PTR/Pearson Education, 2004.

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Gulati, Kanupriya. Hardware acceleration of EDA algorithms: Custom ICs, FPGAs and GPUs. New York: Springer, 2010.

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European Design and Test Conference (1994 Paris, France). The European Design and Test Conference: Proceedings : EDAC, The European Conference on Design Automation : ETC, European Test Conference : EUROASIC, The European Event in ASIC Design : February 28-March 3, 1994, Paris, France. Los Alamitos, Calif: IEEE Computer Society Press, 1994.

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Rammig, Franz J., and Flávio R. Wagner, eds. Electronic Design Automation Frameworks. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3.

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Bayliss, John. Electronic design automation report. London: Cambridge Market Intelligence, 1994.

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Jansen, Dirk, ed. The Electronic Design Automation Handbook. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6.

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Hadburg, Bruce P. The electronic design automation market. [Saratoga, Calif.]: Electronic Trend Publications, 1990.

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Li, Jun. EDA Ji shu yu VHDL bian cheng. Beijing Shi: Dian zi gong ye chu ban she, 2012.

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Soeken, Mathias, and Rolf Drechsler, eds. Natural Language Processing for Electronic Design Automation. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52273-5.

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Ren, Haoxing, and Jiang Hu, eds. Machine Learning Applications in Electronic Design Automation. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-13074-8.

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Book chapters on the topic "ELECTRONIC AND DESIGN AUTOMATION (EDA)"

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Jansen, Dirk. "EDA Tutorial." In The Electronic Design Automation Handbook, 606–22. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_26.

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Keszocze, Oliver, Betina Keiner, Matthias Richter, Gottfried Antpöhler, and Robert Wille. "(Semi)automatic Translation of Legal Regulations to Formal Representations: Expanding the Horizon of EDA Applications." In Natural Language Processing for Electronic Design Automation, 1–11. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52273-5_1.

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Jansen, Dirk. "Library Design." In The Electronic Design Automation Handbook, 398–420. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-0-387-73543-6_17.

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Härder, Theo, and Norbert Ritter. "Transaction-Based Design Data Processing in the PRIMA Framework." In Electronic Design Automation Frameworks, 3–12. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_1.

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Böttger, Ralf, Yaron Engel, Gerd Kachel, Silvia Kolmschlag, Dietmar Nolte, and Elke Radeke. "Enhancing the Data Openness of Frameworks by Database Federation Services." In Electronic Design Automation Frameworks, 99–108. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_10.

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Scholz, Gerhard, and Wolfgang Wilkes. "Interoperability Support by Integration of EXPRESS Models." In Electronic Design Automation Frameworks, 109–18. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_11.

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Videira, I., P. Veríssimo, and H. Sarmento. "Communication in a Distributed Environment." In Electronic Design Automation Frameworks, 121–30. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_12.

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Kunzmann, Arno, and Ralf Seepold. "Basic Requirements for an Efficient Inter-Framework-Communication." In Electronic Design Automation Frameworks, 131–38. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_13.

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Schubert, Jürgen, and Arno Kunzmann. "Resource-Oriented Load Distribution in a Framework Environment." In Electronic Design Automation Frameworks, 139–46. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_14.

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Bosch, Olav, Pieter Wolf, and Alfred Hoeven. "Design Flow Management: More than Convenient Tool Invocation." In Electronic Design Automation Frameworks, 149–58. Boston, MA: Springer US, 1995. http://dx.doi.org/10.1007/978-0-387-34880-3_15.

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Conference papers on the topic "ELECTRONIC AND DESIGN AUTOMATION (EDA)"

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Koushanfar, Farinaz, Saverio Fazzari, Carl McCants, William Bryson, Matthew Sale, Peilin Song, and Miodrag Potkonjak. "Can EDA combat the rise of electronic counterfeiting?" In the 49th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2228360.2228386.

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Zheng, Jia-Nian, Chen-Fu Chien, Tzu-Yu Lin, Shih-Wei Liu, and Wei-Ting Huang. "Electronic Design Automation (EDA) Scheduling System in IC Design Industry." In 2019 IEEE International Conference on Smart Manufacturing, Industrial & Logistics Engineering (SMILE). IEEE, 2019. http://dx.doi.org/10.1109/smile45626.2019.8965281.

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Khazhinsky, Michael G., Shuqing Cao, Harald Gossner, Gianluca Boselli, and Melanie Etherton. "Electronic design automation (EDA) solutions for ESD-robust design and verification." In 2012 IEEE Custom Integrated Circuits Conference - CICC 2012. IEEE, 2012. http://dx.doi.org/10.1109/cicc.2012.6330690.

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Knežević, Mihailo. "Use of electronic design automation tools in computer engineering courses." In 9th International Scientific Conference Technics and Informatics in Education. University of Kragujevac, Faculty of Technical Sciences Čačak, 2022. http://dx.doi.org/10.46793/tie22.137k.

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Electronic Design Automation (EDA) tools are widely used semiconductor industry to support the ever-growing complexity of computer design, and they became an important skill which is required by computer engineers. In this paper, we present the usage of the EDA Playground web platform for practical exercise in the Digital systems design course at the computer engineering department of the Faculty of technical sciences. This platform was used in process of designing and testing of program counter register of a simple processor.
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Zheng, Jia-Nian, Chen-Fu Chien, and Tzu-Yu Lin. "Real Time Electronic Design Automation (EDA) Scheduling System in IC Design Industry." In the 2019 International Conference. New York, New York, USA: ACM Press, 2019. http://dx.doi.org/10.1145/3335550.3335566.

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Potkonjak, Miodrag. "Session details: Can EDA combat the rise of electronic counterfeiting?" In DAC '12: The 49th Annual Design Automation Conference 2012. New York, NY, USA: ACM, 2012. http://dx.doi.org/10.1145/3259190.

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Rifai, Mochammad, Siti Masitoh, and Bachtiar Syaiful Bachri. "The Effect of Electronic Design Automation (EDA) Towards Experimental Learning Method." In Proceedings of the 2nd International Conference on Education Innovation (ICEI 2018). Paris, France: Atlantis Press, 2018. http://dx.doi.org/10.2991/icei-18.2018.137.

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Knechtel, Johann, Elif Bilge Kavun, Francesco Regazzoni, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, et al. "Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDA." In 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020. http://dx.doi.org/10.23919/date48585.2020.9116483.

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Kranen, Kevin. "A guided tour of electronic design automation (EDA) for design of silicon on insulator (SOI) SoCs." In 2009 IEEE International SOI Conference. IEEE, 2009. http://dx.doi.org/10.1109/soi.2009.5318790.

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Evans, Tristan M., Shilpi Mukherjee, Yarui Peng, and H. Alan Mantooth. "Electronic Design Automation (EDA) Tools and Considerations for Electro-Thermo-Mechanical Co-Design of High Voltage Power Modules." In 2020 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2020. http://dx.doi.org/10.1109/ecce44975.2020.9235818.

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Reports on the topic "ELECTRONIC AND DESIGN AUTOMATION (EDA)"

1

SILICON INTEGRATION INITIATIVE INC AUSTIN TX. Electronic Design Automation (EDA) Roadmap Taskforce Report, Design of Microprocessors. Fort Belvoir, VA: Defense Technical Information Center, April 1999. http://dx.doi.org/10.21236/ada408348.

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Turowski, M., A. Przekwas, R. Tramel, H. Q. Yang, and H. Ding. Opto-Electronic and Interconnects Hierarchical Design Automation System (OE-IDEAS). Fort Belvoir, VA: Defense Technical Information Center, May 2004. http://dx.doi.org/10.21236/ada423982.

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Modlo, Yevhenii O., Serhiy O. Semerikov, Stanislav L. Bondarevskyi, Stanislav T. Tolmachev, Oksana M. Markova, and Pavlo P. Nechypurenko. Methods of using mobile Internet devices in the formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects. [б. в.], February 2020. http://dx.doi.org/10.31812/123456789/3677.

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An analysis of the experience of professional training bachelors of electromechanics in Ukraine and abroad made it possible to determine that one of the leading trends in its modernization is the synergistic integration of various engineering branches (mechanical, electrical, electronic engineering and automation) in mechatronics for the purpose of design, manufacture, operation and maintenance electromechanical equipment. Teaching mechatronics provides for the meaningful integration of various disciplines of professional and practical training bachelors of electromechanics based on the concept of modeling and technological integration of various organizational forms and teaching methods based on the concept of mobility. Within this approach, the leading learning tools of bachelors of electromechanics are mobile Internet devices (MID) – a multimedia mobile devices that provide wireless access to information and communication Internet services for collecting, organizing, storing, processing, transmitting, presenting all kinds of messages and data. The authors reveals the main possibilities of using MID in learning to ensure equal access to education, personalized learning, instant feedback and evaluating learning outcomes, mobile learning, productive use of time spent in classrooms, creating mobile learning communities, support situated learning, development of continuous seamless learning, ensuring the gap between formal and informal learning, minimize educational disruption in conflict and disaster areas, assist learners with disabilities, improve the quality of the communication and the management of institution, and maximize the cost-efficiency. Bachelor of electromechanics competency in modeling of technical objects is a personal and vocational ability, which includes a system of knowledge, skills, experience in learning and research activities on modeling mechatronic systems and a positive value attitude towards it; bachelor of electromechanics should be ready and able to use methods and software/hardware modeling tools for processes analyzes, systems synthesis, evaluating their reliability and effectiveness for solving practical problems in professional field. The competency structure of the bachelor of electromechanics in the modeling of technical objects is reflected in three groups of competencies: general scientific, general professional and specialized professional. The implementation of the technique of using MID in learning bachelors of electromechanics in modeling of technical objects is the appropriate methodic of using, the component of which is partial methods for using MID in the formation of the general scientific component of the bachelor of electromechanics competency in modeling of technical objects, are disclosed by example academic disciplines “Higher mathematics”, “Computers and programming”, “Engineering mechanics”, “Electrical machines”. The leading tools of formation of the general scientific component of bachelor in electromechanics competency in modeling of technical objects are augmented reality mobile tools (to visualize the objects’ structure and modeling results), mobile computer mathematical systems (universal tools used at all stages of modeling learning), cloud based spreadsheets (as modeling tools) and text editors (to make the program description of model), mobile computer-aided design systems (to create and view the physical properties of models of technical objects) and mobile communication tools (to organize a joint activity in modeling).
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