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Journal articles on the topic 'Electrical interconnect modeling'

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Author: Grafiati

Published: 14 March 2023

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1

Dong, Chen, Wei Wang, and Maher Rizkalla. "Modeling and Simulation of Carbon Nanotube Interconnect Network." Solid State Phenomena 121-123 (March 2007): 1057–60. http://dx.doi.org/10.4028/www.scientific.net/ssp.121-123.1057.

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The electrical properties of metallic carbon nanotubes (CNT) can rival, or even exceed, the best metals known. It is a potential candidate for future on-chip interconnect, whose performance will be dominant in the next generation integrated circuits. In this paper, a study on the modeling and simulation techniques for the CNT interconnect network is carried out. The frequency-independent models of CNT interconnects in terms of resistance, inductance and capacitance are summarized. A novel frequencydependent circuit model is proposed for CNT for various high-frequency applications. Preliminary analysis shows a good match between numerical simulations and the compact model. The proposed modeling and simulation techniques for CNT interconnect network are expected to play an important role in the future CNT nanotechnology applications.

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2

Kumari, B., R. Sharma, and M. Sahoo. "Electro-thermal modeling and reliability analysis of Cu–carbon hybrid interconnects for beyond-CMOS computing." Applied Physics Letters 121, no. 10 (September 5, 2022): 101901. http://dx.doi.org/10.1063/5.0101329.

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A Cu–carbon hybrid interconnect was recently proposed as an alternate interconnect structure for future VLSI applications because of its superior electrical performance over its counterparts. This study focuses on the electro-thermal aspects of Cu–carbon hybrid interconnects to be adopted as a potential replacement of copper as the back-end-of-line (BEOL) interconnect material. Cu–carbon hybrid shows promise in terms of electro-thermal efficiency when compared to copper as well as other suggested hybrid materials. The maximum temperature attained by the Cu–carbon hybrid interconnect is less than copper by 16%, and its mean time to failure is improved by 96%. Uniform distribution of heat can be observed in the Cu–carbon hybrid BEOL in addition to low temperature rise as compared to the copper based BEOL. These analyses strengthen the claim of Cu–carbon hybrid interconnects to be a worthier possibility for electro-thermal efficient nanoscale systems.

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3

Xu, Yao, Ashok Srivastava, and Ashwani K. Sharma. "Emerging Carbon Nanotube Electronic Circuits, Modeling, and Performance." VLSI Design 2010 (February 17, 2010): 1–8. http://dx.doi.org/10.1155/2010/864165.

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Current transport and dynamic models of carbon nanotube field-effect transistors are presented. A model of single-walled carbon nanotube as interconnect is also presented and extended in modeling of single-walled carbon nanotube bundles. These models are applied in studying the performances of circuits such as the complementary carbon nanotube inverter pair and carbon nanotube as interconnect. Cadence/Spectre simulations show that carbon nanotube field-effect transistor circuits can operate at upper GHz frequencies. Carbon nanotube interconnects give smaller delay than copper interconnects used in nanometer CMOS VLSI circuits.

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4

Poltz, J. "MODELING OF VLSI INTERCONNECT." COMPEL - The international journal for computation and mathematics in electrical and electronic engineering 13, no. 1 (January 1994): 191–94. http://dx.doi.org/10.1108/eb051872.

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5

Carver, Chase, Norman Seastrand, and Robert Welte. "PWB Z Interconnect Technology - Electrical Performance." International Symposium on Microelectronics 2014, no. 1 (October 1, 2014): 000217–21. http://dx.doi.org/10.4071/isom-tp23.

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Driven mainly by Moore's law, there is an ever accelerating drive for smaller, lighter, higher function, and lower power electronics. For PWBs this translates into higher wiring and component densities with ever increasing electrical performance requirements. As high speed serial data rates reach 30 Gbps and beyond, design considerations to promote signal integrity become ever more important. These tighter signal integrity constraints put increased emphasis on via stub effects, via to trace crosstalk in BGA escapes, and adequate ground stitch vias around layer transition vias. With the maturation of sintered paste VIAs in PWBs, VIA structures can be assembled to span only the layers to be connected. This paste technology allows vias to be specifically tailored to only connect the required layers. VIA stubs and their adverse SI effects for high speed signaling are completely eliminated. The elimination of via stubs also makes PWB fabrication easier by removing the need to backdrill or counterbore high speed signal vias. This increases yields and reduces costs associated with this complex and tight tolerance process. In addition to manufacturing advantages provided by Z technology, increased wireability is enabled by opening up area above and below the layers being connected, as well as the ability to use smaller diameter VIAs. These smaller vias also help to reduce crosstalk between high speed wiring channels. Z Interconnect technology also reduces BGA escape crosstalk by the ability to route in areas where via stubs have been removed, and also allows for the tailoring of ground stitch vias to only connect the ground planes associated with the specific stripline environments. However, Z VIAs usually require more pads within the padstack than conventional VIAs (cannot strip pads from non-connection layers) and the resistivity of the paste can be as much as 30 times greater than copper. This paper will quantify the high frequency signal characteristics associated with a PWB design using i3 Electronics sintered paste Z-VIAs. Results are presented based on modeling which is correlated with test vehicle measurements. Modeling also addresses manufacturing tolerances. Suggestions are made for optimizing passive channel structures to use this technology in support of high speed serial interconnects. Integration of i3's 2s1p Cores into new compact high speed stripline structures, which can be built without expensive subassemblies and sequential lamination processes, is also presented. These cores implement the positive aspects of Z Interconnect technology to eliminate via stubs and increase wireability in dense areas. Comparisons of Z Interconnect technology are also made to alternate methods of PWB construction to explain the risks and benefits of this technology.

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6

Hazra, Arnab, and Sukumar Basu. "Graphene Nanoribbon as Potential On-Chip Interconnect Material—A Review." C 4, no. 3 (August 30, 2018): 49. http://dx.doi.org/10.3390/c4030049.

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In recent years, on-chip interconnects have been considered as one of the most challenging areas in ultra-large scale integration. In ultra-small feature size, the interconnect delay becomes more pronounced than the gate delay. The continuous scaling of interconnects introduces significant parasitic effects. The resistivity of interconnects increases because of the grain boundary scattering and side wall scattering of electrons. An increased Joule heating and the low current carrying capability of interconnects in a nano-scale dimension make it unreliable for future technology. The devices resistivity and reliability have become more and more serious problems for choosing the best interconnect materials, like Cu, W, and others. Because of its remarkable electrical and its other properties, graphene becomes a reliable candidate for next-generation interconnects. Graphene is the lowest resistivity material with a high current density, large mean free path, and high electron mobility. For practical implementation, narrow width graphene sheet or graphene nanoribbon (GNR) is the most suitable interconnect material. However, the geometric structure changes the electrical property of GNR to a small extent compared to the ideal behavior of graphene film. In the current article, the structural and electrical properties of single and multilayer GNRs are discussed in detail. Also, the fabrication techniques are discussed so as to pattern the graphene nanoribbons for interconnect application and measurement. A circuit modeling of the resistive-inductive-capacitive distributed network for multilayer GNR interconnects is incorporated in the article, and the corresponding simulated results are compared with the measured data. The performance of GNR interconnects is discussed from the view of the resistivity, resistive-capacitive delay, energy delay product, crosstalk effect, stability analysis, and so on. The performance of GNR interconnects is well compared with the conventional interconnects, like Cu, and other futuristic potential materials, like carbon nanotube and doped GNRs, for different technology nodes of the International Technology Roadmap for Semiconductors (ITRS).

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7

Myeong-Eun Hwang, Seong-Ook Jung, and K. Roy. "Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation." IEEE Transactions on Circuits and Systems I: Regular Papers 56, no. 7 (July 2009): 1428–41. http://dx.doi.org/10.1109/tcsi.2008.2006217.

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8

Liao, Weiping, and Lei He. "Microarchitecture Level Interconnect Modeling Considering Layout Optimization." Journal of Low Power Electronics 1, no. 3 (December 1, 2005): 297–308. http://dx.doi.org/10.1166/jolpe.2005.036.

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9

Banan, Behnam, Farhad Shokraneh, Pierre Berini, and Odile Liboiron-Ladouceur. "Electrical performance analysis of a CPW capable of transmitting microwave and optical signals." International Journal of Microwave and Wireless Technologies 9, no. 8 (June 5, 2017): 1679–86. http://dx.doi.org/10.1017/s1759078717000575.

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A study on the microwave performance of a metallic transmission line capable of simultaneously transmitting microwave and optical signals is presented targeting millimeter-long interconnects. Conventional analytical solution is used to find the optimal structure for a given characteristic impedance. Then, functionality of the link is validated through S-parameter measurements for 3–13 mm long lines. The waveguide parameters, such as resistance, inductance, capacitance, and conductance are extracted based on a lumped circuit model. The modeling enables structure optimization for interconnect bandwidth density of 1 Gb/s/μm and more.

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10

Kurokawa, Atsushi, Takashi Sato, Toshiki Kanamoto, and Masanori Hashimoto. "Interconnect Modeling: A Physical Design Perspective." IEEE Transactions on Electron Devices 56, no. 9 (September 2009): 1840–51. http://dx.doi.org/10.1109/ted.2009.2026208.

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11

YAMADA, K., H. KITAHARA, Y. ASAI, H. SAKAMOTO, N. OKADA, M. YASUDA, N. ODA, et al. "Accurate Modeling Method for Cu Interconnect." IEICE Transactions on Electronics E91-C, no. 6 (June 1, 2008): 968–77. http://dx.doi.org/10.1093/ietele/e91-c.6.968.

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12

EL-MOURSY, MAGDY A., and HEBA A. SHAWKEY. "INTERCONNECT MODELING WITH THE EXISTENCE OF LINE INDUCTANCE." Journal of Circuits, Systems and Computers 22, no. 02 (February 2013): 1250082. http://dx.doi.org/10.1142/s021812661250082x.

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Simple uniform reduced order model is used to model RLC interconnect lines. Waveform characterization is used to evaluate the accuracy of the adopted model. Few number of sections are shown to achieve high accuracy of modeling the RLC interconnect. As compared to RC lines, less than five times the number of sections is sufficient to model RLC lines. The model is shown to be accurate for wide range of relative impedance of the driver, the line, and the load. Look-up tables are provided to simplify the process of choosing the best interconnect section model to characterize an RLC interconnect line. The tables are shown to be accurate for wide range of relative impedance. The presented model reduces the simulation time while keeping the simulation accuracy. The simulation time can be reduced by up to 72% with less than 10% reduction in accuracy using the provided tables. The tables provide a simple and quick mean to characterize an RLC interconnect which is necessary for performance evaluation in digital circuits.

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13

Zhang, Yong Hong, Wei Jin, and Tao Feng. "Nanometer Interconnect Test Structure for Modeling of Process Variation." Advanced Materials Research 960-961 (June 2014): 935–40. http://dx.doi.org/10.4028/www.scientific.net/amr.960-961.935.

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With the interconnection density and doubling the number of layers in VLSI, Interconnect line width,pitch,and the thickness of the dielectric layer will changed within the same chip caused by the process variation. and the interconnect parasitics changes ultimately affect circuit performance and yield.IC designers need an accurate BEoL corner model to help circuit design. Standard Interconnect Performance Parameters (SIPPs) is standard method to measure ultra-large scale integrated circuit BEOL performance. Designed parallel plate, layer-skipping parallel plate, comb meander, comb meander for via resistance test structures to extract SIPPs according to their sensitivity differences to different test structures, and realized them in CIF format file with High-level Perl language automatically. Then change to GDSII format file that wafer used widely by Cadence layout software, and pass electrical rule checks. Greatly improved the efficiency of test structure’s design and realized. Lay the foundations for formulation of Design for Manufacturability physical design rules and further research interconnection statistical models under nanometer technology with more unique physical phenomena.

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14

Guoan Zhong, Cheng-Kok Koh, and K. Roy. "On-chip interconnect modeling by wire duplication." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, no. 11 (November 2003): 1521–32. http://dx.doi.org/10.1109/tcad.2003.818303.

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15

Ma, James D., and Rob A. Rutenbar. "Interval-Valued Reduced-Order Statistical Interconnect Modeling." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, no. 9 (September 2007): 1602–13. http://dx.doi.org/10.1109/tcad.2007.895577.

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16

Farrokhi, Maryam, Rahim Faez, Saeed Haji Nasiri, and Bita Davoodi. "Effect of Varying Aspect Ratio on Relative Stability for Graphene Nanoribbon Interconnects." Applied Mechanics and Materials 229-231 (November 2012): 205–9. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.205.

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Achieving dense off-chip interconnection with satisfactory electrical performance is emerging as a major challenge in advanced system engineering. Graphene nanoribbons (GNRs) have been recently proposed as one of the potential candidate materials for both transistors and interconnect. In addition, development is still underway for alternative materials and processes for high aspect ratio (AR) contacts. Studding the effect of varying aspect ratio on relative stability of graphene nanoribbon interconnects is an important viewpoint in performance evaluation of system. In this paper, Nyquist stability analysis based on transmission line modeling (TLM) for GNR interconnects is investigated. In this analysis, the dependence of the degree of relative stability for multilayer GNR (MLGNR) interconnects on the aspect ratio has been acquired. It is shown that, with increasing the aspect ratio of each ribbon, MLGNR interconnects become more unstable.

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17

Carloni, Luca P., Andrew B. Kahng, Swamy V. Muddu, Alessandro Pinto, Kambiz Samadi, and Puneet Sharma. "Accurate Predictive Interconnect Modeling for System-Level Design." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, no. 4 (April 2010): 679–84. http://dx.doi.org/10.1109/tvlsi.2009.2014772.

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18

Khitun, Alexander. "Magnetic Interconnects Based on Composite Multiferroics." Micromachines 13, no. 11 (November 17, 2022): 1991. http://dx.doi.org/10.3390/mi13111991.

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The development of magnetic logic devices dictates a need for a novel type of interconnect for magnetic signal transmission. Fast signal damping is one of the problems which drastically differs from conventional electric technology. Here, we describe a magnetic interconnect based on a composite multiferroic comprising piezoelectric and magnetostrictive materials. Internal signal amplification is the main reason for using multiferroic material, where a portion of energy can be transferred from electric to magnetic domains via stress-mediated coupling. The utilization of composite multiferroics consisting of piezoelectric and magnetostrictive materials offers flexibility for the separate adjustment of electric and magnetic characteristics. The structure of the proposed interconnect resembles a parallel plate capacitor filled with a piezoelectric, where one of the plates comprises a magnetoelastic material. An electric field applied across the plates of the capacitor produces stress, which, in turn, affects the magnetic properties of the magnetostrictive material. The charging of the capacitor from one edge results in the charge diffusion accompanied by the magnetization change in the magnetostrictive layer. This enables the amplitude of the magnetic signal to remain constant during the propagation. The operation of the proposed interconnects is illustrated by numerical modeling. The model is based on the Landau–Lifshitz–Gilbert equation with the electric field-dependent anisotropy term included. A variety of magnetic logic devices and architectures can benefit from the proposed interconnects, as they provide reliable and low-energy-consuming data transmission. According to the estimates, the group velocity of magnetic signals may be up to 105 m/s with energy dissipation less than 10−18 J per bit per 100 nm. The physical limits and practical challenges of the proposed approach are also discussed.

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19

Chun, Sunghoon, Yongjoon Kim, and Sungho Kang. "MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs." Journal of Electronic Testing 23, no. 4 (May 9, 2007): 357–62. http://dx.doi.org/10.1007/s10836-006-0630-0.

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20

Tekleab, Daniel, K. F. Poole, R. Singh, D. L. Carroll, and W. R. Harrell. "Modeling early failure in integrated circuit interconnect." Microelectronics Reliability 40, no. 6 (June 2000): 991–96. http://dx.doi.org/10.1016/s0026-2714(99)00339-x.

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21

Xu, Zhifei, Blaise Ravelo, Olivier Maurice, Sébastien Lalléchère, and Fayu Wan. "Kron-Branin modeling of symmetric star tree interconnect." International Journal of Circuit Theory and Applications 47, no. 3 (October 15, 2018): 391–405. http://dx.doi.org/10.1002/cta.2575.

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22

Li, Bing-Jie, Zhen-Song Li, Yan-Ping Zhao, Zheng-Wang Li, and Min Miao. "Modeling and Optimization Design of Signal Interconnect Channel Considering Signal Integrity in Three Dimensional Integrated Circuits." Journal of Nanoelectronics and Optoelectronics 16, no. 5 (May 1, 2021): 773–80. http://dx.doi.org/10.1166/jno.2021.2999.

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The signal integrity (SI) analysis of a high-speed signal interconnect channel composed of through silicon vias (TSVs) and horizontal re-distribution layers (RDL) is carried out, and the problems of SI, such as transmission loss, crosstalk and coupling effect in the transmission channel, are analyzed and studied. These signal integrity issues are considered in this paper, a signal interconnect channel model is proposed and the equivalent circuit model is deduced as well. Compared with the traditional one, this interconnect channel model has better performance in SI. Further sweep frequency analysis is carried out for different material parameters to achieve signal transmission performance optimization aimed at this model. Test samples of the proposed signal interconnect channel model are designed and fabricated according to the process index, and measured to verify the actual transmission performance. The design and optimization rule of high-speed signal interconnect channel are summarized which proved that the proposed structure has more advantages in signal transmission performance, and has important guiding significance for practical design.

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23

Al-Daloo, Mohammed, Ahmed Soltan, and Alex Yakovlev. "Advance Interconnect Circuit Modeling Design Using Fractional-Order Elements." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, no. 10 (October 2020): 2722–34. http://dx.doi.org/10.1109/tcad.2019.2962779.

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24

Travaly, Y., M. Bamal, L. Carbonell, F. Iacopi, M. Stucchi, M. Van Hove, and G. P. Beyer. "A novel approach to resistivity and interconnect modeling." Microelectronic Engineering 83, no. 11-12 (November 2006): 2417–21. http://dx.doi.org/10.1016/j.mee.2006.10.048.

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25

Fasig, Jonathan, Gregory Rash, Barbara Randall, Karl Fritz, Steven Currie, Bart McCoy, Paul Riemer, Wendy Wilkins, Barry Gilbert, and Erik Daniel. "Interconnect Analysis for 80-Gbps Serial Link Design." Journal of Microelectronics and Electronic Packaging 5, no. 3 (July 1, 2008): 135–39. http://dx.doi.org/10.4071/1551-4897-5.3.135.

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This paper presents a case study of the modeling and simulation methods used to design the signal path for a proposed 80-Gbps serial data link between digital systems. This design includes flip-chip transitions from custom IBM 8HP integrated circuits to multilayer organic substrates, with coaxial-cable connections between substrates. Discussion topics include interconnect material selection, detailed 3-D electromagnetic modeling of the conductor transitions and signal paths, time-domain circuit simulation of the complete data path including the driver and receiver, and bit-error rate analysis of the complete link. Simulated data are presented.

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26

Mi, Ning, Sheldon X. D. Tan, and Boyuan Yan. "Multiple block structure-preserving reduced order modeling of interconnect circuits." Integration 42, no. 2 (February 2009): 158–68. http://dx.doi.org/10.1016/j.vlsi.2008.04.006.

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27

Ioan, D., G. Ciuprina, M. Radulescu, and E. Seebacher. "Compact modeling and fast simulation of on-chip interconnect lines." IEEE Transactions on Magnetics 42, no. 4 (April 2006): 547–50. http://dx.doi.org/10.1109/tmag.2006.871466.

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28

Xuejue Huang, P. Restle, T. Bucelot, Yu Cao, Tsu-Jae King, and Chenming Hu. "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design." IEEE Journal of Solid-State Circuits 38, no. 3 (March 2003): 457–63. http://dx.doi.org/10.1109/jssc.2002.808313.

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29

Ma, J. D., and R. A. Rutenbar. "Fast interval-valued statistical modeling of interconnect and effective capacitance." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, no. 4 (April 2006): 710–24. http://dx.doi.org/10.1109/tcad.2006.870067.

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30

Jiang, Lijun, Chuan Xu, Barry J. Rubin, Alan J. Weger, Alina Deutsch, Howard Smith, Alain Caron, and Kaustav Banerjee. "A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures." IEEE Transactions on Advanced Packaging 33, no. 4 (November 2010): 777–86. http://dx.doi.org/10.1109/tadvp.2010.2090348.

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31

Chang, R., Y. Cao, and C. J. Spanos. "Modeling the Electrical Effects of Metal Dishing Due to CMP for On-Chip Interconnect Optimization." IEEE Transactions on Electron Devices 51, no. 10 (October 2004): 1577–83. http://dx.doi.org/10.1109/ted.2004.834898.

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32

Xia, Lei, Jicheng Meng, Ruimin Xu, Bo Yan, and Yunchuan Guo. "Modeling of 3-D Vertical Interconnect Using Support Vector Machine Regression." IEEE Microwave and Wireless Components Letters 16, no. 12 (December 2006): 639–41. http://dx.doi.org/10.1109/lmwc.2006.885585.

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33

Murugavel, A. K., and N. Ranganathan. "Petri net modeling of gate and interconnect delays for power estimation." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 5 (October 2003): 921–27. http://dx.doi.org/10.1109/tvlsi.2003.817110.

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34

Demeester, Thomas, and Daniël De Zutter. "Fields at a Finite Conducting Wedge and Applications in Interconnect Modeling." IEEE Transactions on Microwave Theory and Techniques 58, no. 8 (August 2010): 2158–65. http://dx.doi.org/10.1109/tmtt.2010.2053061.

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35

TANJI, Y. "Sparse and Passive Reduced-Order Interconnect Modeling by Eigenspace Method." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E91-A, no. 9 (September 1, 2008): 2419–25. http://dx.doi.org/10.1093/ietfec/e91-a.9.2419.

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36

Zhao, Wei, Xia Li, Sam Gu, Seung H. Kang, Matthew M. Nowak, and Yu Cao. "Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect." IEEE Transactions on Electron Devices 56, no. 9 (September 2009): 1862–72. http://dx.doi.org/10.1109/ted.2009.2026162.

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37

TSENG, W., C. N. J. LIU, and C. SU. "Passive Reduced-Order Macro-Modeling for Linear Time-Delay Interconnect Systems." IEICE Transactions on Electronics E89-C, no. 11 (November 1, 2006): 1713–18. http://dx.doi.org/10.1093/ietele/e89-c.11.1713.

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38

Jain, Neeraj, A. K. Aggarwal, and P. K. Chaudhary. "Carbon Nanotubes: Good Candidate for VLSI Interconnects." Applied Mechanics and Materials 378 (August 2013): 165–71. http://dx.doi.org/10.4028/www.scientific.net/amm.378.165.

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Carbon nanotubes are being seen as a promising new class of electronic materials owing to the change in their properties with chirality and geometry of the nanotube. They are being considered for future VLSI applications due to their superior conductance and inductance properties which are important parameters while considering any material for an interconnect or via applications.In this paper, we report the variation in electrical and thermal conductance as well as inductance of a CNT with its geometrical features using a diameter dependent model. Also the dependence of conductance and inductance of a CNT on the type of nanotubes, tube length and tube diameter has been studied. As we know that at nanometre scale, the electrical and thermal transport properties of the components become extremely important as regards the functioning of the device and it is difficult to accurately measure these properties, therefore predictions using modeling and simulation play an important role in providing a guideline for design and fabrication of CNT interconnects and understanding the working of various other CNT based devices.

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39

Elfadel, I. M., A. Deutsch, H. H. Smith, B. J. Rubin, and G. V. Kopcsay. "A Multiconductor Transmission Line Methodology for Global On-Chip Interconnect Modeling and Analysis." IEEE Transactions on Advanced Packaging 27, no. 1 (February 2004): 71–78. http://dx.doi.org/10.1109/tadvp.2004.825478.

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40

Yan, Zhaowen, Ting Kang, Wei Zhang, and Jianwei Wang. "Modeling and Electromagnetic Analysis of Multilayer Through Silicon Via Interconnect for 3D Integration." International Journal of Antennas and Propagation 2015 (2015): 1–14. http://dx.doi.org/10.1155/2015/470952.

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Convergence of multiple functions in a single device is the main thought behind the development of the current electronic trends. So, the requirement for higher integration in electronic devices has become more important in present days than in the past. Through silicon via (TSV) is the latest interconnect technology proposed mainly for higher integration and higher frequency. Therefore, cross talk will be an essential issue that needs to be taken into consideration. In this paper, we study the electrical property of a GSSG (S-Signal, G-Ground) TSV structure and propose the accurate lumped model which can be used to predict the TSV performance. Since more dies are used within one chip, the single layer TSV cannot satisfy the requirement. Hence, we propose the multilayer TSV structure and study how the bump radius, bump height, and underfill material affect the TSV transmission performance and coupling issue, so that we can conduct a good TSV design. Furthermore, three multilayer 4 × 4 TSV array models are proposed with different GS distribution to analyze the detailed coupling results.

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41

ALAM, MEHBOOB, ARTHUR NIEUWOUDT, and YEHIA MASSOUD. "EFFICIENT MULTI-SHIFTED ARNOLDI PROJECTION USING WAVELET TRANSFORM." Journal of Circuits, Systems and Computers 16, no. 05 (October 2007): 699–709. http://dx.doi.org/10.1142/s0218126607003927.

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As process technology continues to scale into the nanoscale regime and the overall system complexity increases, the reduced order modeling of on-chip interconnect plays a crucial role in determining VLSI system performance. In this paper, we develop an adaptive wavelet interpolation method based on Krylov subspace techniques to generate reduced order interconnect models that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying an inexpensive Haar wavelet and performing irregular sampling in the frequency domain. The results indicate that our method provides greater accuracy than multi-shift Krylov subspace methods with uniform interpolation points.

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42

Daugherty, Robin, and Dragica Vasileska. "Multi-Scale Modeling of Self Heating Effects on Power Consumption in Silicon CMOS Devices." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2017, DPC (January 1, 2017): 1–22. http://dx.doi.org/10.4071/2017dpc-tp3_presentation4.

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This work pursues a multi-scale modeling approach to combine interconnect and device level simulation in order to study the effects of carrier self-heating and thermal transport on device performance. More specifically, this work will focus on power consumption and heat dissipation in silicon CMOS technology. As device dimensions decrease to the nanometer scale, current density in the device active regions and the circuit interconnects increases [4]. This increase in current density leads to substantial increases in operating temperatures in critical regions of nano-scale electronic devices. We have already shown these effects in n-channel MOSFETs [2], and will continue to explore how this phenomenon affects p-channel MOSFETs and CMOS circuits. This paper presents the methodology used for the study, multi-scale results from the n-channel MOSFET simulations, and preliminary results from the device level p-channel MOSFET simulation. The modeling approach combines an electro-thermal device simulation with a thermal transport solver at the circuit level. The electrical simulation solves Poisson's equations self-consistently coupled with an ensemble Monte Carlo to determine internal electric fields and model electron and hole transport in the device [3]. The thermal simulation solves the energy balance equations for acoustic and optical phonons and uses the phonon energy to determine the lattice temperature [5]. The electro-thermal solver couples these two processes by introducing temperature dependent scattering to the carrier transport solver. Thermal transport can be modeled in a variety of ways: phonon Monte Carlo simulations are necessary for modeling extreme nano-scale and hot-carrier devices, energy balance modeling is used in this study to model thermal transport at the device level, and the Joule heating method commonly used in commercial device simulators is used in this study to model thermal transport at the interconnect level. The thermal modeling in the device and the interconnects is coupled using the device structure itself as an interface: the electro-thermal simulator provides Joule heating terms throughout the device to be used in the Joule heating simulator which in turn gives the temperature profile in the interconnects to be used as a boundary condition in the electro-thermal solver. These simulations are repeated in a self-consistent loop until convergence is achieved [2]. This modeling approach has been successfully applied to n-channel MOSFET devices and the results have been confirmed using a novel experimental approach. Two identical MOSEFTs in either common source or common drain configuration can be biased such that one device is in saturation and one device is in cut-off or sub-threshold region. The device in saturation heats up and the device in sub-threshold is used as a sensor; the temperature in the sensor can be determined using the subthreshold slope [2]. Confirming the simulation results with experimental results for the temperature in the subthreshold device substantiates the accuracy of the methodology for determining the temperature throughout the device [2]. This methodology, now verified by comparison with experimental results for n-channel MOSFETS, will be applied to the study of CMOS circuits.

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Bhopte, Siddharth, Jesse Galloway, Kyung-Rok Park, Hyun-Jin Park, Jeong-Han Choi, Ho-Beob Yu, and Sung-Hwan Yang. "Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, DPC (January 1, 2013): 000441–54. http://dx.doi.org/10.4071/2013dpc-ta22.

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Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (<60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

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Qinwei Xu and P. Mazumder. "Equivalent-circuit interconnect modeling based on the fifth-order differential quadrature methods." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11, no. 6 (December 2003): 1068–79. http://dx.doi.org/10.1109/tvlsi.2003.817522.

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Buratynski, E. K. "Thermomechanical Modeling of Direct Chip Interconnection Assembly." Journal of Electronic Packaging 115, no. 4 (December 1, 1993): 382–91. http://dx.doi.org/10.1115/1.2909347.

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Efforts to model thermomechanical aspects of the Direct Chip Interconnection (DCI) assembly process are described. DCI is a method to simultaneously attach and electrically interconnect bare chips to a substrate using Anisotropic Conductive Adhesive Films (ACAF). Emphasis has been placed on describing the numerical procedure used in the analysis. The major components of the analysis include a calibration procedure to “numerically measure” anisotropic properties of the film, a curing model to capture “frozen-in” stresses, a global analysis that considers the overall assembly station but does not resolve details of the interconnection, and a local model, coupled to the global model, that resolves details about the interconnection. Typical results are shown to demonstrate the capabilities of the model.

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Yu-Lin Shen. "On the Elastic Assumption for Copper Lines in Interconnect Stress Modeling." IEEE Transactions on Device and Materials Reliability 8, no. 3 (September 2008): 600–607. http://dx.doi.org/10.1109/tdmr.2008.2002360.

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Tan, Sheldon, Zeyu Sun, and Sheriff Sadiqbatcha. "Interconnect Electromigration Modeling and Analysis for Nanometer ICs: From Physics to Full-Chip." IPSJ Transactions on System LSI Design Methodology 13 (2020): 42–55. http://dx.doi.org/10.2197/ipsjtsldm.13.42.

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Kacker, K., and S. K. Sitaraman. "Electrical/Mechanical Modeling, Reliability Assessment, and Fabrication of FlexConnects: A MEMS-Based Compliant Chip-to-Substrate Interconnect." Journal of Microelectromechanical Systems 18, no. 2 (April 2009): 322–31. http://dx.doi.org/10.1109/jmems.2008.2011117.

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Bai, X., R. Chandra, S. Dey, and P. V. Srinivas. "Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, no. 8 (August 2004): 1256–63. http://dx.doi.org/10.1109/tcad.2004.831568.

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HUANG, Z. "Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew." IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E88-A, no. 12 (December 1, 2005): 3367–74. http://dx.doi.org/10.1093/ietfec/e88-a.12.3367.

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