Dissertations / Theses on the topic 'Electrical interconnect modeling'
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Kim, Byungsub 1978. "Equalized on-chip interconnect : modeling, analysis, and design." Thesis, Massachusetts Institute of Technology, 2010. http://hdl.handle.net/1721.1/58076.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.
Includes bibliographical references (p. 115-118).
This thesis work explores the use of equalization techniques to improve throughput and reduce power consumption of on-chip interconnect. A theoretical model for an equalized on-chip interconnect is first suggested to provide mathematical formulation for the link behavior. Based on the model, a fast-design space exploration methodology is demonstrated to search for the optimal link design parameters (wire and circuit) and to generate the optimal performance-power trade-off curve for the equalized interconnects. This thesis also proposes new circuit techniques, which improve the revealed demerits of the conventional circuit topologies. The proposed charge-injection transmitter directly conducts pre-emphasis current from the supply into the channel, eliminating the power overhead of analog current subtraction in the conventional transmit pre-emphasis, while significantly relaxing the driver coefficient accuracy requirements. The transmitter utilizes a power efficient nonlinear driver by compensating non-linearity with pre-distorted equalization coefficients. A trans-impedance amplifier at the receiver achieves low static power consumption, large signal amplitude, and high bandwidth by mitigating limitations of purely-resistive termination. A test chip is fabricated in 90-nm bulk CMOS technology and tested over a 10 mm, 2[micro]m pitched on-chip differential wire. The transceiver consumes 0.37-0.63 pJ/b with 2-6 Gb/s/ch.
by Byungsub Kim.
Ph.D.
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Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul) 1973. "Interconnect modeling and optimization in deep sub-micron technologies." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29230.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.
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Vittala, Kavya. "Interconnect Modeling and Lifetime Failure Detection in FPGAs using Delay Faults." University of Toledo / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=toledo1404728195.
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Percey, Andrew K. (Andrew Kenneth). "Analysis and modeling of capacitive coupling along metal interconnect lines." Thesis, Massachusetts Institute of Technology, 1996. http://hdl.handle.net/1721.1/39067.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1996.Includes bibliographical references (leaf 87).
by Andrew K. Percey.
M.Eng.
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Kuo, Benjamin S. "Modeling and evaluation of a hierarchical ring interconnect for system-on-chip multiprocessing." Thesis, McGill University, 2004. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=81543.
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This thesis proposes a software model for a multiprocessor system, which is targeted for SoC implementation. The proposed design is based on the two-level ring architecture adopted in the NUMAchine multiprocessor developed at University of Toronto. The proposed system reconsiders the interconnect design alternatives for smaller design area and energy consumption. The system uses an alternative memory architecture to reduce logic complexity, as well as a different deadlock prevention scheme to reflect changes in memory architecture. The software model is implemented in the SystemC modeling language, which allows high-level behavior modeling to reduce both the development time and the simulation time. The model is also at a level of detail which reflects true communication characteristics on the interconnect network. Burst length, memory access latency, FIFO depth, and the operating frequencies for the rings are the four key SoC design parameters which have been identified and optimized for the system.
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Chou, Mike Chuan 1969. "Fast algorithms for ill-conditioned dense matrix problems in VLSI interconnect and substrate modeling." Thesis, Massachusetts Institute of Technology, 1998. http://hdl.handle.net/1721.1/46180.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1998.Includes bibliographical references (leaves 131-135).
by Mike Chuan Chou.
Ph.D.
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Seo, Chung-Seok. "Physical Design of Optoelectronic System-on-a-Chip/Package Using Electrical and Optical Interconnects: CAD Tools and Algorithms." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-11102004-150844/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.David E. Schimmel, Committee Member ; C.P. Wong, Committee Member ; John A. Buck, Committee Member ; Abhijit Chatterjee, Committee Chair ; Madhavan Swaminathan, Committee Member. Vita. Includes bibliographical references.
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Lee, Laurence H. (Laurence Hongsing). "Modeling and design of superconducting microwave passive devices and interconnects." Thesis, Massachusetts Institute of Technology, 1994. http://hdl.handle.net/1721.1/36452.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.Includes bibliographical references (p. 157-163).
by Laurence H. Lee.
Ph.D.
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Chiun-Shen, Liao. "A network approach for thermo-electrical modelling : from IC interconnects to textile composites." Thesis, University of British Columbia, 2010. http://hdl.handle.net/2429/28471.
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Simulations of the temperature distribution in regular IC interconnect networks and textile composites are achieved by means of an analytical-symbolic approach. Analytical heating solutions along each interconnect can provide accurate solutions with far fewer nodes than numerical solutions. To simulate the case of textile composite, the textile composite is modelled by a network of interconnects. The necessary input information is contained in netlist files, similar to the SPICE (Simulation Program with Integrated Circuit Emphasis) input format. Analytical solutions to the heat equation along each interconnect can provide accuracy and require the minimum number of symbolic network nodes. The LU decomposition of the symbolic network scales as the cube of the number of nodes. Multiple evaluations, including iterating temperature-dependent thermal conductivity to achieve a self-consistent solution, scale linearly with the number of nodes and hardly affect the total solution time. Memory consumption, CPU time, and solutions of the new network calculation method compare favorably to a finite element analysis using ABAQUS.
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Bourduas, Stephan. "Modeling, evaluation, and implementation of ring-based interconnects for network-on-chip." Thesis, McGill University, 2008. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=19244.
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This thesis investigates the properties of a hierarchical ring architecture, which is composed of several unidirectional rings arranged to form a hierarchy. The proposed hierarchical ring topology exhibits several characteristics that make it well suited for on-chip use as a system-on-chip (SoC) interconnect. First, unidirectional rings reduce routing complexity thereby lowering buffer, area and energy requirements. Second, the simplicity of the routing logic results in low latencies and high clock rates. Finally, the hierarchical ring structure can be partitioned into multiple clock domains enabling the clock rates of individual rings to be tuned to save power while meeting design constraints. The hierarchical ring architecture has been evaluated using high-level behavioral models as well as a low-level register transfer-level (RTL) implementation. Furthermore, the hierarchical rings are combined with the popular two-dimensional mesh architecture to form several composite architectures in order to improve network performance. The mesh architecture exhibits increased latencies, hop-counts, and congestion with increasing network size. To combat these scalability issues, the hierarchical rings are used in the composite architectures to relieve congestion in the center of the mesh and to reduce hop-counts and latencies for long-distance communication, thereby achieving an overall improvement in performance. Simulation results show that the composite architectures decrease the latencies and hop-counts incurred by global traffic, thereby validating the claim that the use of hierarchical rings for global routing can in fact increase the scalability of the normal mesh network used for network-on-chip (NoC) implementations. Finally,Cette thèse étudie les propriétés d'une interconnexion hiérarchique composée d'anneaux unidirectionnels. La topologie d'anneaux hiérarchique possède plusieurs caractéristiques souhaitables pour être utilisée comme interconnexion pour réseau-sur-puce (NoC). En premier lieu, la structure unidirectionnelle des anneaux sert à réduire la complexité de routage, ce qui implique une diminution de l'importance des mémoires tampon requises et économise l'énergie consommée par l'interconnexion. En second lieu, les faibles temps de latences et d'horloge système élevé résultent de la simplicité logique de chaque routeur. Finalement, la structure de l'interconnexion facilite une partition où chaque anneau appartient à son propre domaine contrôlé par une horloge individuelle, ce qui rend possible l'application de stratégies dynamiques permettant l'économie d'énergie. L'architecture proposée a été évaluée grâce à des simulations de modèles de hauts niveaux et par une implémentation logique résistance-transistor (RTL). De plus, les anneaux hiérarchiques sont combinés avec l'architecture de maille (« mesh ») bidimensionnelle pour former plusieurs architectures hybrides afin d'améliorer la performance du réseau. La topologie de maille démontre l'augmentation de latences, du nombre de sauts, et de la congestion avec l'agrandissement du réseau. Cependant, les architectures hybrides utilisent les anneaux hiérarchiques pour réduire la congestion au centre du réseau et diminuer le nombre de sauts et les temps de latences associés avec les communications à longue distance. Il en résulte donc une amélioration globale de la performance du système. Les résultats des simulations démontrent que les$
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Hsu, Pochang. "A computer-aided design framework for modeling and simulation of VLSI interconnects." Diss., The University of Arizona, 1993. http://hdl.handle.net/10150/186363.
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The rising complexity of interconnect and packaging structures in VLSI systems has increased the necessity of applying modeling and simulation techniques for analysis and design. To effectively manage design data and CAD tools for modeling and simulations of electronic packaging, a framework which provides different levels of services is essential. This paper discusses a computer-aided design framework for the aforementioned purposes. A CAD framework with a five layered architecture is developed to support the analysis and design for VLSI packaging and interconnects. The first layer of the framework emphasizes the fundamental integration of CAD tools and simulation management. In the second layer of the architecture, design data representation and management are stressed. Two design databases termed the Chip Model Library and the Packaging Model Library are developed and coupled in this layer. We applied an object-oriented approach to implement libraries and encapsulate CAD tools. System level (board level) modeling and simulation are presented in the third layer of the framework. CMOS based multichip modules (MCMs) are used for our discussion. The fourth layer is for the automation of design process by coordinating different CAD tools. The highest layer in the proposed CAD framework is the level for design methodology management. A rule and frame based system is illustrated for simulation model generation of electronic packages.
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Park, Tae Hong 1973. "Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8082.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2002.Includes bibliographical references (p. 173-176).
Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this thesis, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is developed. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 gm by 40 tm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. For pattern dependencies in copper CMP, this thesis focuses on the development of test structures and masks (including multi-level structures) to identify key pattern effects in both single-level and multi-level polishing.
(cont.) Especially for the multi-level studies, electrical test structures and measurements in addition to surface profile scans are seen to be important in accurately determining thickness variations. The developed test vehicle and characterization of copper dishing and oxide erosion serve as a basis for further pattern dependent model development. Finally, integration of electroplating and CMP chip-scale models is illustrated; the simulated step and array heights as well as topography pattern density are used as an input for the initial starting topography for CMP simulation of subsequent polishing profile evolution.
by Tae Hong Park.
Ph.D.
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Chen, Quan. "Efficient numerical modeling of random surface roughness for interconnect internal impedance extraction." Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B3955708X.
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Chen, Quan, and 陳全. "Efficient numerical modeling of random surface roughness for interconnect internal impedance extraction." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B3955708X.
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Xie, Jianyong. "Electrical-thermal modeling and simulation for three-dimensional integrated systems." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/50307.
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The continuous miniaturization of electronic systems using the three-dimensional (3D) integration technique has brought in new challenges for the computer-aided design and modeling of 3D integrated circuits (ICs) and systems. The major challenges for the modeling and analysis of 3D integrated systems mainly stem from four aspects: (a) the interaction between the electrical and thermal domains in an integrated system, (b) the increasing modeling complexity arising from 3D systems requires the development of multiscale techniques for the modeling and analysis of DC voltage drop, thermal gradients, and electromagnetic behaviors, (c) efficient modeling of microfluidic cooling, and (d) the demand of performing fast thermal simulation with varying design parameters. Addressing these challenges for the electrical/thermal modeling and analysis of 3D systems necessitates the development of novel numerical modeling methods.
This dissertation mainly focuses on developing efficient electrical and thermal numerical modeling and co-simulation methods for 3D integrated systems. The developed numerical methods can be classified into three categories. The first category aims to investigate the interaction between electrical and thermal characteristics for power delivery networks (PDNs) in steady state and the thermal effect on characteristics of through-silicon via (TSV) arrays at high frequencies. The steady-state electrical-thermal interaction for PDNs is addressed by developing a voltage drop-thermal co-simulation method while the thermal effect on TSV characteristics is studied by proposing a thermal-electrical analysis approach for TSV arrays.
The second category of numerical methods focuses on developing multiscale modeling approaches for the voltage drop and thermal analysis. A multiscale modeling method based on the finite-element non-conformal domain decomposition technique has been developed for the voltage drop and thermal analysis of 3D systems. The proposed method allows the modeling of a 3D multiscale system using independent mesh grids in sub-domains. As a result, the system unknowns can be greatly reduced. In addition, to improve the simulation efficiency, the cascadic multigrid solving approach has been adopted for the voltage drop-thermal co-simulation with a large number of unknowns.
The focus of the last category is to develop fast thermal simulation methods using compact models and model order reduction (MOR). To overcome the computational cost using the computational fluid dynamics simulation, a finite-volume compact thermal model has been developed for the microchannel-based fluidic cooling. This compact thermal model enables the fast thermal simulation of 3D ICs with a large number of microchannels for early-stage design. In addition, a system-level thermal modeling method using domain decomposition and model order reduction is developed for both the steady-state and transient thermal analysis. The proposed approach can efficiently support thermal modeling with varying design parameters without using parameterized MOR techniques.
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Du, Zhaobin. "Area COI-based slow frequency dynamics modeling, analysis and emergency control for interconnected power systems." Click to view the E-thesis via HKUTO, 2008. http://sunzi.lib.hku.hk/hkuto/record/B4175783X.
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Sarker, Partha Sarathi. "DYNAMIC MODELING, STABILITY ANALYSIS AND CONTROL OF AC/DC INTERCONNECTED MICROGRID USING DQ-TRANSFORMATION." Master's thesis, Temple University Libraries, 2018. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/518146.
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Electrical and Computer EngineeringM.S.E.E.
In recent years, there have been significant changes in power systems due to the integration of renewables, distributed generation, switched power loads, and energy storage systems, etc. Locally these AC/DC microgrids include both DC generation (such as solar PV) and AC generation (such as wind generation), various DC and AC loads, converters and inverters, and energy storage systems, such as storage batteries and supercapacitors. DC systems are often characterized as low inertia systems whereas AC generation and systems are usually high inertia and high time constant systems. As such, various components of the microgrid will have different temporal characteristics in case of disturbances, such as short circuit, load switchings, etc. which may lead to instability of the microgrid. This research develops the first principle model for coupling the AC and the DC subsystem of an integrated AC/DC microgrid utilizing the dq-framework. The developed model is highly nonlinear and captures the dynamic interaction between the AC and DC subsystems of the microgrid. Lyapunov stability is used to evaluate the stability of the complete system. Simulation results show that the AC and DC subsystems are tightly dynamically coupled so that any disturbance in one subsystem induces transients in the other subsystem. Induced transients due to pulse loads on the AC and DC subsystems clearly show that generator damper winding alone may not be enough to mitigate transients in the microgrid. Addition of prime mover and excitation system controllers for the generator improves the transients primarily on the AC subsystem. Thus, a battery storage with a charge/discharge controller was also added to the DC subsystem. Simulations of the AC/DC microgrid with all three controllers validate the smooth operation of the system for all types of disturbances. The proposed method can be extended in modeling microgrid with multiple generators and various types of loads.
Temple University--Theses
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Du, Zhaobin, and 杜兆斌. "Area COI-based slow frequency dynamics modeling, analysis and emergency control for interconnected power systems." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2008. http://hub.hku.hk/bib/B4175783X.
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Pasha, Soheila. "Electromagnetic Modeling of High-Speed Interconnects with Frequency Dependent Conductor Losses, Compatible with Passive Model Order Reduction Techniques." Diss., The University of Arizona, 2012. http://hdl.handle.net/10150/268354.
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A computationally efficient, discrete model is presented for transmission line analysis and passive model order reduction of high-speed interconnect systems. The development of this model was motivated by the on-going efforts in chip/package co-design to route a major portion of the on-chip clock and high-speed data buses through the package in order to overcome the bandwidth reduction and delay caused by the high ohmic loss of on-chip wiring. The geometric complexity of the resulting interconnections is such that model order reduction is essential for rapid and accurate signal integrity assessment to support pre-layout design iteration and optimization. The modal network theory of the skin effect in conjunction with the theory of compact differences is used for the development of discrete models for dispersive, multi-conductor interconnects compatible with passive model order reduction algorithms. The passive reduced-order interconnect modeling algorithm, PRIMA, is then used on the resulting discrete model to generate a low-order, multi-port macromodel for interconnect networks. Numerical examples are used to demonstrate the validity and efficiency of the proposed model.
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Han, Ki Jin. "Electromagnetic modeling of interconnections in three-dimensional integration." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29642.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Madhavan Swaminathan; Committee Member: Andrew E. Peterson; Committee Member: Emmanouil M. Tentzeris; Committee Member: Hao-Min Zhou; Committee Member: Saibal Mukhopadhyay. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Sreedhar, Aswin. "Automatic techniques for modeling impact of sub-wavelength lithography on transistors and interconnects and strategies for testing lithography induced defects." Connect to this title online, 2008. http://scholarworks.umass.edu/theses/80/.
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Mao, Jifeng. "Modeling of simultaneous switching noise in on-chip and package power distribution networks using conformal mapping, finite difference time domain and cavity resonator methods." Diss., Available online, Georgia Institute of Technology, 2005, 2004. http://etd.gatech.edu/theses/available/etd-10062004-125025/.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.
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Gencoglu, Cihangir. "Assessment Of The Effect Of Hydroelectric Power Plants'." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12612165/index.pdf.
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The Turkish TSO (TEIAS) has been leading a project that aims the synchronous interconnected operation of the Turkish Power System and the ENTSO-E CESA (former UCTE) System. For this purpose, this study concentrates on the specific problems related to the electromechanical systems of large size hydroelectric power plants regarding low frequency inter area oscillations, which are prone to occur once the interconnected operation is established. The expected frequency of inter area oscillations after interconnected operation is close to 0.15 Hz, which is in the frequency range of the speed governing structures of turbines, as explained in the first two sections of the thesis. In the third section, the nonlinear turbine governor model used throughout the study is explained. In the following part, the governor parameter tuning study with regard to the defined performance objectives is explained. Afterwards, the effect of the retuned governor settings of the sample hydroelectric power plants on a simple multi machine power system is shown. Following that, the system wide effect of removing the sources of negative damping, which are strongly dependent on the governor settings of the major hydroelectric power plants of the Turkish Power System, is shown. In the final part, conclusions are made on the operation of the hydroelectric power plants regarding the frequency stability of the system after synchronous interconnected operation of the Turkish Power System and the ENTSO-E CESA System.
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Reehal, Gursharan Kaur. "Designing Low Power and High Performance Network-on-Chip Communication Architectures for Nanometer SoCs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1340022240.
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Bellache, Kosseila. "Caractérisation Multi-physique des éléments de stockage électrochimique et électrostatique dédiés aux systèmes Multi sources : Approche systémique pour la gestion dynamique d'énergie électrique." Thesis, Normandie, 2018. http://www.theses.fr/2018NORMLH21.
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Ce travail de thèse s’inscrit dans la continuité des activités de recherche du laboratoire GREAH sur les problématiques de la gestion d’énergie électrique et de l’amélioration de la qualité énergétique des systèmes de production aux énergies renouvelables. En effet, le couplage de plusieurs sources de natures différentes entraîne des problématiques de dimensionnement, de qualité d’énergie et de la durée de vie des éléments interconnectés. La démarche scientifique repose sur la caractérisation de l'évolution des résistances et des capacités des cellules de batteries LFP/supercondensateurs en fonction des contraintes électriques et thermiques, suivi de la modélisation du vieillissement accéléré des cellules. Nous proposons dans ce mémoire de thèse des améliorations de la réponse dynamique d’un bateau fluvial à propulsion électrique par l’hybridation des batteries LFP et des supercondensateurs. Nous proposons également une approche électrothermique pour la caractérisation et la modélisation multi-physique du vieillissement des batteries et supercondensateurs en utilisant des contraintes combinées de la température et de la fréquence des ondulations du courant de charge/décharge des cellules. Les données expérimentales collectées ont permis d'établir des modèles des supercondensateurs et des batteries dédiés aux systèmes multi-sources incluant des sources d’énergie renouvelable (éoliens et hydroliens). Les modèles développés se révèlent très précis par rapport aux résultats expérimentaux. Ils permettent une bonne description du phénomène de vieillissement des batteries LFP/supercondensateurs dû aux opérations de charge/décharge avec un courant continu fluctuant combiné à une température variableThis thesis work is a continuation of the research activities of the GREAH laboratory on the issues of the management of electrical energy and improving the energy quality of production systems for renewable energy. Indeed, the coupling of several different nature sources entails the problems of dimension, quality of energy and the lifetime of the interconnected elements. The scientific approach is based on the characterization of the evolution of the resistances and capacitances of the batteries/supercapacitors cells according to the electrical and thermal constraints, followed by the modeling of accelerated cells aging. In this thesis, we propose improvements to the dynamic response of an electric propulsion fluvial boat by using the hybrid system of lithium-batteries and supercapacitors. We also propose an electrothermal approach for the multi-physical characterization and modeling of the batteries and supercapacitors aging, using combined constraints of the temperature and frequency of the DC current ripples. The experimental data has been collected to establish models of batteries and supercapacitors dedicated to multi-source systems including renewable energy sources (wind and tidal turbines). The results of the developed models shown high accuracy compared with experimental results. These models illustrated a good description of the aging phenomenon of batteries/ supercapacitors due to charging/discharging operations with a fluctuating continuous current combined with a variable temperature
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Palaniappan, Arun. "Modeling, Optimization and Power Efficiency Comparison of High-speed Inter-chip Electrical and Optical Interconnect Architectures in Nanometer CMOS Technologies." Thesis, 2010. http://hdl.handle.net/1969.1/ETD-TAMU-2010-12-8618.
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Inter-chip input-output (I/O) communication bandwidth demand, which rapidly scaled with integrated circuit scaling, has leveraged equalization techniques to operate reliably on band-limited channels at additional power and area complexity. High-bandwidth inter-chip optical interconnect architectures have the potential to address this increasing I/O bandwidth. Considering future tera-scale systems, power dissipation of the high-speed I/O link becomes a significant concern. This work presents a design flow for the power optimization and comparison of high-speed electrical and optical links at a given data rate and channel type in 90 nm and 45 nm CMOS technologies.
The electrical I/O design framework combines statistical link analysis techniques, which are used to determine the link margins at a given bit-error rate (BER), with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology to predict the power-optimum equalization architecture, circuit style, and transmit swing at a given data rate and process node for three different channels. The transmitter output swing is scaled to operate the link at optimal power efficiency. Under consideration for optical links are a near-term architecture consisting of discrete vertical-cavity surface-emitting lasers (VCSEL) with p-i-n photodetectors (PD) and three long-term integrated photonic architectures that use waveguide metal-semiconductor-metal (MSM) photodetectors and either electro-absorption modulator (EAM), ring resonator modulator (RRM), or Mach-Zehnder modulator (MZM) sources. The normalized transistor parameters are applied to jointly optimize the transmitter and receiver circuitry to minimize total optical link power dissipation for a specified data rate and process technology at a given BER.
Analysis results shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing, allows electrical links to achieve excellent power efficiency at high data rates. While the high-loss channel is primarily limited by severe frequency dependent losses to 12 Gb/s, the critical timing path of the first tap of the decision feedback equalizer (DFE) limits the operation of low-loss channels above 20 Gb/s. Among the optical links, the VCSEL-based link is limited by its bandwidth and maximum power levels to a data rate of 24 Gb/s whereas EAM and RRM are both attractive integrated photonic technologies capable of scaling data rates past 30 Gb/s achieving excellent power efficiency in the 45 nm node and are primarily limited by coupling and device insertion losses. While MZM offers robust operation due to its wide optical bandwidth, significant improvements in power efficiency must be achieved to become applicable for high density applications.
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Gumede, Nkosinomusa S. "Eskom-ZESA interconnected power system modelling." Thesis, 2016. http://hdl.handle.net/10539/21110.
Full textAbstract:
A research report submitted to the Faculty of Engineering and the Built Environment, University of the Witwatersrand, Johannesburg, in partial fulfilment of the requirements for the degree of Master of Science in Engineering, 2016The power system frequency must be kept as close as possible to the nominal value. This is due to the inherent design of electrical equipment to operate efficiently at the nominal frequency. Frequency regulation in an interconnected power system is the duty of all members of the interconnection. However, in the Eskom-ZESA interconnected power system Eskom engineers ignore the contribution of the ZESA system to primary frequency control. This is mainly due to the prevalent assumption that the ZESA control area is small relative to the Eskom control area and its contribution to primary frequency control of the interconnected power system is negligible. This document presents a project that examines the validity of this assumption via determination of the contribution of the ZESA system to the interconnected power system’s primary frequency control. The interconnected power systems background was studied to understand the theory behind the operation of two or more interconnected power systems. System frequency disturbances deemed to be a good representation of the Eskom-ZESA interconnected power system’s performance were selected and analysed to validate the current assumption. The results show that there is a significant support from ZESA during a system frequency disturbance. This proves that the existing assumption is not valid anymore. Furthermore; the generator model that mimics the Eskom-ZESA tie-line governing behaviour was developed. Two different types of governor models were employed; firstly the IEEEG1 governor was tuned to control generator output to match the tie-line performance and then the TGOV5 governor model was used. The IEEEG1 governor model is a simplified governor representation; as a result, it is not easy to tune the parameters to match tie-line response. However, the performance is acceptable and it can be used to represent the tieline governor response. The TGOV5 governor model is very complex as discussed in section 4.2. The model includes boiler dynamics, and this improves performance such that it is possible to tune the parameters to follow the tie-line performance as close as necessary.
GR2016
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Sun, Ruey-Bo, and 孫瑞伯. "Electrical Modeling and Design for Signal Integrity of Area-Array Vertical Interconnects in Electronic Packaging." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/60943366541212561875.
Full textAbstract:
博士國立臺灣大學
電信工程學研究所
99
In order to optimize the electrical performance of electronic packaging, the electrical modeling and designs for signal integrity (SI) of vertical interconnects are the considerably critical issues. In this dissertation, the various significant kinds of noises, including reflection, crosstalk, simultaneous switching noise (SSN), and substrate loss in the area-array vertical interconnects, are investigated by taking three different types of vertical interconnects, consisting of pin type (pogo pin), ball-shape type (bump and solder ball), and via type (through silicon via, TSV) as examples. A series of novel and systematic methodologies are proposed for the investigations and noise suppression. With regard to the analysis and suppression of SSN, this dissertation takes a bump grid array as an example to propose a systematic design methodology, acquiring the optimal signal-ground assignment with the minimized loop SSN by using genetic algorithm (GA). For the reduction of computing complexity, a new circuit simplification method is developed to simplify a complete I/O buffer circuits, including package traces and a bump array, into a circuit of inductors and current sources together with its applicable range derived analytically. Based on the optimized results, the optimal signal-to-ground ratio and its associated bump assignments are obtained. Also, some heuristic designs are proposed, accordingly. As for suppressions of the reflection and crosstalk, designs of the impedance match and crosstalk reduction for all possible signal-ground assignments are very challenging. In this dissertation, a novel compromise impedance match design is proposed for a pogo pin array with the diverse pin assignments to find the permissible window of the pogo pin geometries and the upper bound of operating frequency such that all pin patterns meet the specification on return loss. Two different types of design charts are developed to greatly facilitate the design. The first one is the equivalent impedance of pogo pin versus the pin radius-to-pitch ratio. The second one is a much general chart in terms of the reflection coefficient versus the electrical length and the relative impedance difference of the pogo pin. On the other hand, for the sake of the crosstalk reduction in the pogo pin array, a new isolation structure directly integrated in a test socket is proposed. The isolation structure is appropriately designed by adopting the full-wave and quasi-static methods so that the reflection and crosstalk for all pin patterns are both smaller than -20 dB over dc to 10 GHz. The measured S parameters obtained by using the new test fixtures have good correlations with simulated ones, validating the proposed ideas and methodologies. Regarding to the suppression of dispersion noise due to the substrate loss, the equalization technique can be introduced to compensate the lossy effect. Considering the TSV interconnect in the three-dimensional integrated circuit (3D IC), a novel passive equalizer capable of the perfect compensation for lossy effects of TSV is devised. It is only composed of a parallel resistance-capacitance (RC) circuit. To design the equalizer, the analytic circuit model of TSV is derived and substantiated up to 20 GHz, and based on which, the novel significance analysis is implemented to inspect the relative importance of each parasitic element, thereby attaining a much simplified capacitance-conductance (CG) circuit model. It proves that the first order effects of TSV are attributed to the oxide liner and the lossy silicon substrate. The design theory and formulas of the equalizer can also be derived accordingly. The output eye diagram of multi-stacked TSVs in series with the designed equalizer is nearly open with zero timing jitter.
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"Modelling, simulation and experimental observation of wave propagation on VLSI interconnects." 1997. http://library.cuhk.edu.hk/record=b5889206.
Full textAbstract:
by Yuen-Pat Lau.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.
Includes bibliographical references (leaves 127-[129]).
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- VLSI Interconnects in Circuits --- p.1
Chapter 1.2 --- Propagating Waves on Interconnects --- p.4
Chapter 2 --- Theory: FDTD --- p.6
Chapter 2.1 --- Modelling Microstrips in FDTD Mesh Space --- p.6
Chapter 2.2 --- FDTD Implementation of a Unit Cell --- p.8
Chapter 2.3 --- FDTD Implementation of a Lumped Element --- p.12
Chapter 2.4 --- FDTD Implementation of a Circuit --- p.14
Chapter 3 --- Theory: TDMS --- p.20
Chapter 3.1 --- FDTD Circuit Simulation --- p.20
Chapter 3.2 --- TDMS: Microstrip Characterization --- p.22
Chapter 3.3 --- TDMS: Parameter Extraction --- p.23
Chapter 3.4 --- TDMS: Circuit Simulation --- p.26
Chapter 4 --- TDMS Simulations --- p.30
Chapter 4.1 --- Example One: Loaded Diode --- p.30
Chapter 4.2 --- Example Two: Unbalanced Mixer --- p.38
Chapter 5 --- TDR Experiments --- p.54
Chapter 5.1 --- Example Three: Uniform Microstrip --- p.54
Chapter 5.2 --- Example Four: Coupled Microstrip --- p.61
Chapter 5.3 --- Example Five: Change-in-width Microstrip --- p.67
Chapter 6 --- Conclusion --- p.78
Chapter 7 --- Program Listing --- p.80
Chapter 7.1 --- Example Two: Unbalanced Mixer --- p.80
Chapter 7.2 --- Example Five: Change-in-width Microstrip --- p.110
Bibliography --- p.127